diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 00000000000..5a588ed021b --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,43 @@ +# Description +This document is cheat sheet for everyone who wants to contribute to mbedmicro/mbed GitHub repository at GitHub. +All changes in code base should originate from GitHub Issues and take advantage of existing GitHub flows. Goal is to attract contributors and allow them contribute to code and documentation at the same time. + +Guidelines from this document are created to help new and existing contributors understand process workflow and align to project rules before pull request is submitted. It explains how a participant should do things like format code, test fixes, and submit patches. + +## Where to get more information? +You can for example read more in our ```docs``` section in [mbedmicro/mbed/doc](https://github.com/PrzemekWirkus/mbed/tree/docs/docs) directory. + +# How to contribute +We really appreciate your contributions! We are Open Source project and we need your help. We want to keep it as easy as possible to contribute changes that get things working in your environment. There are a few guidelines that we need contributors to follow so that we can have a chance of keeping on top of things. + +You can pick up existing [mbed GitHub Issue](https://github.com/mbedmicro/mbed/issues) and solve it or implement new feature you find important, attractive or just necessary. We will review your proposal via pull request mechanism, give you comments and merge your changes if we decide your contribution satisfy criteria such as quality. + +# Enhancements vs Bugs +Enhancements are: +* New features implementation. +* Code refactoring. +* Coding rules, coding styles improvements. +* Code comments improvement. +* Documentation work. + +Bugs are: +* Issues rose internally or externally by mbedmicro/mbed users. +* Internally (within mbed team) created issues from Continuous Integration pipeline and build servers. +* Issues detected using automation tools such as compilers, sanitizers, static code analysis tools etc. + +# Gate Keeper role +Gate Keeper is a person responsible for GitHub process workflow execution and is responsible for repository / project code base. Gate Keeper is also responsible for code (pull request) quality stamp and approves or rejects code changes in project’s code base. + +Gate Keepers will review your pull request code, give you comments in pull request comment section and in the end if everything goes well merge your pull request to one of our branches (most probably default ```master``` branch). + +Please be patient, digest Gate Keeper's feedback and respond promptly :) + +# mbed SDK porting +* For more information regarding mbed SDK porting please refer to [mbed SDK porting](http://developer.mbed.org/handbook/mbed-SDK-porting) handbook. +* Before starting the mbed SDK porting, you might want to familiarize with the [mbed SDK library internals](http://developer.mbed.org/handbook/mbed-library-internals) first. + +# Glossary +* Gate Keeper – persons responsible for overall code-base quality of mbedmicro/mbed project. +* Enhancement – New feature deployment, code refactoring actions or existing code improvements. +* Bugfix – Issues originated from GitHub Issues pool, raised internally within mbed classic team or issues from automated code validators like linters, static code analysis tools etc. +* Mbed classic – mbed SDK 2.0 located in GitHub at mbedmicro/mbed. diff --git a/docs/BUILDING.md b/docs/BUILDING.md new file mode 100644 index 00000000000..243bea5cd4e --- /dev/null +++ b/docs/BUILDING.md @@ -0,0 +1,601 @@ +# Mbed SDK build script environment +## Introduction +Mbed test framework allows users to test their mbed devices’ applications, build mbed SDK library, re-run tests, run mbed SDK regression, add new tests and get all this results automatically. Everything is done on your machine so you have a full control over compilation, and tests you run. + +It's is using Python 2.7 programming language to drive all tests so make sure Python 2.7 is installed on your system and included in your system PATH. To compile mbed SDK and tests you will need one or more supported compilers installed on your system. + +To follow this short introduction you should already: +* Know what mbed SDK is in general. +* Know how to install Python 2.7, ARM target cross compilers. +* You have C/C++ programming experience and at least willingness to learn a bit about Python. + +## Test automation +Currently our simple test framework allows users to run tests on their machines (hosts) in a fully automated manner. All you need to do is to prepare two configuration files. + +## Test automation limitations +Note that for tests which require connected external peripherals, for example Ethernet, SD flash cards, external EEPROM tests, loops etc. you need to: + +* Modify test source code to match components' pin names to actual mbed board pins where peripheral is connected or +* Wire your board the same way test defines it. + +## Prerequisites +mbed test suite and build scripts are Python 2.7 applications and require Python 2.7 runtime environment and [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html) to install dependencies. + +What we need: +* Installed [Python 2.7](https://www.python.org/download/releases/2.7) programming language. +* Installed [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html#installing-setuptools-and-easy-install) +* Optionally you can install [pip](https://pip.pypa.io/en/latest/installing.html) which is the PyPA recommended tool for installing Python packages from command line. + +mbed SDK in its repo root directory specifies ```setup.py``` file which holds information about all packages which are dependencies for it. Bear in mind only few simple steps are required to install all dependencies. + +First, clone mbed SDK repo and go to mbed SDk repo's directory: +``` +$ git clone https://github.com/mbedmicro/mbed.git +$ cd mbed +``` + +Second, invoke ```setup.py``` so ```setuptools``` can install mbed SDK's dependencies (external Python modules required by mbed SDK): +``` +$ python setup.py install +``` +or +``` +$ sudo python setup.py install +``` +when your system requires administrator rights to install new Python packages. + +## Prerequisites (manual Python package dependency installation) +**Please only read this chapter if you had problems installing mbed SDK dependencies to Python packages**. + +Below you can find the list of mbed SDK dependencies to Python modules with instructions how to install them manually. + +You can skip this part if you've already install [Python 2.7](https://www.python.org/download/releases/2.7) and [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html) and successfully [installed all dependencies](#prerequisites). + +* Please make sure you've installed [pip](https://pip.pypa.io/en/latest/installing.html) or [easy_install](https://pythonhosted.org/setuptools/easy_install.html#installing-easy-install) +Note: Easy Install is a python module (easy_install) bundled with [setuptools](https://pythonhosted.org/an_example_pypi_project/setuptools.html#installing-setuptools-and-easy-install) that lets you automatically download, build, install, and manage Python packages. + +* Installed [pySerial](https://pypi.python.org/pypi/pyserial) module for Python 2.7. +pySerial can be installed from PyPI, either manually downloading the files and installing as described below or using: +``` +$ pip install pyserial +``` +or: +``` +easy_install -U pyserial +``` +* Installed [prettytable](https://code.google.com/p/prettytable/wiki/Installation) module for Python 2.7. +prettytable can be installed from PyPI, either manually downloading the files and installing as described below or using: +``` +$ pip install prettytable +``` +* Installed [IntelHex](https://pypi.python.org/pypi/IntelHex) module. +IntelHex may be downloaded from https://launchpad.net/intelhex/+download or http://www.bialix.com/intelhex/. +Assuming Python is properly installed on your platform, installation should just require running the following command from the root directory of the archive: +``` +sudo python setup.py install +``` +This will install the intelhex package into your system’s site-packages directory. After that is done, any other Python scripts or modules should be able to import the package using: +``` +$ python +Python 2.7.8 (default, Jun 30 2014, 16:03:49) [MSC v.1500 32 bit (Intel)] on win32 +Type "help", "copyright", "credits" or "license" for more information. +>>> from intelhex import IntelHex +>>> +``` +* You can check if you have correctly installed the above modules (or you already have them) by starting Python and importing both modules. +``` +$ python +Python 2.7.8 (default, Jun 30 2014, 16:03:49) [MSC v.1500 32 bit (Intel)] on win32 +Type "help", "copyright", "credits" or "license" for more information. +>>> import serial +>>> import prettytable +>>> from intelhex import IntelHex +>>> +``` +* Installed Git open source distributed version control system. +* Installed at least one of the supported by Mbed SDK workspace tools compilers: + +Compiler | Mbed SDK Abbreviation | Example Version +-----------------------|-----------------------|----------- +Keil ARM Compiler | ARM, uARM | ARM C/C++ Compiler, 5.03 [Build 117] +GCC ARM | GCC_ARM | gcc version 4.8.3 20131129 (release) +GCC CodeSourcery | GCC_CS | gcc version 4.8.1 (Sourcery CodeBench Lite 2013.11-24) +GCC CodeRed | GCC_CR | gcc version 4.6.2 20121016 (release) +IAR Embedded Workbench | IAR | IAR ANSI C/C++ Compiler V6.70.1.5641/W32 for ARM + +* Mbed board. You can find list of supported platforms [here](https://mbed.org/platforms/). + +### Getting Mbed SDK sources with test suite +So you have already installed Python (with required modules) together with at least one supported compiler you will use with your mbed board. Great! + +Now let's go further and try to get Mbed SDK with test suite together. So let's clone latest Mbed SDK source code and configure path to our compiler(s) in next few steps. + +* Open console and run command below to clone Mbed SDK repository hosted on [Github](https://github.com/mbedmicro/mbed). +``` +$ git clone https://github.com/mbedmicro/mbed.git +Cloning into 'mbed'... +remote: Counting objects: 37221, done. +remote: Compressing objects: 100% (3/3), done. +remote: Total 37221 (delta 0), reused 0 (delta 0), pack-reused 37218 +Receiving objects: 100% (37221/37221), 20.38 MiB | 511.00 KiB/s, done. +Resolving deltas: 100% (24455/24455), done. +Checking connectivity... done. +Checking out files: 100% (3994/3994), done. +``` +* Now you can go to mbed directory you've just cloned and you can see root directory structure of our Mbed SDK library sources. Just type following commands: +``` +$ cd mbed +$ ls +LICENSE MANIFEST.in README.md libraries setup.py travis workspace_tools +``` +Directory structure we are interested in: +``` + mbed/workspace_tools/ - test suite scripts, build scripts etc. + mbed/library/tests/ - mbed SDK tests, + mbed/library/tests/mbed/ - tests for mbed SDK and peripherals tests, + mbed/library/tests/net/echo/ - tests for Ethernet interface, + mbed/library/tests/rtos/mbed/ - tests for RTOS. +``` + +### Workspace tools +Workspace tools are set of Python scripts used off-line by Mbed SDK team to: +* Compile and build mbed SDK, +* Compile and build libraries included in mbed SDK repo like e.g. ETH (Ethernet), USB, RTOS or CMSIS, +* Compile, build and run mbed SDK tests, +* Run test regression locally and in CI server, +* Get library, target, test configuration (paths, parameters, names etc.). + +### Configure workspace tools to work with your compilers +Before we can run our first test we need to configure our test environment a little! +Now we need to tell workspace tools where our compilers are. + +* Please to go ```mbed/workspace_tools/``` directory and create empty file called ```private_settings.py```. +``` +$ touch private_settings.py +``` +* Populate this file the Python code below: +```python +from os.path import join + +# ARMCC +ARM_PATH = "C:/Work/toolchains/ARMCompiler_5.03_117_Windows" +ARM_BIN = join(ARM_PATH, "bin") +ARM_INC = join(ARM_PATH, "include") +ARM_LIB = join(ARM_PATH, "lib") + +ARM_CPPLIB = join(ARM_LIB, "cpplib") +MY_ARM_CLIB = join(ARM_PATH, "lib", "microlib") + +# GCC ARM +GCC_ARM_PATH = "C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin" + +# GCC CodeSourcery +GCC_CS_PATH = "C:/Work/toolchains/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# GCC CodeRed +GCC_CR_PATH = "C:/Work/toolchains/LPCXpresso_6.1.4_194/lpcxpresso/tools/bin" + +# IAR +IAR_PATH = "C:/Work/toolchains/iar_6_5/arm" + +SERVER_ADDRESS = "127.0.0.1" +LOCALHOST = "127.0.0.1" + +# This is moved to separate JSON configuration file used by singletest.py +MUTs = { +} +``` + +Note: You need to provide the absolute path to your compiler(s) installed on your host machine. Replace corresponding variable values with paths to compilers installed in your system: +* ```ARM_PATH``` for armcc compiler. +* ```GCC_ARM_PATH``` for GCC ARM compiler. +* ```GCC_CS_PATH``` for GCC CodeSourcery compiler. +* ```GCC_CR_PATH``` for GCC CodeRed compiler. +* ```IAR_PATH``` for IAR compiler. + +If for example you do not use ```IAR``` compiler you do not have to modify anything. Workspace tools will use ```IAR_PATH`` variable only if you explicit ask for it from command line. So do not worry and replace only paths for your installed compilers. + +Note: Because this is a Python script and ```ARM_PATH```, ```GCC_ARM_PATH```, ```GCC_CS_PATH```, ```GCC_CR_PATH```, ```IAR_PATH``` are Python string variables please use double backlash or single slash as path's directories delimiter to avoid incorrect path format. For example: +```python +ARM_PATH = "C:/Work/toolchains/ARMCompiler_5.03_117_Windows" +GCC_ARM_PATH = "C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin" +GCC_CS_PATH = "C:/Work/toolchains/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" +GCC_CR_PATH = "C:/Work/toolchains/LPCXpresso_6.1.4_194/lpcxpresso/tools/bin" +IAR_PATH = "C:/Work/toolchains/iar_6_5/arm" +``` + +Note: Settings in ```private_settings.py``` will overwrite variables with default values in ```mbed/workspace_tools/settings.py``` file. + +## Build Mbed SDK library from sources +Let's build mbed SDK library off-line from sources using your compiler. We've already cloned mbed SDK sources, we've also installed compilers and added their paths to ```private_settings.py```. +We now should be ready to use workspace tools script ```build.py``` to compile and build mbed SDK from sources. + +We are still using console. You should be already in ```mbed/workspace_tools/``` directory if not go to ```mbed/workspace_tools/``` and type below command: +``` +$ python build.py -m LPC1768 -t ARM +``` +or if you want to take advantage from multi-threaded compilation please use option ```-j X``` where ```X``` is number of cores you want to use to compile mbed SDK. See below: +``` +$ python build.py -m LPC1768 -t ARM -j 4 +Building library CMSIS (LPC1768, ARM) +Copy: core_ca9.h +Copy: core_caFunc.h +... +Compile: us_ticker_api.c +Compile: wait_api.c +Library: mbed.ar +Creating archive 'C:\temp\x\mbed\build\mbed\TARGET_LPC1768\TOOLCHAIN_ARM_STD\mbed.ar' +Copy: board.o +Copy: retarget.o + +Completed in: (42.58)s + +Build successes: + * ARM::LPC1768 +``` +Above command will build mbed SDK for [LPC1768](http://developer.mbed.org/platforms/mbed-LPC1768/) platform using ARM compiler. + +Let's have a look at directory structure under ```mbed/build/```. We can see for ```LPC1768``` new directory ```TARGET_LPC1768``` was created. This directory contains all build primitives. +Directory ```mbed/TARGET_LPC1768/TOOLCHAIN_ARM_STD/``` conteins mbed SDK library ```mbed.ar```. This directory structure also stores all needed headers which you should use with ```mbed.ar``` when building your own software. +``` +$ tree ./mbed/build/ +Folder PATH listing +Volume serial number is 006C006F 6243:3EA9 +./MBED/BUILD ++---mbed + +---.temp + ¦ +---TARGET_LPC1768 + ¦ +---TOOLCHAIN_ARM_STD + ¦ +---TARGET_NXP + ¦ +---TARGET_LPC176X + ¦ +---TOOLCHAIN_ARM_STD + +---TARGET_LPC1768 + +---TARGET_NXP + ¦ +---TARGET_LPC176X + ¦ +---TARGET_MBED_LPC1768 + +---TOOLCHAIN_ARM_STD +``` + +Note: Why ```LCP1768```? For this example we are using ```LPC1768``` because this platform supports all compilers so you are sure you only need to specify proper compiler. + +If you are not using ARM Compiler replace ```ARM``` with your compiler nickname: ```GCC_ARM```, ```GCC_CS```, ```GCC_CR``` or ```IAR```. For example if you are using IAR type command: +``` +$ python build.py -m LPC1768 -t IAR +``` + +Note: Workspace tools track changes in source code. So if for example mbed SDK or test source code changes ```build.py``` script will recompile project with all dependencies. If there are no changes in code consecutive mbed SDK re-builds using build.py will not rebuild project if this is not necessary. Try to run last command once again, we can see script ```build.py``` will not recompile project (there are no changes): +``` +$ python build.py -m LPC1768 -t ARM +Building library CMSIS (LPC1768, ARM) +Building library MBED (LPC1768, ARM) + +Completed in: (0.15)s + +Build successes: + * ARM::LPC1768 +``` + +### build.py script + +Build script located in mbed/workspace_tools/ is our core script solution to drive compilation, linking and building process for: + +* mbed SDK (with libs like Ethernet, RTOS, USB, USB host). +* Tests which also can be linked with libraries like RTOS or Ethernet. + +Note: Test suite also uses the same build script, inheriting the same properties like auto dependency tracking and project rebuild in case of source code changes. + +Build.py script is a powerful tool to build mbed SDK for all available platforms using all supported by mbed cross-compilers. Script is using our workspace tools build API to create desired platform-compiler builds. Use script option ```--h``` (help) to check all script parameters. +``` +$ python build.py --help +``` + +* The command line parameter ```-m``` specifies the MCUs/platforms for which you want to build the mbed SDK. More than one MCU(s)/platform(s) may be specified with this parameter using comma as delimiter. +Example for one platform build: +``` +$ python build.py -m LPC1768 -t ARM +``` +or for many platforms: +``` +$ python build.py -m LPC1768,NUCLEO_L152RE -t ARM +``` + +* Parameter ```-t``` defined which toolchain should be used for mbed SDK build. You can build Mbed SDK for multiple toolchains using one command. +Below example (note there is no space after commas) will compile mbed SDK for Freescale Freedom KL25Z platform using ARM and GCC_ARM compilers: +``` +$ python build.py -m KL25Z -t ARM,GCC_ARM +``` + +* You can combine this technique to compile multiple targets with multiple compilers. +Below example will compile mbed SDK for Freescale's KL25Z and KL46Z platforms using ARM and GCC_ARM compilers: +``` +$ python build.py -m KL25Z,KL46Z -t ARM,GCC_ARM +``` + +* Building libraries included in mbed SDK's source code. Parameters ```-r```, ```-e```, ```-u```, ```-U```, ```-d```, ```-b``` will add ```RTOS```, ```Ethernet```, ```USB```, ```USB Host```, ```DSP```, ```U-Blox``` libraries respectively. +Below example will build Mbed SDK library for for NXP LPC1768 platform together with RTOS (```-r``` switch) and Ethernet (```-e``` switch) libraries. +``` +$ python build.py -m LPC1768 -t ARM -r -e +Building library CMSIS (LPC1768, ARM) +Building library MBED (LPC1768, ARM) +Building library RTX (LPC1768, ARM) +Building library RTOS (LPC1768, ARM) +Building library ETH (LPC1768, ARM) + +Completed in: (0.48)s + +Build successes: + * ARM::LPC1768 +``` + +* If you’re unsure which platforms and toolchains are supported please use switch ```-S``` to print simple matrix of platform to compiler dependencies. +``` +$ python python build.py -S ++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+ +| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB | ++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+ +| APPNEARME_MICRONFCBOARD | Supported | Default | Supported | - | - | - | - | - | +| ARCH_BLE | Default | - | Supported | Supported | - | - | - | - | +| ARCH_GPRS | Supported | Default | Supported | Supported | Supported | - | - | - | +... +| UBLOX_C029 | Supported | Default | Supported | Supported | - | - | - | - | +| WALLBOT_BLE | Default | - | Supported | Supported | - | - | - | - | +| XADOW_M0 | Supported | Default | Supported | Supported | Supported | - | - | - | ++-------------------------+-----------+-----------+-----------+-----------+-----------+-----------+------------+---------------+ +*Default - default on-line compiler +*Supported - supported off-line compiler + +Total platforms: 90 +Total permutations: 297 +``` + +Above list can be overwhelming so please do not hesitate to use switch ```-f``` to filter ```Platform``` column. +``` +$ python build.py -S -f ^K ++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+ +| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB | ++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+ +| K20D50M | Default | - | Supported | Supported | - | - | - | - | +| K22F | Default | - | Supported | Supported | - | - | - | - | +| K64F | Default | - | Supported | Supported | - | - | - | - | +| KL05Z | Supported | Default | Supported | Supported | - | - | - | - | +| KL25Z | Default | - | Supported | Supported | - | - | Supported | Supported | +| KL43Z | Default | - | Supported | - | - | - | - | - | +| KL46Z | Default | - | Supported | Supported | - | - | - | - | +| NRF51_DK | Default | - | Supported | Supported | - | - | - | - | +| NRF51_DK_OTA | Default | - | Supported | - | - | - | - | - | ++--------------+-----------+---------+-----------+-----------+--------+--------+------------+---------------+ +*Default - default on-line compiler +*Supported - supported off-line compiler + +Total platforms: 9 +Total permutations: 28 +``` +or just give platform name: +``` +$ python build.py -S -f LPC1768 ++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+ +| Platform | ARM | uARM | GCC_ARM | IAR | GCC_CR | GCC_CS | GCC_CW_EWL | GCC_CW_NEWLIB | ++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+ +| LPC1768 | Default | Supported | Supported | Supported | Supported | Supported | - | - | ++----------+---------+-----------+-----------+-----------+-----------+-----------+------------+---------------+ +*Default - default on-line compiler +*Supported - supported off-line compiler + +Total platforms: 1 +Total permutations: 6 +``` + +* You can be more verbose ```-v``` especially if you want to see each compilation / linking command build.py is executing: +``` +$ python build.py -t GCC_ARM -m LPC1768 -j 8 -v +Building library CMSIS (LPC1768, GCC_ARM) +Copy: LPC1768.ld +Compile: startup_LPC17xx.s +[DEBUG] Command: C:/Work/toolchains/gcc_arm_4_8/4_8_2013q4/bin\arm-none-eabi-gcc +-x assembler-with-cpp -c -Wall -Wextra -Wno-unused-parameter -Wno-missing-field-initializers +-fmessage-length=0 -fno-exceptions -fno-builtin -ffunction-sections -fdata-sections -MMD +-fno-delete-null-pointer-checks -fomit-frame-pointer -mcpu=cortex-m3 -mthumb -O2 +-DTARGET_LPC1768 -DTARGET_M3 -DTARGET_CORTEX_M -DTARGET_NXP -DTARGET_LPC176X +-DTARGET_MBED_LPC1768 -DTOOLCHAIN_GCC_ARM -DTOOLCHAIN_GCC -D__CORTEX_M3 -DARM_MATH_CM3 +-DMBED_BUILD_TIMESTAMP=1424903604.77 -D__MBED__=1 -IC:\Work\mbed\libraries\mbed\targets\cmsis +-IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP +-IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X -IC:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM +-o C:\Work\mbed\build\mbed\.temp\TARGET_LPC1768\TOOLCHAIN_GCC_ARM\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM\startup_LPC17xx.o +C:\Work\mbed\libraries\mbed\targets\cmsis\TARGET_NXP\TARGET_LPC176X\TOOLCHAIN_GCC_ARM\startup_LPC17xx.s +[DEBUG] Return: 0 +... +``` + +## CppUCheck analysis +[Cppcheck](http://cppcheck.sourceforge.net/) is a static analysis tool for C/C++ code. Unlike C/C++ compilers and many other analysis tools it does not detect syntax errors in the code. Cppcheck primarily detects the types of bugs that the compilers normally do not detect. The goal is to detect only real errors in the code (i.e. have zero false positives). + +Prerequisites: +* Please install ```CppCheck``` on your system before you want to use it with build scripts. +* You should also add Cppcheck to your system path. + +```build.py``` script supports switching between compilation and building and just static code analysis testing. You can use switch ```--cppcheck``` to perform CppCheck static code analysis. + +* When you are using --cppcheck switch all macros, toolchain dependencies etc. are preserved so you are sure you are checking exactly the same code you would compile for your application. + +* Cppcheck analysis can take up to few minutes on slower machines. + +* Usually you will use switches ```-t``` and ```-m``` to define toolchain and MCU (platform) respectively. You should do the same in case of CppCheck analysis. Please note that build script can also compile and build RTOS, Ethernet library etc. If you want to check those just use corresponding build script switches (e.g. ```-r```, ```-e```, ...). + +Example: +``` +$ python build.py -t uARM -m NUCLEO_F334R8 --cppcheck +``` + +# make.py script +```make.pt``` is a ```mbed/workspace_tools/``` script used to build tests (we call them sometimes 'programs') one by one manually. Script allows you to flash board with test and execute it. This is deprecated functionality and will not be described here. Instead please use ```singletest.py``` file to build mbed SDK, tests and run automation for test cases included in ```mbedmicro/mbed```. +Note: ```make.py``` script depends on existing already built mked SDK and library sources so you need to pre-build mbed SDK and for example RTOS library to link 'program' (test) with mebd SDK and RTOS library. To pre-build mbed SDK please use ```build.py``` script. + +Just for sake of example please see few ways to use ```make.py``` together with Freedom K64F board. + +* We need to build mbed SDK (in directory ```mbed/build/```: +``` +$ python build.py -t GCC_ARM -m K64F -j 8 +Building library CMSIS (K64F, GCC_ARM) +Building library MBED (K64F, GCC_ARM) + +Completed in: (0.59)s + +Build successes: + * GCC_ARM::K64F +``` +* We can print all 'programs' (test cases) ```make.py``` can build for us: +``` +$ python make.py +. +[ 0] MBED_A1: Basic +[ 1] MBED_A2: Semihost file system +[ 2] MBED_A3: C++ STL +[ 3] MBED_A4: I2C TMP102 +. +``` +For example 'program' under index ```2``` is ```MBED_A3``` test case we can build and flash onto K64F board. +* Building test with ```make.py``` by specifying test case name with ```-n``` option: +``` +$ python make.py -t GCC_ARM -m K64F -n MBED_A3 +Building project STL (K64F, GCC_ARM) +Compile: main.cpp +[Warning] main.cpp@76: In function 'int main()': deprecated conversion from string constant to 'char*' [-Wwrite-strings] +. +. +. +[Warning] main.cpp@76: In function 'int main()': deprecated conversion from string constant to 'char*' [-Wwrite-strings] +Compile: test_env.cpp +Link: stl +Elf2Bin: stl +Image: C:\Work\mbed\build\test\K64F\GCC_ARM\MBED_A3\stl.bin +``` +Because we previously have built mbed SDK we are now able to drive test case compilation and linking with mbed SDK and produce ```MBED_A3``` test case binary in build directory: +``` +C:\Work\mbed\build\test\K64F\GCC_ARM\MBED_A3\stl.bin +``` + +For more help type ```$ python make.py --help``` in your command line. + +# project.py script +```project.py``` script is used to export test cases ('programs') from test case portfolio to off-line IDE. This is a easy way to export test project to IDEs such as: +* codesourcery. +* coide. +* ds5_5. +* emblocks. +* gcc_arm. +* iar. +* kds. +* lpcxpresso. +* uvision. + +You can export project using command line. All you need to do is to specify mbed platform name (option ```-m```), your IDE (option ```-i```) and project name you want to export (option ```-n``` or (option ```-p```). + +In below example we export our project so we can work on it using GCC ARM cross-compiler. Building mechanism used to drive exported build will be ```Make```. +``` +$ python project.py -m K64F -n MBED_A3 -i gcc_arm +Copy: test_env.h +Copy: AnalogIn.h +Copy: AnalogOut.h +. +. +. +Copy: K64FN1M0xxx12.ld +Copy: main.cpp + +Successful exports: + * K64F::gcc_arm C:\Work\mbed\build\export\MBED_A3_gcc_arm_K64F.zip +``` +You can see exporter placed compressed project export in ```zip``` file in ```mbed/build/export/``` directory. + +Example export file ```MBED_A3_gcc_arm_K64F.zip``` structure: +``` +MBED_A3 +├───env +└───mbed + ├───api + ├───common + ├───hal + └───targets + ├───cmsis + │ └───TARGET_Freescale + │ └───TARGET_MCU_K64F + │ └───TOOLCHAIN_GCC_ARM + └───hal + └───TARGET_Freescale + └───TARGET_KPSDK_MCUS + ├───TARGET_KPSDK_CODE + │ ├───common + │ │ └───phyksz8081 + │ ├───drivers + │ │ ├───clock + │ │ ├───enet + │ │ │ └───src + │ │ ├───interrupt + │ │ └───pit + │ │ ├───common + │ │ └───src + │ ├───hal + │ │ ├───adc + │ │ ├───can + │ │ ├───dac + │ │ ├───dmamux + │ │ ├───dspi + │ │ ├───edma + │ │ ├───enet + │ │ ├───flextimer + │ │ ├───gpio + │ │ ├───i2c + │ │ ├───llwu + │ │ ├───lptmr + │ │ ├───lpuart + │ │ ├───mcg + │ │ ├───mpu + │ │ ├───osc + │ │ ├───pdb + │ │ ├───pit + │ │ ├───pmc + │ │ ├───port + │ │ ├───rcm + │ │ ├───rtc + │ │ ├───sai + │ │ ├───sdhc + │ │ ├───sim + │ │ ├───smc + │ │ ├───uart + │ │ └───wdog + │ └───utilities + │ └───src + └───TARGET_MCU_K64F + ├───device + │ ├───device + │ │ └───MK64F12 + │ └───MK64F12 + ├───MK64F12 + └───TARGET_FRDM +``` + +After unpacking exporter ```zip``` file we can go to directory and see files inside MBED_A3 directory: +``` +$ ls +GettingStarted.htm Makefile env main.cpp mbed +``` +Exporter generated for us ```Makefile``` so now we can build our software: +``` +$ make -j 8 +. +. +. + text data bss dec hex filename + 29336 184 336 29856 74a0 MBED_A3.elf +``` + +We can see root directory of exporter project is now populated with binary files: +* MBED_A3.bin. +* MBED_A3.elf . +* MBED_A3.hex. +You have also map file ```MBED_A3.map``` for your disposal. +``` +$ ls +GettingStarted.htm MBED_A3.bin MBED_A3.elf MBED_A3.hex MBED_A3.map Makefile env main.cpp main.d main.o mbed +``` + diff --git a/docs/COMMITTERS.md b/docs/COMMITTERS.md new file mode 100644 index 00000000000..ecb092dad8a --- /dev/null +++ b/docs/COMMITTERS.md @@ -0,0 +1,269 @@ +# Committing changes to mbedmicro/mbed +* Our current branching model is very simple. We are using ```master``` branch to merge all pull requests. +* Based on stable ```SHA``` version of ```master``` branch we decide to release and att he same time ```tag``` our build release. +* Our current release versioning follows simple integer version: ```94```, ```95```, ```96``` etc. + +# Committer Guide + +## How to decide what release(s) should be patched +This section provides a guide to help a committer decide the specific base branch that a change set should be merged into. + +Currently our default branch is ```master``` branch. All pull requests should be created against ```master``` branch. +mbed SDK is released currently on master branch under certain tag name (see [Git tagging basics]( http://git-scm.com/book/en/v2/Git-Basics-Tagging)). You can see mbed SDK tags and switch between them to for example go back to previous mbed SDK release. +``` +$ git tag +``` + +Please note: mebd SDK ```master``` branch's ```HEAD``` is our latest code and may not be as stable as you expect. We are putting our best effort to run regression testing (in-house) against pull requests and latest code. +Each commit to ```master``` will trigger [GitHub's Travis Continuous Integration](https://travis-ci.org/mbedmicro/mbed/builds). + +### Pull request +Please send pull requests with changes which are: +* Complete (your code will compile and perform as expected). +* Tested on hardware. + * You can use included mbed SDK test suite to perform testing. See TESTING.md. + * If your change, feature do not have a test case included please add one (or more) to cover new functionality. + * If you can't test your functionality describe why. +* Documented source code: + * New, modified functions have descriptive comments. + * You follow coding rules and styles provided by mbed SDK project. +* Documented pull request description: + * Description of changes is added - explain your change / enhancement. + * References to existing issues, other pull requests or forum discussions are included. + * Test results are added. + +After you send us your pull request our Gate Keeper will change the state of pull request to: + ``` enhancement``` or ```bug``` when pull request creates new improvement or fixed issue. +Than we will set for you labels: + ```review``` to let you know your pull request is under review and you can expect review related comments from us. + ```in progress``` when you pull request requires some additional change which will for now block this pull request from merging. +At the end we will remove ```review``` label and merge your change if everything goes well. + +## C++ coding rules & coding guidelines +### Rules +* The mbed SDK code follows K&R style (Reference: [K&R style](http://en.wikipedia.org/wiki/Indent_style#K.26R_style)) with at least 2 exceptions which can be found in the list below the code snippet: + +```c++ +static const PinMap PinMap_ADC[] = { + {PTC2, ADC0_SE4b, 0}, + {NC , NC , 0} +}; + +uint32_t adc_function(analogin_t *obj, uint32_t options) +{ + uint32_t instance = obj->adc >> ADC_INSTANCE_SHIFT; + switch (options) { + case 1: + timeout = 6; + break; + default: + timeout = 10; + break; + } + + while (!adc_hal_is_conversion_completed(instance, 0)) { + if (timeout == 0) { + break; + } else { + timeout--; + } + } + + if (obj->adc == ADC_CHANNEL0) { + adc_measure_channel(instance); + adc_stop_channel(instance); + } else { + error("channel not available"); + } + +#if DEBUG + for (uint32_t i = 0; i < 10; i++) { + printf("Loop : %d", i); + } +#endif + return adc_hal_get_conversion_value(instance, 0); +} +``` +* Indentation - 4 spaces. Please do not use tabs! +* Braces - K&R, except for functions where the opening brace is on the new line. +* 1 TBS - use braces for statements ```if```, ```else```, ```while```, ```for``` (exception from K&R) Reference: [1TBS](http://en.wikipedia.org/wiki/Indent_style#Variant:_1TBS)). +* One line per statement. +* Preprocessor macro starts at the beginning of a new line, the code inside is indented accordingly the code above it. +* Cases within switch are indented (exception from K&R). +* Space after statements if, while, for, switch, same applies to binary and ternary operators. +* Each line has preferably at most 120 characters. +* For pointers, ```*``` is adjacent to a name (analogin_t *obj). +* Don't leave trailing spaces at the end of lines. +* Empty lines should have no trailing spaces. +* Unix line endings are default option for files. +* Use capital letters for macros. +* A file should have an empty line at the end. +and: +* We are not using C++11 yet so do not write code compliant to this standard. +* We are not using libraries like ```BOOST``` so please so not include any ```BOOST``` headers to your code. +* C++ & templates: please take under consideration templates are not fully supported by cross-compilers. You may have difficulties compiling template code few cross-compilers so make sure your template code compilers for more than one compiler. + +### Naming conventions +Classes: +* Begins with a capital letter, and each word in it begins also with a capital letter (```AnalogIn```, ```BusInOut```). +* Methods contain small letters, distinct words separated by underscore. +* Private members starts with an underscore. + +User defined types (typedef): +* Structures - suffix ```_t``` - to denote it is user defined type +* Enumeration - the type name and values name - same naming convention as classes (e.g ```MyNewEnum```) + +Functions: +* Contain lower case letters (as methods within classes) +* Distinct words separated by underscore (```wait_ms```, ```read_u16```) +* Please make sure that in your module all functions have unique prefix so when your module is compiled with other modules function names (and e.g. extern global variable names) are not in naming conflict. + +Example code look&feel: +```c++ +#define ADC_INSTANCE_SHIFT 8 + +class AnalogIn { +public: + /** Create an AnalogIn, connected to the specified pin + * + * @param pin AnalogIn pin to connect to + * @param name (optional) A string to identify the object + */ + AnalogIn(PinName pin) { + analogin_init(&_adc, pin); + } + + /** Read the input voltage, represented as a float in the range [0.0, 1.0] + * + * @returns + * A floating-point value representing the current input voltage, measured as a percentage + */ + uint32_t read() { + return analogin_read(&_adc, operation); + } + +protected: + analogin_t _adc; +}; + +typedef enum { + ADC0_SE0 = (0 << ADC_INSTANCE_SHIFT) | 0, +} ADCName; + +struct analogin_s { + ADCName adc; +}; + +typedef struct analogin_s analogin_t; +``` +### Doxygen documentation +All functions / methods should contain a documentation using doxygen javadoc in a header file. More information regarding writing API Documentation, follow [this](https://mbed.org/handbook/API-Documentation) link. + +Example of well documentet code: +```c++ +#ifndef ADC_H +#define ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** ADC Measurement method + * + * @param obj Pointer to the analogin object. + * @param options Options to be enabled by ADC peripheral. + * + * @returns + * Measurement value on defined ADC channel. + */ +uint32_t adc_function(analogin_t *obj, uint32_t options) + +#ifdef __cplusplus +} +#endif + +#endif +``` +### C/C++ Source code indenter +In Mbed project you can use AStyle (Reference: [Artistic Style](http://astyle.sourceforge.net/)) source code indenter to help you auto format your source code. It will for sure not correct all your coding styles but for sure will eliminate most of them. You can download AStyle from this location. + +Official Mbed SDK styles include below AStyle styles (defined by command line switched): +``` +--style=kr --indent=spaces=4 --indent-switches +``` +To format your file you can execute below command. Just replace ```$(FULL_CURRENT_PATH)``` with path to your source file. +``` +$ astyle.exe --style=kr --indent=spaces=4 --indent-switches $(FULL_CURRENT_PATH) +``` + +## Python coding rules & coding guidelines +Some of our tools in workspace_tools are written in ```Python 2.7```. In case of developing tools for python we prefer to keep similar code styles across all Python source code. Please note that not all rules must be enforced. For example we do not limit you to 80 characters per line, just be sure your code can fit to widescreen display. + +Please stay compatible with ```Python 2.7``` but nothing stops you to write your code so in the future it will by Python 3 friendly. + +Please check our Python source code (especially ```test_api.py``` and ```singletest.py```) to get notion of how your new code should look like). We know our code is not perfect but please try to fit the same coding style to existing code so source looks consistent and is not series of different flavors. + +Some general guidelines: +* Use Python idioms, please refer to one of many on-line guidelines how to write Pythonic code: [Code Like a Pythonista: Idiomatic Python](http://python.net/~goodger/projects/pycon/2007/idiomatic/handout.html). +* Please do not use TABs. Please use 4 spaces instead for indentations. +* Please put space character between operators, after comma etc. +* Please document your code, write comments and ```doc``` sections for each function or class you implement. + +### Static Code Analizers for Python +If you are old-school developer for sure you remember tools like lint. "lint was the name originally given to a particular program that flagged some suspicious and non-portable constructs (likely to be bugs) in C language source code." Now lint-like programs are used to check similar code issues for multiple languages, also for Python. Please do use them if you want to commit new code to workspace_tools and other mbed SDK Python tooling. + +Below is the list Python lint tools you may want to use: + +* [pyflakes](https://pypi.python.org/pypi/pyflakes) - Please scan your code with pyflakes and remove all issues reported by it. If you are unsure if something should be modified or not you can skip lint report related fix and report this issue as possible additional commit in your pull request description. + +* [pylint](http://www.pylint.org/) - Please scan your code with pylint and check if there are any issues which can be resolved and are obvious "to fix" bugs. For example you may forgot to add 'self' as first parameter in class method parameter list or you are calling unknown functions / functions from not imported modules. + +* [pychecker](http://pychecker.sourceforge.net/) - optional, but more the merrier ;) + +Example Python look&feel: +```python +class HostRegistry: + """ Class stores registry with host tests and objects representing them + """ + HOST_TESTS = {} # host_test_name -> host_test_ojbect + + def register_host_test(self, ht_name, ht_object): + """ Registers (removes) host test by name from HOST_TESTS registry + if host test is not already registered (check by name). + """ + if ht_name not in self.HOST_TESTS: + self.HOST_TESTS[ht_name] = ht_object + + def unregister_host_test(self): + """ Unregisters (removes) host test by name from HOST_TESTS registry. + """ + if ht_name in HOST_TESTS: + self.HOST_TESTS[ht_name] = None + + def get_host_test(self, ht_name): + """ Returns HOST_TEST if host name is valid. + In case no host test is available return None + """ + return self.HOST_TESTS[ht_name] if ht_name in self.HOST_TESTS else None + + def is_host_test(self, ht_name): + """ Function returns True if host name is valid (is in HOST_TESTS) + """ + return ht_name in self.HOST_TESTS +``` + +## Testing +Please refer to TESTING.md document for detais regarding mbed SDK test suite and build scripts included in ```mbed/workspace_tools/```. + +## Before pull request checklist +* Your pull request description section contains: + * Rationale tell us why you submitted this pull request. This is your change to write us summary of your change. + * Description describe changes youve made and tell us which new features / functionalities were implemented. + * Manual / Cookbook / Handbook you can put here manual, cookbook or handbook related to your change / enhancement. Your documentation can stay with pull request. + * Test results (if applicable). +* Make sure you followed project's coding rules and styles. +* No dependencies are created to external C/C++ libraries which are not included already in our repository. +* Please make sure that in your module all functions have unique prefix (no name space collisions). +* You reused existing functionality, please do not add or rewrite existing code. E.g. use mbeds ```FunctionPointer``` if possible to store your function pointers. Do not write another wrapper for it. We already got one. If some functionality is missing, just add it! Extend our APIs wisely! +* Were you consistent? Please continue using style / code formatting, variables naming etc. in file they are modifying. +* Your code compiles and links. Also doesnt generate additional compilation warnings. diff --git a/docs/TESTING.md b/docs/TESTING.md new file mode 100644 index 00000000000..9d17e4d90d5 --- /dev/null +++ b/docs/TESTING.md @@ -0,0 +1,877 @@ +# Mbed SDK automated test suite +## Introduction + +Test suit allows users to run locally on their machines Mbed SDK’s tests included in Mbed SDK repository. It also allows users to create their own tests and for example add new tests to test set as they progress with their project. If test is generic enough it could be included into official Mbed SDK test pool just do it via normal pull request! + +Each test is supervised by python script called “host test” which will at least Test suite is using build script API to compile and build test source together with required by test libraries like CMSIS, Mbed, Ethernet, USB etc. + +## What is host test? +Test suite supports test supervisor concept. This concept is realized by separate Python script called ```host test```. Host tests can be found in ```mbed/workspace_tools/host_tests/``` directory. Note: In newer mbed versions (mbed OS) host tests will be separate library. + +Host test script is executed in parallel with test runner to monitor test execution. Basic host test just monitors device's default serial port for test results returned by test runner. Simple tests will print test result on serial port. In other cases host tests can for example judge by test results returned by test runner is test passed or failed. It all depends on test itself. + +In some cases host test can be TCP server echoing packets from test runner and judging packet loss. In other cases it can just check if values returned from accelerometer are actually valid (sane). + +## Test suite core: singletest.py script + +```singletest.py``` script located in ```mbed/workspace_tools/``` is a test suite script which allows users to compile, build tests and test runners (also supports CppUTest unit test library). Script also is responsible for test execution on devices selected by configuration files. + +### Parameters of singletest.py + +Test execution script ```singletest.py``` is a fairly powerful tool to run tests for mbed SDK platform. It is flexible and allows users to configure test execution process and define which mbed platforms will be tested. + +By specifying external configuration files (in JSON format) you can gain flexibility and prepare many different test scenarios. Just pass configuration file names to your script and run it. + +#### MUTs Specification +You can easily configure your MUTs (Mbed Under Test) by creating configuration file with MUTs description. +Note: This configuration file must be in [JSON format](http://www.w3schools.com/json/). +Note: Unfortunately JSON format is not allowing you to have comments inside JSON code. + +Let’s see some example and let's try to configure small "test farm" with three devices connected to your host computer. In this example no peripherals (like SD card or EEPROM) are connected to our Mbed boards. We will use three platforms in this example: +* [NXP LPC1768](https://mbed.org/platforms/mbed-LPC1768) board. +* \[Freescale KL25Z](https://mbed.org/platforms/KL25Z) board and +* [STMicro Nucleo F103RB](https://mbed.org/platforms/ST-Nucleo-F103RB) board. +After connecting boards to our host machine (PC) we can check which serial ports and disks they occupy. For our example let's assume that: +* ```LPC1768``` serial port is on ```COM4``` and disk drive is ```J:```. +* ```KL25Z``` serial port is on ```COM39``` and disk drive is ```E:```. +* ```NUCLEO_F103RB``` serial port is on ```COM11``` and disk drive is ```I:```. +If you are working under Linux your port and disk could look like /dev/ttyACM5 and /media/usb5. + +This information is needed to create ```muts_all.json``` configuration file. You can create in in ```mbed/workspace_tools/``` directory: +``` +$ touch muts_all.json +``` + +Its name will be passed to ```singletest.py``` script after ```-M``` (MUTs specification) switch. Let’s see how this file's content would look like in our example below: +```json +{ + "1" : {"mcu": "LPC1768", + "port":"COM4", + "disk":"J:\\", + "peripherals": [] + }, + + "2" : {"mcu": "KL25Z", + "port":"COM39", + "disk":"E:\\", + "peripherals": [] + }, + + "3" : {"mcu": "NUCLEO_F103RB", + "port":"COM11", + "disk":"I:\\", + "peripherals": [] + } +} +``` + +Note: We will leave field ```peripherals``` empty for the sake of this example. We will explain it later. All you need to do now is to properly fill fields ```mcu```, ```port``` and ```disk```. + +Note: Please make sure files muts_all.json and test_spec.json are in workspace_tools/ directory. We will assume in this example they are. +Where to find ```mcu``` names? You can use option ```-S``` of ```build.py``` script (in ```mbed/workspace_tools/``` directory) to check all supported off-line MCUs names. + +Note: If you update mbed device firmware or even disconnect / reconnect mbed device you may find that serial port / disk configuration changed. You need to update configuration file accordingly or you will face connection problems and obviously tests will not run. + +#### Peripherals testing +When using MUTs configuration file (switch ```-M```) you can define in MUTs JSON file peripherals connected to your device: +```json +{ + "1" : {"mcu" : "KL25Z", + "port" : "COM39", + "disk" : "E:\\", + "peripherals" : ["SD", "24LC256"]} +} +``` +You can force test suite to run only common tests (switch ```-C```) or only peripheral tests (switch ```-P```). +``` +$ python singletest.py -i test_spec.json -M muts_all.json -C +``` +will not include tests for SD card and EEPROM 24LC256. +``` +$ python singletest.py -i test_spec.json -M muts_all.json -P +``` +will only run tests bind to SD card and EEPROM 24LC256. + +Note: option ```-P``` is useful for example in cases when you have same platform and different shields you want to test. No need to test common part all the time (timers, RTC, RTOS etc.). You can force to test peripherals only on some devices and for example only common tests on other devices. + +#### Additional MUTs configuration file settings +You can add extra information to each MUT configuration. In particular you can specify which flashing (binary copy method) should be used, how to reset target and for example set reset timeout (used to delay test execution just after reset). + +muts_all.json: +```json +{ + "1" : {"mcu" : "LPC1768", + "port" : "COM77", + "disk" : "G:\\", + "peripherals" : ["TMP102", "digital_loop", "port_loop", "analog_loop", "SD"]}, + + "2" : {"mcu" : "KL25Z", + "port" : "COM89", + "disk" : "F:\\", + "peripherals" : ["SD", "24LC256", "KL25Z"], + "copy_method" : "copy", + "reset_type" : "default", + "reset_tout" : "2"}, + + "3" : {"mcu" : "LPC11U24", + "port" : "COM76", + "disk" : "E:\\", + "peripherals" : []} +} +``` +Please note that for MUT no. 2 few extra parameters were defined: ```copy_method```, ```reset_type``` and ```reset_tout```. Using this extra options you can tell test suite more about MUT you are using. This will allow you to be more flexible in terms of how you configure and use your MUTs. + +* ```copy_method``` - STRING - tells test suite which binary copy method should be used. +You may notice that ```singletest.py``` command line help contains description about: + * Option ```-c``` (in MUTs file called ```copy_method```) with available copy methods supported by test suite plugin system. + * Option ```-r``` (in MUTs file called reset_type) with available reset methods supported by test suite plugin system. +* ```reset_type``` - STRING - some boards may require special reset handling, for example vendor specific command must be executed to reset device. +* ```reset_tout``` - INTEGER - extra timeout just after device is reseted. May be used to wait for few seconds so device may finish booting, flashing data internally etc. + +Part of help listing for singletest.py: +``` + -c COPY_METHOD, --copy-method=COPY_METHOD + Select binary copy (flash) method. Default is Python's + shutil.copy() method. Plugin support: copy, cp, + default, eACommander, eACommander-usb, xcopy + -r MUT_RESET_TYPE, --reset-type=MUT_RESET_TYPE + Extra reset method used to reset MUT by host test + script. Plugin support: default, eACommander, + eACommander-usb +``` + +---- + +Now we've already defined how our devices are connected to our host PC. We can continue and define which of this MUTs will be tested and which compilers we will use to compile and build Mbed SDK and tests. To do so we need to create test specification file (let's call it ```test_spec.json```) and put inside our configuration file information about which MUTs we actually want to test. We will pass this file's name to ```singletest.py``` script using ```-i``` switch. + +Below we can see how sample ```test_spec.json``` file content could look like. (I've included all possible toolchains, we will change it in a moment): +```json +{ + "targets": { + "LPC1768" : ["ARM", "uARM", "GCC_ARM", "GCC_CS", "GCC_CR", "IAR"], + "KL25Z" : ["ARM", "GCC_ARM"], + "NUCLEO_F103RB" : ["ARM", "uARM"] + } +} +``` +Above example configuration will force tests for LPC1768, KL25Z, NUCLEO_F103RB platforms and: + +* Compilers: ```ARM```, ```uARM```, ```GCC_ARM```, ```GCC_CS```, ```GCC_CR``` and ```IAR``` will be used to compile tests for NXP's ```LPC1768```. +* Compilers: ```ARM``` and ```GCC_ARM``` will be used for Freescales' ```KL25Z``` platform. +* Compilers: ```ARM``` and ```uARM``` will be used for STMicro's ```NUCLEO_F103RB``` platform. + +For our example purposes let's assume we only have Keil ARM compiler, so let's change configuration in ```test_spec.json``` file and reduce number of compiler to those we actually have: +```json +{ + "targets": { + "LPC1768" : ["ARM", "uARM"], + "KL25Z" : ["ARM"], + "NUCLEO_F103RB" : ["ARM", "uARM"] + } +} +``` +#### Run your tests + +After you configure all your MUTs and compilers you are ready to run tests. Make sure your devices are connected and your configuration files reflect your current configuration (serial ports, devices). Go to workspace_tools directory in your mbed location. +``` +$ cd workspace_tools/ +``` +and execute test suite script. +``` +$ python singletest.py -i test_spec.json -M muts_all.json +``` +To check your configuration before test execution please use ```--config``` switch: +``` +$ python singletest.py -i test_spec.json -M muts_all.json --config +MUTs configuration in m.json: ++-------+-------------+---------------+------+-------+ +| index | peripherals | mcu | disk | port | ++-------+-------------+---------------+------+-------+ +| 1 | | LPC1768 | J:\ | COM4 | +| 3 | | NUCLEO_F103RB | I:\ | COM11 | +| 2 | | KL25Z | E:\ | COM39 | ++-------+-------------+---------------+------+-------+ + +Test specification in t.json: ++---------------+-----+------+ +| mcu | ARM | uARM | ++---------------+-----+------+ +| NUCLEO_F103RB | Yes | Yes | +| KL25Z | Yes | - | +| LPC1768 | Yes | Yes | ++---------------+-----+------+ +``` +It should help you localize basic problems with configuration files and toolchain configuration. +Note: Configurations with issues will be marked with ```*``` sign. + +Having multiple configuration files allows you to manage your test scenarios in more flexible manner. You can: + +* Set up all platforms and toolchains used during testing. +* Define (using script's ```-n``` switch) which tests you want to run during testing. +* Just run regression (all tests). Regression is default setting for test script. + +You can also force ```singletest.py``` script to: +* Run only peripherals' tests (switch ```-P```) or +* Just skip peripherals' tests (switch ```-C```). +* Build mbed SDK, libraries and corresponding tests with multiple cores, just use ```-j X``` option where ```X``` is number of cores you want to use for compilation. +``` +$ python singletest.py -i test_spec.json -M muts_all.json -j 8 +``` +* Print test cases console output using ```-V``` option. +* Only build mbed SDK, tests and dependant libraries with switch ```-O```: +``` +$ python singletest.py -i test_spec.json -M muts_all.json -j 8 -O +``` +* Execute each test case multiple times with ```--global-loops X``` option, where ```X``` number of repeats. Additionally use option ```-W``` to continue repeating test cases execution only if they continue to fail. +``` +$ python singletest.py -i test_spec.json -M muts_all.json --global-loops 3 -W +``` +* Option ```--loops``` can be used to overwrite global loop count and redefine loop count for particular tests. Define test loops as ```TEST_ID=X``` where ```X``` is integer and separate loops count definitions by comma if necessary. E.g. ```TEST_1=5,TEST_2=20,TEST_3=2```. +``` +$ python singletest.py -i test_spec.json -M muts_all.json RTOS_1=10,RTOS_2=5 +``` +This will execute test ```RTOS_1``` ten (10) times and test ```RTOS_2``` five (5) times. +* Force non default copy method. Note that mbed platforms can be flashed with just binary drag&drop. We simply copy file onto mbed's disk and interface chip flashes target MCU with given binary. Force non standard (Python specific) copy method by using option ```-c COPY_METHOD``` where ```COPY_METHOD``` can be shell, command line copy command like: ```cp```, ```copy````, ```xcopy``` etc. Make sure those commands are available from command line! +``` +$ python singletest.py -i test_spec.json -M muts_all.json -c cp +``` +* Run only selected tests. You can select which tests should be executed when you run test suite. Use ```-n``` switch to define tests by their ids you want to execute. Use comma to separate test ids: +``` +$ python singletest.py -i test_spec.json -M muts_all.json -n RTOS_1,RTOS_2,RTOS_3,MBED_10,MBED_16,MBED_11 +``` +* Set common output binary name for all tests. In some cases you would like to have the same name for all tests. You can use switch ```--firmware-name``` to specify (without extension) build script output binary name. +In below example we would like to have all test binaries called ```firmware.bin`` (or with other extension like .elf, .hex depending on target accepted format). +``` +$ python singletest.py -i test_spec.json -M muts_all.json --firmware-name firmware +``` +* Where to find test list? Tests are defined in file ```tests.py``` in ```mbed/workspace_tools/``` directory. ```singletest.py``` uses test metadata in ```tests.py``` to resolve libraries dependencies and build tests for proper platforms and peripherals. Option ```-R``` can be used to get test names and direct path and test configuration. +``` +$ python singletest.py -R ++-------------+-----------+---------------------------------------+--------------+-------------------+----------+--------------------------------------------------------+ +| id | automated | description | peripherals | host_test | duration | source_dir | ++-------------+-----------+---------------------------------------+--------------+-------------------+----------+--------------------------------------------------------+ +| MBED_1 | False | I2C SRF08 | SRF08 | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\i2c_SRF08 | +| MBED_10 | True | Hello World | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\hello | +| MBED_11 | True | Ticker Int | - | host_test | 20 | C:\Work\mbed\libraries\tests\mbed\ticker | +| MBED_12 | True | C++ | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\cpp | +| MBED_13 | False | Heap & Stack | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\heap_and_stack | +| MBED_14 | False | Serial Interrupt | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\serial_interrupt | +| MBED_15 | False | RPC | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\rpc | +| MBED_16 | True | RTC | - | host_test | 15 | C:\Work\mbed\libraries\tests\mbed\rtc | +| MBED_17 | False | Serial Interrupt 2 | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\serial_interrupt_2 | +| MBED_18 | False | Local FS Directory | - | host_test | 10 | C:\Work\mbed\libraries\tests\mbed\dir | +... +``` +Note: you can filter tests by ```id``` column, just use ```-f``` option and give test name or regular expression: +``` +$ python singletest.py -R -f RTOS ++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+ +| id | automated | description | peripherals | host_test | duration | source_dir | ++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+ +| CMSIS_RTOS_1 | False | Basic | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\basic | +| CMSIS_RTOS_2 | False | Mutex | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\mutex | +| CMSIS_RTOS_3 | False | Semaphore | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\semaphore | +| CMSIS_RTOS_4 | False | Signals | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\signals | +| CMSIS_RTOS_5 | False | Queue | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\queue | +| CMSIS_RTOS_6 | False | Mail | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\cmsis\mail | +| CMSIS_RTOS_7 | False | Timer | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\timer | +| CMSIS_RTOS_8 | False | ISR | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\cmsis\isr | +| RTOS_1 | True | Basic thread | - | host_test | 15 | C:\Work\mbed\libraries\tests\rtos\mbed\basic | +| RTOS_2 | True | Mutex resource lock | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\mbed\mutex | +| RTOS_3 | True | Semaphore resource lock | - | host_test | 20 | C:\Work\mbed\libraries\tests\rtos\mbed\semaphore | +| RTOS_4 | True | Signals messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\signals | +| RTOS_5 | True | Queue messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\queue | +| RTOS_6 | True | Mail messaging | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\mail | +| RTOS_7 | True | Timer | - | host_test | 15 | C:\Work\mbed\libraries\tests\rtos\mbed\timer | +| RTOS_8 | True | ISR (Queue) | - | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\isr | +| RTOS_9 | True | SD File write-read | SD | host_test | 10 | C:\Work\mbed\libraries\tests\rtos\mbed\file | ++--------------+-----------+-------------------------+-------------+-----------+----------+---------------------------------------------------+ +``` + +* Shuffle your tests. We strongly encourage you to shuffle your test order each time you execute test suite script. +Rationale: It is probable that tests executed in one particular order will pass and in other will fail. To shuffle your tests’ order please use option ```–u``` (or ```--shuffle```): +``` +$ python singletest.py -i test_spec.json -M muts_all.json --shuffle +``` +Above command with force test script to randomly generate shuffle seed and shuffle test order execution. Note: Shuffle seed is float in ```[0.0, 1.0)```. + +You can always recreate particular test order by forcing shuffle (```-u``` or ```--shuffle```} switch) and passing shuffle seed back to test suite using ```--shuffle-seed``` switch: +``` +$ python singletest.py -i test_spec.json -M muts_all.json --shuffle --shuffle-seed 0.4041028336 +``` +Note: You can also supply your own randomly generated shuffle seed to drive particular test execution order scenarios. Just make sure shuffle seed is float in ```[0.0, 1.0)```. +You can find test shuffle seed in test summary: +``` +... +| OK | LPC1768 | ARM | MBED_A9 | Serial Echo at 115200 | 2.84 | 10 | 1/1 | ++--------+---------+-----------+-----------+-----------------------------+--------------------+---------------+-------+ +Result: 1 FAIL / 22 OK +Shuffle Seed: 0.4041028336 + +Completed in 234.85 sec +``` + +### Exmple of device configuration (one device connected to host computer) + +This example will show you how to configure single device, run general tests or only peripheral tests. We will also show some real test result examples. + +1. We will test only one board STMIcro Nucleo ```F334R8``` board connected to our PC (port ```COM46``` and disk is ```E:```). +2. We will also connect EEPROM ```24LC256``` to SDA, SCL pins of our Nucleo board and define 24LC256 peripheral to make sure our test suite will run all available tests for ```24LC256```. + +Let's configure our one MUT and set uARM as the only compiler we will use to compiler Mbed SDK and tests. +We also need to create two configuration files ```muts_all.json``` and ```test_spec.json``` to pass our small testbed configuration to test script. + +muts_all.json: +```json +{ + "1" : { + "mcu": "NUCLEO_F334R8", + "port":"COM46", + "disk":"E:\\", + "peripherals": ["24LC256"] + } +} +``` +Note: By defining ```"peripherals": ["24LC256"]``` we are passing to test suite information that this particular board has EEPROM 24LC256 connected to our board. + +test_spec.json: +```json +{ + "targets": { + "NUCLEO_F334R8" : ["uARM"] + } +} +``` +Note: +* Please make sure device is connected before we will start running tests. +* Please make sure files ```muts_all.json``` and ```test_spec.json``` are in ```mbed/workspace_tools/``` directory. +Now you can call test suite and execute tests: +``` +$ python singletest.py -i test_spec.json -M muts_all.json +... +Test summary: ++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+ +| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) | ++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+ +| OK | NUCLEO_F334R8 | uARM | MBED_A25 | I2C EEPROM line read/write test | 12.41 | 15 | +| OK | NUCLEO_F334R8 | uARM | MBED_A1 | Basic | 3.42 | 10 | +| OK | NUCLEO_F334R8 | uARM | EXAMPLE_1 | /dev/null | 3.42 | 10 | +| OK | NUCLEO_F334R8 | uARM | MBED_24 | Timeout Int us | 11.47 | 15 | +| OK | NUCLEO_F334R8 | uARM | MBED_25 | Time us | 11.43 | 15 | +| OK | NUCLEO_F334R8 | uARM | MBED_26 | Integer constant division | 3.37 | 10 | +| OK | NUCLEO_F334R8 | uARM | MBED_23 | Ticker Int us | 12.43 | 15 | +| OK | NUCLEO_F334R8 | uARM | MBED_A19 | I2C EEPROM read/write test | 11.42 | 15 | +| OK | NUCLEO_F334R8 | uARM | MBED_11 | Ticker Int | 12.43 | 20 | +| OK | NUCLEO_F334R8 | uARM | MBED_10 | Hello World | 2.42 | 10 | +| OK | NUCLEO_F334R8 | uARM | MBED_12 | C++ | 3.42 | 10 | +| OK | NUCLEO_F334R8 | uARM | MBED_16 | RTC | 4.76 | 15 | +| UNDEF | NUCLEO_F334R8 | uARM | MBED_2 | stdio | 20.42 | 20 | +| UNDEF | NUCLEO_F334R8 | uARM | MBED_A9 | Serial Echo at 115200 | 10.37 | 10 | ++--------+---------------+-----------+-----------+---------------------------------+--------------------+---------------+ +Result: 2 UNDEF / 12 OK + +Completed in 160 sec +``` + +If we want to get additional test summary with results in separate columns please use option ```-t```. +``` +$ python singletest.py -i test_spec.json -M muts_all.json -t +... +Test summary: ++---------------+-----------+---------------------------------+-------+ +| Target | Test ID | Test Description | uARM | ++---------------+-----------+---------------------------------+-------+ +| NUCLEO_F334R8 | EXAMPLE_1 | /dev/null | OK | +| NUCLEO_F334R8 | MBED_10 | Hello World | OK | +| NUCLEO_F334R8 | MBED_11 | Ticker Int | OK | +| NUCLEO_F334R8 | MBED_12 | C++ | OK | +| NUCLEO_F334R8 | MBED_16 | RTC | OK | +| NUCLEO_F334R8 | MBED_2 | stdio | UNDEF | +| NUCLEO_F334R8 | MBED_23 | Ticker Int us | OK | +| NUCLEO_F334R8 | MBED_24 | Timeout Int us | OK | +| NUCLEO_F334R8 | MBED_25 | Time us | OK | +| NUCLEO_F334R8 | MBED_26 | Integer constant division | OK | +| NUCLEO_F334R8 | MBED_A1 | Basic | OK | +| NUCLEO_F334R8 | MBED_A19 | I2C EEPROM read/write test | OK | +| NUCLEO_F334R8 | MBED_A25 | I2C EEPROM line read/write test | OK | +| NUCLEO_F334R8 | MBED_A9 | Serial Echo at 115200 | UNDEF | ++---------------+-----------+---------------------------------+-------+ +``` +---- +Please do not forget you can combine few options together to get result you want. For example you want to repeat few tests multiple number of times, shuffle test ids execution order and select only tests which are critical for you at this point. You can do it using switch -n, --global-loops with --loops and --shuffle: + +Execute above command to: + +* Run only tests: ```RTOS_1```, ```RTOS_2```, ```RTOS_3```, ```MBED_10```, ```MBED_16```, ```MBED_11```. +* Shuffle test execution order. Note tests in loops will not be shuffled. +* Set global loop count to 3 - each test will repeated 3 times. +* Overwrite global loop count (set above to 3) and: + * Force to loop test RTOS_1 to execute 3 times. + * Force to loop test RTOS_2 to execute 4 times. + * Force to loop test RTOS_3 to execute 5 times. + * Force to loop test MBED_11 to execute 5 times. + +``` +$ python singletest.py -i test_spec.json -M muts_all.json -n RTOS_1,RTOS_2,RTOS_3,MBED_10,MBED_16,MBED_11 --shuffle --global-loops 3 --loops RTOS_1=3,RTOS_2=4,RTOS_3=5,MBED_11=5 +``` + +# CppUTest unit test library support +## CppUTest in Mbed SDK testing introduction +[CppUTest](http://cpputest.github.io/) is a C / C++ based unit xUnit test framework for unit testing and for test-driving your code. It is written in C++ but is used in C and C++ projects and frequently used in embedded systems but it works for any C / C++ project. + +Mbed SDK test suite supports writing tests using CppUTest. All you need to do it to provide CppUTest sources and includes with Mbed SDK port. This is already done for you so all you need to do it to get proper sources in your project directory. +CppUTest’s core design principles are: +* Simple in design and simple in use. +* Portable to old and new platforms. +* Build with Test-driven Development in mind. + +## From where you can get more help about CppUTest library and unit testing +• You can read [CppUTest manual](http://cpputest.github.io/manual.html) +* [CppUTest forum](https://groups.google.com/forum/?fromgroups#!forum/cpputest) +* [CppUTest on GitHub](https://github.com/cpputest/cpputest) +* Finally, if you think unit testing is new concept for you, you can have a grasp of it on Wikipedia pages about [unit testing](http://en.wikipedia.org/wiki/Unit_testing) and continue from there. + +## How to add CppUTest to your current Mbed SDK installation + +### Do I need CppUTest port for Mbed SDK? +Yes, you do. If you want to use CppUTest with Mbed SDK you need to have CppUTest version with ARMCC compiler (only ARM flavor for now) port and Mbed SDK console port (if you want to have output on serial port). All is already prepared by Mbed engineers and you can get it for example here: http://mbed.org/users/rgrover1/code/CppUTest/ + +### Prerequisites +* Installed [git client](http://git-scm.com/downloads/). +* Installed [Mercurial client](http://mercurial.selenic.com/). + +### How / where to install +We want to create directory structure similar to one below: +``` +\your_project_directory +│ +├───cpputest +│ ├───include +│ └───src +└───mbed + ├───libraries + ├───travis + └───workspace_tools +``` + +Please go to directory with your project. For example it could be c:\Projects\Project. +``` +$ cd c:\Projects\Project +``` +If your project directory already has your mbed SDK repository included just execute below command (Mercurial console client). It should download CppUTest with Mbed SDK port. +``` +$ hg clone https://mbed.org/users/rgrover1/code/cpputest/ +``` + +You should see something like this after you execute Mercurial clone command: +``` +$ hg clone https://mbed.org/users/rgrover1/code/cpputest/ +destination directory: cpputest +requesting all changes +adding changesets +adding manifests +adding file changes +added 3 changesets with 69 changes to 42 files +updating to branch default +41 files updated, 0 files merged, 0 files removed, 0 files unresolved +``` + +Confirm your project structure. It should look more or less like this: +``` +$ ls +cpputest mbed +``` +From now on CppUTest is in correct path. Each time you want to compile unit tests for CppUTest build script will always look for CppUTest library in the same directory where mbed library is. + +## New off-line mbed SDK project with CppUTest support + +If you are creating new mbed SDK project and you want to use CppUTest with it you need to download both mbed SDK and CppUTest with mbed port to the same directory. You can do it like this: +``` +$ cd c:\Projects\Project +$ git clone https://github.com/mbedmicro/mbed.git +$ hg clone https://mbed.org/users/rgrover1/code/cpputest/ +``` + +After above three steps you should have proper directory structure. All you need to do now is to configure your ```private_settings.py``` in ```mbed/workspace_tools/``` directory. Please refer to mbed SDK build script documentation for details. + +## CppUTest with mbed port +To make sure you actualy have CppUTest library with mbed SDK port you can go to CppUTest ```armcc``` platform directory: +``` +$ cd c:/Projects/Project/cpputest/src/Platforms/armcc/ +``` +And open file ```UtestPlatform.cpp```. + +You should find part of code responsible for porting console on default serial port of the mbed device: +```c++ +#include "Serial.h" +using namespace mbed; + +int PlatformSpecificPutchar(int c) +{ + /* Please modify this block for test results to be reported as + * console output. The following is a sample implementation using a + * Serial object connected to the console. */ +#define NEED_TEST_REPORT_AS_CONSOLE_OUTPUT 1 +#if NEED_TEST_REPORT_AS_CONSOLE_OUTPUT + extern Serial console; + + #define NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE 1 + #if NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE + /* CppUTest emits \n line terminators in its reports; some terminals + * need the linefeed (\r) in addition. */ + if (c == '\n') { + console.putc('\r'); + } + #endif /* #if NEED_LINE_FEED_IN_ADDITION_TO_NEWLINE */ + + return (console.putc(c)); +#else /* NEED_TEST_REPORT_AS_CONSOLE_OUTPUT */ + return (0); +#endif /* NEED_TEST_REPORT_AS_CONSOLE_OUTPUT */ +} +``` + +You can find cpputest UT test runner main function in mbed sources: ```c:/Projects/Project/mbed/libraries/tests/utest/testrunner/testrunner.cpp```. Test runner code (in ```testrunner.cpp```) only defined console object and executes all unit tests: +```c++ +#include "CommandLineTestRunner.h" +#include +#include "mbed.h" +#include "testrunner.h" +#include "test_env.h" + +/** +Object 'mbed_cpputest_console' is used to show prints on console. +It is declared in \cpputest\src\Platforms\armcc\UtestPlatform.cpp +*/ +Serial mbed_cpputest_console(STDIO_UART_TX, STDIO_UART_RX); + +int main(int ac, char** av) { + MBED_HOSTTEST_TIMEOUT(20); + MBED_HOSTTEST_SELECT(default_auto); + MBED_HOSTTEST_DESCRIPTION(Unit test); + MBED_HOSTTEST_START("UT"); + + unsigned failureCount = 0; + { + // Some compilers may not pass ac, av so we need to supply them ourselves + int ac = 2; + char* av[] = {__FILE__, "-v"}; + failureCount = CommandLineTestRunner::RunAllTests(ac, av); + } + + MBED_HOSTTEST_RESULT(failureCount == 0); + return failureCount; +} +``` + +## Unit test location +Unit tests source code is located in below directory: ```c:/Projects/Project/mbed/libraries/tests/utest/``` + +Each sub directory except testrunner contains compilable unit test source files with test groups and test cases. You can see utest structure below. Please note this is just example and in the future this directory will contain many sub directories with unit tests. +``` +$ c:\Projects\Project\mbed\libraries\tests\utest> tree +utest +├───basic +├───semihost_fs +└───testrunner +``` + +## Define unit tests in mbed SDK test suite structure +All tests defined in test suite are described in ```mbed/workspace_tools/tests.py``` file. This file stores data structure ```TESTS``` which is a list of simple structures describing each test. Below you can find example of ```TESTS``` structure which is configuring one of the unit tests. +``` +. +. +. + { + "id": "UT_2", "description": "Semihost file system", + "source_dir": join(TEST_DIR, "utest", "file"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY], + "automated": False, + "mcu": ["LPC1768", "LPC2368", "LPC11U24"] + }, +. +. +. +``` +Note: In dependency section we've added library ```CPPUTEST_LIBRARY``` which is pointing build script to CppUTest library with mbed port. This is a must for unit tests to be compiled with CppUTest library. + +### Tests are now divided into two types: +#### 'Hello world' tests +First type of test cases we call 'hello world' tests. They do not dependent on CppUTest library and are monolithic programs usually composed of one main function. Yo can find this tests in below example directories: + +* ```mbed/libraries/tests/mbed/``` +* ```mbed/libraries/tests/net/``` +* ```mbed/libraries/tests/rtos/``` +* ```mbed/libraries/tests/usb/``` + +Usually ‘hello world’ test cases are using ```test_env.cpp``` and ```test_env.h``` files which implement simple test framework used to communicate with host test and help test framework instrument your tests. + +Below you can see listing of ```test_env.h``` file which contains simple macro definitions used to communicate (via serial port printouts) between test case (on hardware) and host test script (on host computer). +Each use case should print on console basic information like: +* Default test case timeout. +* Which host test should be used to supervise test case execution. +* Test description and test case ID (short identifier). + +```c++ +. +. +. +// Test result related notification functions +void notify_start(); +void notify_completion(bool success); +bool notify_completion_str(bool success, char* buffer); +void notify_performance_coefficient(const char* measurement_name, const int value); +void notify_performance_coefficient(const char* measurement_name, const unsigned int value); +void notify_performance_coefficient(const char* measurement_name, const double value); + +// Host test auto-detection API +void notify_host_test_name(const char *host_test); +void notify_timeout(int timeout); +void notify_test_id(const char *test_id); +void notify_test_description(const char *description); + +// Host test auto-detection API +#define MBED_HOSTTEST_START(TESTID) notify_test_id(TESTID); notify_start() +#define MBED_HOSTTEST_SELECT(NAME) notify_host_test_name(#NAME) +#define MBED_HOSTTEST_TIMEOUT(SECONDS) notify_timeout(SECONDS) +#define MBED_HOSTTEST_DESCRIPTION(DESC) notify_test_description(#DESC) +#define MBED_HOSTTEST_RESULT(RESULT) notify_completion(RESULT) + +/** + Test auto-detection preamble example: + main() { + MBED_HOSTTEST_TIMEOUT(10); + MBED_HOSTTEST_SELECT( host_test ); + MBED_HOSTTEST_DESCRIPTION(Hello World); + MBED_HOSTTEST_START("MBED_10"); + // Proper 'host_test.py' should take over supervising of this test + + // Test code + bool result = ...; + + MBED_HOSTTEST_RESULT(result); + } +*/ +. +. +. +``` + +Example of 'hello world' test: +```c++ +#include "mbed.h" +#include "test_env.h" + +#define CUSTOM_TIME 1256729737 + +int main() { + MBED_HOSTTEST_TIMEOUT(20); + MBED_HOSTTEST_SELECT(rtc_auto); + MBED_HOSTTEST_DESCRIPTION(RTC); + MBED_HOSTTEST_START("MBED_16"); + + char buffer[32] = {0}; + set_time(CUSTOM_TIME); // Set RTC time to Wed, 28 Oct 2009 11:35:37 + while(1) { + time_t seconds = time(NULL); + strftime(buffer, 32, "%Y-%m-%d %H:%M:%S %p", localtime(&seconds)); + printf("MBED: [%ld] [%s]\r\n", seconds, buffer); + wait(1); + } +} +``` + +#### 'Unit test' test cases +Second group of tests are unit tests. They are using CppUTest library and require you to write ```TEST_GROUP```s and ```TEST```s in your test files. Test suite will add test runner sources to your test automatically so you can concentrate on writing tests. + +Example of unit test: +```c++ +#include "TestHarness.h" +#include +#include "mbed.h" + +TEST_GROUP(BusOut_mask) +{ +}; + +TEST(BusOut_mask, led_1_2_3) +{ + BusOut bus_data(LED1, LED2, LED3); + CHECK_EQUAL(0x07, bus_data.mask()); +} + +TEST(BusOut_mask, led_nc_nc_nc_nc) +{ + BusOut bus_data(NC, NC, NC, NC); + CHECK_EQUAL(0x00, bus_data.mask()); +} + +TEST(BusOut_mask, led_1_2_3_nc_nc) +{ + BusOut bus_data(LED1, LED2, LED3, NC, NC); + CHECK_EQUAL(0x07, bus_data.mask()); +} + +TEST(BusOut_mask, led_1_nc_2_nc_nc_3) +{ + BusOut bus_data(LED1, NC, LED2, NC, NC, LED3); + CHECK_EQUAL(0x25, bus_data.mask()); +} + +/////////////////////////////////////////////////////////////////////////////// + +#ifdef MBED_OPERATORS +TEST_GROUP(BusOut_digitalout_write) +{ +}; + +TEST(BusOut_digitalout_write, led_nc) +{ + BusOut bus_data(NC); + CHECK_EQUAL(false, bus_data[0].is_connected()) +} + +TEST(BusOut_digitalout_write, led_1_2_3) +{ + BusOut bus_data(LED1, LED2, LED3); + bus_data[0].write(1); + bus_data[1].write(1); + bus_data[2].write(1); + CHECK(bus_data[0].read()); + CHECK(bus_data[1].read()); + CHECK(bus_data[2].read()); +} + +TEST(BusOut_digitalout_write, led_1_2_3_nc_nc) +{ + BusOut bus_data(LED1, LED2, LED3, NC, NC); + bus_data[0].write(0); + bus_data[1].write(0); + bus_data[2].write(0); + CHECK(bus_data[0].read() == 0); + CHECK(bus_data[1].read() == 0); + CHECK(bus_data[2].read() == 0); +} + +TEST(BusOut_digitalout_write, led_1_nc_2_nc_nc_3) +{ + BusOut bus_data(LED1, NC, LED2, NC, NC, LED3); + bus_data[0].write(1); + bus_data[2].write(0); + bus_data[5].write(0); + CHECK(bus_data[0].read()); + CHECK(bus_data[2].read() == 0); + CHECK(bus_data[5].read() == 0); +} +#endif +``` + +## Example +In below example we will run two example unit tests that are now available. tests ```UT_1``` and ```UT_2``` are unit tests used for now only to check if mbed SDK works with CppUTest library and if tests are being executed. In future number of unit tests will increase, nothing is also should stop you from writing and executing your own unit tests! + +### Example configuration +By default unit tests ```UT_1``` and ```UT_2``` are not automated - simply test suite will ignore them. Also we do not want to create dependency to CppUTest library each time someone executes automation. + +Note: To compile ```UT_1``` and ```UT_2``` tests CppUTest library described above installation is needed and not all users wish to add UT libs to their project. Also new to mbed users may find it difficult. This is why unit testing is an extra feature active only after you deliberately install and enable needed components. + +Bellow snippet shows how to modify 'automated' flag so test suite will consider unit tests ```UT_1``` and ```UT_2``` as part of "automated test portfolio". Just change flag 'automated' from ```False``` to ```True```. + +```tests.py``` listing related to ```UT_1``` and ```UT_2```: +```python +. +. +. + # CPPUTEST Library provides Unit testing Framework + # + # To write TESTs and TEST_GROUPs please add CPPUTEST_LIBRARY to 'dependencies' + # + # This will also include: + # 1. test runner - main function with call to CommandLineTestRunner::RunAllTests(ac, av) + # 2. Serial console object to print test result on serial port console + # + + # Unit testing with cpputest library + { + "id": "UT_1", "description": "Basic", + "source_dir": join(TEST_DIR, "utest", "basic"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY], + "automated": True, + }, + { + "id": "UT_2", "description": "Semihost file system", + "source_dir": join(TEST_DIR, "utest", "semihost_fs"), + "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB, CPPUTEST_LIBRARY], + "automated": True, + "mcu": ["LPC1768", "LPC2368", "LPC11U24"] + }, +. +. +. +``` + +### Execute tests +In my test I will use common [LPC1768](http://developer.mbed.org/platforms/mbed-LPC1768/) mbed-enabled board because unit test ```UT_2``` is checking semi-host functionality which is available on this board and handful of others. + +Configure your ```test_spec.json``` and ```muts_all.json``` files (refer to test suite build script and automation description) and set mbed disk and serial port. + +``` +$ singletest.py -i test_spec.json -M muts_all.json -n UT_1,UT_2 -V +Building library CMSIS (LPC1768, ARM) +Building library MBED (LPC1768, ARM) +Building library CPPUTEST (LPC1768, ARM) +Building project BASIC (LPC1768, ARM) +Executing 'python host_test.py -p COM77 -d E:\ -t 10' +Test::Output::Start +Host test instrumentation on port: "COM77" and disk: "E:\" +TEST(FirstTestGroup, FirstTest) - 0 ms + +OK (1 tests, 1 ran, 3 checks, 0 ignored, 0 filtered out, 3 ms) + +{{success}} +{{end}} +Test::Output::Finish +TargetTest::LPC1768::ARM::UT_1::Basic [OK] in 2.43 of 10 sec +Building library CPPUTEST (LPC1768, ARM) +Building project SEMIHOST_FS (LPC1768, ARM) +Executing 'python host_test.py -p COM77 -d E:\ -t 10' +Test::Output::Start +Host test instrumentation on port: "COM77" and disk: "E:\" +TEST(FirstTestGroup, FirstTest) - 9 ms + +OK (1 tests, 1 ran, 10 checks, 0 ignored, 0 filtered out, 10 ms) + +{{success}} +{{end}} +Test::Output::Finish +TargetTest::LPC1768::ARM::UT_2::Semihost file system [OK] in 2.43 of 10 sec +Test summary: ++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+ +| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) | Loops | ++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+ +| OK | LPC1768 | ARM | UT_1 | Basic | 2.43 | 10 | 1/1 | +| OK | LPC1768 | ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 | ++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+ +Result: 2 OK + +Completed in 12.02 sec +``` + +You can compile unit tests using various number of supported compilers, below just few examples with working solutions: +``` +Test summary: ++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+ +| Result | Target | Toolchain | Test ID | Test Description | Elapsed Time (sec) | Timeout (sec) | Loops | ++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+ +| OK | LPC1768 | ARM | UT_1 | Basic | 2.43 | 10 | 1/1 | +| OK | LPC1768 | ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 | +| OK | LPC1768 | uARM | UT_1 | Basic | 2.43 | 10 | 1/1 | +| OK | LPC1768 | uARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 | +| OK | LPC1768 | GCC_ARM | UT_1 | Basic | 2.43 | 10 | 1/1 | +| OK | LPC1768 | GCC_ARM | UT_2 | Semihost file system | 2.43 | 10 | 1/1 | +| OK | LPC1768 | GCC_CR | UT_1 | Basic | 3.44 | 10 | 1/1 | +| OK | LPC1768 | GCC_CR | UT_2 | Semihost file system | 3.43 | 10 | 1/1 | ++--------+---------+-----------+---------+----------------------+--------------------+---------------+-------+ +Result: 8 OK + +Completed in 55.85 sec +``` diff --git a/libraries/USBDevice/USBDevice/USBDevice.cpp b/libraries/USBDevice/USBDevice/USBDevice.cpp index e64eab5e74c..dc3efc96f4d 100644 --- a/libraries/USBDevice/USBDevice/USBDevice.cpp +++ b/libraries/USBDevice/USBDevice/USBDevice.cpp @@ -187,7 +187,7 @@ bool USBDevice::controlOut(void) /* Check we should be transferring data OUT */ if (transfer.direction != HOST_TO_DEVICE) { -#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) | defined(TARGET_K22F) +#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) /* * We seem to have a pending device-to-host transfer. The host must have * sent a new control request without waiting for us to finish processing diff --git a/libraries/USBDevice/USBDevice/USBEndpoints.h b/libraries/USBDevice/USBDevice/USBEndpoints.h index 130f49a7907..e7e78bf018f 100644 --- a/libraries/USBDevice/USBDevice/USBEndpoints.h +++ b/libraries/USBDevice/USBDevice/USBEndpoints.h @@ -41,7 +41,7 @@ typedef enum { #include "USBEndpoints_LPC17_LPC23.h" #elif defined(TARGET_LPC11UXX) || defined(TARGET_LPC1347) || defined (TARGET_LPC11U6X) || defined (TARGET_LPC1549) #include "USBEndpoints_LPC11U.h" -#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) +#elif defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) #include "USBEndpoints_KL25Z.h" #elif defined (TARGET_STM32F4) #include "USBEndpoints_STM32F4.h" diff --git a/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp b/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp index 86452653d4c..f92a99979b2 100644 --- a/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp +++ b/libraries/USBDevice/USBDevice/USBHAL_KL25Z.cpp @@ -16,7 +16,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ -#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) +#if defined(TARGET_KL25Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1) #include "USBHAL.h" diff --git a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c index aa2158efce8..4b45c719f03 100644 --- a/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c +++ b/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/system_MK20DX256.c @@ -47,6 +47,7 @@ 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode Reference clock source for MCG module is the slow internal clock source 32.768kHz Core clock = 41.94MHz, BusClock = 41.94MHz + This works on Teensy3.1 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode Reference clock source for MCG module is an external crystal 8MHz Core clock = 48MHz, BusClock = 48MHz @@ -56,7 +57,7 @@ 3 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode Reference clock source for MCG module is an external crystal 16MHz Core clock = 72MHz, BusClock = 48MHz - This is the Teensy3.1 72Mhz set up + This is the default Teensy3.1 72Mhz set up */ /*---------------------------------------------------------------------------- @@ -98,7 +99,6 @@ uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; /* ---------------------------------------------------------------------------- -- SystemInit() ---------------------------------------------------------------------------- */ - void SystemInit (void) { #if (DISABLE_WDOG) /* Disable the WDOG module */ @@ -106,143 +106,120 @@ void SystemInit (void) { WDOG->UNLOCK = (uint16_t)0xC520u; /* Key 1 */ /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */ WDOG->UNLOCK = (uint16_t)0xD928u; /* Key 2 */ - /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ + /* WDOG_STCTRLH: DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */ WDOG->STCTRLH = (uint16_t)0x01D2u; #endif /* (DISABLE_WDOG) */ + #if (CLOCK_SETUP == 0) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 41.94MHz cpu, 41.94MHz system, 20.97MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); /* Switch to FEI Mode */ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x06u; - /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ + MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; + /* MCG->C2: LOCKRE0=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */ MCG->C2 = (uint8_t)0x00u; /* MCG_C4: DMX32=0,DRST_DRS=1 */ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u); - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ MCG->C5 = (uint8_t)0x00u; /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */ - } - while((MCG->S & 0x0Cu) != 0x00u) { /* Wait until output of the FLL is selected */ - } + while((MCG->S & MCG_S_IREFST_MASK) == 0u) { } /* Check that the source of the FLL reference clock is the internal reference clock. */ + while((MCG->S & 0x0Cu) != 0x00u) { } /* Wait until output of the FLL is selected */ + #elif (CLOCK_SETUP == 1) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 48MHz cpu, 48MHz system, 24MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0->CR = (uint8_t)0x00u; /* MCG->C7: OSCSEL=0 */ MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; + /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = MCG_C2_RANGE0(2); /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x9Au; + MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x03u; + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = MCG_C5_PRDIV0(3); /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ - } -#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ - while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } -#endif - while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ - } + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ + while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ /* Switch to PBE Mode */ - /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x03u; + /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ + MCG->C5 = MCG_C5_PRDIV0(3); /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x40u; - while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } + MCG->C6 = MCG_C6_PLLS_MASK; + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ /* Switch to PEE Mode */ /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x1Au; - while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } + MCG->C1 = MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; + while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ + #elif (CLOCK_SETUP == 2) - /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 8MHz cpu, 8MHz system, 8MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ + /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ OSC0->CR = (uint8_t)0x00u; /* MCG->C7: OSCSEL=0 */ MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; + /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x9Au; + MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; /* MCG->C4: DMX32=0,DRST_DRS=0 */ MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */ MCG->C5 = (uint8_t)0x00u; /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ - } -#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ - while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } -#endif - while((MCG->S & 0x0CU) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ - } + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ + while((MCG->S & 0x0CU) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ /* Switch to BLPE Mode */ - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; + /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; #elif (CLOCK_SETUP == 3) - /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */ - SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */ + /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV4=1 Set Prescalers 72MHz cpu, 72MHz system, 36MHz flash*/ + SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV4(1); + /* SIM->CLKDIV2: USBDIV=2,USBFRAC=1 Divide 72MHz system clock for USB 48MHz */ + SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(2) | SIM_CLKDIV2_USBFRAC_MASK; + /* OSC0->CR: ERCLKEN=0,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=1,SC16P=0 10pF loading capacitors for 16MHz system oscillator*/ + OSC0->CR = OSC_CR_SC8P_MASK | OSC_CR_SC2P_MASK; /* Switch to FBE Mode */ - /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ - OSC0->CR = (uint8_t)0x0Au; // this is required if there are no external capacitors fitted to the Xtal /* MCG->C7: OSCSEL=0 */ MCG->C7 = (uint8_t)0x00u; - /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ - MCG->C2 = (uint8_t)0x24u; + /* MCG->C2: LOCKRE0=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */ + MCG->C2 = MCG_C2_RANGE0(2) | MCG_C2_EREFS0_MASK; + //MCG->C2 = (uint8_t)0x24u; /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x9Au; - /* MCG->C4: DMX32=0,DRST_DRS=0 */ - MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; - /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x07u; + MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; + /* MCG->C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */ + MCG->C4 &= (uint8_t)~(uint8_t)0xE0u; + /* MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=7 */ + MCG->C5 = MCG_C5_PRDIV0(7); /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */ MCG->C6 = (uint8_t)0x00u; - while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */ - } -#if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */ - while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */ - } -#endif - while((MCG->S & 0x0Cu) != 0x08u) { /* Wait until external reference clock is selected as MCG output */ - } + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } /* Check that the oscillator is running */ + while((MCG->S & 0x0Cu) != 0x08u) { } /* Wait until external reference clock is selected as MCG output */ /* Switch to PBE Mode */ - /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */ - MCG->C5 = (uint8_t)0x05u; - /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */ - MCG->C6 = (uint8_t)0x43u; - while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } + /* MCG_C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=5 */ + MCG->C5 = MCG_C5_PRDIV0(5); + /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 */ + MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3); + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } /* Wait until the source of the PLLS clock has switched to the PLL */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ /* Switch to PEE Mode */ - /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ - MCG->C1 = (uint8_t)0x22u; - while((MCG->S & 0x0Cu) != 0x0Cu) { /* Wait until output of the PLL is selected */ - } - while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */ - } - -#endif /* (CLOCK_SETUP == 3) */ + /* MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ + MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK; + while((MCG->S & 0x0Cu) != 0x0Cu) { } /* Wait until output of the PLL is selected */ + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } /* Wait until locked */ +#endif /* (CLOCK_SETUP) */ } /* ---------------------------------------------------------------------------- diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/Release_Notes_stm32l0xx_hal.html b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/Release_Notes_stm32l0xx_hal.html index d19459b6ced..14e154b2f63 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/Release_Notes_stm32l0xx_hal.html +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/Release_Notes_stm32l0xx_hal.html @@ -645,7 +645,8 @@ {margin-bottom:0in;} --> - + +

 

@@ -665,7 +666,7 @@

Release Notes for STM32L0xx HAL Drivers

Copyright -2014 STMicroelectronics

+2015 STMicroelectronics

@@ -676,7 +677,13 @@

-

Update History

V1.1.0 +

Update History


V1.2.0 +/ 06-February-2015

Main +Changes
  • HAL has been updated to support the STM32L071xx  STM32L072xx STM32L073xx STM32L082xx STM32L083xx series
  • HAL Flash update
    • Flash :  192K Dual Bank 
  • HAL TIM update : 
    • Four new instances  : TIM3, TIM7, TIM21, TIM22
  • HAL USART update :
    • Two new instances : USART 4, USART 5
  • HAL I2C update :
    • One new instance I2C3
  • HAL GPIO update :
    • GPIO Port E
  • HAL DAC update :
    • A second channel has been introduced
  • HAL FIREWALL introduction
  • All other HAL IPs have also been updated in the context of the overall HAL alignment effort of all the STM32 family
  • More than 120 corrections have been implemented since the previous V1.1.0 delivery
  • Known limitations :
    • Introduced +a FW patch to deactivate the HW SPI-V2.3 correction in case of I2S PCM +Short mode usage (Please refer to the STM32L073xx Errata Sheet for more +details). In this use case, we come back to the HW SPI 2.2 behavior +which is correct for the I2S PCM short mode

V1.1.0 / 18-June-2014

Main Changes

  • @@ -1067,13 +1074,13 @@

    V1.0.0 +

    V1.0.0 / 22-April-2014

    Main Changes

    First official release.
    -

    License

    +

    License

    Redistribution and use in source and binary forms, with or without diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l053xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l053xx.h index 8f467f6da8e..2191ba427b1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l053xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l053xx.h @@ -2,21 +2,21 @@ ****************************************************************************** * @file stm32l053xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L0xx devices. + * definitions and memory mapping for stm32l053xx devices. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2015 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -71,7 +71,6 @@ #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - /** * @} */ @@ -81,7 +80,7 @@ */ /** - * @brief STM32L0xx Interrupt Number Definition, according to the selected device + * @brief stm32l053xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ @@ -90,39 +89,39 @@ typedef enum { /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ /****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ - LCD_IRQn = 30, /*!< LCD Interrupts */ - USB_IRQn = 31 /*!< USB global Interrupt */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM21_IRQn = 20, /*!< TIM21 Interrupt */ + TIM22_IRQn = 22, /*!< TIM22 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ + LCD_IRQn = 30, /*!< LCD Interrupt */ + USB_IRQn = 31, /*!< USB global Interrupt */ } IRQn_Type; /** @@ -156,7 +155,7 @@ typedef struct __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ + uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ } ADC_TypeDef; @@ -183,7 +182,7 @@ typedef struct typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ @@ -193,6 +192,7 @@ typedef struct /** * @brief Clock Recovery System */ + typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ @@ -236,35 +236,35 @@ typedef struct typedef struct { - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2015 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -44,8 +44,8 @@ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************** - */ + ****************************************************************************** + */ /** @addtogroup CMSIS * @{ @@ -54,56 +54,69 @@ /** @addtogroup stm32l0xx * @{ */ - + #ifndef __STM32L0xx_H #define __STM32L0xx_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ - + /** @addtogroup Library_configuration_section * @{ */ +/** + * @brief STM32 Family + */ +#if !defined (STM32L0) +#define STM32L0 +#endif /* STM32L0 */ + /* Uncomment the line below according to the target STM32 device used in your - application + application */ -#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L062xx) && \ - !defined (STM32L063xx) && !defined (STM32L061xx) - /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6,STM32L051C8,STM32L051R6 and STM32L051R8 Devices */ - /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8,STM32L052C6,STM32L052C8,STM32L052R6 and STM32L052R8 Devices */ - #define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, and STM32L053R8 Devices */ +#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \ + && !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) + /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */ + /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */ +#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ + /* #define STM32L061xx */ /*!< */ /* #define STM32L062xx */ /*!< STM32L062K8 */ - /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */ - /* #define STM32L061xx */ + /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */ + /* #define STM32L071xx */ /*!< */ + /* #define STM32L072xx */ /*!< */ + /* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */ + /* #define STM32L081xx */ /*!< */ + /* #define STM32L082xx */ /*!< */ + /* #define STM32L083xx */ /*!< */ #endif - + /* Tip: To avoid modifying this file each time you need to switch between these devices, you can define the device in your toolchain compiler preprocessor. */ #if !defined (USE_HAL_DRIVER) /** * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers */ - #define USE_HAL_DRIVER +#define USE_HAL_DRIVER #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.1.0 + * @brief CMSIS Device version number V1.2.0 */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\ |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\ |(__CMSIS_DEVICE_HAL_VERSION_RC)) - + /** * @} */ @@ -112,7 +125,11 @@ * @{ */ -#if defined(STM32L051xx) +#if defined(STM32L031xx) + #include "stm32l031xx.h" +#elif defined(STM32L041xx) + #include "stm32l041xx.h" +#elif defined(STM32L051xx) #include "stm32l051xx.h" #elif defined(STM32L052xx) #include "stm32l052xx.h" @@ -124,6 +141,18 @@ #include "stm32l063xx.h" #elif defined(STM32L061xx) #include "stm32l061xx.h" +#elif defined(STM32L071xx) + #include "stm32l071xx.h" +#elif defined(STM32L072xx) + #include "stm32l072xx.h" +#elif defined(STM32L073xx) + #include "stm32l073xx.h" +#elif defined(STM32L082xx) + #include "stm32l082xx.h" +#elif defined(STM32L083xx) + #include "stm32l083xx.h" +#elif defined(STM32L081xx) + #include "stm32l081xx.h" #else #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" #endif @@ -134,23 +163,23 @@ /** @addtogroup Exported_types * @{ - */ -typedef enum + */ +typedef enum { - RESET = 0, + RESET = 0, SET = !RESET } FlagStatus, ITStatus; -typedef enum +typedef enum { - DISABLE = 0, + DISABLE = 0, ENABLE = !DISABLE } FunctionalState; #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) -typedef enum +typedef enum { - ERROR = 0, + ERROR = 0, SUCCESS = !ERROR } ErrorStatus; @@ -177,7 +206,6 @@ typedef enum #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - /** * @} */ @@ -186,7 +214,6 @@ typedef enum #include "stm32l0xx_hal.h" #endif /* USE_HAL_DRIVER */ - #ifdef __cplusplus } #endif /* __cplusplus */ @@ -199,7 +226,7 @@ typedef enum /** * @} */ - + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c index 7a3b870a54a..2c7167a6a72 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c @@ -2,20 +2,20 @@ ****************************************************************************** * @file system_stm32l0xx.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. * - * This file provides two functions and one global variable to be called from + * This file provides two functions and one global variable to be called from * user application: - * - SystemInit(): This function is called at startup just after reset and + * - SystemInit(): This function is called at startup just after reset and * before branch to main program. This call is made inside * the "startup_stm32l0xx.s" file. * * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick + * by the user application to setup the SysTick * timer or configure other parameters. - * + * * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must * be called whenever the core clock is changed * during program execution. @@ -40,7 +40,7 @@ ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2015 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -73,8 +73,8 @@ /** @addtogroup stm32l0xx_system * @{ - */ - + */ + /** @addtogroup STM32L0xx_System_Private_Includes * @{ */ @@ -82,14 +82,14 @@ #include "stm32l0xx.h" #include "hal_tick.h" -#if !defined (HSE_VALUE) +#if !defined (HSE_VALUE) #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ #endif /* HSE_VALUE */ #if !defined (MSI_VALUE) #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ - + #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ @@ -115,7 +115,7 @@ /*!< Uncomment the following line if you need to relocate your vector Table in Internal SRAM. */ /* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ /******************************************************************************/ /** @@ -140,7 +140,7 @@ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. @@ -177,19 +177,19 @@ uint8_t SetSysClock_PLL_HSI(void); * @retval None */ void SystemInit (void) -{ +{ /*!< Set MSION bit */ RCC->CR |= (uint32_t)0x00000100; /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ RCC->CFGR &= (uint32_t) 0x88FF400C; - + /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ RCC->CR &= (uint32_t)0xFEF6FFF6; - + /*!< Reset HSI48ON bit */ RCC->CRRCR &= (uint32_t)0xFFFFFFFE; - + /*!< Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; @@ -198,7 +198,7 @@ void SystemInit (void) /*!< Disable all interrupts */ RCC->CIER = 0x00000000; - + /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ @@ -224,34 +224,34 @@ void SystemInit (void) * The SystemCoreClock variable contains the core clock (HCLK), it can * be used by the user application to setup the SysTick timer or configure * other parameters. - * + * * @note Each time the core clock (HCLK) changes, this function must be called * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI * value as defined by the MSI range. - * + * * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * + * * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * + * * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * + * * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * + * in voltage and temperature. + * * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value * 8 MHz), user has to ensure that HSE_VALUE is same as the real * frequency of the crystal used. Otherwise, this function may * have wrong result. - * + * * - The result of this function could be not correct when using fractional * value for HSE crystal. * @param None @@ -263,11 +263,12 @@ void SystemCoreClockUpdate (void) /* Get SYSCLK source -------------------------------------------------------*/ tmp = RCC->CFGR & RCC_CFGR_SWS; - + switch (tmp) { case 0x00: /* MSI used as system clock */ - SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000); + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); break; case 0x04: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; @@ -281,7 +282,7 @@ void SystemCoreClockUpdate (void) plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; pllmul = PLLMulTable[(pllmul >> 18)]; plldiv = (plldiv >> 22) + 1; - + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; if (pllsource == 0x00) @@ -310,8 +311,8 @@ void SystemCoreClockUpdate (void) /** * @brief Configures the System clock source, PLL Multiplier and Divider factors, * AHB/APBx prescalers and Flash settings - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). + * @note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). * @param None * @retval None */ @@ -337,7 +338,7 @@ void SetSysClock(void) } } } - + /* Output clock on MCO1 pin(PA8) for debugging purpose */ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); @@ -357,13 +358,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { return 0; } - - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value + + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value regarding system frequency refer to product datasheet. */ __PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - + /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; if (bypass == 0) @@ -385,7 +386,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) { return 0; // FAIL } - + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz @@ -402,7 +403,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz //else // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz - + return 1; // OK } #endif @@ -415,12 +416,12 @@ uint8_t SetSysClock_PLL_HSI(void) RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; - /* The voltage scaling allows optimizing the power consumption when the device is - clocked below the maximum system frequency, to update the voltage scaling value + /* The voltage scaling allows optimizing the power consumption when the device is + clocked below the maximum system frequency, to update the voltage scaling value regarding system frequency refer to product datasheet. */ __PWR_CLK_ENABLE(); __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); - + /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; RCC_OscInitStruct.HSEState = RCC_HSE_OFF; @@ -435,7 +436,7 @@ uint8_t SetSysClock_PLL_HSI(void) { return 0; // FAIL } - + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz @@ -449,7 +450,7 @@ uint8_t SetSysClock_PLL_HSI(void) /* Output clock on MCO1 pin(PA8) for debugging purpose */ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz - + return 1; // OK } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.h index 02c94f1f471..c831006ce7f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2015 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -41,8 +41,8 @@ /** @addtogroup stm32l0xx_system * @{ - */ - + */ + /** * @brief Define to prevent recursive inclusion */ @@ -51,7 +51,7 @@ #ifdef __cplusplus extern "C" { -#endif +#endif /** @addtogroup STM32L0xx_System_Includes * @{ @@ -68,7 +68,7 @@ /* This variable is updated in three ways: 1) by calling CMSIS function SystemCoreClockUpdate() 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency Note: If you use this function to configure the system clock; then there is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. @@ -98,7 +98,7 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Cloc /** @addtogroup STM32L0xx_System_Exported_Functions * @{ */ - + extern void SystemInit(void); extern void SystemCoreClockUpdate(void); extern void SetSysClock(void); @@ -116,8 +116,8 @@ extern void SetSysClock(void); /** * @} */ - + /** * @} - */ + */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.s index 82152a6380b..deb767857ab 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.s +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32l053xx.s ;* Author : MCD Application Team -;* Version : V1.1.0 -;* Date : 18-June-2014 +;* Version : V1.2.0 +;* Date : 06-February-2015 ;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -12,9 +12,9 @@ ;* calls main()). ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> +;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* -;* +;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.s index c15b196c9c0..e79c386efe4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.s +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.s @@ -1,8 +1,8 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32l053xx.s ;* Author : MCD Application Team -;* Version : V1.1.0 -;* Date : 18-June-2014 +;* Version : V1.2.0 +;* Date : 06-February-2015 ;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP @@ -12,9 +12,9 @@ ;* calls main()). ;* After Reset the Cortex-M0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> +;* <<< Use Configuration Wizard in Context Menu >>> ;******************************************************************************* -;* +;* ;* Redistribution and use in source and binary forms, with or without modification, ;* are permitted provided that the following conditions are met: ;* 1. Redistributions of source code must retain the above copyright notice, diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.s index 688e6230603..5cd63713d5a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.s +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.s @@ -2,8 +2,8 @@ ****************************************************************************** * @file startup_stm32l053xx.s * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain. * This module performs: * - Set the initial SP diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/startup_stm32l053xx.s b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/startup_stm32l053xx.s index 20869b07f1e..30b0ffa1658 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/startup_stm32l053xx.s +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/startup_stm32l053xx.s @@ -1,8 +1,8 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** ;* File Name : startup_stm32l053xx.s ;* Author : MCD Application Team -;* Version : V1.1.0 -;* Date : 18-June-2014 +;* Version : V1.2.0 +;* Date : 06-February-2015 ;* Description : STM32L053xx Ultra Low Power Devices vector ;* This module performs: ;* - Set the initial SP diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/cmsis_nvic.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/cmsis_nvic.h index 0e0ab96f824..027dd9f78a6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/cmsis_nvic.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/cmsis_nvic.h @@ -32,7 +32,6 @@ #ifndef MBED_CMSIS_NVIC_H #define MBED_CMSIS_NVIC_H -// STM32L053R8 // CORE: 16 vectors = 64 bytes from 0x00 to 0x3F // MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF // Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l053xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l053xx.h index 8f467f6da8e..2191ba427b1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l053xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/stm32l053xx.h @@ -2,21 +2,21 @@ ****************************************************************************** * @file stm32l053xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits - * definitions and memory mapping for STM32L0xx devices. + * definitions and memory mapping for stm32l053xx devices. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral’s registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention * - *

    © COPYRIGHT(c) 2014 STMicroelectronics

    + *

    © COPYRIGHT(c) 2015 STMicroelectronics

    * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -71,7 +71,6 @@ #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - /** * @} */ @@ -81,7 +80,7 @@ */ /** - * @brief STM32L0xx Interrupt Number Definition, according to the selected device + * @brief stm32l053xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ @@ -90,39 +89,39 @@ typedef enum { /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ - SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */ /****** STM32L-0 specific Interrupt Numbers *********************************************************/ - WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ - PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ - RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ - FLASH_IRQn = 3, /*!< FLASH Interrupt */ - RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ - EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ - EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ - EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ - TSC_IRQn = 8, /*!< TSC Interrupt */ - DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ - DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */ + RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */ + FLASH_IRQn = 3, /*!< FLASH Interrupt */ + RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + TSC_IRQn = 8, /*!< TSC Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ - ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ - LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ - TIM2_IRQn = 15, /*!< TIM2 Interrupt */ - TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ - TIM21_IRQn = 20, /*!< TIM21 Interrupt */ - TIM22_IRQn = 22, /*!< TIM22 Interrupt */ - I2C1_IRQn = 23, /*!< I2C1 Interrupt */ - I2C2_IRQn = 24, /*!< I2C2 Interrupt */ - SPI1_IRQn = 25, /*!< SPI1 Interrupt */ - SPI2_IRQn = 26, /*!< SPI2 Interrupt */ - USART1_IRQn = 27, /*!< USART1 Interrupt */ - USART2_IRQn = 28, /*!< USART2 Interrupt */ - RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ - LCD_IRQn = 30, /*!< LCD Interrupts */ - USB_IRQn = 31 /*!< USB global Interrupt */ + ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */ + LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 Interrupt */ + TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */ + TIM21_IRQn = 20, /*!< TIM21 Interrupt */ + TIM22_IRQn = 22, /*!< TIM22 Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ + USART2_IRQn = 28, /*!< USART2 Interrupt */ + RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */ + LCD_IRQn = 30, /*!< LCD Interrupt */ + USB_IRQn = 31, /*!< USB global Interrupt */ } IRQn_Type; /** @@ -156,7 +155,7 @@ typedef struct __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ - uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ + uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */ __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */ } ADC_TypeDef; @@ -183,7 +182,7 @@ typedef struct typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ @@ -193,6 +192,7 @@ typedef struct /** * @brief Clock Recovery System */ + typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ @@ -236,35 +236,35 @@ typedef struct typedef struct { - __IO uint32_t CCR; /*!< DMA channel x configuration register */ - __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ - __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ - __IO uint32_t CMAR; /*!< DMA channel x memory address register */ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; typedef struct { - __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ - __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */ -} DMA_Request_TypeDef; - -/** - * @brief External Interrupt/Event Controller - */ - -typedef struct -{ - __IO uint32_t IMR; /*!
    © COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -66,18 +66,31 @@ * @{ */ +/** + * @brief STM32 Family + */ +#if !defined (STM32L0) +#define STM32L0 +#endif /* STM32L0 */ + /* Uncomment the line below according to the target STM32 device used in your application */ -#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L062xx) && \ - !defined (STM32L063xx) && !defined (STM32L061xx) - /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6,STM32L051C8,STM32L051R6 and STM32L051R8 Devices */ - /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8,STM32L052C6,STM32L052C8,STM32L052R6 and STM32L052R8 Devices */ -#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, and STM32L053R8 Devices */ +#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \ + && !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx) + /* #define STM32L051xx */ /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */ + /* #define STM32L052xx */ /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */ +#define STM32L053xx /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */ + /* #define STM32L061xx */ /*!< */ /* #define STM32L062xx */ /*!< STM32L062K8 */ /* #define STM32L063xx */ /*!< STM32L063C8, STM32L063R8 */ - /* #define STM32L061xx */ + /* #define STM32L071xx */ /*!< */ + /* #define STM32L072xx */ /*!< */ + /* #define STM32L073xx */ /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */ + /* #define STM32L081xx */ /*!< */ + /* #define STM32L082xx */ /*!< */ + /* #define STM32L083xx */ /*!< */ #endif /* Tip: To avoid modifying this file each time you need to switch between these @@ -93,10 +106,10 @@ #endif /* USE_HAL_DRIVER */ /** - * @brief CMSIS Device version number V1.1.0 + * @brief CMSIS Device version number V1.2.0 */ #define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32L0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\ @@ -112,7 +125,11 @@ * @{ */ -#if defined(STM32L051xx) +#if defined(STM32L031xx) + #include "stm32l031xx.h" +#elif defined(STM32L041xx) + #include "stm32l041xx.h" +#elif defined(STM32L051xx) #include "stm32l051xx.h" #elif defined(STM32L052xx) #include "stm32l052xx.h" @@ -124,6 +141,18 @@ #include "stm32l063xx.h" #elif defined(STM32L061xx) #include "stm32l061xx.h" +#elif defined(STM32L071xx) + #include "stm32l071xx.h" +#elif defined(STM32L072xx) + #include "stm32l072xx.h" +#elif defined(STM32L073xx) + #include "stm32l073xx.h" +#elif defined(STM32L082xx) + #include "stm32l082xx.h" +#elif defined(STM32L083xx) + #include "stm32l083xx.h" +#elif defined(STM32L081xx) + #include "stm32l081xx.h" #else #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)" #endif @@ -177,7 +206,6 @@ typedef enum #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - /** * @} */ @@ -186,7 +214,6 @@ typedef enum #include "stm32l0xx_hal.h" #endif /* USE_HAL_DRIVER */ - #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c index 4eba16be936..2c7167a6a72 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file system_stm32l0xx.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from @@ -40,7 +40,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -145,12 +145,9 @@ is no need to call the 2 first functions listed above, since SystemCoreClock variable is updated automatically. */ -uint32_t SystemCoreClock = 32000000; - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; -const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -//const uint32_t MSIRangeTable[7] = {64000, 128000, 256000, 512000, 1000000, 2000000, 4000000}; + uint32_t SystemCoreClock = 32000000; +__IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +__IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; /** * @} @@ -270,7 +267,8 @@ void SystemCoreClockUpdate (void) switch (tmp) { case 0x00: /* MSI used as system clock */ - SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000); + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; + SystemCoreClock = (32768 * (1 << (msirange + 1))); break; case 0x04: /* HSI used as system clock */ SystemCoreClock = HSI_VALUE; diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.h index 7ba1eb06015..c831006ce7f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file system_stm32l0xx.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32_hal_legacy.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32_hal_legacy.h new file mode 100644 index 00000000000..5797360f5a0 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32_hal_legacy.h @@ -0,0 +1,2250 @@ +/** + ****************************************************************************** + * @file stm32_hal_legacy.h + * @author MCD Application Team + * @version V1.2.0RC4 + * @date 23-January-2015 + * @brief This file contains aliases definition for the STM32Cube HAL constants + * macros and functions maintained for legacy purpose. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + UART * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32_HAL_LEGACY +#define __STM32_HAL_LEGACY + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose + * @{ + */ +#define AES_FLAG_RDERR CRYP_FLAG_RDERR +#define AES_FLAG_WRERR CRYP_FLAG_WRERR +#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF +#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR +#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR + +/** + * @} + */ + +/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose + * @{ + */ +#define ADC_RESOLUTION12b ADC_RESOLUTION_12B +#define ADC_RESOLUTION10b ADC_RESOLUTION_10B +#define ADC_RESOLUTION8b ADC_RESOLUTION_8B +#define ADC_RESOLUTION6b ADC_RESOLUTION_6B +#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN +#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED +#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV +#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV +#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV +#define REGULAR_GROUP ADC_REGULAR_GROUP +#define INJECTED_GROUP ADC_INJECTED_GROUP +#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP +#define AWD_EVENT ADC_AWD_EVENT +#define AWD1_EVENT ADC_AWD1_EVENT +#define AWD2_EVENT ADC_AWD2_EVENT +#define AWD3_EVENT ADC_AWD3_EVENT +#define OVR_EVENT ADC_OVR_EVENT +#define JQOVF_EVENT ADC_JQOVF_EVENT +#define ALL_CHANNELS ADC_ALL_CHANNELS +#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS +#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS +#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR +#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT +#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 +#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 +#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 +#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO +#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 +#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO +#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 +#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO +#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 +#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 +#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE +#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING +#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING +#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING +/** + * @} + */ + +/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE +#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE +#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 +#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 + +/** + * @} + */ + +/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE +#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define DAC1_CHANNEL_1 DAC_CHANNEL_1 +#define DAC1_CHANNEL_2 DAC_CHANNEL_2 +#define DAC2_CHANNEL_1 DAC_CHANNEL_1 +#define DAC_WAVE_NONE ((uint32_t)0x00000000) +#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0) +#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) +#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE +#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE +#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE + +/** + * @} + */ + + +/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD +#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD +#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS +#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES +#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES +#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE +#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE +#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE +#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE +#define OBEX_PCROP OPTIONBYTE_PCROP +#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG +#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE +#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE +#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE +#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD +#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD +#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD +#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD +#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE +#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD +#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#define PAGESIZE FLASH_PAGE_SIZE +#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE +#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD +#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD +#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 +#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 +#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 +#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 +#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST +#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST +#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA +#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB +#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA +#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB +#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE +#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN +#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE +#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN +#define IS_NBSECTORS IS_FLASH_NBSECTORS +#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE +#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD +#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP +#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV +#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR +#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG +#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA +#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE +#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS +#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS +#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST +#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR +#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO +#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION +#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS + +/** + * @} + */ + +/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose + * @{ + */ + +#define SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 +#define SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 +#define SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 +#define SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 + +/** + * @} + */ + + +/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef +#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef +/** + * @} + */ + +/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose + * @{ + */ +#define GET_GPIO_SOURCE GPIO_GET_INDEX +#define GET_GPIO_INDEX GPIO_GET_INDEX +/** + * @} + */ + + +/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE +#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE +#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE +#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE +#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE +#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE +#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE +#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose + * @{ + */ +#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE +#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define KR_KEY_RELOAD IWDG_KEY_RELOAD +#define KR_KEY_ENABLE IWDG_KEY_ENABLE +#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE +#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE +/** + * @} + */ + +/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose + * @{ + */ + +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION +#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS +#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS + +#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING +#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING +#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING +/** + * @} + */ + +/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose + * @{ + */ +#define NAND_AddressTypedef NAND_AddressTypeDef + +/** + * @} + */ + +/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose + * @{ + */ +#define NOR_StatusTypedef HAL_NOR_StatusTypeDef +#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS +#define NOR_ONGOING HAL_NOR_STATUS_ONGOING +#define NOR_ERROR HAL_NOR_STATUS_ERROR +#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT + +/** + * @} + */ + +/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose + * @{ + */ + +#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 +#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 +#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 +#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 + +#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 +#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 +#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 +#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 + +#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 +#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 + +#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 +#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 + +#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO +#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 +#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 + +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +/** + * @} + */ + +/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose + * @{ + */ + +/* Compact Flash-ATA registers description */ +#define CF_DATA ATA_DATA +#define CF_SECTOR_COUNT ATA_SECTOR_COUNT +#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER +#define CF_CYLINDER_LOW ATA_CYLINDER_LOW +#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH +#define CF_CARD_HEAD ATA_CARD_HEAD +#define CF_STATUS_CMD ATA_STATUS_CMD +#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE +#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA + +/* Compact Flash-ATA commands */ +#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD +#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD +#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD +#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD + +#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef +#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS +#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING +#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR +#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose + * @{ + */ + +#define FORMAT_BIN RTC_FORMAT_BIN +#define FORMAT_BCD RTC_FORMAT_BCD + +#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE + +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE +#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE +#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE +#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE +#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT +#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT + +/** + * @} + */ + + +/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE +#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE + +#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE +#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE +#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE + +#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE +#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE + +#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE +#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE +/** + * @} + */ + + + /** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose + * @{ + */ +#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE +#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE +#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE +#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE +#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE +#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE +#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE +#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE +#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN +/** + * @} + */ + + /** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose + * @{ + */ +#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE +#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE + +#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE +#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE + +#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE +#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE + +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose + * @{ + */ +#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK +#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK + +#define TIM_DMABase_CR1 TIM_DMABASE_CR1 +#define TIM_DMABase_CR2 TIM_DMABASE_CR2 +#define TIM_DMABase_SMCR TIM_DMABASE_SMCR +#define TIM_DMABase_DIER TIM_DMABASE_DIER +#define TIM_DMABase_SR TIM_DMABASE_SR +#define TIM_DMABase_EGR TIM_DMABASE_EGR +#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 +#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 +#define TIM_DMABase_CCER TIM_DMABASE_CCER +#define TIM_DMABase_CNT TIM_DMABASE_CNT +#define TIM_DMABase_PSC TIM_DMABASE_PSC +#define TIM_DMABase_ARR TIM_DMABASE_ARR +#define TIM_DMABase_RCR TIM_DMABASE_RCR +#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 +#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 +#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 +#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 +#define TIM_DMABase_BDTR TIM_DMABASE_BDTR +#define TIM_DMABase_DCR TIM_DMABASE_DCR +#define TIM_DMABase_DMAR TIM_DMABASE_DMAR +#define TIM_DMABase_OR1 TIM_DMABASE_OR1 +#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 +#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 +#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 +#define TIM_DMABase_OR2 TIM_DMABASE_OR2 +#define TIM_DMABase_OR3 TIM_DMABASE_OR3 + +#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE +#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 +#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 +#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 +#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 +#define TIM_EventSource_COM TIM_EVENTSOURCE_COM +#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER +#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK +#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 + +#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER +#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS +#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS +#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS +#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS +#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS +#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS +#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS +#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS +#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS +#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS +#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS +#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS +#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS +#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS +#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS +#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS +#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose + * @{ + */ +#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE +#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE +#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE + +#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE +#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE + +#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 +#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 +#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 +#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 + +#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 +#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 +#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 +#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 + +#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE +#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose + * @{ + */ + +#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE +#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE + +#define USARTNACK_ENABLED USART_NACK_ENABLE +#define USARTNACK_DISABLED USART_NACK_DISABLE +/** + * @} + */ + +/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose + * @{ + */ +#define CFR_BASE WWDG_CFR_BASE + +/** + * @} + */ + +/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose + * @{ + */ +#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 +#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME +#define INAK_TIMEOUT CAN_TIMEOUT_VALUE +#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE +#define CAN_TXSTATUS_FAILED ((uint8_t)0x00) +#define CAN_TXSTATUS_OK ((uint8_t)0x01) +#define CAN_TXSTATUS_PENDING ((uint8_t)0x02) + +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose + * @{ + */ + +#define VLAN_TAG ETH_VLAN_TAG +#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD +#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD +#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD +#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK +#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK +#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK +#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK + +#define ETH_MMCCR ((uint32_t)0x00000100) +#define ETH_MMCRIR ((uint32_t)0x00000104) +#define ETH_MMCTIR ((uint32_t)0x00000108) +#define ETH_MMCRIMR ((uint32_t)0x0000010C) +#define ETH_MMCTIMR ((uint32_t)0x00000110) +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) +#define ETH_MMCTGFCR ((uint32_t)0x00000168) +#define ETH_MMCRFCECR ((uint32_t)0x00000194) +#define ETH_MMCRFAECR ((uint32_t)0x00000198) +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) + +/** + * @} + */ + +/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ + +/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose + * @{ + */ + +#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish +#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish +#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish +#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish + +/*HASH Algorithm Selection*/ + +#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 +#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 +#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 +#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 + +#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH +#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC + +#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY +#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY +/** + * @} + */ + +/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode +#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode +#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode +#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode +#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode +#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode +#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) +#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect +#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) +#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) +#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) +#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose + * @{ + */ +#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram +#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown +#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock +#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock +#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase +#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program + + /** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter +#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter + +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) + /** + * @} + */ + +/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose + * @{ + */ +#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD +#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg +#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown +#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor +#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg +#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown +#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor +#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler +#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD +#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler +#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback +#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive +#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive +#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC +#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC +#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM + +#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL +#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING +#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING +#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING +#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING +#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING +#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING + +#define CR_OFFSET_BB PWR_CR_OFFSET_BB +#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB + +#define DBP_BitNumber DBP_BIT_NUMBER +#define PVDE_BitNumber PVDE_BIT_NUMBER +#define PMODE_BitNumber PMODE_BIT_NUMBER +#define EWUP_BitNumber EWUP_BIT_NUMBER +#define FPDS_BitNumber FPDS_BIT_NUMBER +#define ODEN_BitNumber ODEN_BIT_NUMBER +#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER +#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER +#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER +#define BRE_BitNumber BRE_BIT_NUMBER + +#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL + + /** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt +#define HAL_TIM_DMAError TIM_DMAError +#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt +#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose + * @{ + */ +#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback +/** + * @} + */ + + + /** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +/* Exported macros ------------------------------------------------------------*/ + +/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose + * @{ + */ +#define AES_IT_CC CRYP_IT_CC +#define AES_IT_ERR CRYP_IT_ERR +#define AES_FLAG_CCF CRYP_FLAG_CCF +/** + * @} + */ + +/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE +#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH +#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH +#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM +#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC +#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM +#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC +#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI +#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK +#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG +#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG +#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE +#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE + +#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY +#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 +#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS +#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER +#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER + +/** + * @} + */ + + +/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __ADC_ENABLE __HAL_ADC_ENABLE +#define __ADC_DISABLE __HAL_ADC_DISABLE +#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS +#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS +#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE +#define __ADC_IS_ENABLED ADC_IS_ENABLE +#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR +#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR +#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED +#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING +#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE + +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR_RK ADC_JSQR_RK +#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT +#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR +#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION +#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE +#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS +#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM +#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT +#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS +#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN +#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ +#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET +#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET +#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL +#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL +#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET +#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET +#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD + +#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION +#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION +#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER +#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI +#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE +#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER +#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER +#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE + +#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT +#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT +#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL +#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM +#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET +#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE +#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE +#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER + +#define __HAL_ADC_SQR1 ADC_SQR1 +#define __HAL_ADC_SMPR1 ADC_SMPR1 +#define __HAL_ADC_SMPR2 ADC_SMPR2 +#define __HAL_ADC_SQR3_RK ADC_SQR3_RK +#define __HAL_ADC_SQR2_RK ADC_SQR2_RK +#define __HAL_ADC_SQR1_RK ADC_SQR1_RK +#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS +#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS +#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV +#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection +#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq +#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION +#define __HAL_ADC_JSQR ADC_JSQR + +#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL +#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS +#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF +#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT +#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS +#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN +#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR +#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT +#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT +#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT +#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE + +/** + * @} + */ + +/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 +#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 +#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 +#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 +#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 +#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 +#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 +#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 +#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 +#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 +#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 +#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 +#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 +#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 +#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 +#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 + +#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 +#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 +#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 +#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 +#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 +#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 +#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 +#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 +#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 +#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 +#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 +#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 +#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 +#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 + + +#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 +#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 +#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 +#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 +#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 +#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 +#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC +#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC +#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG +#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG +#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG +#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG +#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT +#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT +#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT +#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT +#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT +#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT +#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 +#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 +#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 +#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 +#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 +#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 + +/** + * @} + */ + +/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) +#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_ENABLE_IT()) +#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ + __HAL_COMP_COMP2_EXTI_DISABLE_IT()) +#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ + __HAL_COMP_COMP2_EXTI_GET_FLAG()) +#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) +#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE + +/** + * @} + */ + +/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ + ((WAVE) == DAC_WAVE_NOISE)|| \ + ((WAVE) == DAC_WAVE_TRIANGLE)) + +/** + * @} + */ + +/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_WRPAREA IS_OB_WRPAREA +#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM +#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM +#define IS_TYPEERASE IS_FLASH_TYPEERASE + +/** + * @} + */ + +/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 +#define __HAL_I2C_GENERATE_START I2C_GENERATE_START +#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE +#define __HAL_I2C_RISE_TIME I2C_RISE_TIME +#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD +#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST +#define __HAL_I2C_SPEED I2C_SPEED +#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE +#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ +#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS +#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE +#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ +#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB +#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB +#define __HAL_I2C_FREQRANGE I2C_FREQRANGE +/** + * @} + */ + +/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose + * @{ + */ + +#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE +#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT + +/** + * @} + */ + +/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __IRDA_DISABLE __HAL_IRDA_DISABLE +#define __IRDA_ENABLE __HAL_IRDA_ENABLE + +#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION +#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE +#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION + +#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE + + +/** + * @} + */ + + +/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS +#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS +/** + * @} + */ + + +/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT +#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT +#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE + +/** + * @} + */ + + +/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose + * @{ + */ +#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD +#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX +#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX +#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX +#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX +#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L +#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H +#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM +#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES +#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX +#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT +#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION +#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET + +/** + * @} + */ + + +/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE +#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE +#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE +#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine +#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig +#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() +#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT +#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE +#define __HAL_PWR_PVM_DISABLE() HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4() +#define __HAL_PWR_PVM_ENABLE() HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4() +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention +#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention +#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 +#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 +#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE +#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE +#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB +#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB + +#if defined (STM32F4) +#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() +#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() +#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() +#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() +#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() +#else +#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG +#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT +#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT +#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT +#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG +#endif /* STM32F4 */ +/** + * @} + */ + + +/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose + * @{ + */ + +#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI +#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI + +#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) + +#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE +#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE +#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE +#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE +#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET +#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET +#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE +#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE +#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET +#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET +#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE +#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE +#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE +#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE +#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET +#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET +#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE +#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE +#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET +#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET +#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE +#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE +#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE +#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE +#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET +#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET +#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE +#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE +#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE +#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET +#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE +#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE +#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET +#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET +#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET +#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET +#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET +#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET +#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET +#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET +#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET +#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET +#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET +#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET +#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET +#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE +#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE +#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET +#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET +#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE +#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE +#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE +#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE +#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET +#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET +#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE +#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE +#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET +#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET +#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE +#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE +#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE +#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE +#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET +#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET +#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE +#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE +#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET +#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET +#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE +#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE +#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE +#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE +#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET +#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET +#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE +#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE +#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET +#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET +#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE +#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE +#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE +#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE +#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET +#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET +#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE +#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE +#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE +#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE +#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET +#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET +#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE +#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE +#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE +#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE +#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET +#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET +#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE +#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE +#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE +#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE +#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET +#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET +#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE +#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE +#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET +#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET +#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE +#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE +#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE +#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE +#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE +#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE +#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE +#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE +#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE +#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE +#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET +#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET +#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE +#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE +#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET +#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET +#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE +#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE +#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE +#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE +#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE +#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE +#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET +#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET +#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE +#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE +#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE +#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE +#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE +#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE +#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET +#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET +#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE +#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE +#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE +#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE +#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET +#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET +#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE +#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE +#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE +#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE +#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET +#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET +#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE +#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE +#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE +#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE +#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET +#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET +#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE +#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE +#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE +#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE +#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET +#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET +#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE +#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE +#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE +#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE +#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET +#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET +#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE +#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE +#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE +#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE +#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET +#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET +#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE +#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE +#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE +#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE +#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET +#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET +#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE +#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE +#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE +#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE +#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET +#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET +#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE +#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE +#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE +#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE +#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET +#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET +#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE +#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE +#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE +#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE +#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET +#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET +#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE +#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE +#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE +#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE +#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET +#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET +#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE +#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE +#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE +#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE +#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET +#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET +#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE +#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE +#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE +#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE +#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET +#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET +#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE +#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE +#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE +#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE +#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET +#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET +#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE +#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE +#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE +#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE +#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET +#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET +#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE +#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE +#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE +#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE +#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET +#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET +#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE +#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE +#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE +#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE +#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET +#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET +#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE +#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE +#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE +#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE +#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET +#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET +#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE +#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE +#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE +#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE +#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET +#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET +#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE +#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE +#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE +#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE +#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET +#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET +#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE +#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE +#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE +#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE +#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET +#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET +#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE +#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE +#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE +#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE +#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE +#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE +#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET +#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET +#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE +#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE +#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE +#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE +#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET +#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET +#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE +#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE +#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE +#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE +#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET +#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET +#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE +#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE +#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE +#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE +#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET +#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET +#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE +#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE +#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE +#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE +#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE +#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE +#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE +#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE +#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE +#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE +#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET +#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET +#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE +#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE +#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE +#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE +#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET +#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET +#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE +#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE +#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE +#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE +#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET +#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET +#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE +#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE +#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET +#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET +#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE +#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE +#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET +#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET +#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE +#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE +#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET +#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET +#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE +#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE +#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET +#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET +#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE +#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE +#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET +#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET +#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE +#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE +#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE +#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE +#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET +#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET +#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE +#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE +#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE +#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE +#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET +#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET +#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE +#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE +#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE +#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE +#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET +#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET +#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE +#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE +#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE +#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE +#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET +#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET +#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE +#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE +#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE +#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE +#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET +#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET +#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE +#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE +#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE +#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE +#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET +#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET +#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE +#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE +#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE +#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE +#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET +#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET +#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE +#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE +#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE +#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE +#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET +#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET +#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE +#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE +#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE +#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE +#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET +#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET +#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE +#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE +#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE +#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE +#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET +#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET +#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE +#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE +#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET +#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET +#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE +#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE +#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE +#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE +#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET +#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET +#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE +#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE +#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE +#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE +#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET +#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET +#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE +#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE +#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE +#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE +#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET +#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET +#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE +#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE +#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE +#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE +#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET +#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET +#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE +#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE +#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE +#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE +#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET +#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET +#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE +#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE +#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE +#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE +#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET +#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET +#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE +#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE +#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET +#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE +#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE +#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE +#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE +#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET +#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE +#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE +#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE +#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE +#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET +#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET +#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE +#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE +#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET +#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET +#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE +#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE +#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE +#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE +#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET +#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET +#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE +#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE +#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE +#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE +#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE +#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE +#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET +#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET +#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE +#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE + +#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET +#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE +#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE +#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE +#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE +#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE +#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE +#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE +#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE +#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE +#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE +#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE +#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE +#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE +#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE +#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE +#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET +#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET +#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE +#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE +#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE +#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE +#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE +#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET +#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET +#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE +#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE +#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE +#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE +#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET +#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET +#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE +#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE +#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE +#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE +#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET +#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET +#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE +#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE +#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE +#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE +#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE +#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE +#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE +#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE +#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE +#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE +#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE +#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE +#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE +#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE +#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE +#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE +#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE +#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE +#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE +#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE +#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET +#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET +#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE +#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE +#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE +#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE +#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET +#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET +#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE +#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE +#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE +#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE +#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET +#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET +#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE +#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE +#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE +#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE +#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET +#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET +#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE +#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE +#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE +#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE +#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET +#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE +#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE +#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE +#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE +#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE +#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE +#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET +#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET +#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE +#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE +#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE +#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE +#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET +#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET +#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE +#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE +#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE +#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE +#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET +#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET +#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE +#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE +#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE +#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE +#define __OTGHS_FORCE_RESET __HAL_RCC_OTGHS_FORCE_RESET +#define __OTGHS_RELEASE_RESET __HAL_RCC_OTGHS_RELEASE_RESET +#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE +#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE +#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET +#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE +#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE +#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE +#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE +#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE +#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE +#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE +#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE +#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET +#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET +#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE +#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE +#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET +#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET +#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE +#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE +#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE +#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET +#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET +#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE +#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE + +/* alias define maintained for legacy */ +#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET +#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET + +#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG +#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG + +#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE + +#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE +#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE +#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK +#define IS_RCC_HCLK_DIV IS_RCC_PCLK + +#define RCC_MCO_NODIV RCC_MCODIV_1 + +#define HSION_BitNumber RCC_HSION_BIT_NUMBER +#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER +#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER +#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER +#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER +#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER +#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER +#define LSION_BitNumber RCC_LSION_BIT_NUMBER +#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER +#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER + +#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS +#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS +#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS +#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS +#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE +#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE + +#define CR_HSION_BB RCC_CR_HSION_BB +#define CR_CSSON_BB RCC_CR_CSSON_BB +#define CR_PLLON_BB RCC_CR_PLLON_BB +#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB +#define CR_MSION_BB RCC_CR_MSION_BB +#define CSR_LSION_BB RCC_CSR_LSION_BB +#define CSR_LSEON_BB RCC_CSR_LSEON_BB +#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB +#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB +#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB +#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB +#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB +#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB +#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB +#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB + +/** + * @} + */ + +/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose + * @{ + */ +#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) + +/** + * @} + */ + +/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT +#if defined (RTC_EXTI_LINE_WAKEUPTIMER_EVENT) +#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ +((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) +#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ + ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) +#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ + ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) +#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ + ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) +#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) ((__EXTI_LINE__ == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ + ((__EXTI_LINE__ == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) + +#else +#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() + +#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() + +#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() + +#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() + +#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() + +#endif + +#define IS_ALARM IS_RTC_ALARM +#define IS_ALARM_MASK IS_RTC_ALARM_MASK +#define IS_TAMPER IS_RTC_TAMPER +#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE +#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER +#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT +#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE +#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION +#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE +#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ +#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION +#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER +#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK +#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER + +#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE +#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE + +/** + * @} + */ + +/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE +#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS + +/** + * @} + */ + +/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT +#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT +#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE +#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE +#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE +#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE + +#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE +#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE + +#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE + +/** + * @} + */ + +/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 +#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 +#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START +#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH +#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR +#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE +#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE +#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED +/** + * @} + */ + +/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_SPI_1LINE_TX SPI_1LINE_TX +#define __HAL_SPI_1LINE_RX SPI_1LINE_RX +#define __HAL_SPI_RESET_CRC SPI_RESET_CRC + +/** + * @} + */ + +/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION +#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE +#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION + +#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD + +#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE +#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE + +/** + * @} + */ + + +/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT +#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT +#define __USART_ENABLE __HAL_USART_ENABLE +#define __USART_DISABLE __HAL_USART_DISABLE + +#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE +#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE + +/** + * @} + */ + +/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose + * @{ + */ +#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE + +#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE +#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE +#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE + +#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE +#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE +#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE +#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE + +#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE + +#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT + +#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT +#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT +#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG +#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE +#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE +#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT + +#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup +#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup + +#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo +#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +/** + * @} + */ + +/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE +#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE + +#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE +#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT + +#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN +#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER +#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER +#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER +#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD +#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD +#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION +#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION +#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER +#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER +#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE +#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE + +#define TIM_TS_ITR0 ((uint32_t)0x0000) +#define TIM_TS_ITR1 ((uint32_t)0x0010) +#define TIM_TS_ITR2 ((uint32_t)0x0020) +#define TIM_TS_ITR3 ((uint32_t)0x0030) +#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ + ((SELECTION) == TIM_TS_ITR1) || \ + ((SELECTION) == TIM_TS_ITR2) || \ + ((SELECTION) == TIM_TS_ITR3)) + +#define TIM_CHANNEL_1 ((uint32_t)0x0000) +#define TIM_CHANNEL_2 ((uint32_t)0x0004) +#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)) + +#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) + +#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ + ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) + +#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) +#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) + +#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ + ((STATE) == TIM_OUTPUTSTATE_ENABLE)) +/** + * @} + */ + +/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose + * @{ + */ + +#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT +#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT +#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG +#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG +#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER +#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER + +#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE +#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE +#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE +/** + * @} + */ + +/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose + * @{ + */ +#define __HAL_LTDC_LAYER LTDC_LAYER +/** + * @} + */ + +/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose + * @{ + */ +#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE +#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE +#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE +#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE +#define SAI_STREOMODE SAI_STEREOMODE +#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY +#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL +#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL +#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL +#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL +#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL +#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE + +/** + * @} + */ + + +/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose + * @{ + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* ___STM32_HAL_LEGACY */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.c index 25d751c2098..5efcb67b22f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief HAL module driver. * This is the common part of the HAL initialization * @@ -15,7 +15,7 @@ The common HAL driver contains a set of generic and common APIs that can be used by the PPP peripheral drivers and the user to start using the HAL. [..] - The HAL contains two APIs' categories: + The HAL contains two APIs categories: (+) Common HAL APIs (+) Services HAL APIs @@ -23,7 +23,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -57,20 +57,33 @@ * @{ */ -/** @defgroup HAL +/** @addgroup HAL * @brief HAL module driver. * @{ */ - #ifdef HAL_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ + +/** @addtogroup HAL_Exported_Constants + * + * @{ + */ + +/** @defgroup HAL_Version HAL Version + * @{ + */ +#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) +#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_MEM_MODE_0) +#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE) + + +#define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ + /** - * @brief STM32L0xx HAL Driver version number V1.1.0 + * @brief STM32L0xx HAL Driver version number V1.2.0 */ #define __STM32L0xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32L0xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */ +#define __STM32L0xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */ #define __STM32L0xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ #define __STM32L0xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */ #define __STM32L0xx_HAL_VERSION ((__STM32L0xx_HAL_VERSION_MAIN << 24)\ @@ -79,17 +92,28 @@ |(__STM32L0xx_HAL_VERSION_RC)) #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ +/** @defgroup HAL_Private_Data + * @{ + */ static __IO uint32_t uwTick; -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup HAL_Private_Functions +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions HAL Exported Functions * @{ */ -/** @defgroup HAL_Group1 Initialization and de-initialization Functions +/** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions * @brief Initialization and de-initialization functions * @verbatim @@ -116,7 +140,7 @@ static __IO uint32_t uwTick; peripheral ISR process, the Tick interrupt line must have higher priority (numerically lower) than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - (++) functions affecting time base configurations are declared as __Weak + (++) functions affecting time base configurations are declared as __weak to make override possible in case of other implementations in user file. @endverbatim @@ -171,17 +195,17 @@ HAL_StatusTypeDef HAL_Init(void) HAL_StatusTypeDef HAL_DeInit(void) { /* Reset of all peripherals */ - __APB1_FORCE_RESET(); - __APB1_RELEASE_RESET(); + __HAL_RCC_APB1_FORCE_RESET(); + __HAL_RCC_APB1_RELEASE_RESET(); - __APB2_FORCE_RESET(); - __APB2_RELEASE_RESET(); + __HAL_RCC_APB2_FORCE_RESET(); + __HAL_RCC_APB2_RELEASE_RESET(); - __AHB_FORCE_RESET(); - __AHB_RELEASE_RESET(); + __HAL_RCC_AHB_FORCE_RESET(); + __HAL_RCC_AHB_RELEASE_RESET(); - __IOP_FORCE_RESET(); - __IOP_RELEASE_RESET(); + __HAL_RCC_IOP_FORCE_RESET(); + __HAL_RCC_IOP_RELEASE_RESET(); /* De-Init the low level hardware */ HAL_MspDeInit(); @@ -214,9 +238,6 @@ __weak void HAL_MspDeInit(void) */ } -/** - * @} - */ /** * @brief This function configures the source of the time base. @@ -246,8 +267,12 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) return HAL_OK; } -/** @defgroup HAL_Group2 HAL Control functions - * @brief HAL Control functions +/** + * @} + */ + +/** @addtogroup HAL_Exported_Functions_Group2 + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -262,6 +287,7 @@ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) (+) Get the device identifier (+) Get the device revision identifier (+) Configures low power mode behavior when the MCU is in Debug mode + (+) Manages the VEREFINT feature (activation, lock, output selection) @endverbatim * @{ @@ -295,8 +321,7 @@ __weak uint32_t HAL_GetTick(void) } /** - * @brief This function provides accurate delay (in milliseconds) based - * on variable incremented. + * @brief This function provides accurate delay (in ms) based on a variable incremented. * @note In the default implementation , SysTick timer is the source of time base. * It is used to generate interrupts at regular time intervals where uwTick * is incremented. @@ -383,7 +408,7 @@ uint32_t HAL_GetDEVID(void) * @param None * @retval None */ -void HAL_EnableDBGSleepMode(void) +void HAL_DBGMCU_EnableDBGSleepMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } @@ -393,7 +418,7 @@ void HAL_EnableDBGSleepMode(void) * @param None * @retval None */ -void HAL_DisableDBGSleepMode(void) +void HAL_DBGMCU_DisableDBGSleepMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); } @@ -403,7 +428,7 @@ void HAL_DisableDBGSleepMode(void) * @param None * @retval None */ -void HAL_EnableDBGStopMode(void) +void HAL_DBGMCU_EnableDBGStopMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } @@ -413,7 +438,7 @@ void HAL_EnableDBGStopMode(void) * @param None * @retval None */ -void HAL_DisableDBGStopMode(void) +void HAL_DBGMCU_DisableDBGStopMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); } @@ -423,7 +448,7 @@ void HAL_DisableDBGStopMode(void) * @param None * @retval None */ -void HAL_EnableDBGStandbyMode(void) +void HAL_DBGMCU_EnableDBGStandbyMode(void) { SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } @@ -433,32 +458,41 @@ void HAL_EnableDBGStandbyMode(void) * @param None * @retval None */ -void HAL_DisableDBGStandbyMode(void) +void HAL_DBGMCU_DisableDBGStandbyMode(void) { CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); } /** - * @brief Configures low power mode behavior when the MCU is in Debug mode. + * @brief Enable low power mode behavior when the MCU is in Debug mode. * @param Periph: specifies the low power mode. * This parameter can be any combination of the following values: * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode * @arg DBGMCU_STOP: Keep debugger connection during STOP mode * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode - * @param NewState: new state of the specified low power mode in Debug mode. - * This parameter can be: ENABLE or DISABLE. * @retval None */ -void HAL_DBG_LowPowerConfig(uint32_t Periph, FunctionalState NewState) +void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph) +{ + /* Check the parameters */ + assert_param(IS_DBGMCU_PERIPH(Periph)); + + DBGMCU->CR |= Periph; + +} +/** + * @brief Disable low power mode behavior when the MCU is in Debug mode. + * @param Periph: specifies the low power mode. + * This parameter can be any combination of the following values: + * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode + * @arg DBGMCU_STOP: Keep debugger connection during STOP mode + * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode + * @retval None + */ +void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph) { /* Check the parameters */ assert_param(IS_DBGMCU_PERIPH(Periph)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - if (NewState != DISABLE) - { - DBGMCU->CR |= Periph; - } - else { DBGMCU->CR &= ~Periph; } @@ -473,78 +507,40 @@ void HAL_DBG_LowPowerConfig(uint32_t Periph, FunctionalState NewState) * - 0x00000100: Boot is configured in System Flash memory * - 0x00000300: Boot is configured in Embedded SRAM memory */ -uint32_t HAL_GetBootMode(void) +uint32_t HAL_SYSCFG_GetBootMode(void) { return (SYSCFG->CFGR1 & SYSCFG_CFGR1_BOOT_MODE); } /** - * @brief Configures the I2C fast mode plus driving capability. - * @param SYSCFG_I2CFastModePlus: selects the pin. - * This parameter can be one of the following values: - * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6 - * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7 - * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8 - * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9 - * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for I2C1 pins - * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins - * @param NewState: This parameter can be: - * ENABLE: Enable fast mode plus driving capability for selected I2C pin - * DISABLE: Disable fast mode plus driving capability for selected I2C pin - * @note For I2C1, fast mode plus driving capability can be enabled on all selected - * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently - * on each one of the following pins PB6, PB7, PB8 and PB9. - * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability - * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter. - * @note For all I2C2 pins fast mode plus driving capability can be enabled - * only by using SYSCFG_I2CFastModePlus_I2C2 parameter. + * @brief Enables the VREFINT. + * @param None * @retval None */ -void HAL_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState) +void HAL_SYSCFG_EnableVREFINT(void) { - /* Check the parameters */ - assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable fast mode plus driving capability for selected pin */ - SYSCFG->CFGR2 |= (uint32_t)SYSCFG_I2CFastModePlus; - } - else - { - /* Disable fast mode plus driving capability for selected pin */ - SYSCFG->CFGR2 &= (uint32_t)(~SYSCFG_I2CFastModePlus); - } + /* Enable the VREFINT by setting EN_VREFINT bit in the CFGR3 register */ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_EN_VREFINT); } /** - * @brief Enables or disables the VREFINT. - * @param NewState: new state of the Vrefint. - * This parameter can be: ENABLE or DISABLE. + * @brief Disables the VREFINT. + * @param None. * @retval None */ -void HAL_VREFINT_Cmd(FunctionalState NewState) +void HAL_SYSCFG_DisableVREFINT(void) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the VREFINT by setting EN_VREFINT bit in the CFGR3 register */ - SYSCFG->CFGR3 |= SYSCFG_CFGR3_EN_VREFINT; - } - else - { /* Disable the VREFINT by setting EN_VREFINT bit in the CFGR3 register */ - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)SYSCFG_CFGR3_EN_VREFINT); - } + CLEAR_BIT(SYSCFG->CFGR3,SYSCFG_CFGR3_EN_VREFINT); } - /** * @brief Selects the output of internal reference voltage (VREFINT). * The VREFINT output can be routed to(PB0) or * (PB1) or both. + * @note Kept for backward compatibility + * We recommend to use the MACRO + * __HAL_SYSCFG_VREFINT_OUTPUT_SELECT(__VREFINT_OUTPUT__) + * rather than this function * @param SYSCFG_Vrefint_OUTPUT: new state of the Vrefint output. * This parameter can be one of the following values: * @arg SYSCFG_VREFINT_OUT_NONE @@ -553,7 +549,7 @@ void HAL_VREFINT_Cmd(FunctionalState NewState) * @arg SYSCFG_VREFINT_OUT_PB0_PB1 * @retval None */ -void HAL_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT) +void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT) { /* Check the parameters */ assert_param(IS_SYSCFG_VREFINT_OUT_SELECT(SYSCFG_Vrefint_OUTPUT)); @@ -564,122 +560,23 @@ void HAL_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT) } /** - * @brief Enables or disables the Buffer Vrefint for the ADC. - * @param NewState: new state of the Vrefint. - * This parameter can be: ENABLE or DISABLE. - * @note This is functional only if the LOCK is not set - * @retval None - */ -void HAL_ADC_EnableBuffer_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_VREFINT_ADC in the CFGR3 register */ - SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT); - } - else - { - /* Disable the Vrefint by resetting ENBUF_BGAP_ADC bit and the EN_VREFINT bit in the CFGR3 register */ - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT)); - } -} - -/** - * @brief Enables or disables the Buffer Sensor for the ADC. - * @param NewState: new state of the Vrefint. - * This parameter can be: ENABLE or DISABLE. - * @note This is functional only if the LOCK is not set. - * @retval None - */ -void HAL_ADC_EnableBufferSensor_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ - SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT); - } - else - { - /* Disable the Vrefint by resetting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT)); - } -} - -/** - * @brief Enables or disables the Buffer Vrefint for the COMP. - * @param NewState: new state of the Vrefint. - * This parameter can be: ENABLE or DISABLE. - * @note This is functional only if the LOCK is not set - * @retval None - */ -void HAL_COMP_EnableBuffer_Cmd(FunctionalState NewState) -{ - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Buffer for the COMP by setting EN_VREFINT bit and the ENBUFLP_VREFINT_COMP in the CFGR3 register */ - SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT); - } - else - { - /* Disable the Vrefint by resetting ENBUFLP_BGAP_COMP bit and the EN_VREFINT bit in the CFGR3 register */ - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT)); - } -} - -/** - * @brief Enables or disables the Buffer Vrefint for the RC48. - * @param NewState: new state of the Vrefint. - * This parameter can be: ENABLE or DISABLE. - * @note This is functional only if the LOCK is not set + * @brief Lock the SYSCFG VREF register values * @retval None */ -void HAL_RC48_EnableBuffer_Cmd(FunctionalState NewState) +void HAL_SYSCFG_Enable_Lock_VREFINT(void) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the SYSCFG_CFGR3_ENREF_HSI48 in the CFGR3 register */ - SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); - } - else - { - /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit and the EN_VREFINT bit in the CFGR3 register */ - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); - } + /* Enable the LOCK by setting REF_LOCK bit in the CFGR3 register */ + SET_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); } /** - * @brief Enables or disables the Lock. - * @param NewState: new state of the Lock. - * This parameter can be: ENABLE or DISABLE. + * @brief Unlock the overall SYSCFG VREF register values * @retval None */ -void HAL_Lock_Cmd(FunctionalState NewState) +void HAL_SYSCFG_Disable_Lock_VREFINT(void) { - /* Check the parameters */ - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - if (NewState != DISABLE) - { - /* Enable the LOCK by setting REF_LOCK bit in the CFGR3 register */ - SYSCFG->CFGR3 |= SYSCFG_CFGR3_REF_LOCK; - } - else - { /* Disable the LOCK by setting REF_LOCK bit in the CFGR3 register */ - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)SYSCFG_CFGR3_REF_LOCK); - } + CLEAR_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_REF_LOCK); } /** @@ -700,3 +597,4 @@ void HAL_Lock_Cmd(FunctionalState NewState) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.h index f5c73d14058..719aff1abc2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l0xx_hal.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief This file contains all the functions prototypes for the HAL * module driver. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -51,50 +51,55 @@ * @{ */ -/** @addtogroup HAL +/** @defgroup HAL HAL + * @{ + */ +/** @defgroup HAL_Exported_Constants HAL Exported constants * @{ */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Constants +/** @defgroup SYSCFG_BootMode Boot Mode * @{ + */ +#define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) +#define SYSCFG_BOOT_SYSTEMFLASH ((uint32_t)SYSCFG_CFGR1_MEM_MODE_0) +#define SYSCFG_BOOT_SRAM ((uint32_t)SYSCFG_CFGR1_BOOT_MODE) + +/** + * @} */ -/** @defgroup HAL_DBGMCU_Low_Power_Config +/** @defgroup DBGMCU_Low_Power_Config * @{ */ #define DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP #define DBGMCU_STOP DBGMCU_CR_DBG_STOP #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY -#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) +#define IS_DBGMCU_PERIPH(__PERIPH__) ((((__PERIPH__) & (~(DBGMCU_CR_DBG))) == 0x00) && ((__PERIPH__) != 0x00)) + /** * @} */ - -/** @defgroup HAL_SYSCFG_I2C_FastModePlus_Config +/** @defgroup HAL_SYSCFG_LCD_EXT_CAPA * @{ - */ -#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /* Enable Fast Mode Plus on PB6 */ -#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /* Enable Fast Mode Plus on PB7 */ -#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /* Enable Fast Mode Plus on PB8 */ -#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /* Enable Fast Mode Plus on PB9 */ -#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR2_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ -#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR2_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ - -#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \ - ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \ - ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \ - ((PIN) == SYSCFG_I2CFastModePlus_I2C2)) + */ +#define SYSCFG_LCD_EXT_CAPA SYSCFG_CFGR2_CAPA /*!< Connection of internal Vlcd rail to external capacitors */ +#define SYSCFG_VLCD_PB2_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_0 /*!< Connection on PB2 */ +#define SYSCFG_VLCD_PB12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_1 /*!< Connection on PB12 */ +#define SYSCFG_VLCD_PE11_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_2 /*!< Connection on PB0 */ +#if defined (SYSCFG_CFGR2_CAPA_3) +#define SYSCFG_VLCD_PB0_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_3 /*!< Connection on PE11 */ +#endif +#if defined (SYSCFG_CFGR2_CAPA_4) +#define SYSCFG_VLCD_PE12_EXT_CAPA_ON SYSCFG_CFGR2_CAPA_4 /*!< Connection on PE12 */ +#endif /** * @} - */ - + */ + /** @defgroup HAL_SYSCFG_VREFINT_OUT_SELECT * @{ */ @@ -103,10 +108,10 @@ #define SYSCFG_VREFINT_OUT_PB1 SYSCFG_CFGR3_VREF_OUT_1 /* Selects PB1 as output for the Vrefint */ #define SYSCFG_VREFINT_OUT_PB0_PB1 SYSCFG_CFGR3_VREF_OUT /* Selects PBO and PB1 as output for the Vrefint */ -#define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \ +#define IS_SYSCFG_VREFINT_OUT_SELECT(OUTPUT) (((OUTPUT) == SYSCFG_VREFINT_OUT_NONE) || \ + ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0) || \ ((OUTPUT) == SYSCFG_VREFINT_OUT_PB1) || \ ((OUTPUT) == SYSCFG_VREFINT_OUT_PB0_PB1)) - /** * @} */ @@ -114,73 +119,157 @@ /** @defgroup HAL_SYSCFG_flags_definition * @{ */ +#define SYSCFG_FLAG_VREFINT_READY SYSCFG_CFGR3_VREFINT_RDYF -#define SYSCFG_FLAG_RC48 SYSCFG_CFGR3_REF_HSI48_RDYF -#define SYSCFG_FLAG_SENSOR_ADC SYSCFG_CFGR3_SENSOR_ADC_RDYF -#define SYSCFG_FLAG_VREF_ADC SYSCFG_VREFINT_ADC_RDYF -#define SYSCFG_FLAG_VREF_COMP SYSCFG_CFGR3_VREFINT_COMP_RDYF -#define SYSCFG_FLAG_VREF_READY SYSCFG_CFGR3_VREFINT_RDYF - -#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_RC48) || \ - ((FLAG) == SYSCFG_FLAG_SENSOR_ADC) || \ - ((FLAG) == SYSCFG_FLAG_VREF_ADC) || \ - ((FLAG) == SYSCFG_FLAG_VREF_COMP) || \ - ((FLAG) == SYSCFG_FLAG_VREF_READY)) +#define IS_SYSCFG_FLAG(FLAG) ((FLAG) == SYSCFG_FLAG_VREFINT_READY)) /** * @} */ -/* Exported macro ------------------------------------------------------------*/ + /** + * @} + */ + + /** @defgroup HAL_Exported_Macros HAL Exported Macros + * @{ + */ /** @brief Freeze/Unfreeze Peripherals in Debug mode */ -#define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_STOP)) -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_STOP)) -#define __HAL_FREEZE_LPTIMER_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)) -#define __HAL_FREEZE_TIM22_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM22_STOP)) -#define __HAL_FREEZE_TIM21_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM21_STOP)) - -#define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) -#define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) -#define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) -#define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) -#define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_STOP)) -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_STOP)) -#define __HAL_UNFREEZE_LPTIMER_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_LPTIMER_STOP)) -#define __HAL_UNFREEZE_TIM22_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM22_STOP)) -#define __HAL_UNFREEZE_TIM21_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM21_STOP)) +#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP) +/** + * @brief TIM2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM2_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP) +/** + * @brief TIM3 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZ,DBGMCU_APB1_FZ_DBG_TIM3_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP) +/** + * @brief TIM6 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP) +/** + * @brief TIM7 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP) +/** + * @brief RTC Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) +#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP) +/** + * @brief WWDG Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP) +/** + * @brief IWDG Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_I2C1_STOP) +/** + * @brief I2C1 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_I2C2_STOP) +/** + * @brief I2C2 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT_DBGMCU() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT_DBGMCU() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_I2C3_STOP) +/** + * @brief I2C3 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) +#define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C3_STOP) +#endif + +#if defined (DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) +/** + * @brief LPTIMER Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_LPTIMER() SET_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) +#define __HAL_DBGMCU_UNFREEZE_LPTIMER() CLEAR_BIT(DBGMCU->APB1FZ ,DBGMCU_APB1_FZ_DBG_LPTIMER_STOP) +#endif + +#if defined (DBGMCU_APB2_FZ_DBG_TIM22_STOP) +/** + * @brief TIM22 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM22() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM22() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM22_STOP) +#endif + +#if defined (DBGMCU_APB2_FZ_DBG_TIM21_STOP) +/** + * @brief TIM21 Peripherals Debug mode + */ +#define __HAL_DBGMCU_FREEZE_TIM21() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) +#define __HAL_DBGMCU_UNFREEZE_TIM21() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM21_STOP) +#endif /** @brief Main Flash memory mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_FLASH (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) +#define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE) /** @brief System Flash memory mapped at 0x00000000 */ -#define __HAL_REMAPMEMORY_SYSTEMFLASH do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE);\ - SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0;\ - }while(0); +#define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0) + /** @brief Embedded SRAM mapped at 0x00000000 + */ +#define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1) + +/** @brief Configuration of the DBG Low Power mode. + * @param __DBGLPMODE__: bit field to indicate in wich Low Power mode DBG is still active. + * This parameter can be a value of @ref HAL_DBGMCU_Low_Power_Config */ -#define __HAL_REMAPMEMORY_SRAM do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE);\ - SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1);\ - }while(0); +#define __HAL_SYSCFG_DBG_LP_CONFIG(__DBGLPMODE__) do {assert_param(IS_DBGMCU_PERIPH(__DBGLPMODE__)); \ + MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG, (__DBGLPMODE__)); \ + } while (0) +/** + * @brief Returns the boot mode as configured by user. + * @retval The boot mode as configured by user. The returned can be a value of @ref HAL_SYSCFG_BootMode + */ +#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOT_MODE) + /** @brief Check whether the specified SYSCFG flag is set or not. * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * SYSCFG_FLAG_PE: SRAM parity error flag. - * @arg SYSCFG_FLAG_RC48 - * @arg SYSCFG_FLAG_SENSOR_ADC - * @arg SYSCFG_FLAG_VREF_ADC - * @arg SYSCFG_FLAG_VREF_COMP - * @arg SYSCFG_FLAG_VREF_READY + * This parameter can a value of @ref HAL_SYSCFG_flags_definition * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define __HAL_SYSCFG_GET_FLAG(__FLAG__) (((SYSCFG->CFGR3) & (__FLAG__)) == (__FLAG__)) @@ -188,16 +277,28 @@ /** * @} */ -/* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions ******************************/ +/** @defgroup HAL_Exported_Functions HAL Exported Functions + * @{ + */ +/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and de-initialization functions + * @{ + */ HAL_StatusTypeDef HAL_Init(void); HAL_StatusTypeDef HAL_DeInit(void); void HAL_MspInit(void); void HAL_MspDeInit(void); HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); -/* Peripheral Control functions ************************************************/ +/** + * @} + */ + + /** @defgroup HAL_Exported_Functions_Group2 Peripheral Control functions + * @brief Peripheral Control functions + * @{ + */ void HAL_IncTick(void); void HAL_Delay(__IO uint32_t Delay); uint32_t HAL_GetTick(void); @@ -206,22 +307,27 @@ void HAL_ResumeTick(void); uint32_t HAL_GetHalVersion(void); uint32_t HAL_GetREVID(void); uint32_t HAL_GetDEVID(void); -void HAL_EnableDBGSleepMode(void); -void HAL_DisableDBGSleepMode(void); -void HAL_EnableDBGStopMode(void); -void HAL_DisableDBGStopMode(void); -void HAL_EnableDBGStandbyMode(void); -void HAL_DisableDBGStandbyMode(void); -void HAL_DBG_LowPowerConfig(uint32_t Periph, FunctionalState NewState); -uint32_t HAL_GetBootMode(void); -void HAL_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState); -void HAL_VREFINT_Cmd(FunctionalState NewState); -void HAL_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); -void HAL_ADC_EnableBuffer_Cmd(FunctionalState NewState); -void HAL_ADC_EnableBufferSensor_Cmd(FunctionalState NewState); -void HAL_COMP_EnableBuffer_Cmd(FunctionalState NewState); -void HAL_RC48_EnableBuffer_Cmd(FunctionalState NewState); -void HAL_Lock_Cmd(FunctionalState NewState); +void HAL_DBGMCU_EnableDBGSleepMode(void); +void HAL_DBGMCU_DisableDBGSleepMode(void); +void HAL_DBGMCU_EnableDBGStopMode(void); +void HAL_DBGMCU_DisableDBGStopMode(void); +void HAL_DBGMCU_EnableDBGStandbyMode(void); +void HAL_DBGMCU_DisableDBGStandbyMode(void); +void HAL_DBGMCU_DBG_EnableLowPowerConfig(uint32_t Periph); +void HAL_DBGMCU_DBG_DisableLowPowerConfig(uint32_t Periph); +uint32_t HAL_SYSCFG_GetBootMode(void); +void HAL_SYSCFG_EnableVREFINT(void); +void HAL_SYSCFG_DisableVREFINT(void); +void HAL_SYSCFG_Enable_Lock_VREFINT(void); +void HAL_SYSCFG_Disable_Lock_VREFINT(void); +void HAL_SYSCFG_VREFINT_OutputSelect(uint32_t SYSCFG_Vrefint_OUTPUT); + +/** + * @} + */ +/** + * @} + */ /** * @} @@ -238,3 +344,4 @@ void HAL_Lock_Cmd(FunctionalState NewState); #endif /* __STM32L0xx_HAL_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.c index fb22a91ab6c..c552d572212 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_adc.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -72,12 +72,12 @@ Depending on both possible clock sources: PCLK clock or ADC asynchronous clock. - __ADC1_CLK_ENABLE(); + __HAL_RCC_ADC1_CLK_ENABLE(); (#) ADC pins configuration (++) Enable the clock for the ADC GPIOs using the following function: - __GPIOx_CLK_ENABLE(); + __HAL_RCC_GPIOx_CLK_ENABLE(); (++) Configure these ADC pins in analog mode using HAL_GPIO_Init(); (#) Configure the ADC parameters (conversion resolution, oversampler, @@ -105,7 +105,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -148,6 +148,17 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/* Delay for ADC stabilization time. */ +/* Maximum delay is 1us (refer to device datasheet, parameter tSTART). */ +/* Unit: us */ +#define ADC_STAB_DELAY_US ((uint32_t) 1) + +/* Delay for temperature sensor stabilization time. */ +/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ +/* Unit: us */ +#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10) + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ @@ -157,6 +168,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); static void ADC_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); +static void ADC_DelayMicroSecond(uint32_t microSecond); /* Private functions ---------------------------------------------------------*/ @@ -204,7 +216,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) uint32_t tickstart = 0x00; /* Check ADC handle */ - if(hadc == HAL_NULL) + if(hadc == NULL) { return HAL_ERROR; } @@ -214,7 +226,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTime)); - assert_param(IS_ADC_SCAN_DIRECTION(hadc->Init.ScanDirection)); + assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); @@ -225,7 +237,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerFrequencyMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoOff)); + assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); if(hadc->State == HAL_ADC_STATE_RESET) @@ -234,6 +246,21 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) HAL_ADC_MspInit(hadc); } + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed. */ + /* and if there is no conversion on going (ADC can be enabled anyway, */ + /* in case of call of this function to update a parameter */ + /* on the fly). */ + if ((hadc->State == HAL_ADC_STATE_ERROR) || + (ADC_IS_CONVERSION_ONGOING(hadc) != RESET) ) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + return HAL_ERROR; + } + /* Initialize the ADC state */ hadc->State = HAL_ADC_STATE_BUSY; @@ -248,16 +275,11 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Enable voltage regulator (if disabled at this step) */ if (HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADVREGEN)) { - /* Note: The software must wait for the startup time of the ADC voltage */ - /* regulator before launching a calibration or enabling the ADC. */ - /* This temporization must be implemented by software and is equal */ - /* to 10 micro seconds in the worst case process/temperature/power supply. */ - /* Disable the ADC (if not already disabled) */ - if (__HAL_ADC_IS_ENABLED(hadc) != RESET ) + if (ADC_IS_ENABLE(hadc) != RESET ) { /* Check if conditions to disable the ADC are fulfilled */ - if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET) + if (ADC_DISABLING_CONDITIONS(hadc) != RESET) { __HAL_ADC_DISABLE(hadc); } @@ -296,9 +318,6 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) /* Set ADVREGEN bit */ hadc->Instance->CR |= ADC_CR_ADVREGEN; - /* Delay of 10 microseconds minimum (value from design, cf reference manual) */ - /* Delay fixed to worst case: maximum CPU frequency */ - HAL_Delay(10); } /* Configuration of ADC: */ @@ -326,16 +345,16 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) hadc->Instance->CFGR1 |= ( hadc->Init.Resolution | hadc->Init.DataAlign | - hadc->Init.ScanDirection | + ADC_SCANDIR(hadc->Init.ScanConvMode) | hadc->Init.ExternalTrigConvEdge | - __HAL_ADC_CFGR1_CONTINUOUS(hadc->Init.ContinuousConvMode) | - __HAL_ADC_CFGR1_DMAContReq(hadc->Init.DMAContinuousRequests) | + ADC_CONTINUOUS(hadc->Init.ContinuousConvMode) | + ADC_DMACONTREQ(hadc->Init.DMAContinuousRequests) | hadc->Init.Overrun | __HAL_ADC_CFGR1_AutoDelay(hadc->Init.LowPowerAutoWait) | - __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoOff)); + __HAL_ADC_CFGR1_AUTOFF(hadc->Init.LowPowerAutoPowerOff)); /* Configure the external trigger only if Conversion edge is not "NONE" */ - if (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIG_EDGE_NONE) + if (hadc->Init.ExternalTrigConvEdge != ADC_EXTERNALTRIGCONVEDGE_NONE) { hadc->Instance->CFGR1 |= hadc->Init.ExternalTrigConv; } @@ -407,7 +426,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) uint32_t tickstart = 0; /* Check ADC handle */ - if(hadc == HAL_NULL) + if(hadc == NULL) { return HAL_ERROR; } @@ -581,30 +600,43 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ - __HAL_LOCK(hadc); - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - - /* Set ADC error code to none */ - hadc->ErrorCode = HAL_ADC_ERROR_NONE; - - /* Enable ADC */ - tmpHALStatus = ADC_Enable(hadc); + /* Perform ADC enable and conversion start if no conversion is on going */ + if (ADC_IS_CONVERSION_ONGOING(hadc) == RESET) + { + /* Process locked */ + __HAL_LOCK(hadc); + + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; + + /* Set ADC error code to none */ + hadc->ErrorCode = HAL_ADC_ERROR_NONE; - /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmpHALStatus = ADC_Enable(hadc); + } + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* ADC start conversion command */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + else { - /* ADC start conversion command */ - hadc->Instance->CR |= ADC_CR_ADSTART; + tmpHALStatus = HAL_BUSY; } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); /* Return function status */ - return HAL_OK; + return tmpHALStatus; } /** @@ -621,16 +653,16 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) __HAL_LOCK(hadc); /* 1. Stop potential conversion ongoing (regular conversion) */ - tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_GROUP); + tmpHALStatus = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* 2. Disable ADC peripheral if conversions are effectively stopped */ if (tmpHALStatus != HAL_ERROR) { /* Disable the ADC peripheral */ - ADC_Disable(hadc); + tmpHALStatus = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ - if (hadc->State != HAL_ADC_STATE_ERROR) + if ((hadc->State != HAL_ADC_STATE_ERROR) && (tmpHALStatus != HAL_ERROR)) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_READY; @@ -653,10 +685,20 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) } /** - * @brief Poll for conversion complete. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @brief Wait for regular group conversion to be completed. + * @note ADC conversion flags EOS (end of sequence) and EOC (end of + * conversion) are cleared by this function, with an exception: + * if low power feature "LowPowerAutoWait" is enabled, flags are + * not cleared to not interfere with this feature until data register + * is read using function HAL_ADC_GetValue(). + * @note This function cannot be used in a particular setup: ADC configured + * in DMA mode and polling for end of each conversion (ADC init + * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). + * In this case, DMA resets the flag EOC and polling cannot be + * performed on each conversion. Nevertheless, polling can still + * be performed on the complete sequence. + * @param hadc: ADC handle + * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -666,30 +708,50 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* If interruption after each sequence */ - if (hadc->Init.EOCSelection == EOC_SEQ_CONV) + + /* If end of conversion selected to end of sequence */ + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { tmp_Flag_EOC = ADC_FLAG_EOS; } - /* If interruption after each conversion */ - else /* EOC_SINGLE_CONV */ + /* If end of conversion selected to end of each conversion */ + else /* ADC_EOC_SINGLE_CONV */ { - tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); + /* Verification that ADC configuration is compliant with polling for */ + /* each conversion: */ + /* Particular case is ADC configured in DMA mode and ADC sequencer with */ + /* several ranks and polling for end of each conversion. */ + /* For code simplicity sake, this particular case is generalized to */ + /* ADC configured in DMA mode and and polling for end of each conversion. */ + if (HAL_IS_BIT_SET(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN)) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + + return HAL_ERROR; + } + else + { + tmp_Flag_EOC = (ADC_FLAG_EOC | ADC_FLAG_EOS); + } } - - /* Get timeout */ + + /* Get tick */ tickstart = HAL_GetTick(); - + /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_EOC)) { - /* Check for the Timeout */ + /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)|| ((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { - hadc->State= HAL_ADC_STATE_TIMEOUT; + /* Update ADC state machine to timeout */ + hadc->State = HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hadc); @@ -707,9 +769,13 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti /* Clear regular group conversion flag */ __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); } - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_EOC; + + /* Update state machine on conversion status if not in error state */ + if(hadc->State != HAL_ADC_STATE_ERROR) + { + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_EOC; + } /* Return ADC state */ return HAL_OK; @@ -720,8 +786,8 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti * @param hadc: ADC handle. * @param EventType: the ADC event type. * This parameter can be one of the following values: - * @arg AWD_EVENT: ADC Analog watchdog event. - * @arg OVR_EVENT: ADC Overrun event. + * @arg ADC_AWD_EVENT: ADC Analog watchdog event. + * @arg ADC_OVR_EVENT: ADC Overrun event. * @param Timeout: Timeout value in millisecond. * @retval HAL status */ @@ -758,7 +824,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy switch(EventType) { /* Check analog watchdog flag */ - case AWD_EVENT: + case ADC_AWD_EVENT: /* Change ADC state */ hadc->State = HAL_ADC_STATE_AWD; @@ -766,7 +832,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD); break; - /* Case OVR_EVENT */ + /* Case ADC_OVR_EVENT */ default: /* Change ADC state */ hadc->State = HAL_ADC_STATE_ERROR; @@ -793,52 +859,65 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ - __HAL_LOCK(hadc); - - /* State machine update: Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - - /* Set ADC error code to none */ - hadc->ErrorCode = HAL_ADC_ERROR_NONE; - - /* Enable the ADC peripheral */ - tmpHALStatus = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + /* Perform ADC enable and conversion start if no conversion is on going */ + if (ADC_IS_CONVERSION_ONGOING(hadc) == RESET) { - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + /* Process locked */ + __HAL_LOCK(hadc); + + /* State machine update: Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; + + /* Set ADC error code to none */ + hadc->ErrorCode = HAL_ADC_ERROR_NONE; + + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmpHALStatus = ADC_Enable(hadc); + } + + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable ADC end of conversion interrupt */ + switch(hadc->Init.EOCSelection) + { + case ADC_EOC_SEQ_CONV: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); + break; + /* case ADC_EOC_SINGLE_CONV */ + default: + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOS); + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); + break; + } + + /* ADC start conversion command */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } - /* Enable ADC end of conversion interrupt */ - switch(hadc->Init.EOCSelection) + else { - case EOC_SEQ_CONV: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); - break; - /* case EOC_SINGLE_CONV */ - default: - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOS); - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); - break; + tmpHALStatus = HAL_ERROR; } - /* ADC start conversion command */ - hadc->Instance->CR |= ADC_CR_ADSTART; + /* Process unlocked */ + __HAL_UNLOCK(hadc); } - else { - return HAL_ERROR; + tmpHALStatus = HAL_BUSY; } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - + /* Return function status */ - return HAL_OK; + return tmpHALStatus; } /** @@ -856,7 +935,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) __HAL_LOCK(hadc); /* 1. Stop potential conversion ongoing (regular conversion) */ - tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_GROUP); + tmpHALStatus = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* 2. Disable ADC peripheral if conversions are effectively stopped */ if (tmpHALStatus != HAL_ERROR) @@ -865,10 +944,10 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); /* Disable the ADC peripheral */ - ADC_Disable(hadc); + tmpHALStatus = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ - if (hadc->State != HAL_ADC_STATE_ERROR) + if ((hadc->State != HAL_ADC_STATE_ERROR) && (tmpHALStatus != HAL_ERROR)) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_READY; @@ -914,7 +993,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) /* Disable interruption if no further conversion upcoming by continuous mode or external trigger */ if((hadc->Init.ContinuousConvMode == DISABLE) && \ - (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIG_EDGE_NONE) + (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE) ) { /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit ADSTART==0 (no conversion on going) */ @@ -922,14 +1001,26 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { /* Cases of interruption after each conversion or after each sequence */ /* If interruption after each sequence */ - if (hadc->Init.EOCSelection == EOC_SEQ_CONV) + if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { - /* If End of Sequence is reached, disable interrupts */ - if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS/ADC_IT_OVR only if bit*/ + /* ADSTART==0 (no conversion on going) */ + if (ADC_IS_CONVERSION_ONGOING(hadc) == RESET) { - /* DISABLE ADC end of sequence conversion interrupt */ - /* DISABLE ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR); + /* If End of Sequence is reached, disable interrupts */ + if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) + { + /* DISABLE ADC end of sequence conversion interrupt */ + /* DISABLE ADC overrun interrupt */ + __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR); + } + } + else + { + /* Change ADC state to error state */ + hadc->State = HAL_ADC_STATE_ERROR; + /* Set ADC error code to ADC IP internal error */ + hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL; } } /* If interruption after each conversion */ @@ -1005,52 +1096,64 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - /* Process locked */ - __HAL_LOCK(hadc); - - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_BUSY_REG; - - /* Set ADC error code to none */ - hadc->ErrorCode = HAL_ADC_ERROR_NONE; - - /* Enable ADC */ - tmpHALStatus = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmpHALStatus != HAL_ERROR) + /* Perform ADC enable and conversion start if no conversion is on going */ + if (ADC_IS_CONVERSION_ONGOING(hadc) == RESET) { - /* Enable ADC DMA mode */ - hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; + /* Process locked */ + __HAL_LOCK(hadc); - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, - ADC start (in case of SW start) */ - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + /* Change ADC state */ + hadc->State = HAL_ADC_STATE_BUSY_REG; - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - + /* Set ADC error code to none */ + hadc->ErrorCode = HAL_ADC_ERROR_NONE; + + /* Enable the ADC peripheral */ + /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ + /* performed automatically by hardware. */ + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) + { + tmpHALStatus = ADC_Enable(hadc); + } - /* ADC start conversion command */ - hadc->Instance->CR |= ADC_CR_ADSTART; - } + /* Start conversion if ADC is effectively enabled */ + if (tmpHALStatus != HAL_ERROR) + { + /* Enable ADC DMA mode */ + hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; - /* Process unlocked */ - __HAL_UNLOCK(hadc); + /* Set the DMA transfer complete callback */ + hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; + + /* Set the DMA half transfer complete callback */ + hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; + + /* Set the DMA error callback */ + hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; + + /* Manage ADC and DMA start: ADC overrun interruption, DMA start, + ADC start (in case of SW start) */ + + /* Enable ADC overrun interrupt */ + __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); + + /* ADC start conversion command */ + hadc->Instance->CR |= ADC_CR_ADSTART; + } + + /* Process unlocked */ + __HAL_UNLOCK(hadc); + } + else + { + tmpHALStatus = HAL_BUSY; + } /* Return function status */ - return HAL_OK; + return tmpHALStatus; } /** @@ -1067,7 +1170,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) __HAL_LOCK(hadc); /* 1. Stop potential conversion ongoing (regular conversion) */ - tmpHALStatus = ADC_ConversionStop(hadc, REGULAR_GROUP); + tmpHALStatus = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP); /* 2. Disable ADC peripheral if conversions are effectively stopped */ if (tmpHALStatus != HAL_ERROR) @@ -1091,10 +1194,10 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); /* Disable the ADC peripheral */ - ADC_Disable(hadc); + tmpHALStatus = ADC_Disable(hadc); /* Check if ADC is effectively disabled */ - if (hadc->State != HAL_ADC_STATE_ERROR) + if ((hadc->State != HAL_ADC_STATE_ERROR) && (tmpHALStatus != HAL_ERROR)) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_READY; @@ -1210,7 +1313,6 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) { - /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfig->Channel)); @@ -1218,6 +1320,20 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf /* Process locked */ __HAL_LOCK(hadc); + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going : */ + /* - Channel number */ + /* - Management of internal measurement channels: Vbat/VrefInt/TempSensor */ + if (ADC_IS_CONVERSION_ONGOING(hadc) != RESET) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + return HAL_ERROR; + } + /* Enable selected channels */ hadc->Instance->CHSELR |= (uint32_t)(sConfig->Channel & ADC_CHANNEL_MASK); @@ -1230,6 +1346,9 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf if (((sConfig->Channel & ADC_CHANNEL_MASK) & ADC_CHANNEL_TEMPSENSOR ) == (ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_MASK)) { ADC->CCR |= ADC_CCR_TSEN; + + /* Delay for temperature sensor stabilization time */ + ADC_DelayMicroSecond(ADC_TEMPSENSOR_DELAY_US); } /* If VRefInt channel is selected, then enable the internal buffers and path */ @@ -1270,12 +1389,26 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(__HAL_ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); + assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); /* Process locked */ __HAL_LOCK(hadc); + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going : */ + /* - Analog watchdog channels */ + /* - Analog watchdog thresholds */ + if (ADC_IS_CONVERSION_ONGOING(hadc) != RESET) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + /* Process unlocked */ + __HAL_UNLOCK(hadc); + return HAL_ERROR; + } + /* Configure ADC Analog watchdog interrupt */ if(AnalogWDGConfig->ITMode == ENABLE) { @@ -1294,7 +1427,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* mode "all channels": ADC_CFGR1_AWD1SGL=0) */ hadc->Instance->CFGR1 &= ~( ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN | - ADC_CFGR1_AWDCH ); + ADC_CFGR1_AWDCH); hadc->Instance->CFGR1 |= ( AnalogWDGConfig->WatchdogMode | (AnalogWDGConfig->Channel & ADC_CHANNEL_AWD_MASK)); @@ -1302,14 +1435,14 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG /* Shift the offset in function of the selected ADC resolution: Thresholds */ /* have to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ - tmpAWDHighThresholdShifted = __HAL_ADC_AWD1Threshold_shift_resolution(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = __HAL_ADC_AWD1Threshold_shift_resolution(hadc, AnalogWDGConfig->LowThreshold); + tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); + tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); /* Clear High & Low high thresholds */ hadc->Instance->TR &= (uint32_t) ~ (ADC_TR_HT | ADC_TR_LT); /* Set the high threshold */ - hadc->Instance->TR = __HAL_ADC_TRx_HighThreshold (tmpAWDHighThresholdShifted); + hadc->Instance->TR = ADC_TRX_HIGHTHRESHOLD (tmpAWDHighThresholdShifted); /* Set the low threshold */ hadc->Instance->TR |= tmpAWDLowThresholdShifted; @@ -1372,21 +1505,27 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) * @brief Enable the selected ADC. * @note Prerequisite condition to use this function: ADC must be disabled * and voltage regulator must be enabled (done into HAL_ADC_Init()). + * @note If low power mode AutoPowerOff is enabled, power-on/off phases are + * performed automatically by hardware. + * In this mode, this function is useless and must not be called because + * flag ADC_FLAG_RDY is not usable. + * Therefore, this function must be called under condition of + * "if (hadc->Init.LowPowerAutoPowerOff != ENABLE)". * @param hadc: ADC handle * @retval HAL status. */ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) { uint32_t tickstart = 0; - + /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ /* enabling phase not yet completed: flag ADC ready not yet set). */ /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ /* causes: ADC clock not running, ...). */ - if (__HAL_ADC_IS_ENABLED(hadc) == RESET) + if (ADC_IS_ENABLE(hadc) == RESET) { /* Check if conditions to enable the ADC are fulfilled */ - if (__HAL_ADC_ENABLING_CONDITIONS(hadc) == RESET) + if (ADC_ENABLING_CONDITIONS(hadc) == RESET) { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; @@ -1400,12 +1539,15 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) /* Enable the ADC peripheral */ __HAL_ADC_ENABLE(hadc); + /* Delay for ADC stabilization time. */ + ADC_DelayMicroSecond(ADC_STAB_DELAY_US); + /* Wait for ADC effectively enabled */ /* Get timeout */ tickstart = HAL_GetTick(); /* Skip polling for RDY ADRDY when AutoOFF is enabled */ - if (hadc->Init.LowPowerAutoOff != ENABLE) + if (hadc->Init.LowPowerAutoPowerOff != ENABLE) { while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) { @@ -1445,10 +1587,10 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) /* Verification if ADC is not already disabled: */ /* forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ /* disabled. */ - if (__HAL_ADC_IS_ENABLED(hadc) != RESET ) + if (ADC_IS_ENABLE(hadc) != RESET ) { /* Check if conditions to disable the ADC are fulfilled */ - if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET) + if (ADC_DISABLING_CONDITIONS(hadc) != RESET) { /* Disable the ADC peripheral */ __HAL_ADC_DISABLE(hadc); @@ -1498,7 +1640,7 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) * @param hadc: ADC handle * @param ConversionGroup: Only ADC group regular. * This parameter can be one of the following values: - * @arg REGULAR_GROUP: ADC regular conversion type. + * @arg ADC_REGULAR_GROUP: ADC regular conversion type. * @retval HAL status. */ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) @@ -1508,12 +1650,23 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Co /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); - + + /* Parameters update conditioned to ADC state: */ + /* Parameters that can be updated when ADC is disabled or enabled without */ + /* conversion on going : */ + if (ADC_IS_CONVERSION_ONGOING(hadc) != RESET) + { + /* Update ADC state machine to error */ + hadc->State = HAL_ADC_STATE_ERROR; + /* Process unlocked */ + return HAL_ERROR; + } + /* Verification: if ADC is not already stopped, bypass this function */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART)) { /* Stop potential conversion on regular group */ - if (ConversionGroup == REGULAR_GROUP) + if (ConversionGroup == ADC_REGULAR_GROUP) { /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && \ @@ -1593,6 +1746,22 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma) HAL_ADC_ErrorCallback(hadc); } +/** + * @brief Delay micro seconds + * @param microSecond : delay + * @retval None + */ +static void ADC_DelayMicroSecond(uint32_t microSecond) +{ + /* Compute number of CPU cycles to wait for */ + __IO uint32_t waitLoopIndex = (microSecond * (SystemCoreClock / 1000000)); + + while(waitLoopIndex != 0) + { + waitLoopIndex--; + } +} + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h index 202f45931bb..e1ec37d1a27 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l0xx_hal_adc.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -108,8 +108,8 @@ typedef struct uint32_t SamplingTime; /*!< The sample time value to be set for all channels. This parameter can be a value of @ref ADC_sampling_times Note: This parameter can be modified only if there is no conversion ongoing. */ - uint32_t ScanDirection; /*!< The scan sequence direction. - This parameter can be a value of @ref ADC_scan_direction + uint32_t ScanConvMode; /*!< The scan sequence direction. + This parameter can be a value of @ref ADC_Scan_mode Note: This parameter can be modified only if there is no conversion is ongoing. */ uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right. This parameter can be a value of @ref ADC_data_align @@ -123,7 +123,7 @@ typedef struct This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing. */ uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger. - This parameter can be a value of @ref ADC_External_trigger_Edge + This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge Note: This parameter can be modified only if there is no conversion is ongoing. */ uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion. This parameter can be a value of @ref ADC_External_trigger_Source @@ -149,7 +149,7 @@ typedef struct it is mandatory to first enable the Low Frequency Mode. This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing. */ - uint32_t LowPowerAutoOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically + uint32_t LowPowerAutoPowerOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically wakes-up when a conversion is started (by software or hardware trigger). This parameter can be set to ENABLE or DISABLE. Note: This parameter can be modified only if there is no conversion is ongoing. */ @@ -216,8 +216,8 @@ typedef struct #define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */ #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking, enable/disable, erroneous state */ -#define HAL_ADC_ERROR_OVR ((uint32_t)0x01) /*!< OVR error */ -#define HAL_ADC_ERROR_DMA ((uint32_t)0x02) /*!< DMA transfer error */ +#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< OVR error */ +#define HAL_ADC_ERROR_DMA ((uint32_t)0x03) /*!< DMA transfer error */ /** * @} */ @@ -258,14 +258,17 @@ typedef struct #define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ #define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 1 */ -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 2 */ -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 4 */ +#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 1 + This configuration must be enabled only if PCLK has a 50% + duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock + must by 50% duty cycle)*/ +#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 2 */ +#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 4 */ #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\ - ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV1) ||\ - ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV2) ||\ - ((ADC_CLOCK) == ADC_CLOCKPRESCALER_PCLK_DIV4) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ + ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ @@ -285,18 +288,18 @@ typedef struct /** @defgroup ADC_Resolution * @{ */ -#define ADC_RESOLUTION12b ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ -#define ADC_RESOLUTION10b ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ -#define ADC_RESOLUTION8b ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ -#define ADC_RESOLUTION6b ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ +#define ADC_RESOLUTION_12B ((uint32_t)0x00000000) /*!< ADC 12-bit resolution */ +#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ +#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ +#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \ - ((RESOLUTION) == ADC_RESOLUTION10b) || \ - ((RESOLUTION) == ADC_RESOLUTION8b) || \ - ((RESOLUTION) == ADC_RESOLUTION6b)) +#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ + ((RESOLUTION) == ADC_RESOLUTION_10B) || \ + ((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B)) -#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) || \ - ((RESOLUTION) == ADC_RESOLUTION6b)) +#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ + ((RESOLUTION) == ADC_RESOLUTION_6B)) /** * @} */ @@ -313,18 +316,18 @@ typedef struct * @} */ -/** @defgroup ADC_External_trigger_Edge +/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group * @{ */ -#define ADC_EXTERNALTRIG_EDGE_NONE ((uint32_t)0x00000000) -#define ADC_EXTERNALTRIG_EDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) -#define ADC_EXTERNALTRIG_EDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) +#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) +#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) -#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIG_EDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIG_EDGE_RISING) || \ - ((EDGE) == ADC_EXTERNALTRIG_EDGE_FALLING) || \ - ((EDGE) == ADC_EXTERNALTRIG_EDGE_RISINGFALLING)) +#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ + ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) /** * @} */ @@ -332,19 +335,19 @@ typedef struct /** @defgroup ADC_External_trigger_Source * @{ */ -#define ADC_EXTERNALTRIG0_T6_TRGO ((uint32_t)0x00000000) -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_CFGR1_EXTSEL_0 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_CFGR1_EXTSEL_1 -#define ADC_EXTERNALTRIG3_T2_CC4 ((uint32_t)0x000000C0) -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_CFGR1_EXTSEL_2 -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_CFGR1_EXTSEL +#define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)0x00000000) +#define ADC_EXTERNALTRIGCONV_T21_CC2 ADC_CFGR1_EXTSEL_0 +#define ADC_EXTERNALTRIGCONV_T2_TRGO ADC_CFGR1_EXTSEL_1 +#define ADC_EXTERNALTRIGCONV_T2_CC4 ((uint32_t)0x000000C0) +#define ADC_EXTERNALTRIGCONV_T22_TRGO ADC_CFGR1_EXTSEL_2 +#define ADC_EXTERNALTRIGCONV_EXT_IT11 ADC_CFGR1_EXTSEL -#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_EXTERNALTRIG0_T6_TRGO ) || \ - ((CONV) == ADC_EXTERNALTRIG1_T21_CC2 ) || \ - ((CONV) == ADC_EXTERNALTRIG2_T2_TRGO ) || \ - ((CONV) == ADC_EXTERNALTRIG3_T2_CC4 ) || \ - ((CONV) == ADC_EXTERNALTRIG4_T22_TRGO ) || \ - ((CONV) == ADC_EXTERNALTRIG7_EXT_IT11 )) +#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_EXTERNALTRIGCONV_T6_TRGO ) || \ + ((CONV) == ADC_EXTERNALTRIGCONV_T21_CC2 ) || \ + ((CONV) == ADC_EXTERNALTRIGCONV_T2_TRGO ) || \ + ((CONV) == ADC_EXTERNALTRIGCONV_T2_CC4 ) || \ + ((CONV) == ADC_EXTERNALTRIGCONV_T22_TRGO ) || \ + ((CONV) == ADC_EXTERNALTRIGCONV_EXT_IT11 )) /** * @} @@ -353,13 +356,13 @@ typedef struct /** @defgroup ADC_EOCSelection * @{ */ -#define EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) -#define EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) -#define EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ +#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) +#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) +#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ -#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV) || \ - ((EOC_SELECTION) == EOC_SEQ_CONV) || \ - ((EOC_SELECTION) == EOC_SINGLE_SEQ_CONV)) +#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \ + ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV)) /** * @} */ @@ -367,11 +370,11 @@ typedef struct /** @defgroup ADC_Overrun * @{ */ -#define OVR_DATA_PRESERVED ((uint32_t)0x00000000) -#define OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD) +#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000) +#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD) -#define IS_ADC_OVERRUN(OVR) (((OVR) == OVR_DATA_PRESERVED) || \ - ((OVR) == OVR_DATA_OVERWRITTEN)) +#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ + ((OVR) == ADC_OVR_DATA_OVERWRITTEN)) /** * @} */ @@ -464,15 +467,29 @@ typedef struct * @} */ - /** @defgroup ADC_scan_direction + +/** @defgroup ADC_Scan_mode ADC Scan mode * @{ - */ -#define ADC_SCAN_DIRECTION_UPWARD ((uint32_t)0x00000000) -#define ADC_SCAN_DIRECTION_BACKWARD ADC_CFGR1_SCANDIR + */ +/* Note: Scan mode values must be compatible with other STM32 devices having */ +/* a configurable sequencer. */ +/* Scan direction setting values are defined by taking in account */ +/* already defined values for other STM32 devices: */ +/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */ +/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */ +/* Scan direction forward is considered as default setting equivalent */ +/* to scan enable. */ +/* Scan direction backward is considered as additional setting. */ +/* In case of migration from another STM32 device, the user will be */ +/* warned of change of setting choices with assert check. */ +#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001) /*!< Scan direction forward: from channel 0 to channel 18 */ +#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002) /*!< Scan direction backward: from channel 18 to channel 0 */ + +#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ +#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ + ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD)) -#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_SCAN_DIRECTION_UPWARD) || \ - ((DIRECTION) == ADC_SCAN_DIRECTION_BACKWARD)) /** * @} */ @@ -555,8 +572,8 @@ typedef struct /** @defgroup ADC_conversion_type * @{ */ -#define REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) -#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == REGULAR_GROUP) +#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) +#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP) /** * @} */ @@ -564,11 +581,11 @@ typedef struct /** @defgroup ADC_Event_type * @{ */ -#define AWD_EVENT ((uint32_t)ADC_FLAG_AWD) -#define OVR_EVENT ((uint32_t)ADC_FLAG_OVR) +#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) +#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) -#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT) || \ - ((EVENT) == OVR_EVENT)) +#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ + ((EVENT) == ADC_OVR_EVENT)) /** * @} */ @@ -624,10 +641,10 @@ typedef struct * @{ */ #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ - ((((RESOLUTION) == ADC_RESOLUTION12b) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ - (((RESOLUTION) == ADC_RESOLUTION10b) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ - (((RESOLUTION) == ADC_RESOLUTION8b) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ - (((RESOLUTION) == ADC_RESOLUTION6b) && ((ADC_VALUE) <= ((uint32_t)0x003F)))) + ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFF))) || \ + (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FF))) || \ + (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FF))) || \ + (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003F)))) /** * @} */ @@ -666,7 +683,7 @@ typedef struct * @param __HANDLE__: ADC handle * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) */ -#define __HAL_ADC_ENABLING_CONDITIONS(__HANDLE__) \ +#define ADC_ENABLING_CONDITIONS(__HANDLE__) \ (( ( ((__HANDLE__)->Instance->CR) & \ (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \ ADC_CR_ADDIS | ADC_CR_ADEN ) \ @@ -689,7 +706,7 @@ typedef struct * @param __HANDLE__: ADC handle * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) */ -#define __HAL_ADC_DISABLING_CONDITIONS(__HANDLE__) \ +#define ADC_DISABLING_CONDITIONS(__HANDLE__) \ (( ( ((__HANDLE__)->Instance->CR) & \ (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ ) ? SET : RESET) @@ -699,7 +716,7 @@ typedef struct * @param __HANDLE__: ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ -#define __HAL_ADC_IS_ENABLED(__HANDLE__) \ +#define ADC_IS_ENABLE(__HANDLE__) \ (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ ) ? SET : RESET) @@ -709,14 +726,14 @@ typedef struct * @param __HANDLE__: ADC handle * @retval None */ -#define __HAL_ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) +#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) /** * @brief Check if no conversion is ongoing on regular groups * @param __HANDLE__: ADC handle * @retval SET (conversion is on going) or RESET (no conversion is on going) */ -#define __HAL_ADC_IS_CONVERSION_ONGOING(__HANDLE__) \ +#define ADC_IS_CONVERSION_ONGOING(__HANDLE__) \ (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART)) == RESET ) ? RESET : SET) /** @@ -724,7 +741,17 @@ typedef struct * @param _CONTINUOUS_MODE_: Continuous mode. * @retval None */ -#define __HAL_ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13) +#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13) + +/** + * @brief Enable ADC scan mode to convert multiple ranks with sequencer. + * @param _SCAN_MODE_: Scan conversion mode. + * @retval None + */ +#define ADC_SCANDIR(_SCAN_MODE_) \ + ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ + )? (ADC_CFGR1_SCANDIR) : (0x00000000) \ + ) /** * @brief Configures the number of discontinuous conversions for the regular group channels. @@ -738,7 +765,7 @@ typedef struct * @param _DMAContReq_MODE_: DMA continuous request mode. * @retval None */ -#define __HAL_ADC_CFGR1_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1) +#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1) /** * @brief Enable the ADC Auto Delay. @@ -748,7 +775,7 @@ typedef struct #define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14) /** - * @brief Enable the ADC LowPowerAutoOff. + * @brief Enable the ADC LowPowerAutoPowerOff. * @param _AUTOFF_: AutoOff bit enable or disable. * @retval None */ @@ -759,7 +786,7 @@ typedef struct * @param _Threshold_: Threshold value * @retval None */ -#define __HAL_ADC_TRx_HighThreshold(_Threshold_) ((_Threshold_) << 16) +#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16) /** * @brief Enable the ADC Low Frequency mode. @@ -780,7 +807,7 @@ typedef struct * @param _Offset_: Value to be shifted * @retval None */ -#define __HAL_ADC_Offset_shift_resolution(__HANDLE__, _Offset_) \ +#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \ ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3)*2)) /** @@ -795,7 +822,7 @@ typedef struct * @param _Threshold_: Value to be shifted * @retval None */ -#define __HAL_ADC_AWD1Threshold_shift_resolution(__HANDLE__, _Threshold_) \ +#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3)*2)) /** @@ -857,9 +884,9 @@ typedef struct #define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \ do{ \ - if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCKPRESCALER_PCLK_DIV1) || \ - (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCKPRESCALER_PCLK_DIV2) || \ - (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCKPRESCALER_PCLK_DIV2)) \ + if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ + (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ + (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \ { \ (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; \ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.c index e21eaf3b7f9..d9588d7de50 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) * peripheral: @@ -33,7 +33,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -82,7 +82,7 @@ /* Private functions ---------------------------------------------------------*/ -/** @defgroup ADCEx_Group ADC Extended features functions +/** @addtgroup ADCEx_Group ADC Extended features functions * @brief ADC Extended features functions * @verbatim @@ -121,10 +121,10 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t __HAL_LOCK(hadc); /* Disable the ADC (if not already disabled) */ - if (__HAL_ADC_IS_ENABLED(hadc) != RESET ) + if (ADC_IS_ENABLE(hadc) != RESET ) { /* Check if conditions to disable the ADC are fulfilled */ - if (__HAL_ADC_DISABLING_CONDITIONS(hadc) != RESET) + if (ADC_DISABLING_CONDITIONS(hadc) != RESET) { __HAL_ADC_DISABLE(hadc); } @@ -233,8 +233,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 /* Verification of hardware constraints before modifying the calibration */ /* factors register: ADC must be enabled, no conversion on going. */ - if ( (__HAL_ADC_IS_ENABLED(hadc) != RESET) && - (__HAL_ADC_IS_CONVERSION_ONGOING(hadc) == RESET) ) + if ( (ADC_IS_ENABLE(hadc) != RESET) && + (ADC_IS_CONVERSION_ONGOING(hadc) == RESET) ) { /* Set the selected ADC calibration value */ hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT; @@ -256,6 +256,50 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32 return tmpHALStatus; } +/** + * @brief Enables the Buffer Vrefint for the ADC. + * @note This is functional only if the LOCK is not set. + * @retval None + */ +void HAL_ADCEx_EnableVREFINT(void) +{ + /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ + SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT)); +} + +/** + * @brief Disables the Buffer Vrefint for the ADC. + * @note This is functional only if the LOCK is not set. + * @retval None + */ +void HAL_ADCEx_DisableVREFINT(void) +{ + /* Disable the Vrefint by resetting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ + CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_VREFINT_ADC | SYSCFG_CFGR3_EN_VREFINT)); +} + +/** + * @brief Enables VEREFINT and the Sensor for the ADC. + * @note This is functional only if the LOCK is not set. + * @retval None + */ +void HAL_ADCEx_EnableVREFINTTempSensor(void) +{ + /* Enable the Buffer for the ADC by setting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ + SET_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT)); +} + +/** + * @brief Disables the VEREFINT and Sensor for the ADC. + * @note This is functional only if the LOCK is not set. + * @retval None + */ +void HAL_ADCEx_DisableVREFINTTempSensor(void) +{ + /* Disable the Vrefint by resetting EN_VREFINT bit and the ENBUF_SENSOR_ADC in the CFGR3 register */ + CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENBUF_SENSOR_ADC | SYSCFG_CFGR3_EN_VREFINT)); +} + /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.h index 7241f0c47db..fedaad33e3c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_adc_ex.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l0xx_hal_adc_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief This file contains all the functions prototypes for the ADC firmware * library. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -92,6 +92,9 @@ * @} */ +#define ADC_FLAG_SENSOR SYSCFG_CFGR3_SENSOR_ADC_RDYF +#define ADC_FLAG_VREFINT SYSCFG_VREFINT_ADC_RDYF + /** * @} */ @@ -101,6 +104,10 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff); uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); +void HAL_ADCEx_EnableVREFINT(void); +void HAL_ADCEx_DisableVREFINT(void); +void HAL_ADCEx_EnableVREFINTTempSensor(void); +void HAL_ADCEx_DisableVREFINTTempSensor(void); /** @@ -119,3 +126,4 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.c index 72f4c95d7c6..df8ea9e1d3b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_comp.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief COMP HAL module driver. * * This file provides firmware functions to manage the following @@ -38,8 +38,8 @@ From the corresponding IRQ handler, the right interrupt source can be retrieved with the macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are: - (++) COMP_EXTI_LINE_COMP1_EVENT - (++) COMP_EXTI_LINE_COMP2_EVENT + (++) COMP_EXTI_LINE_COMP1 + (++) COMP_EXTI_LINE_COMP2 [..] Table 1. COMP Inputs for the STM32L0xx devices @@ -101,7 +101,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -135,7 +135,7 @@ * @{ */ -/** @defgroup COMP +/** @addtogroup COMP * @brief COMP HAL module driver * @{ */ @@ -147,16 +147,12 @@ /* CSR register reset value */ #define COMP_CSR_RESET_VALUE ((uint32_t)0x00000000) -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup COMP_Private_Functions +/** @addtogroup COMP_Exported_Functions * @{ */ -/** @defgroup HAL_COMP_Group1 Initialization/de-initialization functions +/** @addtogroup COMP_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim @@ -184,7 +180,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) { status = HAL_ERROR; } @@ -198,7 +194,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); assert_param(IS_COMP_MODE(hcomp->Init.Mode)); - if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLED) + if(hcomp->Init.WindowMode != COMP_WINDOWMODE_DISABLE) { assert_param(IS_COMP_WINDOWMODE_INSTANCE(hcomp->Instance)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); @@ -207,7 +203,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp) if(hcomp->State == HAL_COMP_STATE_RESET) { /* Init SYSCFG and the low level hardware to access comparators */ - __SYSCFG_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); /* Init the low level hardware : SYSCFG to access comparators */ HAL_COMP_MspInit(hcomp); } @@ -250,7 +246,7 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) { status = HAL_ERROR; } @@ -302,7 +298,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup HAL_COMP_Group2 I/O operation functions +/** @addtogroup COMP_Exported_Functions_Group2 * @brief Data transfers functions * @verbatim @@ -327,7 +323,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) { status = HAL_ERROR; } @@ -362,7 +358,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) { status = HAL_ERROR; } @@ -390,7 +386,6 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) /** * @brief Enables the interrupt and starts the comparator * @param hcomp: COMP handle - * @param mode: IT trigger mode: a value of @ref COMP_TriggerMode * @retval HAL status. */ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) @@ -402,33 +397,69 @@ HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp) if(status == HAL_OK) { /* Check the Exti Line output configuration */ - extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); - + extiline = COMP_GET_EXTI_LINE(hcomp->Instance); + /* Configure the rising edge */ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != 0x00) { - __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline); + if (extiline == COMP_EXTI_LINE_COMP1) + { + __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); + } + else + { + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); + } } else { - __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline); + if (extiline == COMP_EXTI_LINE_COMP1) + { + __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); + } + else + { + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); + } } /* Configure the falling edge */ if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != 0x00) { - __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline); + if (extiline == COMP_EXTI_LINE_COMP1) + { + __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); + } + else + { + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); + } } else { - __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline); + if (extiline == COMP_EXTI_LINE_COMP1) + { + __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); + } + else + { + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); + } } - /* Enable Exti interrupt mode */ - __HAL_COMP_EXTI_ENABLE_IT(extiline); - - /* Clear COMP Exti pending bit */ - __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + if (extiline == COMP_EXTI_LINE_COMP1) + { + /* Clear COMP Exti pending bit */ + __HAL_COMP_COMP1_EXTI_CLEAR_FLAG(); + /* Enable Exti interrupt mode */ + __HAL_COMP_COMP1_EXTI_ENABLE_IT(); + } else + { + /* Clear COMP Exti pending bit */ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG(); + /* Enable Exti interrupt mode */ + __HAL_COMP_COMP2_EXTI_ENABLE_IT(); + } } return status; @@ -443,8 +474,14 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) { HAL_StatusTypeDef status = HAL_OK; - /* Disable the Exti Line interrupt mode */ - __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance)); + if (COMP_GET_EXTI_LINE(hcomp->Instance) == COMP_EXTI_LINE_COMP1) + { + __HAL_COMP_COMP1_EXTI_DISABLE_IT(); + } + if (COMP_GET_EXTI_LINE(hcomp->Instance) == COMP_EXTI_LINE_COMP2) + { + __HAL_COMP_COMP2_EXTI_DISABLE_IT(); + } status = HAL_COMP_Stop(hcomp); @@ -458,13 +495,18 @@ HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp) */ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) { - uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance); - + /* Check COMP Exti flag */ - if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET) + + if(__HAL_COMP_COMP1_EXTI_GET_FLAG() != RESET) { /* Clear COMP Exti pending bit */ - __HAL_COMP_EXTI_CLEAR_FLAG(extiline); + __HAL_COMP_COMP1_EXTI_CLEAR_FLAG(); + } + if(__HAL_COMP_COMP2_EXTI_GET_FLAG() != RESET) + { + /* Clear COMP Exti pending bit */ + __HAL_COMP_COMP2_EXTI_CLEAR_FLAG(); } /* COMP trigger user callback */ @@ -475,7 +517,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup HAL_COMP_Group3 Peripheral Control functions +/** @addtogroup COMP_Exported_Functions_Group3 * @brief management functions * @verbatim @@ -500,18 +542,33 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef status = HAL_OK; /* Check the COMP handle allocation and lock status */ - if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) + if((hcomp == NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != 0x00)) { status = HAL_ERROR; } else { - /* Check the parameter */ + /* Check the parameter */ assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); - /* Set lock flag */ - hcomp->State |= COMP_STATE_BIT_LOCK; - + /* Set lock flag on state */ + switch(hcomp->State) + { + case HAL_COMP_STATE_BUSY: + hcomp->State = HAL_COMP_STATE_BUSY_LOCKED; + break; + case HAL_COMP_STATE_READY: + hcomp->State = HAL_COMP_STATE_READY_LOCKED; + break; + default: + /* unexpected state */ + status = HAL_ERROR; + break; + } + } + + if(status == HAL_OK) + { /* Set the lock bit corresponding to selected comparator */ __HAL_COMP_LOCK(hcomp); } @@ -561,7 +618,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) * @} */ -/** @defgroup HAL_COMP_Group4 Peripheral State functions +/** @addtogroup COMP_Exported_Functions_Group4 * @brief Peripheral State functions * @verbatim @@ -584,7 +641,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp) HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) { /* Check the COMP handle allocation */ - if(hcomp == HAL_NULL) + if(hcomp == NULL) { return HAL_COMP_STATE_RESET; } @@ -594,10 +651,12 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) return hcomp->State; } + /** * @} */ + /** * @} */ @@ -612,3 +671,4 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.h index 522c0f3bebf..df5e9d2c374 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_comp.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of COMP HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,12 +50,19 @@ * @{ */ -/** @addtogroup COMP +/** @defgroup COMP COMP * @{ */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup COMP_Exported_Types COMP Exported Types + * @{ + */ + + /** @defgroup COMP_Init COMP init configuration structure + * @{ + */ /** * @brief COMP Init structure definition */ @@ -87,6 +94,13 @@ typedef struct }COMP_InitTypeDef; +/** + * @} + */ + +/** @defgroup COMP_state COMP state definition + * @{ + */ /** * @brief HAL State structures definition */ @@ -98,7 +112,13 @@ typedef enum HAL_COMP_STATE_BUSY = 0x02, /*!< COMP is running */ HAL_COMP_STATE_BUSY_LOCKED = 0x12 /*!< COMP is running and the configuration is locked */ }HAL_COMP_StateTypeDef; +/** + * @} + */ +/** @defgroup COMP_handle COMP handler + * @{ + */ /** * @brief COMP Handle Structure definition */ @@ -110,12 +130,19 @@ typedef struct __IO HAL_COMP_StateTypeDef State; /*!< COMP communication state */ } COMP_HandleTypeDef; +/** + * @} + */ +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ -/** @defgroup COMP_Exported_Constants +/** @defgroup COMP_Exported_Constants COMP Exported Constants * @{ */ -/** @defgroup COMP_OutputPolarity +/** @defgroup COMP_OutputPolarity COMP output polarity definitions * @{ */ #define COMP_OUTPUTPOL_NONINVERTED ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ @@ -127,7 +154,7 @@ typedef struct */ -/** @defgroup COMP_InvertingInput +/** @defgroup COMP_InvertingInput COMP inverting input definitions * @{ */ @@ -158,7 +185,7 @@ typedef struct */ -/** @defgroup COMP_NonInvertingInput +/** @defgroup COMP_NonInvertingInput COMP non inverting input definitions * @{ */ @@ -184,7 +211,7 @@ typedef struct */ -/** @defgroup COMP_Mode +/** @defgroup COMP_Mode COMP mode definition * @{ */ /* Please refer to the electrical characteristics in the device datasheet for @@ -198,20 +225,25 @@ typedef struct * @} */ -/** @defgroup COMP_WindowMode +/** @defgroup COMP_WindowMode COMP window mode definition * @{ */ -#define COMP_WINDOWMODE_DISABLED ((uint32_t)0x00000000) /*!< Window mode disabled (Plus input of comparator 1 connected to PA1)*/ -#define COMP_WINDOWMODE_ENABLED COMP_CSR_COMP1WM /*!< Window mode enabled: Plus input of comparator 1 shorted with Plus input of comparator 2 */ -#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \ - ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED)) - +#define COMP_WINDOWMODE_DISABLE ((uint32_t)0x00000000) /*!< Window mode disabled (Plus input of comparator 1 connected to PA1)*/ +#define COMP_WINDOWMODE_ENABLE COMP_CSR_COMP1WM /*!< Window mode enabled: Plus input of comparator 1 shorted with Plus input of comparator 2 */ +#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLE) || \ + ((WINDOWMODE) == COMP_WINDOWMODE_ENABLE)) + +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) ||\ + ((INSTANCE) == COMP2)) +#else #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP1) +#endif /** * @} */ -/** @defgroup COMP_LPTIMConnection +/** @defgroup COMP_LPTIMConnection COMP Low power timer connection definition * @{ */ #define COMP_LPTIMCONNECTION_DISABLED ((uint32_t)0x00000000) /*!< COMPx signal is gated */ @@ -223,7 +255,7 @@ typedef struct * @} */ -/** @defgroup COMP_OutputLevel +/** @defgroup COMP_OutputLevel COMP output level definition * @{ */ /* When output polarity is not inverted, comparator output is low when @@ -244,7 +276,7 @@ typedef struct #define COMP_STATE_BIT_LOCK ((uint32_t)0x10) -/** @defgroup COMP_TriggerMode +/** @defgroup COMP_TriggerMode COMP trigger mode definition * @{ */ #define COMP_TRIGGERMODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */ @@ -257,26 +289,36 @@ typedef struct * @} */ -/** @defgroup COMP_ExtiLineEvent +/** @defgroup COMP_ExtiLineEvent COMP EXTI line definition * @{ */ -#define COMP_EXTI_LINE_COMP2_EVENT ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to COMP2 */ -#define COMP_EXTI_LINE_COMP1_EVENT ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to COMP1 */ +#define COMP_EXTI_LINE_COMP2 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to COMP2 */ +#define COMP_EXTI_LINE_COMP1 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to COMP1 */ -/** - * @} - */ /** * @} */ +/** + * @} + */ /* Exported macro ------------------------------------------------------------*/ /** @brief Reset COMP handle state * @param __HANDLE__: COMP handle. * @retval None */ + +/** @defgroup COMP_Exported_Macro COMP Exported Macro + * @{ + */ +/** + * @brief Reset the state machine associated to the handler + * @param __HANDLE__: COMP handle. + * @retval None. + */ + #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) /** @@ -301,7 +343,7 @@ typedef struct #define __HAL_COMP_LOCK(__HANDLE__) ((__HANDLE__)->Instance->CSR |= COMP_CSR_COMPxLOCK) /** @brief Checks whether the specified COMP flag is set or not. - * @param __HANDLE__: specifies the COMP Handle. + * @param __HANDLE__: COMP handle. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg COMP_FLAG_LOCK: lock flag @@ -309,108 +351,197 @@ typedef struct */ #define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->CSR & (__FLAG__)) == (__FLAG__)) +/** + * @brief Enable the Exti Line rising edge trigger. + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) /** - * @brief Enable the Exti Line rising edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent + * @brief Disable the Exti Line rising edge trigger. + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the Exti Line falling edge trigger. * @retval None. */ -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (EXTI->RTSR |= (__EXTILINE__)) +#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) /** - * @brief Disable the Exti Line rising edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent + * @brief Disable the Exti Line falling edge trigger. + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None. */ -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (EXTI->RTSR &= ~(__EXTILINE__)) +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) /** - * @brief Enable the Exti Line falling edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent + * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None. */ -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (EXTI->FTSR |= (__EXTILINE__)) +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) /** - * @brief Disable the Exti Line falling edge trigger. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent + * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None. */ -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (EXTI->FTSR &= ~(__EXTILINE__)) +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \ + } while(0) +/** + * @brief Disable the COMP2 EXTI line rising & falling edge trigger. + * @retval None. + */ +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) + /** * @brief Get the specified EXTI line for a comparator instance * @param __INSTANCE__: specifies the COMP instance. * @retval value of @ref COMP_ExtiLineEvent */ -#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1_EVENT : \ - COMP_EXTI_LINE_COMP2_EVENT) +#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \ + COMP_EXTI_LINE_COMP2) /** * @brief Enable the COMP Exti Line. - * @param __EXTILINE__: specifies the COMP Exti sources to be enabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent * @retval None. */ -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) + +#define __HAL_COMP_COMP1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) /** * @brief Disable the COMP Exti Line. - * @param __EXTILINE__: specifies the COMP Exti sources to be disabled. - * This parameter can be a value of @ref COMP_ExtiLineEvent * @retval None. */ -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) + +#define __HAL_COMP_COMP1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Generate a software interrupt on the COMP EXTI line. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, COMP_EXTI_LINE_COMP2) + +/** + * @brief Enable the COMP EXTI Line in event mode + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) + +/** + * @brief Disable the COMP EXTI Line in event mode. + * @retval None + */ +#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, COMP_EXTI_LINE_COMP2) /** * @brief Checks whether the specified EXTI line flag is set or not. - * @param __FLAG__: specifies the COMP Exti sources to be checked. - * This parameter can be a value of @ref COMP_ExtiLineEvent * @retval The state of __FLAG__ (SET or RESET). */ -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (EXTI->PR & (__FLAG__)) + +#define __HAL_COMP_COMP1_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_GET_FLAG() READ_BIT(EXTI->PR, COMP_EXTI_LINE_COMP2) /** * @brief Clear the COMP Exti flags. - * @param __FLAG__: specifies the COMP Exti sources to be cleared. - * This parameter can be a value of @ref COMP_ExtiLineEvent * @retval None. */ -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) +#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP1) +#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() WRITE_REG(EXTI->PR, COMP_EXTI_LINE_COMP2) + + +/** + * @} + */ +/* Include COMP HAL Extended module */ +#include "stm32l0xx_hal_comp_ex.h" /* Exported functions --------------------------------------------------------*/ +/** @defgroup COMP_Exported_Functions COMP Exported Functions + * @{ + */ + +/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ /* Initialization/de-initialization functions **********************************/ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); +/** + * @} + */ +/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions + * @{ + */ /* I/O operation functions *****************************************************/ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp); void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp); +/** + * @} + */ +/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ /* Peripheral Control functions ************************************************/ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp); uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp); /* Callback in Interrupt mode */ void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp); +/** + * @} + */ +/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions + * @{ + */ /* Peripheral State functions **************************************************/ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); /** * @} - */ + */ + + +/** + * @} + */ + +/** + * @} + */ /** * @} @@ -423,3 +554,4 @@ HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp); #endif /* __STM32L0xx_HAL_COMP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.c new file mode 100644 index 00000000000..e6cbdc82c92 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.c @@ -0,0 +1,120 @@ +/** + ****************************************************************************** + * @file stm32l0xx_hal_comp_ex.c + * @author MCD Application Team + * @version V1.2.0 + * @date 06-February-2015 + * @brief Extended COMP HAL module driver. + * @brief This file provides firmware functions to manage the VREFINT + * which can act as input to the comparator. + @verbatim + ============================================================================== + ##### COMP peripheral Extended features ##### + ============================================================================== + + [..] Comparing to other previous devices, the COMP interface for STM32L0XX + devices contains the following additional features + + (+) Possibility to enable or disable the VREFINT which is used as input + to the comparator. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_hal.h" + +/** @addtogroup STM32L0xx_HAL_Driver + * @{ + */ + +/** @addtogroup COMPEx + * @brief Extended COMP HAL module driver + * @{ + */ + +#ifdef HAL_COMP_MODULE_ENABLED + + +/** @addtogroup COMPEx_Exported_Functions + * @{ + */ + +/** @addtogroup COMPEx_Exported_Functions_Group1 + * @brief Extended functions to manage VREFINT for the comparator + * + * @{ + */ + +/** + * @brief Enables the Buffer Vrefint for the COMP. + * @note This is functional only if the LOCK bit is not set + + * @retval None + */ +void HAL_COMPEx_EnableVREFINT(void) +{ + /* Enable the Buffer for the COMP by setting EN_VREFINT bit and the ENBUFLP_VREFINT_COMP in the CFGR3 register */ + + SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT); +} + +/** + * @brief Disables the Buffer Vrefint for the COMP. + * @note This is functional only if the LOCK bit is not set + * @retval None + */ +void HAL_COMPEx_DisableVREFINT(void) +{ + /* Disable the Vrefint by resetting ENBUFLP_BGAP_COMP bit and the EN_VREFINT bit in the CFGR3 register */ + + SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP | SYSCFG_CFGR3_EN_VREFINT)); +} + +/** + * @} + */ + +/** + * @} + */ + + +#endif /* HAL_COMP_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.h new file mode 100644 index 00000000000..be9973422ad --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_comp_ex.h @@ -0,0 +1,91 @@ +/** + ****************************************************************************** + * @file stm32l0xx_hal_comp_ex.h + * @author MCD Application Team + * @version V1.2.0 + * @date 06-February-2015 + * @brief Header file of COMP HAL Extended module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_HAL_COMP_EX_H +#define __STM32L0xx_HAL_COMP_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_hal_def.h" + +/** @addtogroup STM32L0xx_HAL_Driver + * @{ + */ + +/** @defgroup COMPEx COMPEx + * @{ + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup COMPEx_Exported_Functions COMP Extended Exported Functions + * @{ + */ + +/** @defgroup COMPEx_Exported_Functions_Group1 Extended COMP VREFINT setup functions + * @{ + */ +/* COMP specific functions to manage VREFINT *************************************/ +void HAL_COMPEx_EnableVREFINT(void); +void HAL_COMPEx_DisableVREFINT(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_HAL_COMP_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h index 805a1803234..e7694284836 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_conf.h @@ -1,14 +1,16 @@ /** ****************************************************************************** - * @file stm32l0xx_hal_conf.h + * @file stm32l0xx_hal_conf_template.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 - * @brief HAL configuration file. + * @version V1.2.0 + * @date 06-February-2015 + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32l0xx_hal_conf.h. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -57,7 +59,8 @@ #define HAL_CRYP_MODULE_ENABLED #define HAL_DAC_MODULE_ENABLED #define HAL_DMA_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED +#define HAL_FIREWALL_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED #define HAL_GPIO_MODULE_ENABLED #define HAL_I2C_MODULE_ENABLED #define HAL_I2S_MODULE_ENABLED @@ -80,7 +83,6 @@ #define HAL_CORTEX_MODULE_ENABLED #define HAL_PCD_MODULE_ENABLED - /* ########################## Oscillator Values adaptation ####################*/ /** * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. @@ -102,7 +104,6 @@ #if !defined (MSI_VALUE) #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* MSI_VALUE */ - /** * @brief Internal High Speed oscillator (HSI) value. * This value is used by the RCC HAL module to compute the system frequency @@ -111,7 +112,7 @@ #if !defined (HSI_VALUE) #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ #endif /* HSI_VALUE */ - + /** * @brief External Low Speed oscillator (LSE) value. * This value is used by the UART, RTC HAL module to compute the system frequency @@ -134,10 +135,10 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY ((uint32_t)3) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (((uint32_t)1<<__NVIC_PRIO_BITS) - 1) /*!< tick interrupt priority */ #define USE_RTOS 0 #define PREFETCH_ENABLE 1 -#define PREREAD_ENABLE 1 +#define PREREAD_ENABLE 0 #define BUFFER_CACHE_DISABLE 0 /* ########################## Assert Selection ############################## */ @@ -155,7 +156,7 @@ #ifdef HAL_RCC_MODULE_ENABLED #include "stm32l0xx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ - + #ifdef HAL_GPIO_MODULE_ENABLED #include "stm32l0xx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ @@ -163,7 +164,7 @@ #ifdef HAL_DMA_MODULE_ENABLED #include "stm32l0xx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ - + #ifdef HAL_CORTEX_MODULE_ENABLED #include "stm32l0xx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ @@ -175,7 +176,7 @@ #ifdef HAL_COMP_MODULE_ENABLED #include "stm32l0xx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ - + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32l0xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ @@ -188,6 +189,10 @@ #include "stm32l0xx_hal_dac.h" #endif /* HAL_DAC_MODULE_ENABLED */ +#ifdef HAL_FIREWALL_MODULE_ENABLED + #include "stm32l0xx_hal_firewall.h" +#endif /* HAL_FIREWALL_MODULE_ENABLED */ + #ifdef HAL_FLASH_MODULE_ENABLED #include "stm32l0xx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ @@ -222,7 +227,6 @@ #ifdef HAL_RTC_MODULE_ENABLED #include "stm32l0xx_hal_rtc.h" - #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED @@ -290,3 +294,4 @@ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.c index 6db8507c73a..babbb7862f0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_cortex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -67,7 +67,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,26 +101,26 @@ * @{ */ -/** @defgroup CORTEX +/** @addtogroup CORTEX * @brief CORTEX HAL module driver * @{ */ #ifdef HAL_CORTEX_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ +/* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Functions +/** @addtogroup CORTEX_Exported_Functions * @{ */ -/** @defgroup CORTEX_Group1 Initialization and de-initialization functions +/** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -166,6 +166,9 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Enable interrupt */ NVIC_EnableIRQ(IRQn); } @@ -179,6 +182,9 @@ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) */ void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) { + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + /* Disable interrupt */ NVIC_DisableIRQ(IRQn); } @@ -209,7 +215,7 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) * @} */ -/** @defgroup CORTEX_Group2 Peripheral Control functions +/** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions * @brief Cortex control functions * @verbatim @@ -331,3 +337,4 @@ __weak void HAL_SYSTICK_Callback(void) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.h index 0818be7c2dc..bb9902e7c81 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cortex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_cortex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,34 +50,42 @@ * @{ */ -/** @addtogroup CORTEX +/** @defgroup CORTEX CORTEX * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Constants +/** @defgroup CORTEX_Exported_Constants CORTEX Exported constants * @{ */ -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) +#define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4) + +#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) /** @defgroup CORTEX_SysTick_clock_source * @{ */ #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) +#define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ + ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) /** * @} */ + +/** + * @} + */ /* Exported Macros -----------------------------------------------------------*/ - +/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros + * @{ + */ /** @brief Configures the SysTick clock source. - * @param __CLKSRC__: specifies the SysTick clock source. + * @param __CLKSRC__ : specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. @@ -97,16 +105,28 @@ * @} */ -/* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions *******************************/ +/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * @{ + */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); void HAL_NVIC_SystemReset(void); uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); - -/* Peripheral Control functions *************************************************/ +/** + * @} + */ + +/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions + * @brief Cortex control functions + * @{ + */ uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); @@ -114,6 +134,14 @@ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); void HAL_SYSTICK_IRQHandler(void); void HAL_SYSTICK_Callback(void); +/** + * @} + */ + + /** + * @} + */ + /** * @} */ @@ -130,3 +158,4 @@ void HAL_SYSTICK_Callback(void); /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.c index b662a88c4a6..a7f8f773b36 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_crc.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CRC HAL module driver. * * This file provides firmware functions to manage the following @@ -18,7 +18,7 @@ =============================================================================== [..] - (#) Enable CRC AHB clock using __CRC_CLK_ENABLE(); + (#) Enable CRC AHB clock using __HAL_RCC_CRC_CLK_ENABLE(); (#) Initialize CRC calculator (++) specify generating polynomial (IP default or non-default one) @@ -38,7 +38,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -72,7 +72,7 @@ * @{ */ -/** @defgroup CRC +/** @addtogroup CRC * @brief CRC HAL module driver * @{ */ @@ -87,14 +87,13 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength); static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength); -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup CRC_Private_Functions +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_Exported_Functions * @{ */ -/** @defgroup CRC_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup CRC_Exported_Functions_Group1 + * @brief Initialization and Configuration functions. * @verbatim =============================================================================== @@ -125,15 +124,19 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) { /* Check the CRC handle allocation */ - if(hcrc == HAL_NULL) + if(hcrc == NULL) { return HAL_ERROR; } - assert_param(IS_CRC_INSTANCE(hcrc->Instance)); + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); if(hcrc->State == HAL_CRC_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcrc->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_CRC_MspInit(hcrc); } @@ -199,12 +202,13 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) { /* Check the CRC handle allocation */ - if(hcrc == HAL_NULL) + if(hcrc == NULL) { return HAL_ERROR; } - assert_param(IS_CRC_INSTANCE(hcrc->Instance)); + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance)); /* Check the CRC peripheral state */ if(hcrc->State == HAL_CRC_STATE_BUSY) @@ -214,6 +218,9 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) /* Change CRC peripheral state */ hcrc->State = HAL_CRC_STATE_BUSY; + + /* Reset CRC calculation unit */ + __HAL_CRC_DR_RESET(hcrc); /* DeInit the low level hardware */ HAL_CRC_MspDeInit(hcrc); @@ -257,7 +264,7 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) * @} */ -/** @defgroup CRC_Group2 Peripheral Control functions +/** @addtogroup CRC_Exported_Functions_Group2 * @brief management functions. * @verbatim @@ -390,40 +397,6 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t } - -/** - * @} - */ - -/** @defgroup CRC_Group3 Peripheral State functions - * @brief Peripheral State functions. - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the CRC state. - * @param hcrc: CRC handle - * @retval HAL state - */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) -{ - return hcrc->State; -} - -/** - * @} - */ - /** * @brief Enter 8-bit input data to the CRC calculator. * Specific data handling to optimize processing time. @@ -434,30 +407,30 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) { - uint32_t i; /* input data buffer index */ + uint32_t i = 0; /* input data buffer index */ /* Processing time optimization: 4 bytes are entered in a row with a single word write, * last bytes must be carefully fed to the CRC calculator to ensure a correct type * handling by the IP */ for(i = 0; i < (BufferLength/4); i++) { - hcrc->Instance->DR = (uint32_t)(((uint32_t)(pBuffer[4*i])<<24) | ((uint32_t)(pBuffer[4*i+1])<<16) | ((uint32_t)(pBuffer[4*i+2])<<8) | (uint32_t)(pBuffer[4*i+3])); + hcrc->Instance->DR = (pBuffer[4*i]<<24) | (pBuffer[4*i+1]<<16) | (pBuffer[4*i+2]<<8) | pBuffer[4*i+3]; } /* last bytes specific handling */ if ((BufferLength%4) != 0) { if (BufferLength%4 == 1) { - *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i]; + *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i]; } if (BufferLength%4 == 2) { - *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1])); + *(uint16_t*) (&hcrc->Instance->DR) = (pBuffer[4*i]<<8) | pBuffer[4*i+1]; } if (BufferLength%4 == 3) { - *(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint32_t)(pBuffer[4*i])<<8) | (uint32_t)(pBuffer[4*i+1])); - *(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; + *(uint16_t*) (&hcrc->Instance->DR) = (pBuffer[4*i]<<8) | pBuffer[4*i+1]; + *(uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; } } @@ -475,18 +448,18 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) { - uint32_t i ; /* input data buffer index */ + uint32_t i = 0; /* input data buffer index */ /* Processing time optimization: 2 HalfWords are entered in a row with a single word write, * in case of odd length, last HalfWord must be carefully fed to the CRC calculator to ensure * a correct type handling by the IP */ for(i = 0; i < (BufferLength/2); i++) { - hcrc->Instance->DR = (((uint32_t)(pBuffer[2*i])<<16) | (uint32_t)(pBuffer[2*i+1])); + hcrc->Instance->DR = (pBuffer[2*i]<<16) | pBuffer[2*i+1]; } if ((BufferLength%2) != 0) { - *(__IO uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; + *(uint16_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; } /* Return the CRC computed value */ @@ -496,7 +469,40 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 * @} */ +/** @addtogroup CRC_Exported_Functions_Group3 + * @brief Peripheral State functions. + * +@verbatim + =============================================================================== + ##### Peripheral State functions ##### + =============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral. + +@endverbatim + * @{ + */ + +/** + * @brief Returns the CRC state. + * @param hcrc: CRC handle + * @retval HAL state + */ +HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc) +{ + return hcrc->State; +} + +/** + * @} + */ + +/** + * @} + */ + #endif /* HAL_CRC_MODULE_ENABLED */ + /** * @} */ @@ -506,3 +512,4 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.h index 96e051e9915..2ea77371eb0 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_crc.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup CRC +/** @defgroup CRC CRC * @{ */ @@ -60,14 +60,15 @@ * @brief CRC HAL State Structure definition */ typedef enum -{ - HAL_CRC_STATE_RESET = 0x00, /*!< CRC Reset State */ - HAL_CRC_STATE_READY = 0x01, /*!< CRC Initialized and ready for use */ - HAL_CRC_STATE_BUSY = 0x02, /*!< CRC process is ongoing */ - HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC Timeout State */ - HAL_CRC_STATE_ERROR = 0x04 /*!< CRC Error State */ +{ + HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */ + HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */ + HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */ + HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */ + HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */ }HAL_CRC_StateTypeDef; + /** * @brief CRC Init Structure definition */ @@ -89,7 +90,7 @@ typedef struct e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65. No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE */ - uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Size_Definitions and indicates CRC length. + uint32_t CRCLength; /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length. Value can be either one of CRC_POLYLENGTH_32B (32-bit CRC) CRC_POLYLENGTH_16B (16-bit CRC) @@ -98,18 +99,18 @@ typedef struct uint32_t InitValue; /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse is set to DEFAULT_INIT_VALUE_ENABLE */ - - uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRC_Input_Data_Inversion and specifies input data inversion mode. + + uint32_t InputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode. Can be either one of the following values CRC_INPUTDATA_INVERSION_NONE no input data inversion CRC_INPUTDATA_INVERSION_BYTE byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2 CRC_INPUTDATA_INVERSION_HALFWORD halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C CRC_INPUTDATA_INVERSION_WORD word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */ - uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRC_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. + uint32_t OutputDataInversionMode; /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode. Can be either - CRC_OUTPUTDATA_INVERSION_DISABLED no CRC inversion, or - CRC_OUTPUTDATA_INVERSION_ENABLED CRC 0x11223344 is converted into 0x22CC4488 */ + CRC_OUTPUTDATA_INVERSION_DISABLE no CRC inversion, or + CRC_OUTPUTDATA_INVERSION_ENABLE CRC 0x11223344 is converted into 0x22CC4488 */ }CRC_InitTypeDef; @@ -119,13 +120,13 @@ typedef struct typedef struct { CRC_TypeDef *Instance; /*!< Register base address */ - + CRC_InitTypeDef Init; /*!< CRC configuration parameters */ - + HAL_LockTypeDef Lock; /*!< CRC Locking object */ - + __IO HAL_CRC_StateTypeDef State; /*!< CRC communication state */ - + uint32_t InputDataFormat; /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format. Can be either CRC_INPUTDATA_FORMAT_BYTES input data is a stream of bytes (8-bit data) @@ -136,11 +137,11 @@ typedef struct }CRC_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ -/** @defgroup CRC_Exported_Constants +/** @defgroup CRC_Exported_Constants CRC exported constants * @{ */ -/** @defgroup CRC_Default_Polynomial_Value +/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial * @{ */ #define DEFAULT_CRC32_POLY 0x04C11DB7 @@ -149,7 +150,7 @@ typedef struct * @} */ -/** @defgroup CRC_Default_Init_Value +/** @defgroup CRC_Default_InitValue Default CRC computation initialization value * @{ */ #define DEFAULT_CRC_INITVALUE 0xFFFFFFFF @@ -158,45 +159,48 @@ typedef struct * @} */ -/** @defgroup CRC_Default_Polynomial +/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used * @{ */ #define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00) #define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01) -#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \ - ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE)) + +#define IS_DEFAULT_POLYNOMIAL(__DEFAULT__) (((__DEFAULT__) == DEFAULT_POLYNOMIAL_ENABLE) || \ + ((__DEFAULT__) == DEFAULT_POLYNOMIAL_DISABLE)) + /** * @} */ -/** @defgroup CRC_Default_InitValue_Use +/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used * @{ */ #define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00) #define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01) -#define IS_DEFAULT_INIT_VALUE(VALUE) (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \ - ((VALUE) == DEFAULT_INIT_VALUE_DISABLE)) + +#define IS_DEFAULT_INIT_VALUE(__VALUE__) (((__VALUE__) == DEFAULT_INIT_VALUE_ENABLE) || \ + ((__VALUE__) == DEFAULT_INIT_VALUE_DISABLE)) /** * @} */ -/** @defgroup CRC_Polynomial_Sizes +/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP * @{ */ #define CRC_POLYLENGTH_32B ((uint32_t)0x00000000) #define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0) #define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1) #define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE) -#define IS_CRC_POL_LENGTH(LENGTH) (((LENGTH) == CRC_POLYLENGTH_32B) || \ - ((LENGTH) == CRC_POLYLENGTH_16B) || \ - ((LENGTH) == CRC_POLYLENGTH_8B) || \ - ((LENGTH) == CRC_POLYLENGTH_7B)) +#define IS_CRC_POL_LENGTH(__LENGTH__) (((__LENGTH__) == CRC_POLYLENGTH_32B) || \ + ((__LENGTH__) == CRC_POLYLENGTH_16B) || \ + ((__LENGTH__) == CRC_POLYLENGTH_8B) || \ + ((__LENGTH__) == CRC_POLYLENGTH_7B)) /** * @} */ -/** @defgroup CRC_Polynomial_Size_Definitions +/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions * @{ */ #define HAL_CRC_LENGTH_32B 32 @@ -208,33 +212,7 @@ typedef struct * @} */ -/** @defgroup CRC_Input_Data_Inversion - * @{ - */ -#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) -#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) -#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) -#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) -#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_INPUTDATA_INVERSION_NONE) || \ - ((MODE) == CRC_INPUTDATA_INVERSION_BYTE) || \ - ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ - ((MODE) == CRC_INPUTDATA_INVERSION_WORD)) -/** - * @} - */ - -/** @defgroup CRC_Output_Data_Inversion - * @{ - */ -#define CRC_OUTPUTDATA_INVERSION_DISABLED ((uint32_t)0x00000000) -#define CRC_OUTPUTDATA_INVERSION_ENABLED ((uint32_t)CRC_CR_REV_OUT) -#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE) (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLED) || \ - ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLED)) -/** - * @} - */ - -/** @defgroup CRC_Input_Buffer_Format +/** @defgroup CRC_Input_Buffer_Format CRC input buffer format * @{ */ /* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but @@ -245,9 +223,10 @@ typedef struct #define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001) #define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002) #define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003) -#define IS_CRC_INPUTDATA_FORMAT(FORMAT) (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES) || \ - ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ - ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS)) + +#define IS_CRC_INPUTDATA_FORMAT(__FORMAT__) (((__FORMAT__) == CRC_INPUTDATA_FORMAT_BYTES) || \ + ((__FORMAT__) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \ + ((__FORMAT__) == CRC_INPUTDATA_FORMAT_WORDS)) /** * @} */ @@ -255,25 +234,18 @@ typedef struct /** * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CRC_Exported_Macro +/** @defgroup CRC_Exported_Macros CRC exported macros * @{ */ /** @brief Reset CRC handle state - * @param __HANDLE__: CRC handle + * @param __HANDLE__: CRC handle. * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) -/** - * @brief Check that instance is correctly set to CRC - * @param __PERIPH__: CRC handle instance - * @retval None. - */ -#define IS_CRC_INSTANCE(__PERIPH__) ((__PERIPH__) == CRC) - /** * @brief Reset CRC Data Register. * @param __HANDLE__: CRC handle @@ -289,23 +261,20 @@ typedef struct */ #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) - /** - * @brief Set CRC output reversal - * @param __HANDLE__ : CRC handle - * @retval None. + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * @param __HANDLE__: CRC handle + * @param __VALUE__: 8-bit value to be stored in the ID register + * @retval None */ -#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) - +#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__)) /** - * @brief Unset CRC output reversal - * @param __HANDLE__ : CRC handle - * @retval None. + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * @param __HANDLE__: CRC handle + * @retval 8-bit value of the ID register */ -#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) - - +#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR) /** * @} */ @@ -315,19 +284,49 @@ typedef struct #include "stm32l0xx_hal_crc_ex.h" /* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_Exported_Functions CRC Exported Functions + * @{ + */ +/** @defgroup CRC_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc); HAL_StatusTypeDef HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc); void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc); void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/* Aliases for inter STM32 series compatibility */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse +/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ /* Peripheral Control functions ***********************************************/ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength); +/** + * @} + */ +/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions + * @{ + */ /* Peripheral State and Error functions ***************************************/ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +/** + * @} + */ + +/** + * @} + */ + /** * @} @@ -344,3 +343,4 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); #endif /* __STM32L0xx_HAL_CRC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.c index e73023fd2fc..73343a06656 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Extended CRC HAL module driver. * * This file provides firmware functions to manage the following @@ -16,33 +16,14 @@ ============================================================================== [..] (#) Polynomial configuration. - - - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Enable CRC AHB clock using __CRC_CLK_ENABLE(); - - (#) Initialize CRC calculator - (++) specify generating polynomial (IP default or non-default one) - (++) specify initialization value (IP default or non-default one) - (++) specify input data format - (++) specify input or output data inversion mode if any - - (#) Use HAL_CRC_Accumulate() function to compute the CRC value of the - input data buffer starting with the previously computed CRC as - initialization value - - (#) Use HAL_CRC_Calculate() function to compute the CRC value of the - input data buffer starting with the defined initialization value - (default or non-default) to initiate CRC calculation + (#) Input data reverse mode. + (#) Output data reverse mode. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -76,10 +57,10 @@ * @{ */ -/** @addtogroup CRCEx - * @brief CRC driver modules +/** @addtogroup CRCEx + * @brief CRC Extended HAL module driver * @{ - */ + */ #ifdef HAL_CRC_MODULE_ENABLED @@ -90,9 +71,12 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/** @addtogroup CRCEx_Exported_Functions + * @{ + */ -/** @defgroup CRCEx_Group CRC Extended features functions - * @brief CRC Extended features functions +/** @addtogroup CRCEx_Exported_Functions_Group1 + * @brief Extended CRC features functions * @verbatim =============================================================================== @@ -136,29 +120,18 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol * Look for MSB position: msb will contain the degree of * the second to the largest polynomial member. E.g., for * X^7 + X^6 + X^5 + X^2 + 1, msb = 6. */ - while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0)) - { - } + while (((Pol & ((uint32_t)(0x1) << msb)) == 0) && (msb-- > 0)); switch (PolyLength) { case CRC_POLYLENGTH_7B: - if (msb >= HAL_CRC_LENGTH_7B) - { - return HAL_ERROR; - } + if (msb >= HAL_CRC_LENGTH_7B) return HAL_ERROR; break; case CRC_POLYLENGTH_8B: - if (msb >= HAL_CRC_LENGTH_8B) - { - return HAL_ERROR; - } + if (msb >= HAL_CRC_LENGTH_8B) return HAL_ERROR; break; case CRC_POLYLENGTH_16B: - if (msb >= HAL_CRC_LENGTH_16B) - { - return HAL_ERROR; - } + if (msb >= HAL_CRC_LENGTH_16B) return HAL_ERROR; break; case CRC_POLYLENGTH_32B: /* no polynomial definition vs. polynomial length issue possible */ @@ -188,7 +161,7 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol * @arg CRC_INPUTDATA_INVERSION_WORD: Word-wise bit reversal * @retval HAL status */ -HAL_StatusTypeDef HAL_CRC_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode) { /* Check the parameters */ assert_param(IS_CRC_INPUTDATA_INVERSION_MODE(InputReverseMode)); @@ -210,11 +183,11 @@ HAL_StatusTypeDef HAL_CRC_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t I * @param hcrc: CRC handle * @param OutputReverseMode: Output Data inversion mode * This parameter can be one of the following values: - * @arg CRC_OUTPUTDATA_INVERSION_DISABLED: no CRC inversion (default value) - * @arg CRC_OUTPUTDATA_INVERSION_ENABLED: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) + * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value) + * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD) * @retval HAL status */ -HAL_StatusTypeDef HAL_CRC_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode) { /* Check the parameters */ assert_param(IS_CRC_OUTPUTDATA_INVERSION_MODE(OutputReverseMode)); @@ -232,6 +205,14 @@ HAL_StatusTypeDef HAL_CRC_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t return HAL_OK; } + + + +/** + * @} + */ + + /** * @} */ @@ -247,3 +228,4 @@ HAL_StatusTypeDef HAL_CRC_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.h index 4c6dd078a57..d4e08d31797 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_crc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_crc_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 - * @brief Header file of CRC HAL module. + * @version V1.2.0 + * @date 06-February-2015 + * @brief Header file of CRC HAL extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,18 +50,68 @@ * @{ */ -/** @addtogroup CRCEx +/** @defgroup CRCEx CRCEx * @{ */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ + +/** @defgroup CRCEx_Exported_Constants CRC Extended exported constants + * @{ + */ + +/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes + * @{ + */ +#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000) +#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0) +#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1) +#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN) + +#define IS_CRC_INPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_INPUTDATA_INVERSION_NONE) || \ + ((__MODE__) == CRC_INPUTDATA_INVERSION_BYTE) || \ + ((__MODE__) == CRC_INPUTDATA_INVERSION_HALFWORD) || \ + ((__MODE__) == CRC_INPUTDATA_INVERSION_WORD)) +/** + * @} + */ + +/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes + * @{ + */ +#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000) +#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT) + +#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \ + ((__MODE__) == CRC_OUTPUTDATA_INVERSION_ENABLE)) +/** + * @} + */ + + +/** + * @} + */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRCEx_Extended_Exported_Macro +/** @defgroup CRCEx_Exported_Macros CRC Extended exported macros * @{ */ + +/** + * @brief Set CRC output reversal + * @param __HANDLE__ : CRC handle + * @retval None. + */ +#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT) +/** + * @brief Unset CRC output reversal + * @param __HANDLE__ : CRC handle + * @retval None. + */ +#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT)) /** * @brief Set CRC non-default polynomial @@ -70,22 +120,36 @@ * @retval None. */ #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__)) - - + /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRCEx_Exported_Functions CRC Extended Exported Functions + * @{ + */ + +/** @defgroup CRCEx_Exported_Functions_Group1 Extended CRC features functions + * @{ + */ +/* Exported functions --------------------------------------------------------*/ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength); -HAL_StatusTypeDef HAL_CRC_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); -HAL_StatusTypeDef HAL_CRC_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); +HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode); +HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode); /* Peripheral Control functions ***********************************************/ /* Peripheral State and Error functions ***************************************/ +/** + * @} + */ + +/** + * @} + */ + /** * @} @@ -102,3 +166,4 @@ HAL_StatusTypeDef HAL_CRC_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t #endif /* __STM32L0xx_HAL_CRC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.c index c1aa51c721f..a7987df3383 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_cryp.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CRYP HAL module driver. * * This file provides firmware functions to manage the following @@ -22,18 +22,18 @@ The CRYP HAL driver can be used as follows: (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE() - (##) In case of using interrupts (e.g. HAL_AES_ECB_Encrypt_IT()) + (##) Enable the CRYP interface clock using __HAL_RCC_AES_CLK_ENABLE() + (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT()) (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA()) + (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA()) (+) Enable the DMA1 interface clock using - (++) __DMA1_CLK_ENABLE() + (++) __HAL_RCC_DMA1_CLK_ENABLE() (+) Configure and enable two DMA Channels one for managing data transfer from memory to peripheral (input channel) and another channel for managing data transfer from peripheral to memory (output channel) - (+) Associate the initilalized DMA handle to the CRYP DMA handle + (+) Associate the initialized DMA handle to the CRYP DMA handle using __HAL_LINKDMA() (+) Configure the priority and enable the NVIC for the transfer complete interrupt on the two DMA Streams. The output stream should have higher @@ -57,20 +57,20 @@ i.e. the data transfer is ensured by DMA e.g. HAL_CRYP_AESCBC_Encrypt_DMA() - (#)When the processing function is called at first time after HAL_CRYP_Init() + (#)When the processing function is called for the first time after HAL_CRYP_Init() the CRYP peripheral is initialized and processes the buffer in input. At second call, the processing function performs an append of the already processed buffer. When a new data block is to be processed, call HAL_CRYP_Init() then the processing function. - (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. + (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -97,41 +97,62 @@ ****************************************************************************** */ +#if defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#ifdef HAL_CRYP_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup CRYP +/** @defgroup CRYP CRYP * @brief CRYP HAL module driver. * @{ */ -#ifdef HAL_CRYP_MODULE_ENABLED -#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ + +/** @defgroup CRYP_Private_Defines CRYP Private Defines + * @{ + */ + #define CRYP_ALGO_CHAIN_MASK (AES_CR_MODE | AES_CR_CHMOD) + +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector); -static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key); -static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout); -static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); -static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); -static void CRYP_DMAError(DMA_HandleTypeDef *hdma); -static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); + +/** @defgroup CRYP_Private_Functions CRYP Private Functions + * @{ + */ + +static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp); +static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector); +static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key); +static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout); +static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma); +static void CRYP_DMAError(DMA_HandleTypeDef *hdma); +static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr); + +/** + * @} + */ + /* Private functions ---------------------------------------------------------*/ -/** @defgroup CRYP_Private_Functions +/** @defgroup CRYP_Exported_Functions CRYP Exported Functions * @{ */ -/** @defgroup CRYP_Group1 Initialization and de-initialization functions +/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions. * @verbatim @@ -157,40 +178,57 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) -{ +{ /* Check the CRYP handle allocation */ - if(hcryp == HAL_NULL) + if(hcryp == NULL) { return HAL_ERROR; } /* Check the parameters */ + assert_param(IS_AES_ALL_INSTANCE(hcryp->Instance)); assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType)); if(hcryp->State == HAL_CRYP_STATE_RESET) { + /* Allocate lock resource and initialize it */ + hcryp->Lock = HAL_UNLOCKED; + /* Init the low level hardware */ HAL_CRYP_MspInit(hcryp); } - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Set the data type*/ - AES->CR = hcryp->Init.DataType; - - /* Reset CrypInCount and CrypOutCount */ - hcryp->CrypInCount = 0; - hcryp->CrypOutCount = 0; - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Set the default CRYP phase */ - hcryp->Phase = HAL_CRYP_PHASE_READY; - - /* Return function status */ - return HAL_OK; + /* Check if AES already enabled */ + if (HAL_IS_BIT_CLR(hcryp->Instance->CR, AES_CR_EN)) + { + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + + /* Set the data type*/ + MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType); + + /* Reset CrypInCount and CrypOutCount */ + hcryp->CrypInCount = 0; + hcryp->CrypOutCount = 0; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Set the default CRYP phase */ + hcryp->Phase = HAL_CRYP_PHASE_READY; + + /* Return function status */ + return HAL_OK; + } + else + { + /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */ + /* enabled is forbidden to avoid unpredictable AES behavior.*/ + + /* Return function status */ + return HAL_ERROR; + } + } /** @@ -202,7 +240,7 @@ HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp) HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) { /* Check the CRYP handle allocation */ - if(hcryp == HAL_NULL) + if(hcryp == NULL) { return HAL_ERROR; } @@ -218,7 +256,7 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) hcryp->CrypOutCount = 0; /* Disable the CRYP Peripheral Clock */ - __HAL_CRYP_DISABLE(); + __HAL_CRYP_DISABLE(hcryp); /* DeInit the low level hardware: CLOCK, NVIC.*/ HAL_CRYP_MspDeInit(hcryp); @@ -241,9 +279,8 @@ HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp) */ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspInit could be implemented in the user file - */ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspInit can be implemented in the user file */ } /** @@ -254,16 +291,15 @@ __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp) */ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_MspDeInit could be implemented in the user file - */ + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_MspDeInit can be implemented in the user file */ } /** * @} */ -/** @defgroup CRYP_Group2 AES processing functions +/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions * @brief processing functions. * @verbatim @@ -287,9 +323,9 @@ __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp) * then encrypt pPlainData. The cypher data are available in pCypherData * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Timeout: Specify Timeout value * @retval HAL status */ @@ -297,43 +333,65 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP { /* Process Locked */ __HAL_LOCK(hcryp); + + /* Check that data aligned on u32 and Size multiple of 16*/ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB mode */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + /* Write Plain Data and Get Cypher Data */ + if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK) + else { - return HAL_TIMEOUT; + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; } /** @@ -341,9 +399,9 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP * then encrypt pPlainData. The cypher data are available in pCypherData * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Timeout: Specify Timeout value * @retval HAL status */ @@ -352,45 +410,67 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /* Process Locked */ __HAL_LOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CBC mode */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp,pPlainData, Size, pCypherData, Timeout) != HAL_OK) + if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) { return HAL_TIMEOUT; } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } } /** @@ -398,9 +478,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP * then encrypt pPlainData. The cypher data are available in pCypherData * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Timeout: Specify Timeout value * @retval HAL status */ @@ -409,57 +489,77 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pP /* Process Locked */ __HAL_LOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CTR mode */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Write Plain Data and Get Cypher Data */ if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK) { return HAL_TIMEOUT; } + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; + } + else + { + /* Release Lock */ + __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_ERROR; + } } - - /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Timeout: Specify Timeout value * @retval HAL status */ @@ -468,42 +568,64 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /* Process Locked */ __HAL_LOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } - /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + /* Write Cypher Data and Get Plain Data */ + if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; + /* Return function status */ + return HAL_OK; } + else + { + /* Release Lock */ + __HAL_UNLOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_ERROR; + } } /** @@ -511,9 +633,9 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC * then decrypted pCypherData. The cypher data are available in pPlainData * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Timeout: Specify Timeout value * @retval HAL status */ @@ -522,45 +644,67 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /* Process Locked */ __HAL_LOCK(hcryp); - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) + /* Check if HAL_CRYP_Init has been called */ + if(hcryp->State != HAL_CRYP_STATE_RESET) { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Enable CRYP */ + __HAL_CRYP_ENABLE(hcryp); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } - /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + /* Write Cypher Data and Get Plain Data */ + if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; - /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + /* Return function status */ + return HAL_OK; } - - /* Write Plain Data and Get Cypher Data */ - if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) + else { - return HAL_TIMEOUT; - } - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); + /* Release Lock */ + __HAL_UNLOCK(hcryp); - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_ERROR; + } } /** @@ -568,9 +712,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC * then decrypted pCypherData. The cypher data are available in pPlainData * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Timeout: Specify Timeout value * @retval HAL status */ @@ -579,8 +723,18 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /* Process Locked */ __HAL_LOCK(hcryp); + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } + /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY)) { /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; @@ -588,23 +742,23 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC /* Set the key */ CRYP_SetKey(hcryp, hcryp->Init.pKey); - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CTR decryption mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - + /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } - /* Write Plain Data and Get Cypher Data */ + /* Write Cypher Data and Get Plain Data */ if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK) { return HAL_TIMEOUT; @@ -624,17 +778,26 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pC * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if(hcryp->State == HAL_CRYP_STATE_READY) + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -654,111 +817,73 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Set the key */ CRYP_SetKey(hcryp, hcryp->Init.pKey); - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; /* Return function status */ return HAL_OK; } - - else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF)) + else { - /* Clear CCF Flag */ - AES->CR |= AES_CR_CCFC; - - /* Get the last Output data adress */ - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - - /* Read the Output block from the Data Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - - /* Check if all input text is encrypted */ - if(hcryp->CrypOutCount == 0) - { - /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call computation complete callback */ - HAL_CRYPEx_ComputationCpltCallback(hcryp); - } - else /* Process the rest of input text */ - { - /* Get the last Intput data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - } - } + /* Release Lock */ + __HAL_UNLOCK(hcryp); - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_ERROR; + } } /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if(hcryp->State == HAL_CRYP_STATE_READY) + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -778,11 +903,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Set the key */ CRYP_SetKey(hcryp, hcryp->Init.pKey); - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CBC mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -792,100 +917,62 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; /* Return function status */ return HAL_OK; } - - else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF)) + else { - /* Clear CCF Flag */ - AES->CR |= AES_CR_CCFC; - - /* Get the last Output data adress */ - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - - /* Read the Output block from the Data Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - - /* Check if all input text is encrypted */ - if(hcryp->CrypOutCount == 0) - { - /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call computation complete callback */ - HAL_CRYPEx_ComputationCpltCallback(hcryp); - } - else /* Process the rest of input text */ - { - /* Get the last Intput data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - } + /* Release Lock */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; } - - /* Return function status */ - return HAL_OK; } /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if(hcryp->State == HAL_CRYP_STATE_READY) + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -905,11 +992,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Set the key */ CRYP_SetKey(hcryp, hcryp->Init.pKey); - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); @@ -919,101 +1006,62 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t } /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; /* Return function status */ return HAL_OK; } - - else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF)) + else { - /* Clear CCF Flag */ - AES->CR |= AES_CR_CCFC; - - /* Get the last Output data adress */ - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - - /* Read the Output block from the Data Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - - /* Check if all input text is encrypted */ - if(hcryp->CrypOutCount == 0) - { - /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call computation complete callback */ - HAL_CRYPEx_ComputationCpltCallback(hcryp); - } - else /* Process the rest of input text */ - { - /* Get the last Intput data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - } - } + /* Release Lock */ + __HAL_UNLOCK(hcryp); - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_ERROR; + } } - /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if(hcryp->State == HAL_CRYP_STATE_READY) + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1027,118 +1075,79 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; /* Return function status */ return HAL_OK; } - - else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF)) + else { - /* Clear CCF Flag */ - AES->CR |= AES_CR_CCFC; - - /* Get the last Output data adress */ - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - - /* Read the Output block from the Output register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - - /* Check if all input text is decrypted */ - if(hcryp->CrypOutCount == 0) - { - /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call computation complete callback */ - HAL_CRYPEx_ComputationCpltCallback(hcryp); - } - else /* Process the rest of input text */ - { - /* Get the last Intput data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - } - } + /* Release Lock */ + __HAL_UNLOCK(hcryp); - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_ERROR; + } } /** * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if(hcryp->State == HAL_CRYP_STATE_READY) + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1152,121 +1161,82 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; /* Return function status */ return HAL_OK; } - - else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF)) - { - /* Clear CCF Flag */ - AES->CR |= AES_CR_CCFC; - - /* Get the last Output data adress */ - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - - /* Read the Output block from the Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - - /* Check if all input text is decrypted */ - if(hcryp->CrypOutCount == 0) - { - /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call computation complete callback */ - HAL_CRYPEx_ComputationCpltCallback(hcryp); - } - else /* Process the rest of input text */ - { - /* Get the last Intput data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - } - } + else + { + /* Release Lock */ + __HAL_UNLOCK(hcryp); - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_ERROR; + } } /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if(hcryp->State == HAL_CRYP_STATE_READY) + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1280,121 +1250,83 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - /* Check if initialization phase has already been performed */ - if(hcryp->Phase == HAL_CRYP_PHASE_READY) - { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES CTR decryption mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); - - /* Set the Initialization Vector */ - CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + /* Check if initialization phase has already been performed */ + if(hcryp->Phase == HAL_CRYP_PHASE_READY) + { + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES CTR decryption mode */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + + /* Set the Initialization Vector */ + CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Enable Interrupts */ - __HAL_CRYP_ENABLE_IT(AES_IT_CC); + __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CC); /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); /* Get the last input data adress */ inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); hcryp->pCrypInBuffPtr += 16; hcryp->CrypInCount -= 16; /* Return function status */ return HAL_OK; } - - else if(__HAL_CRYP_GET_FLAG(AES_FLAG_CCF)) + else { - /* Clear CCF Flag */ - AES->CR |= AES_CR_CCFC; - - /* Get the last Output data adress */ - outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; - - /* Read the Output block from the Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; - - hcryp->pCrypOutBuffPtr += 16; - hcryp->CrypOutCount -= 16; - - /* Check if all input text is decrypted */ - if(hcryp->CrypOutCount == 0) - { - /* Disable Computation Complete Interrupt */ - __HAL_CRYP_DISABLE_IT(AES_IT_CC); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_READY; - - /* Call computation complete callback */ - HAL_CRYPEx_ComputationCpltCallback(hcryp); - } - else /* Process the rest of input text */ - { - /* Get the last Intput data adress */ - inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; - - /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); - hcryp->pCrypInBuffPtr += 16; - hcryp->CrypInCount -= 16; - } - } + /* Release Lock */ + __HAL_UNLOCK(hcryp); - /* Return function status */ - return HAL_OK; + /* Return function status */ + return HAL_ERROR; + } } /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1412,22 +1344,25 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } /* Set the input and output addresses and start DMA transfer */ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); /* Process Unlocked */ __HAL_UNLOCK(hcryp); - + /* Return function status */ return HAL_OK; } else - { + { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1436,17 +1371,27 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1456,33 +1401,36 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /* Change the CRYP state */ hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Check if initialization phase has already been performed */ if(hcryp->Phase == HAL_CRYP_PHASE_READY) { /* Set the key */ CRYP_SetKey(hcryp, hcryp->Init.pKey); - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); + /* Set the CRYP peripheral in AES CBC mode */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; - } - /* Set the input and output addresses and start DMA transfer */ - CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - - /* Return function status */ - return HAL_OK; + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + } + /* Set the input and output addresses and start DMA transfer */ + CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_OK; } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1491,17 +1439,27 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1509,23 +1467,23 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t inputaddr = (uint32_t)pPlainData; outputaddr = (uint32_t)pCypherData; - /* Change the CRYP state */ - hcryp->State = HAL_CRYP_STATE_BUSY; - + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_BUSY; + /* Check if initialization phase has already been performed */ if(hcryp->Phase == HAL_CRYP_PHASE_READY) { /* Set the key */ CRYP_SetKey(hcryp, hcryp->Init.pKey); - /* Set the CRYP peripheral in AES ECB mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); + /* Set the CRYP peripheral in AES CTR mode */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } /* Set the input and output addresses and start DMA transfer */ @@ -1539,6 +1497,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1547,17 +1508,27 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1571,30 +1542,33 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t /* Check if initialization phase has already been performed */ if(hcryp->Phase == HAL_CRYP_PHASE_READY) { - /* Set the key */ - CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); - - /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); - - /* Set the phase */ - hcryp->Phase = HAL_CRYP_PHASE_PROCESS; + /* Set the key */ + CRYP_SetKey(hcryp, hcryp->Init.pKey); + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + + /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */ + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT); + + /* Set the phase */ + hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } - + /* Set the input and output addresses and start DMA transfer */ CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr); - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); /* Return function status */ return HAL_OK; } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1603,17 +1577,27 @@ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1629,16 +1613,16 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t { /* Set the key */ CRYP_SetKey(hcryp, hcryp->Init.pKey); - - /* Reset the CHMOD & MODE bits & */ - AES->CR &= (uint32_t)(~CRYP_ALGO_CHAIN_MASK); - + + /* Reset the CHMOD & MODE bits */ + CLEAR_BIT(hcryp->Instance->CR, CRYP_ALGO_CHAIN_MASK); + /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); - + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT); + /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - + /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } @@ -1654,6 +1638,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1662,17 +1649,27 @@ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer + * @param pCypherData: Pointer to the cyphertext buffer (aligned on u32) * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pPlainData: Pointer to the plaintext buffer (aligned on u32) * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) { - uint32_t inputaddr; - uint32_t outputaddr; + uint32_t inputaddr = 0, outputaddr = 0; + + /* Check that data aligned on u32 */ + if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0)) + { + /* Process Locked */ + __HAL_UNLOCK(hcryp); + + /* Return function status */ + return HAL_ERROR; + } - if((hcryp->State == HAL_CRYP_STATE_READY) || (hcryp->Phase == HAL_CRYP_PHASE_PROCESS)) + /* Check if HAL_CRYP_Init has been called */ + if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY)) { /* Process Locked */ __HAL_LOCK(hcryp); @@ -1690,11 +1687,11 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t CRYP_SetKey(hcryp, hcryp->Init.pKey); /* Set the CRYP peripheral in AES CTR mode */ - __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); + __HAL_CRYP_SET_MODE(hcryp, CRYP_CR_ALGOMODE_AES_CTR_DECRYPT); /* Set the Initialization Vector */ CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect); - + /* Set the phase */ hcryp->Phase = HAL_CRYP_PHASE_PROCESS; } @@ -1710,6 +1707,9 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t } else { + /* Release Lock */ + __HAL_UNLOCK(hcryp); + return HAL_ERROR; } } @@ -1718,8 +1718,7 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t * @} */ - -/** @defgroup CRYP_Group3 DMA callback functions +/** @defgroup CRYP_Exported_Functions_Group3 DMA callback functions * @brief DMA callback functions. * @verbatim @@ -1736,41 +1735,41 @@ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t */ /** - * @brief CRYP error callbacks. + * @brief CRYP error callback. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_ErrorCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_ErrorCallback can be implemented in the user file */ } /** - * @brief Input transfer completed callbacks. + * @brief Input transfer completed callback. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_InCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_InCpltCallback can be implemented in the user file */ } /** - * @brief Output transfer completed callbacks. + * @brief Output transfer completed callback. * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_CRYP_OutCpltCallback could be implemented in the user file + /* NOTE : This function should not be modified; when the callback is needed, + the HAL_CRYP_OutCpltCallback can be implemented in the user file */ } @@ -1778,7 +1777,7 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) * @} */ -/** @defgroup CRYP_Group4 CRYP IRQ handler +/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler * @brief CRYP IRQ handler. * @verbatim @@ -1799,34 +1798,44 @@ __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp) */ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) { - switch(AES->CR & CRYP_CR_ALGOMODE_DIRECTION) + /* Check if error occurred*/ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERR) != RESET) { - case CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT: - HAL_CRYP_AESECB_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL); - break; + if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_RDERR) != RESET) + { + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_RDERR); + } - case CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT: - HAL_CRYP_AESECB_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL); - break; + if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_WRERR) != RESET) + { + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_WRERR); + } - case CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT: - HAL_CRYP_AESCBC_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL); - break; + if (__HAL_CRYP_GET_FLAG(hcryp,CRYP_FLAG_CCF) != RESET) + { + __HAL_CRYP_CLEAR_FLAG(hcryp,CRYP_CLEARFLAG_CCF); + } - case CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT: - HAL_CRYP_AESCBC_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL); - break; + hcryp->State= HAL_CRYP_STATE_ERROR; + /* Disable Computation Complete Interrupt */ + __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC); + __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR); - case CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT: - HAL_CRYP_AESCTR_Encrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL); - break; + HAL_CRYP_ErrorCallback(hcryp); - case CRYP_CR_ALGOMODE_AES_CTR_DECRYPT: - HAL_CRYP_AESCTR_Decrypt_IT(hcryp, HAL_NULL, 0, HAL_NULL); - break; + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); - default: - break; + return; + } + + /* Check if computation complete interrupt was enabled*/ + if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CC) != RESET) + { + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF); + + CRYP_EncryptDecrypt_IT(hcryp); } } @@ -1834,7 +1843,7 @@ void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp) * @} */ -/** @defgroup CRYP_Group5 Peripheral State functions +/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions * @brief Peripheral State functions. * @verbatim @@ -1863,6 +1872,73 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp) * @} */ +/** + * @} + */ + +/** @addtogroup CRYP_Private_Functions + * @{ + */ + +/** + * @brief IT function called under interruption context to continue encryption or decryption + * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * the configuration information for CRYP module + * @retval HAL status + */ +static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp) +{ + uint32_t inputaddr = 0, outputaddr = 0; + + /* Get the last Output data adress */ + outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr; + + /* Read the Output block from the Output Register */ + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + outputaddr+=4; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; + + hcryp->pCrypOutBuffPtr += 16; + hcryp->CrypOutCount -= 16; + + /* Check if all input text is encrypted or decrypted */ + if(hcryp->CrypOutCount == 0) + { + /* Disable Computation Complete Interrupt */ + __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_CC); + __HAL_CRYP_DISABLE_IT(hcryp,CRYP_IT_ERR); + + /* Process Unlocked */ + __HAL_UNLOCK(hcryp); + + /* Change the CRYP state */ + hcryp->State = HAL_CRYP_STATE_READY; + + /* Call computation complete callback */ + HAL_CRYPEx_ComputationCpltCallback(hcryp); + } + else /* Process the rest of input text */ + { + /* Get the last Intput data adress */ + inputaddr = (uint32_t)hcryp->pCrypInBuffPtr; + + /* Write the Input block in the Data Input register */ + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + inputaddr+=4; + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); + hcryp->pCrypInBuffPtr += 16; + hcryp->CrypInCount -= 16; + } + return HAL_OK; +} /** * @brief DMA CRYP Input Data process complete callback. * @param hdma: DMA handle @@ -1873,7 +1949,7 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; /* Disable the DMA transfer for input request */ - AES->CR &= (uint32_t)(~AES_CR_DMAINEN); + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); /* Call input data transfer complete callback */ HAL_CRYP_InCpltCallback(hcryp); @@ -1888,12 +1964,15 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - /* Disable the DMA transfer for output request by resetting the DOEN bit + /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit in the DMACR register */ - AES->CR &= (uint32_t)(~AES_CR_DMAOUTEN); - + CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN); + + /* Clear CCF Flag */ + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF); + /* Disable CRYP */ - __HAL_CRYP_DISABLE(); + __HAL_CRYP_DISABLE(hcryp); /* Change the CRYP state to ready */ hcryp->State = HAL_CRYP_STATE_READY; @@ -1910,7 +1989,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) static void CRYP_DMAError(DMA_HandleTypeDef *hdma) { CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - hcryp->State= HAL_CRYP_STATE_READY; + hcryp->State= HAL_CRYP_STATE_ERROR; HAL_CRYP_ErrorCallback(hcryp); } @@ -1919,20 +1998,25 @@ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @note Key must be written as little endian. + * If Key pointer points at address n, + * n[15:0] contains key[96:127], + * (n+4)[15:0] contains key[64:95], + * (n+8)[15:0] contains key[32:63] and + * (n+12)[15:0] contains key[0:31] * @retval None */ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key) -{ +{ uint32_t keyaddr = (uint32_t)Key; - AES->KEYR3 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR3 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; - AES->KEYR2 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR2 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; - AES->KEYR1 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR1 = __REV(*(uint32_t*)(keyaddr)); keyaddr+=4; - AES->KEYR0 = __REV(*(uint32_t*)(keyaddr)); + hcryp->Instance->KEYR0 = __REV(*(uint32_t*)(keyaddr)); } /** @@ -1940,55 +2024,61 @@ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key) * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param InitVector: Pointer to InitVector/InitCounter buffer - * @param IVSize: Size of the InitVector/InitCounter + * @note Init Vector must be written as little endian. + * If Init Vector pointer points at address n, + * n[15:0] contains Vector[96:127], + * (n+4)[15:0] contains Vector[64:95], + * (n+8)[15:0] contains Vector[32:63] and + * (n+12)[15:0] contains Vector[0:31] * @retval None */ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) { uint32_t ivaddr = (uint32_t)InitVector; - AES->IVR3 = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->IVR3 = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; - AES->IVR2 = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->IVR2 = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; - AES->IVR1 = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->IVR1 = __REV(*(uint32_t*)(ivaddr)); ivaddr+=4; - AES->IVR0 = __REV(*(uint32_t*)(ivaddr)); + hcryp->Instance->IVR0 = __REV(*(uint32_t*)(ivaddr)); } /** - * @brief Process Data: Writes Input data in polling mode and read the output data + * @brief Process Data: Writes Input data in polling mode and reads the output data * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @param Input: Pointer to the Input buffer * @param Ilength: Length of the Input buffer, must be a multiple of 16. * @param Output: Pointer to the returned buffer + * @param Timeout: Specify Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) { uint32_t tickstart = 0; - uint32_t i = 0; + uint32_t index = 0; uint32_t inputaddr = (uint32_t)Input; uint32_t outputaddr = (uint32_t)Output; - for(i=0; (i < Ilength); i+=16) + for(index=0; (index < Ilength); index += 16) { /* Write the Input block in the Data Input register */ - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; - AES->DINR = *(uint32_t*)(inputaddr); + hcryp->Instance->DINR = *(uint32_t*)(inputaddr); inputaddr+=4; /* Get timeout */ tickstart = HAL_GetTick(); - - while(HAL_IS_BIT_CLR(AES->SR, AES_SR_CCF)) + + while(HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF)) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) @@ -2006,16 +2096,16 @@ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* In } } /* Clear CCF Flag */ - AES->CR |= AES_CR_CCFC; + __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CLEARFLAG_CCF); /* Read the Output block from the Data Output Register */ - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; - *(uint32_t*)(outputaddr) = AES->DOUTR; + *(uint32_t*)(outputaddr) = hcryp->Instance->DOUTR; outputaddr+=4; } /* Return function status */ @@ -2042,25 +2132,24 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt; /* Set the DMA error callback */ hcryp->hdmaout->XferErrorCallback = CRYP_DMAError; - + /* Enable the DMA In DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&AES->DINR, Size/4); - + HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size/4); + /* Enable the DMA Out DMA Stream */ - HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&AES->DOUTR, outputaddr, Size/4); - + HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size/4); + /* Enable In and Out DMA requests */ - AES->CR |= (AES_CR_DMAINEN | AES_CR_DMAOUTEN); - + SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN)); + /* Enable CRYP */ - __HAL_CRYP_ENABLE(); + __HAL_CRYP_ENABLE(hcryp); } /** * @} */ -#endif /* STM32L051xx && STM32L052xx && STM32L053xx*/ -#endif /* HAL_CRYP_MODULE_ENABLED */ + /** * @} */ @@ -2069,4 +2158,7 @@ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uin * @} */ +#endif /* HAL_CRYP_MODULE_ENABLED */ +#endif /* STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.h index e3fe97028e4..41e5d219184 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_cryp.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of CRYP HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) +#if defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" @@ -58,6 +58,10 @@ /* Exported types ------------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Types CRYP Exported Types + * @{ + */ + /** * @brief CRYP Configuration Structure definition */ @@ -99,38 +103,44 @@ typedef enum * @brief CRYP handle Structure definition */ typedef struct -{ - CRYP_InitTypeDef Init; /*!< CRYP required parameters */ - - uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - - uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ - - __IO uint16_t CrypInCount; /*!< Counter of inputed data */ - - __IO uint16_t CrypOutCount; /*!< Counter of outputed data */ - - HAL_StatusTypeDef Status; /*!< CRYP peripheral status */ - - HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */ - - DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ - - DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< CRYP locking object */ - - __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ - +{ + AES_TypeDef *Instance; /*!< Register base address */ + + CRYP_InitTypeDef Init; /*!< CRYP required parameters */ + + uint8_t *pCrypInBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + + uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */ + + __IO uint16_t CrypInCount; /*!< Counter of inputed data */ + + __IO uint16_t CrypOutCount; /*!< Counter of outputed data */ + + HAL_StatusTypeDef Status; /*!< CRYP peripheral status */ + + HAL_PhaseTypeDef Phase; /*!< CRYP peripheral phase */ + + DMA_HandleTypeDef *hdmain; /*!< CRYP In DMA handle parameters */ + + DMA_HandleTypeDef *hdmaout; /*!< CRYP Out DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< CRYP locking object */ + + __IO HAL_CRYP_STATETypeDef State; /*!< CRYP peripheral state */ + }CRYP_HandleTypeDef; +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ -/** @defgroup CRYP_Exported_Constants +/** @defgroup CRYP_Exported_Constants CRYP Exported Constants * @{ */ -/** @defgroup CRYP_Data_Type +/** @defgroup CRYP_Data_Type CRYP Data Type * @{ */ #define CRYP_DATATYPE_32B ((uint32_t)0x00000000) @@ -146,7 +156,7 @@ typedef struct * @} */ -/** @defgroup CRYP_AlgoModeDirection +/** @defgroup CRYP_AlgoModeDirection CRYP Algo Mode Direction * @{ */ #define CRYP_CR_ALGOMODE_DIRECTION (uint32_t)(AES_CR_MODE|AES_CR_CHMOD) @@ -161,30 +171,41 @@ typedef struct * @} */ -/** @defgroup AES_Interrupts +/** @defgroup CRYP_AES_Interrupts AES Interrupts * @{ */ -#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */ -#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */ +#define CRYP_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */ +#define CRYP_IT_ERR AES_CR_ERRIE /*!< Error interrupt */ -#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00000000) && ((IT) != 0x00000000)) -#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR)) +#define IS_CRYP_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00000000) && ((IT) != 0x00000000)) +#define IS_CRYP_AES_GET_IT(IT) (((IT) == CRYP_IT_CC) || ((IT) == CRYP_IT_ERR)) /** * @} */ -/** @defgroup AES_Flags +/** @defgroup CRYP_AES_Flags AES Flags * @{ */ -#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */ -#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */ -#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */ +#define CRYP_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */ +#define CRYP_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */ +#define CRYP_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */ + +#define IS_CRYP_STATUS_FLAG(FLAG) (((FLAG) == CRYP_FLAG_CCF) || \ + ((FLAG) == CRYP_FLAG_RDERR) || \ + ((FLAG) == CRYP_FLAG_WRERR)) +/** + * @} + */ + +/** @defgroup CRYP_AES_Clear_Flags AES Clear Flags + * @{ + */ +#define CRYP_CLEARFLAG_CCF AES_CR_CCFC /*!< Computation Complete Flag Clear */ +#define CRYP_CLEARFLAG_RDERR AES_CR_ERRC /*!< Read Error Clear */ +#define CRYP_CLEARFLAG_WRERR AES_CR_ERRC /*!< Write Error Clear */ -#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \ - ((FLAG) == AES_FLAG_RDERR) || \ - ((FLAG) == AES_FLAG_WRERR)) /** * @} */ @@ -195,105 +216,194 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRYP_Exported_Macros CRYP Exported Macros + * @{ + */ + /** @brief Reset CRYP handle state - * @param __HANDLE__: specifies the CRYP Handle. + * @param __HANDLE__: specifies the CRYP handle. * @retval None */ #define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET) /** * @brief Enable/Disable the CRYP peripheral. - * @param None + * @param __HANDLE__: specifies the CRYP handle. * @retval None */ -#define __HAL_CRYP_ENABLE() (AES->CR |= AES_CR_EN) -#define __HAL_CRYP_DISABLE() (AES->CR &= ~AES_CR_EN) +#define __HAL_CRYP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, AES_CR_EN) +#define __HAL_CRYP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, AES_CR_EN) /** * @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,... - * @param MODE: The algorithm mode. + * @param __HANDLE__: specifies the CRYP handle. + * @param __MODE__: The algorithm mode. * @retval None */ -#define __HAL_CRYP_SET_MODE(MODE) (AES->CR |= (uint32_t)(MODE)) +#define __HAL_CRYP_SET_MODE(__HANDLE__,__MODE__) SET_BIT((__HANDLE__)->Instance->CR, (__MODE__)) /** @brief Check whether the specified CRYP flag is set or not. + * @param __HANDLE__: specifies the CRYP handle. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: - * @arg AES_FLAG_CCF : Computation Complete Flag - * @arg AES_FLAG_RDERR : Read Error Flag - * @arg AES_FLAG_WRERR : Write Error Flag + * @arg CRYP_FLAG_CCF : Computation Complete Flag + * @arg CRYP_FLAG_RDERR : Read Error Flag + * @arg CRYP_FLAG_WRERR : Write Error Flag * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_CRYP_GET_FLAG(__FLAG__) ((AES->SR & (__FLAG__)) == (__FLAG__)) - +#define __HAL_CRYP_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** @brief Clear the CRYP pending flag. + * @param __HANDLE__: specifies the CRYP handle. + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg CRYP_CLEARFLAG_CCF : Computation Complete Clear Flag + * @arg CRYP_CLEARFLAG_RDERR : Read Error Clear + * @arg CRYP_CLEARFLAG_WRERR : Write Error Clear + * @retval None + */ +#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT((__HANDLE__)->Instance->CR, (__FLAG__)) + /** * @brief Enable the CRYP interrupt. + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP Interrupt. * @retval None */ -#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__) ((AES->CR) |= (__INTERRUPT__)) +#define __HAL_CRYP_ENABLE_IT(__HANDLE__,__INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** * @brief Disable the CRYP interrupt. + * @param __HANDLE__: specifies the CRYP handle. * @param __INTERRUPT__: CRYP interrupt. * @retval None */ -#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__) ((AES->CR) &= ~(__INTERRUPT__)) +#define __HAL_CRYP_DISABLE_IT(__HANDLE__,__INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) + +/** @brief Checks if the specified CRYP interrupt source is enabled or disabled. + * @param __HANDLE__: specifies the CRYP handle. + * @param __INTERRUPT__: CRYP interrupt source to check + * This parameter can be one of the following values: + * @arg CRYP_IT_CC : Computation Complete interrupt + * @arg CRYP_IT_ERR : Error interrupt (used for RDERR and WRERR) + * @retval State of interruption (SET or RESET) + */ +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + (( ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__) \ + )? SET : RESET \ + ) + +/** @brief Clear the CRYP pending IT. + * @param __HANDLE__: specifies the CRYP handle. + * @param __IT__: specifies the IT to clear. + * This parameter can be one of the following values: + * @arg CRYP_CLEARFLAG_CCF : Computation Complete Clear Flag + * @arg CRYP_CLEARFLAG_RDERR : Read Error Clear + * @arg CRYP_CLEARFLAG_WRERR : Write Error Clear + * @retval None + */ +#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT((__HANDLE__)->Instance->CR, (__IT__)) + +/** + * @} + */ /* Include CRYP HAL Extension module */ #include "stm32l0xx_hal_cryp_ex.h" /* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRYP_Exported_Functions + * @{ + */ + +/** @addtogroup CRYP_Exported_Functions_Group1 + * @{ + */ + /* Initialization/de-initialization functions *********************************/ -HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); -HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp); +HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp); + +/* MSP functions *************************************************************/ +void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group2 + * @{ + */ /* AES encryption/decryption using polling ***********************************/ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout); /* AES encryption/decryption using interrupt *********************************/ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); /* AES encryption/decryption using DMA ***************************************/ -HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); -HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData); +HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group3 + * @{ + */ + +/* CallBack functions ********************************************************/ +void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); + +/** + * @} + */ + +/** @addtogroup CRYP_Exported_Functions_Group4 + * @{ + */ /* Processing functions ********************************************************/ -void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); +void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp); -/* Peripheral State functions **************************************************/ -HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); +/** + * @} + */ -/* MSP functions *************************************************************/ -void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); +/** @addtogroup CRYP_Exported_Functions_Group5 + * @{ + */ -/* CallBack functions ********************************************************/ -void HAL_CRYP_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp); -void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); +/* Peripheral State functions **************************************************/ +HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp); -/* Aliases for inter STM32 series compatibility */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback +/** + * @} + */ -#endif /* STM32L051xx && STM32L052xx && STM32L053xx*/ +/** + * @} + */ /** * @} @@ -303,6 +413,7 @@ void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); * @} */ +#endif /* STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */ #ifdef __cplusplus } #endif @@ -310,3 +421,4 @@ void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp); #endif /* __STM32L0xx_HAL_CRYP_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.c index 19c9b1c7399..a71b1678433 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.c @@ -2,71 +2,18 @@ ****************************************************************************** * @file stm32l0xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief CRYPEx HAL module driver. * * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) extension peripheral: * + Computation completed callback. * - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The CRYP HAL driver can be used as follows: - - (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit(): - (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE() - (##) In case of using interrupts (e.g. HAL_AES_ECB_Encrypt_IT()) - (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority() - (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ() - (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler() - (##) In case of using DMA to control data transfer (e.g. HAL_AES_ECB_Encrypt_DMA()) - (+) Enable the DMA1 interface clock using - (++) __DMA1_CLK_ENABLE() - (+) Configure and enable two DMA Channels one for managing data transfer from - memory to peripheral (input channel) and another channel for managing data - transfer from peripheral to memory (output channel) - (+) Associate the initilalized DMA handle to the CRYP DMA handle - using __HAL_LINKDMA() - (+) Configure the priority and enable the NVIC for the transfer complete - interrupt on the two DMA Streams. The output stream should have higher - priority than the input stream. - (++) HAL_NVIC_SetPriority() - (++) HAL_NVIC_EnableIRQ() - - (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly: - (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit - (##) The encryption/decryption key. - (##) The initialization vector (counter). It is not used ECB mode. - - (#)Three processing (encryption/decryption) functions are available: - (##) Polling mode: encryption and decryption APIs are blocking functions - i.e. they process the data and wait till the processing is finished - e.g. HAL_CRYP_AESCBC_Encrypt() - (##) Interrupt mode: encryption and decryption APIs are not blocking functions - i.e. they process the data under interrupt - e.g. HAL_CRYP_AESCBC_Encrypt_IT() - (##) DMA mode: encryption and decryption APIs are not blocking functions - i.e. the data transfer is ensured by DMA - e.g. HAL_CRYP_AESCBC_Encrypt_DMA() - - (#)When the processing function is called at first time after HAL_CRYP_Init() - the CRYP peripheral is initialized and processes the buffer in input. - At second call, the processing function performs an append of the already - processed buffer. - When a new data block is to be processed, call HAL_CRYP_Init() then the - processing function. - - (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral. - - @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -93,20 +40,20 @@ ****************************************************************************** */ +#if defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#ifdef HAL_CRYP_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup CRYPEx +/** @defgroup CRYPEx CRYPEx * @brief CRYP HAL Extended module driver. * @{ */ -#ifdef HAL_CRYP_MODULE_ENABLED -#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -115,12 +62,12 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup CRYPEx_Private_Functions +/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions * @{ */ -/** @defgroup CRYPEX_Group1 Extended features functions +/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions * @brief Extended features functions. * @verbatim @@ -155,8 +102,6 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) /** * @} */ -#endif /* STM32L051xx && STM32L052xx && STM32L053xx*/ -#endif /* HAL_CRYP_MODULE_ENABLED */ /** * @} */ @@ -165,4 +110,7 @@ __weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp) * @} */ +#endif /* HAL_CRYP_MODULE_ENABLED */ +#endif /* STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.h index 6144aff202a..b6b54d74dc9 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_cryp_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_cryp_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of CRYPEx HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) +#if defined (STM32L041xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) || (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" @@ -60,10 +60,25 @@ /* Exported constants --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRYPEx_Exported_Functions + * @{ + */ + +/** @addtogroup CRYPEx_Exported_Functions_Group1 + * @{ + */ + /* CallBack functions ********************************************************/ void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); -#endif /* STM32L051xx && STM32L052xx && STM32L053xx*/ +/** + * @} + */ + +/** + * @} + */ + /** * @} @@ -73,6 +88,8 @@ void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); * @} */ +#endif /* STM32L041xx || STM32L061xx || STM32L062xx || STM32L063xx || STM32L081xx || STM32L082xx || STM32L083xx */ + #ifdef __cplusplus } #endif @@ -80,3 +97,4 @@ void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp); #endif /* __STM32L0xx_HAL_CRYP_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.c index 034664a26a5..a0e022f52b7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.c @@ -2,14 +2,15 @@ ****************************************************************************** * @file stm32l0xx_hal_dac.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief DAC HAL module driver. - * * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: - * + DAC channels configuration: trigger, output buffer, data format - * + DMA management + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + Peripheral State and Errors functions * * @verbatim @@ -20,8 +21,15 @@ *** DAC Channels *** ==================== [..] - The device integrates 1 12-bit Digital Analog Converters: + STM32F0 devices integrates no, one or two 12-bit Digital Analog Converters. + STM32L05x & STM32L06x devices have one converter (channel1) + STM32L07x & STM32L08x devices have two converters (i.e. channel1 & channel2) + + When 2 converters are present (i.e. channel1 & channel2) they + can be used independently or simultaneously (dual mode): (#) DAC channel1 with DAC_OUT1 (PA4) as output + (#) DAC channel2 with DAC_OUT2 (PA5) as output (STM32L07x/STM32L08x only) + (#) Channel1 & channel2 can be used independently or simultaneously in dual mode (STM32L07x/STM32L08x only) *** DAC Triggers *** ==================== @@ -33,7 +41,9 @@ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9. The used pin (GPIOx_Pin9) must be configured in input mode. - (#) Timers TRGO: TIM2, TIM6 and TIM21 + (#) Timers TRGO: + STM32L05x/STM32L06x : TIM2, TIM6 and TIM21 + STM32L07x/STM32L08x : TIM2, TIM3, TIM6, TIM7 and TIM21 (DAC_Trigger_T2_TRGO, DAC_Trigger_T6_TRGO...) (#) Software using DAC_Trigger_Software @@ -54,8 +64,8 @@ =================================== [..] Both DAC channels can be used to generate - (#) Noise wave using HAL_DAC_NoiseWaveGenerate() - (#) Triangle wave using HAL_DAC_TriangleWaveGenerate() + (#) Noise wave using HAL_DACEx_NoiseWaveGenerate() + (#) Triangle wave using HAL_DACEx_TriangleWaveGenerate() *** DAC data format *** ======================= @@ -86,6 +96,11 @@ DMA1 requests are mapped as following: (#) DAC channel1 : mapped on DMA1 Request9 channel2 which must be already configured + (#) DAC channel2 : mapped on DMA1 Request15 channel4 which must be + already configured (STM32L07x/STM32L08x only) + + -@- For Dual mode (STM32L07x/STM32L08x only) and specific signal Triangle and noise generation please + refer to Extension Features Driver description ##### How to use this driver ##### @@ -93,15 +108,56 @@ [..] (+) DAC APB clock must be enabled to get write access to DAC registers using HAL_DAC_Init() - (+) Configure DAC_OUTx (DAC_OUT1: PA4) in analog mode. + (+) Configure DAC_OUT1: PA4 in analog mode. + (+) Configure DAC_OUT2: PA5 in analog mode (STM32L07x/STM32L08x only). (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions + *** Polling mode IO operation *** + ================================= + [..] + (+) Start the DAC peripheral using HAL_DAC_Start() + (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function. + (+) Stop the DAC peripheral using HAL_DAC_Stop() + + *** DMA mode IO operation *** + ============================== + [..] + (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length + of data to be transferred at each end of conversion + (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DAC_ConvHalfCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2 + (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2 + (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. + HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DAC_DMAUnderrunCallbackCh2() + function is executed and user can add his own code by customization of function pointer + HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DAC_DMAUnderrunCallbackCh2 + add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 + (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() + + *** DAC HAL driver macros list *** + ============================================= + [..] + Below the list of most used macros in DAC HAL driver. + + (+) __HAL_DAC_ENABLE : Enable the DAC peripheral + (+) __HAL_DAC_DISABLE : Disable the DAC peripheral + (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags + (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status + + [..] + (@) You can refer to the DAC HAL driver header file for more useful macros + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -129,37 +185,34 @@ */ +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#ifdef HAL_DAC_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup DAC +/** @defgroup DAC DAC HAL module driver * @brief DAC driver modules * @{ */ -#ifdef HAL_DAC_MODULE_ENABLED -#if !defined (STM32L051xx) && !defined (STM32L061xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); /* Private functions ---------------------------------------------------------*/ -/** @defgroup DAC_Private_Functions +/** @defgroup DAC_Exported_Functions DAC Exported Functions * @{ */ -/** @defgroup DAC_Group1 Initialization and de-initialization functions +/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -184,7 +237,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) { /* Check DAC handle */ - if(hdac == HAL_NULL) + if(hdac == NULL) { return HAL_ERROR; } @@ -219,7 +272,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) { /* Check DAC handle */ - if(hdac == HAL_NULL) + if(hdac == NULL) { return HAL_ERROR; } @@ -276,8 +329,8 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) * @} */ -/** @defgroup DAC_Group2 I/O operation functions - * @brief I/O operation functions +/** @defgroup DAC_Exported_Functions_Group2 IO operation functions + * @brief IO operation functions * @verbatim ============================================================================== @@ -289,6 +342,7 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) (+) Start conversion and enable DMA transfer. (+) Stop conversion and disable DMA transfer. (+) Get result of conversion. + (+) Get result of dual mode conversion (STM32L07xx/STM32L08xx only) @endverbatim * @{ @@ -298,38 +352,17 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) * @brief Enables DAC and starts conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel) +__weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) { - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(channel)); - - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Enable the Peripharal */ - __HAL_DAC_ENABLE(hdac, channel); - - /* Check if software trigger enabled */ - if(((hdac->Instance->CR & DAC_CR_TEN1) == DAC_CR_TEN1) && ((hdac->Instance->CR & DAC_CR_TSEL1) == DAC_CR_TSEL1)) - { - /* Enable the selected DAC software conversion */ - hdac->Instance->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1; - } - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; - - /* Process unlocked */ - __HAL_UNLOCK(hdac); - + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32l0xx_hal_dac_ex.c */ + /* Return function status */ return HAL_OK; } @@ -338,18 +371,19 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel) * @brief Disables DAC and stop conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel) +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) { /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(channel)); + assert_param(IS_DAC_CHANNEL(Channel)); /* Disable the Peripheral */ - __HAL_DAC_DISABLE(hdac, channel); + __HAL_DAC_DISABLE(hdac, Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -362,101 +396,42 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel) * @brief Enables DAC and starts conversion of channel using DMA. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) * @param pData: The destination peripheral Buffer address. * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param alignment: Specifies the data alignment for DAC channel. + * @param Alignment: Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment) +__weak HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) { - uint32_t tmpreg = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(channel)); - assert_param(IS_DAC_ALIGN(alignment)); + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32l0xx_hal_dac_ex.c */ - /* Process locked */ - __HAL_LOCK(hdac); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_BUSY; - - /* Set the DMA transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; - - /* Set the DMA half transfer complete callback for channel1 */ - hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; - - /* Set the DMA error callback for channel1 */ - hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; - - /* Enable the selected DAC channel1 DMA request */ - hdac->Instance->CR |= DAC_CR_DMAEN1; - - /* Case of use of channel 1 */ - switch(alignment) - { - case DAC_ALIGN_12B_R: - /* Get DHR12R1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12R1; - break; - case DAC_ALIGN_12B_L: - /* Get DHR12L1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR12L1; - break; - case DAC_ALIGN_8B_R: - /* Get DHR8R1 address */ - tmpreg = (uint32_t)&hdac->Instance->DHR8R1; - break; - default: - break; - } - - /* Enable the DMA Channel */ - /* Enable the DAC DMA underrun interrupt */ - __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); - - HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); - - /* Enable the Peripharal */ - __HAL_DAC_ENABLE(hdac, channel); - - /* Process Unlocked */ - __HAL_UNLOCK(hdac); - /* Return function status */ return HAL_OK; } /** - * @brief Disables DAC and stop conversion of channel using DMA. + * @brief Disables DAC and stop conversion of channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel) +__weak HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) { - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(channel)); - - /* Disable the selected DAC channel DMA request */ - hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << channel); - - /* Disable the Peripharal */ - __HAL_DAC_DISABLE(hdac, channel); - - /* Change DAC state */ - hdac->State = HAL_DAC_STATE_READY; + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32l0xx_hal_dac_ex.c */ /* Return function status */ return HAL_OK; @@ -466,25 +441,91 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel) * @brief Returns the last data output value of the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) * @retval The selected DAC channel data output value. */ -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel) +__weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) { - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(channel)); - - /* Returns the DAC channel data output register value */ - return hdac->Instance->DOR1; + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32l0xx_hal_dac_ex.c */ + + /* Return function status */ + return 0; +} + +/** + * @brief Handles DAC interrupt request + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32l0xx_hal_dac_ex.c */ + +} + +/** + * @brief Conversion complete callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel1. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file + */ } /** * @} */ -/** @defgroup DAC_Group3 Peripheral Control functions +/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral Control functions * @verbatim @@ -494,7 +535,6 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel) [..] This section provides functions allowing to: (+) Configure channels. (+) Set the specified data holding register value for DAC channel. - (+) Set the specified data holding register value for Dual DAC channels. @endverbatim * @{ @@ -505,19 +545,20 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel) * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig: DAC configuration structure. - * @param channel: The selected DAC channel. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t channel) +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { uint32_t tmpreg1 = 0, tmpreg2 = 0; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); - assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); + assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); @@ -526,20 +567,19 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf hdac->State = HAL_DAC_STATE_BUSY; /* Get the DAC CR value */ - tmpreg1 = DAC->CR; + tmpreg1 = hdac->Instance->CR; /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */ - tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << channel); + tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel); /* Configure for the selected DAC channel: buffer output, trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ /* Set BOFFx bit according to DAC_OutputBuffer value */ tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer); /* Calculate CR register value depending on DAC_Channel */ - tmpreg1 |= tmpreg2 << channel; + tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CR */ - DAC->CR = tmpreg1; + hdac->Instance->CR = tmpreg1; /* Disable wave generation */ - DAC->CR &= ~(DAC_CR_WAVE1 << channel); - + CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << Channel)); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; @@ -554,29 +594,22 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf * @brief Set the specified data holding register value for DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param alignment: Specifies the data alignment for DAC channel1. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) + * @param Alignment: Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param data: Data to be loaded in the selected data holding register. + * @param Data: Data to be loaded in the selected data holding register. * @retval HAL status */ -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data) +__weak HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) { - __IO uint32_t tmp = 0; - - /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(channel)); - assert_param(IS_DAC_ALIGN(alignment)); - assert_param(IS_DAC_DATA(data)); - - tmp = (uint32_t)DAC_BASE; - - tmp += __HAL_DHR12R1_ALIGNEMENT(alignment); - - /* Set the DAC channel1 selected data holding register */ - *(__IO uint32_t *) tmp = data; + /* Note : This function is defined into this file for library reference. */ + /* Function content is located into file stm32l0xx_hal_dac_ex.c */ /* Return function status */ return HAL_OK; @@ -586,16 +619,17 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, ui * @} */ -/** @defgroup DAC_Group4 DAC Peripheral State functions - * @brief DAC Peripheral State functions +/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions + * @brief Peripheral State and Errors functions * @verbatim ============================================================================== - ##### DAC Peripheral State functions ##### + ##### Peripheral State and Errors functions ##### ============================================================================== [..] This subsection provides functions allowing to (+) Check the DAC state. + (+) Check the DAC Errors. @endverbatim * @{ @@ -613,33 +647,6 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) return hdac->State; } -/** - * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) -{ - /* Check Overrun flag */ - if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) - { - /* Change DAC state to error state */ - hdac->State = HAL_DAC_STATE_ERROR; - - /* Set DAC error code to chanel1 DMA underrun error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; - - /* Clear the underrun flag */ - __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); - - /* Disable the selected DAC channel1 DMA request */ - hdac->Instance->CR &= ~DAC_CR_DMAEN1; - - /* Error callback */ - HAL_DAC_DMAUnderrunCallbackCh1(hdac); - } -} /** * @brief Return the DAC error code @@ -657,107 +664,17 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) */ /** - * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_ErrorCallback could be implemented in the user file - */ -} - - -/** - * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains - * the configuration information for the specified DAC. - * @retval None - */ -__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file - */ -} - -/** - * @brief DMA conversion complete callback. - * @param hdma: pointer to DMA handle. - * @retval None - */ -static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - HAL_DAC_ConvCpltCallbackCh1(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma: pointer to DMA handle. - * @retval None + * @} */ -static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* Conversion complete callback */ - HAL_DAC_ConvHalfCpltCallbackCh1(hdac); -} -/** - * @brief DMA error callback - * @param hdma: pointer to DMA handle. - * @retval None +/** @addtogroup DAC_Private_Functions + * @{ */ -static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) -{ - DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* Set DAC error code to DMA error */ - hdac->ErrorCode |= HAL_DAC_ERROR_DMA; - - HAL_DAC_ErrorCallbackCh1(hdac); - - hdac->State= HAL_DAC_STATE_READY; -} /** * @} */ -#endif /* STM32L051xx && STM32L061xx*/ -#endif /* HAL_DAC_MODULE_ENABLED */ /** * @} @@ -766,5 +683,8 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) /** * @} */ +#endif /* HAL_DAC_MODULE_ENABLED */ +#endif /* !STM32L031xx && !STM32L041xx && !STM32L051xx && !STM32L061xx&& !STM32L071xx&& !STM32L081xx*/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.h index 2d08ea3966c..caed47a40ce 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_dac.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of DAC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if !defined (STM32L051xx) && !defined (STM32L061xx) +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" @@ -58,6 +58,10 @@ /* Exported types ------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Types DAC Exported Types + * @{ + */ + /** * @brief HAL State structures definition */ @@ -84,7 +88,11 @@ typedef struct DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */ - __IO uint32_t ErrorCode; /*!< DAC Error code */ +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) + DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */ +#endif + + __IO uint32_t ErrorCode; /*!< DAC Error code */ }DAC_HandleTypeDef; @@ -101,40 +109,66 @@ typedef struct }DAC_ChannelConfTypeDef; +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ -/** @defgroup HAL DAC Error Code +/** @defgroup DAC_Exported_Constants DAC Exported Constants + * @{ + */ + +/** @defgroup DAC_Error_Code DAC Error Code * @{ */ #define HAL_DAC_ERROR_NONE 0x00 /*!< No error */ -#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DMA underrun error */ +#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */ +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */ +#endif #define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */ /** * @} */ -/** @defgroup DAC_trigger_selection +/** @defgroup DAC_trigger_selection DAC trigger selection * @{ */ -#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register - has been loaded, and not by external trigger */ -#define DAC_TRIGGER_T6_TRGO ((uint32_t)DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T21_TRGO ((uint32_t)(DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ -#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ +#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register has been loaded, and not by external trigger */ +#define DAC_TRIGGER_T6_TRGO ((uint32_t) DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T21_TRGO ((uint32_t)( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM21 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_EXT_IT9 ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_SOFTWARE ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */ + +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define DAC_TRIGGER_T3_TRGO ((uint32_t)( DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_TRIGGER_T7_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ +#endif +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ + ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ + ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ + ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) +#else /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */ #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE) || \ ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T21_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \ ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \ ((TRIGGER) == DAC_TRIGGER_SOFTWARE)) +#endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */ /** * @} */ -/** @defgroup DAC_output_buffer +/** @defgroup DAC_output_buffer DAC output buffer * @{ */ #define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000) @@ -146,17 +180,25 @@ typedef struct * @} */ -/** @defgroup DAC_Channel_selection +/** @defgroup DAC_Channel_selection DAC Channel selection * @{ */ #define DAC_CHANNEL_1 ((uint32_t)0x00000000) +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define DAC_CHANNEL_2 ((uint32_t)0x00000010) +#endif +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \ + ((CHANNEL) == DAC_CHANNEL_2)) +#else #define IS_DAC_CHANNEL(CHANNEL) ((CHANNEL) == DAC_CHANNEL_1) +#endif /** * @} */ -/** @defgroup DAC_data_alignement +/** @defgroup DAC_data_alignement DAC data alignement * @{ */ #define DAC_ALIGN_12B_R ((uint32_t)0x00000000) @@ -170,8 +212,7 @@ typedef struct * @} */ - -/** @defgroup DAC_data +/** @defgroup DAC_data DAC data * @{ */ #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) @@ -179,22 +220,42 @@ typedef struct * @} */ -/** @defgroup DAC_flags_definition +/** @defgroup DAC_flags_definition DAC flags definition * @{ */ #define DAC_FLAG_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define DAC_FLAG_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +#endif -#define IS_DAC_FLAG(FLAG) ((FLAG) == DAC_FLAG_DMAUDR1) +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR1) || \ + ((FLAG) == DAC_FLAG_DMAUDR2)) +#else +#define IS_DAC_FLAG(FLAG) ((FLAG) == DAC_FLAG_DMAUDR1) +#endif /** * @} */ -/** @defgroup DAC_flags_definition +/** @defgroup DAC_IT_definition DAC IT definition * @{ */ -#define DAC_IT_DMAUDR1 ((uint32_t)DAC_CR_DMAUDRIE1) +#define DAC_IT_DMAUDR1 ((uint32_t)DAC_SR_DMAUDR1) +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define DAC_IT_DMAUDR2 ((uint32_t)DAC_SR_DMAUDR2) +#endif +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR1) || \ + ((IT) == DAC_IT_DMAUDR2)) +#else #define IS_DAC_IT(IT) ((IT) == DAC_IT_DMAUDR1) +#endif + +/** + * @} + */ /** * @} @@ -202,58 +263,138 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ +/** @defgroup DAC_Exported_Macros DAC Exported Macros + * @{ + */ + /** @brief Reset DAC handle state - * @param __HANDLE__: specifies the DAC Handle. + * @param __HANDLE__: specifies the DAC handle. * @retval None */ #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET) -/* Enable the DAC peripheral */ -#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__))) +/** @brief Enable the DAC channel + * @param __HANDLE__: specifies the DAC handle. + * @param __DAC_CHANNEL__: specifies the DAC channel + * @retval None + */ +#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \ +SET_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__))) -/* Disable the DAC peripheral */ -#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \ -((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__))) +/** @brief Disable the DAC channel + * @param __HANDLE__: specifies the DAC handle + * @param __DAC_CHANNEL__: specifies the DAC channel. + * @retval None + */ +#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \ +CLEAR_BIT((__HANDLE__)->Instance->CR, (DAC_CR_EN1 << (__DAC_CHANNEL__))) +/** @brief Set DHR12R1 alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __DAC_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) -/* Set DHR12R1 alignment */ -#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__)) +/** @brief Set DHR12R2 alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __DAC_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__)) -/* Enable the DAC interrupt */ -#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__)) +/** @brief Set DHR12RD alignment + * @param __ALIGNEMENT__: specifies the DAC alignement + * @retval None + */ +#define __DAC_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__)) -/* Disable the DAC interrupt */ -#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__)) +/** @brief Enable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ +#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ +SET_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__) -/* Get the selected DAC's flag status */ + +/** @brief Disable the DAC interrupt + * @param __HANDLE__: specifies the DAC handle + * @param __INTERRUPT__: specifies the DAC interrupt. + * @retval None + */ +#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ +CLEAR_BIT((__HANDLE__)->Instance->CR, __INTERRUPT__) + + +/** @brief Get the selected DAC's flag status. + * @param __HANDLE__: specifies the DAC handle. + * @param __FLAG__: specifies the FLAG. + * @retval None + */ #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) -/* Clear the DAC's flag */ +/** @brief Clear the DAC's flag. + * @param __HANDLE__: specifies the DAC handle. + * @param __FLAG__: specifies the FLAG. + * @retval None + */ #define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__)) +/** + * @} + */ + + /* Include DAC HAL Extension module */ #include "stm32l0xx_hal_dac_ex.h" /* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization functions *****************************/ + +/** @addtogroup DAC_Exported_Functions + * @{ + */ + +/** @addtogroup DAC_Exported_Functions_Group1 + * @{ + */ +/* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac); HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac); void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac); void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac); -/* I/O operation functions ******************************************************/ -HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t channel); -HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t channel); -HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t* pData, uint32_t Length, uint32_t alignment); -HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t channel); -uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t channel); +/** + * @} + */ + +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment); +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel); +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data); +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel); + +/** + * @} + */ +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t channel); -HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t alignment, uint32_t data); +HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel); + +/** + * @} + */ -/* Peripheral State and Error functions ***************************************/ +/** @addtogroup DAC_Exported_Functions_Group2 + * @{ + */ +/* Peripheral State functions ***************************************************/ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac); void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac); uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac); @@ -263,21 +404,29 @@ void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac); void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac); void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac); -#endif /* STM32L051xx && STM32L061xx*/ +/** + * @} + */ /** * @} */ + /** * @} */ + +/** + * @} + */ + +#endif /* STM32L031xx && STM32L041xx && STM32L061xx && STM32L071xx && STM32L081xx*/ #ifdef __cplusplus } #endif - #endif /*__STM32L0xx_HAL_DAC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.c index 854dd935c91..7d4ab681f18 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.c @@ -2,21 +2,30 @@ ****************************************************************************** * @file stm32l0xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 - * @brief DAC HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the Digital to Analog Converter (DAC) peripheral: - * + DAC wave generation + * @version V1.2.0 + * @date 06-February-2015 + * @brief Extended DAC HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of DAC extension peripheral: + * + Extended features functions + * * @verbatim + ============================================================================== + ##### How to use this driver ##### + ============================================================================== + [..] + (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) : + Use HAL_DACEx_DualGetValue() to get digital data to be converted and use + HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2. + (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal. + (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,20 +52,21 @@ ****************************************************************************** */ + +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#ifdef HAL_DAC_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup DACEx +/** @defgroup DACEx DACEx * @brief DAC driver modules * @{ */ -#ifdef HAL_DAC_MODULE_ENABLED -#if !defined (STM32L051xx) && !defined (STM32L061xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -64,34 +74,61 @@ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/** @addtogroup DACEx_Private_Functions + * @{ + */ +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma); +static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma); +static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); +#endif +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); + +/** + * @} + */ -/** @defgroup DACEx_Private_Functions +/** @defgroup DACEx_Exported_Functions DACEx Exported Functions * @{ */ - -/** @defgroup DACEx_Group Peripheral Control functions - * @brief Peripheral Control functions +/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] This section provides functions allowing to: - (+) Configure Triangle wave generation. - (+) Configure Noise wave generation. - -@endverbatim + * @{ */ +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) /** - * @brief Enables or disables the selected DAC channel wave triangle generation. + * @brief Returns the last data output value of the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param channel: The selected DAC channel. + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac) +{ + uint32_t tmp = 0; + + tmp |= hdac->Instance->DOR1; + + tmp |= hdac->Instance->DOR2 << 16; + + /* Returns the DAC channel data output register value */ + return tmp; +} +#endif + +/** + * @brief Enables or disables the selected DAC channel wave generation. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) * @param Amplitude: Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 @@ -108,10 +145,10 @@ * @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095 * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude) +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) { /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(channel)); + assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); /* Process locked */ @@ -120,8 +157,9 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - /* Enable the selected wave generation for the selected DAC channel */ - hdac->Instance->CR |= (DAC_WAVEGENERATION_TRIANGLE | Amplitude) << channel; + /* Enable the triangle wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY; @@ -134,10 +172,13 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 } /** - * @brief Enables or disables the selected DAC channel wave noise generation. - * @param channel: The selected DAC channel. + * @brief Enables or disables the selected DAC channel wave generation. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected (STM32L07x/STM32L08x only) * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation @@ -154,10 +195,10 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32 * @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation * @retval HAL status */ -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude) +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude) { /* Check the parameters */ - assert_param(IS_DAC_CHANNEL(channel)); + assert_param(IS_DAC_CHANNEL(Channel)); assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude)); /* Process locked */ @@ -166,8 +207,8 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; - /* Enable the selected wave generation for the selected DAC channel */ - hdac->Instance->CR |= (DAC_WAVEGENERATION_NOISE | Amplitude) << channel; +/* Enable the noise wave generation for the selected DAC channel */ + MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1)|(DAC_CR_MAMP1))<State = HAL_DAC_STATE_READY; @@ -179,6 +220,702 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t return HAL_OK; } +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +/** + * @brief Set the specified data holding register value for dual DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Alignment: Specifies the data alignment for dual channel DAC. + * This parameter can be one of the following values: + * DAC_ALIGN_8B_R: 8bit right data alignment selected + * DAC_ALIGN_12B_L: 12bit left data alignment selected + * DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @note In dual mode, a unique register access is required to write in both + * DAC channels at the same time. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2) +{ + uint32_t data = 0, tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data1)); + assert_param(IS_DAC_DATA(Data2)); + + /* Calculate and set dual DAC data holding register value */ + if (Alignment == DAC_ALIGN_8B_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)hdac->Instance; + tmp += __DAC_DHR12RD_ALIGNEMENT(Alignment); + + /* Set the dual DAC selected data holding register */ + *(__IO uint32_t *)tmp = data; + + /* Return function status */ + return HAL_OK; +} + + +/** + * @brief Conversion complete callback in non blocking mode for Channel2 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Error DAC callback for Channel2. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief DMA underrun DAC callback for channel2. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file + */ +} + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + if(Channel == DAC_CHANNEL_1) + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN1; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); + } + } + else + { + tmp1 = hdac->Instance->CR & DAC_CR_TEN2; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL2; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2)) + { + /* Enable the selected DAC software conversion*/ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); + } + } + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel using DMA. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param pData: The destination peripheral Buffer address. + * @param Length: The length of data to be transferred from memory to DAC peripheral + * @param Alignment: Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + if(Channel == DAC_CHANNEL_1) + { + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + + /* Enable the selected DAC channel1 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Case of use of channel 1 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ + } + else + { + /* Set the DMA transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; + + /* Set the DMA half transfer complete callback for channel2 */ + hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; + + /* Set the DMA error callback for channel2 */ + hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; + + /* Enable the selected DAC channel2 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + + /* Case of use of channel 2 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R2; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L2; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R2 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R2; + break; + default: + break; + } + } + + /* Enable the DMA Stream */ + if(Channel == DAC_CHANNEL_1) + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + } + else + { + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); + } + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + /* Process Unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the selected DAC channel DMA request */ + CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel)); + + /* Disable the Peripharal */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Disable the DMA Channel */ + /* Channel1 is used */ + if(Channel == DAC_CHANNEL_1) + { + status = HAL_DMA_Abort(hdac->DMA_Handle1); + } + else /* Channel2 is used for */ + { + status = HAL_DMA_Abort(hdac->DMA_Handle2); + } + + /* Check if DMA Channel effectively disabled */ + if(status != HAL_OK) + { + /* Update DAC state machine to error */ + hdac->State = HAL_DAC_STATE_ERROR; + } + else + { + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Returns the DAC channel data output register value */ + if(Channel == DAC_CHANNEL_1) + { + return hdac->Instance->DOR1; + } + else + { + return hdac->Instance->DOR2; + } +} + +/** + * @brief Handles DAC interrupt request + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + /* Check underrun flag of DAC channel 1 */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to chanel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Error callback */ + HAL_DAC_DMAUnderrunCallbackCh1(hdac); + } + + /* Check underrun flag of DAC channel 2 */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to channel2 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); + + /* Disable the selected DAC channel1 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); + + /* Error callback */ + HAL_DACEx_DMAUnderrunCallbackCh2(hdac); + } +} + + +/** + * @brief Set the specified data holding register value for DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @arg DAC_CHANNEL_2: DAC Channel2 selected + * @param Alignment: Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)hdac->Instance; + if(Channel == DAC_CHANNEL_1) + { + tmp += __DAC_DHR12R1_ALIGNEMENT(Alignment); + } + else + { + tmp += __DAC_DHR12R2_ALIGNEMENT(Alignment); + } + + /* Set the DAC channel selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} +#else /* All products with only one channel */ + +/** + * @brief Enables DAC and starts conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + uint32_t tmp1 = 0, tmp2 = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + tmp1 = hdac->Instance->CR & DAC_CR_TEN1; + tmp2 = hdac->Instance->CR & DAC_CR_TSEL1; + /* Check if software trigger enabled */ + if((tmp1 == DAC_CR_TEN1) && (tmp2 == DAC_CR_TSEL1)) + { + /* Enable the selected DAC software conversion */ + SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); + } + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + + /* Process unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Enables DAC and starts conversion of channel using DMA. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @param pData: The destination peripheral Buffer address. + * @param Length: The length of data to be transferred from memory to DAC peripheral + * @param Alignment: Specifies the data alignment for DAC channel. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) +{ + uint32_t tmpreg = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + + /* Process locked */ + __HAL_LOCK(hdac); + + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_BUSY; + + /* Set the DMA transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; + + /* Set the DMA half transfer complete callback for channel1 */ + hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; + + /* Set the DMA error callback for channel1 */ + hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; + + /* Enable the selected DAC channel1 DMA request */ + SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Case of use of channel 1 */ + switch(Alignment) + { + case DAC_ALIGN_12B_R: + /* Get DHR12R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12R1; + break; + case DAC_ALIGN_12B_L: + /* Get DHR12L1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR12L1; + break; + case DAC_ALIGN_8B_R: + /* Get DHR8R1 address */ + tmpreg = (uint32_t)&hdac->Instance->DHR8R1; + break; + default: + break; + } + UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ + + /* Enable the DMA Stream */ + /* Enable the DAC DMA underrun interrupt */ + __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); + + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); + + /* Enable the Peripharal */ + __HAL_DAC_ENABLE(hdac, Channel); + + /* Process Unlocked */ + __HAL_UNLOCK(hdac); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Disables DAC and stop conversion of channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Disable the selected DAC channel DMA request */ + CLEAR_BIT(hdac->Instance->CR, (DAC_CR_DMAEN1 << Channel)); + + /* Disable the Peripharal */ + __HAL_DAC_DISABLE(hdac, Channel); + + /* Disable the DMA Channel */ + status = HAL_DMA_Abort(hdac->DMA_Handle1); + + /* Check if DMA Channel effectively disabled */ + if(status != HAL_OK) + { + /* Update DAC state machine to error */ + hdac->State = HAL_DAC_STATE_ERROR; + } + else + { + /* Change DAC state */ + hdac->State = HAL_DAC_STATE_READY; + } + + /* Return function status */ + return status; +} + +/** + * @brief Returns the last data output value of the selected DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @retval The selected DAC channel data output value. + */ +uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + + /* Returns the DAC channel data output register value */ + return hdac->Instance->DOR1; +} + +/** + * @brief Handles DAC interrupt request + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @retval None + */ +void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) +{ + /* Check underrun flag of DAC channel 1 */ + if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) + { + /* Change DAC state to error state */ + hdac->State = HAL_DAC_STATE_ERROR; + + /* Set DAC error code to chanel1 DMA underrun error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1; + + /* Clear the underrun flag */ + __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); + + /* Disable the selected DAC channel1 DMA request */ + CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); + + /* Error callback */ + HAL_DAC_DMAUnderrunCallbackCh1(hdac); + } +} + +/** + * @brief Set the specified data holding register value for DAC channel. + * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * the configuration information for the specified DAC. + * @param Channel: The selected DAC channel. + * This parameter can be one of the following values: + * @arg DAC_CHANNEL_1: DAC Channel1 selected + * @param Alignment: Specifies the data alignment. + * This parameter can be one of the following values: + * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected + * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected + * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected + * @param Data: Data to be loaded in the selected data holding register. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) +{ + __IO uint32_t tmp = 0; + + /* Check the parameters */ + assert_param(IS_DAC_CHANNEL(Channel)); + assert_param(IS_DAC_ALIGN(Alignment)); + assert_param(IS_DAC_DATA(Data)); + + tmp = (uint32_t)hdac->Instance; + tmp += __DAC_DHR12R1_ALIGNEMENT(Alignment); + + /* Set the DAC channel selected data holding register */ + *(__IO uint32_t *) tmp = Data; + + /* Return function status */ + return HAL_OK; +} + +#endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ /** * @} @@ -188,15 +925,117 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t * @} */ -#endif /* STM32L051xx && STM32L061xx*/ -#endif /* HAL_DAC_MODULE_ENABLED */ +/** @defgroup DACEx_Private_Functions DACEx Private Functions + * @{ + */ +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_DACEx_ConvCpltCallbackCh2(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + + HAL_DACEx_ErrorCallbackCh2(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} +#endif /* STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */ + +/** + * @brief DMA conversion complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + HAL_DAC_ConvCpltCallbackCh1(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} + +/** + * @brief DMA half transfer complete callback. + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* Conversion complete callback */ + HAL_DAC_ConvHalfCpltCallbackCh1(hdac); +} + +/** + * @brief DMA error callback + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. + * @retval None + */ +static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) +{ + DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + + /* Set DAC error code to DMA error */ + hdac->ErrorCode |= HAL_DAC_ERROR_DMA; + + HAL_DAC_ErrorCallbackCh1(hdac); + + hdac->State= HAL_DAC_STATE_READY; +} /** * @} */ + + /** * @} */ +/** + * @} + */ +#endif /* HAL_DAC_MODULE_ENABLED */ +#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.h index bdc72a8c914..042b6490592 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dac_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_dac_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 - * @brief Header file of DAC HAL module. + * @version V1.2.0 + * @date 06-February-2015 + * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +43,7 @@ extern "C" { #endif -#if !defined (STM32L051xx) && !defined (STM32L061xx) +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" @@ -58,27 +58,13 @@ /* Exported types ------------------------------------------------------------*/ -/** - * @brief HAL State structures definition - */ - /* Exported constants --------------------------------------------------------*/ -/** @defgroup DACEx_wave_generation +/** @defgroup DACEx_Exported_Constants DACEx Exported Constants * @{ - */ -#define DAC_WAVEGENERATION_NONE ((uint32_t)0x00000000) -#define DAC_WAVEGENERATION_NOISE ((uint32_t)DAC_CR_WAVE1_0) -#define DAC_WAVEGENERATION_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1) - -#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE) || \ - ((WAVE) == DAC_WAVEGENERATION_NOISE) || \ - ((WAVE) == DAC_WAVEGENERATION_TRIANGLE)) -/** - * @} - */ - -/** @defgroup DACEx_lfsrunmask_triangleamplitude + */ + +/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude * @{ */ #define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ @@ -134,14 +120,43 @@ * @} */ + +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ + /* Exported functions --------------------------------------------------------*/ -/* Peripheral Control methods *************************************************/ -HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude); -HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t channel, uint32_t Amplitude); +/** @addtogroup DACEx_Exported_Functions + * @{ + */ + +/** @addtogroup DACEx_Exported_Functions_Group1 + * @{ + */ +/* Extension features functions ***********************************************/ +HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); +HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude); + +#if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac); +HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2); +void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac); +void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac); +#endif + +/** + * @} + */ + +/** + * @} + */ -#endif /* STM32L051xx && STM32L061xx*/ /** * @} */ @@ -149,12 +164,13 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t /** * @} */ +#endif /* STM32L031xx && STM32L041xx && !STM32L051xx && !STM32L061xx && !STM32L071xx && !STM32L081xx*/ #ifdef __cplusplus } #endif - -#endif /*__STM32L0xx_HAL_DAC_H */ +#endif /*__STM32L0xx_HAL_DAC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_def.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_def.h index d1231243470..4b11a6ffbef 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_def.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_def.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l0xx_hal_def.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief This file contains HAL common defines, enumeration, macros and * structures definitions. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -46,6 +46,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx.h" +#include "stm32_hal_legacy.h" +#include /* Exported types ------------------------------------------------------------*/ @@ -70,9 +72,8 @@ typedef enum } HAL_LockTypeDef; /* Exported macro ------------------------------------------------------------*/ -#ifndef HAL_NULL - #define HAL_NULL (void *) 0 -#endif + +#define UNUSED(x) ((void)(x)) #define HAL_MAX_DELAY 0xFFFFFFFF @@ -133,6 +134,9 @@ typedef enum #ifndef __packed #define __packed __attribute__((__packed__)) #endif /* __packed */ + + #define __NOINLINE __attribute__ ( (noinline) ) + #endif /* __GNUC__ */ @@ -172,6 +176,9 @@ typedef enum */ #define __RAM_FUNC HAL_StatusTypeDef +#define __NOINLINE __attribute__ ( (noinline) ) + + #elif defined ( __ICCARM__ ) /* ICCARM Compiler --------------- @@ -179,6 +186,8 @@ typedef enum */ #define __RAM_FUNC __ramfunc HAL_StatusTypeDef +#define __NOINLINE _Pragma("optimize = no_inline") + #elif defined ( __GNUC__ ) /* GNU Compiler ------------ @@ -196,3 +205,4 @@ typedef enum #endif /* ___STM32L0xx_HAL_DEF */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.c index 9d9ca5b1855..b1a7aa543c6 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_dma.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief DMA HAL module driver. * * This file provides firmware functions to manage the following @@ -48,18 +48,18 @@ add his own function by customization of function pointer XferCpltCallback and XferErrorCallback (i.e a member of DMA handle structure). - (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error - detection. + (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error + detection. - (#) Use HAL_DMA_Abort() function to abort the current transfer + (#) Use HAL_DMA_Abort() function to abort the current transfer - -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. + -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -93,28 +93,38 @@ * @{ */ -/** @defgroup DMA +/** @addtogroup DMA DMA * @brief DMA HAL module driver * @{ */ #ifdef HAL_DMA_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/** @defgroup DMA_Private_Types DMA Private Types + * + * @{ + */ #define HAL_TIMEOUT_DMA_ABORT ((uint32_t)1000) /* 1s */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ -/** @defgroup DMA_Private_Functions +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup DMA_Private_Functions DMA Private Functions * @{ */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +/** + * @} + */ -/** @defgroup DMA_Group1 Initialization/de-initialization functions +/** @addtogroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @addtogroup DMA_Exported_Functions_Group1 * @brief Initialization/de-initialization functions * @verbatim @@ -141,7 +151,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) uint32_t tmp = 0; /* Check the DMA peripheral state */ - if(hdma == HAL_NULL) + if(hdma == NULL) { return HAL_ERROR; } @@ -250,7 +260,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) { /* Check the DMA peripheral state */ - if(hdma == HAL_NULL) + if(hdma == NULL) { return HAL_ERROR; } @@ -335,7 +345,7 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup DMA_Group2 I/O operation functions +/** @addtogroup DMA_Exported_Functions_Group2 * @brief I/O operation functions * @verbatim @@ -591,7 +601,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Process Unlocked */ __HAL_UNLOCK(hdma); - if (hdma->XferErrorCallback != HAL_NULL) + if (hdma->XferErrorCallback != NULL) { /* Transfer error callback */ hdma->XferErrorCallback(hdma); @@ -616,7 +626,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_HALF; - if(hdma->XferHalfCpltCallback != HAL_NULL) + if(hdma->XferHalfCpltCallback != NULL) { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); @@ -646,7 +656,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) /* Process Unlocked */ __HAL_UNLOCK(hdma); - if(hdma->XferCpltCallback != HAL_NULL) + if(hdma->XferCpltCallback != NULL) { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); @@ -659,7 +669,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * @} */ -/** @defgroup DMA_Group3 Peripheral State functions +/** @addtogroup DMA_Exported_Functions_Group3 * @brief Peripheral State functions * @verbatim @@ -702,6 +712,18 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) */ /** + * @} + */ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + + +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup DMA_Private_Functions DMA Private Functions + * @{ + */ + + /* * @brief Sets the DMA Transfer parameter. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. @@ -734,7 +756,6 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t hdma->Instance->CMAR = DstAddress; } } - /** * @} */ @@ -749,3 +770,4 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h index 94e522c04b9..297828b2630 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_dma.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_dma.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of DMA HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup DMA +/** @defgroup DMA DMA * @{ */ @@ -69,18 +69,22 @@ typedef struct This parameter can be a value of @ref DMA_Data_transfer_direction */ uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. + When Memory to Memory transfer is used, this is the Source Increment mode This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. + When Memory to Memory transfer is used, this is the Destination Increment mode This parameter can be a value of @ref DMA_Memory_incremented_mode */ uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. + When Memory to Memory transfer is used, this is the Source Alignment format This parameter can be a value of @ref DMA_Peripheral_data_size */ uint32_t MemDataAlignment; /*!< Specifies the Memory data width. + When Memory to Memory transfer is used, this is the Destination Alignment format This parameter can be a value of @ref DMA_Memory_data_size */ - uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. + uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx (Normal or Circular). This parameter can be a value of @ref DMA_mode @note The circular buffer mode cannot be used if the memory-to-memory data transfer is configured on the selected Channel */ @@ -150,19 +154,16 @@ typedef struct __DMA_HandleTypeDef /* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA_Exported_Constants +/** @defgroup DMA_Exported_Constants DMA Exported Constants * @{ */ -/** @defgroup DMA_Error_Code +/** @defgroup DMA_Error_Code DMA Error Codes * @{ */ #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */ #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */ #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */ -/** - * @} - */ #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \ ((PERIPH) == DMA1_Channel2) || \ @@ -178,9 +179,48 @@ typedef struct __DMA_HandleTypeDef * @} */ -/** @defgroup DMA_request +/** @defgroup DMA_request DMA request defintiions * @{ */ + +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) + +#define DMA_REQUEST_0 ((uint32_t)0x00000000) +#define DMA_REQUEST_1 ((uint32_t)0x00000001) +#define DMA_REQUEST_2 ((uint32_t)0x00000002) +#define DMA_REQUEST_3 ((uint32_t)0x00000003) +#define DMA_REQUEST_4 ((uint32_t)0x00000004) +#define DMA_REQUEST_5 ((uint32_t)0x00000005) +#define DMA_REQUEST_6 ((uint32_t)0x00000006) +#define DMA_REQUEST_7 ((uint32_t)0x00000007) +#define DMA_REQUEST_8 ((uint32_t)0x00000008) +#define DMA_REQUEST_9 ((uint32_t)0x00000009) +#define DMA_REQUEST_10 ((uint32_t)0x0000000A) +#define DMA_REQUEST_11 ((uint32_t)0x0000000B) +#define DMA_REQUEST_12 ((uint32_t)0x0000000C) +#define DMA_REQUEST_13 ((uint32_t)0x0000000D) +#define DMA_REQUEST_14 ((uint32_t)0x0000000E) +#define DMA_REQUEST_15 ((uint32_t)0x0000000F) + +#define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ + ((REQUEST) == DMA_REQUEST_1) || \ + ((REQUEST) == DMA_REQUEST_2) || \ + ((REQUEST) == DMA_REQUEST_3) || \ + ((REQUEST) == DMA_REQUEST_4) || \ + ((REQUEST) == DMA_REQUEST_5) || \ + ((REQUEST) == DMA_REQUEST_6) || \ + ((REQUEST) == DMA_REQUEST_7) || \ + ((REQUEST) == DMA_REQUEST_8) || \ + ((REQUEST) == DMA_REQUEST_9) || \ + ((REQUEST) == DMA_REQUEST_10) || \ + ((REQUEST) == DMA_REQUEST_11) || \ + ((REQUEST) == DMA_REQUEST_12) || \ + ((REQUEST) == DMA_REQUEST_13) || \ + ((REQUEST) == DMA_REQUEST_14) || \ + ((REQUEST) == DMA_REQUEST_15)) + +#else /* #if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ + #define DMA_REQUEST_0 ((uint32_t)0x00000000) #define DMA_REQUEST_1 ((uint32_t)0x00000001) #define DMA_REQUEST_2 ((uint32_t)0x00000002) @@ -204,11 +244,13 @@ typedef struct __DMA_HandleTypeDef ((REQUEST) == DMA_REQUEST_8) || \ ((REQUEST) == DMA_REQUEST_9) || \ ((REQUEST) == DMA_REQUEST_11)) +#endif /* #if defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ + /** * @} */ -/** @defgroup DMA_Data_transfer_direction +/** @defgroup DMA_Data_transfer_direction DMA Data Transfer directions * @{ */ #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */ @@ -361,9 +403,17 @@ typedef struct __DMA_HandleTypeDef /** * @} */ - + +/** + * @} + */ + /* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_Exported_Macros DMA Exported Macros + * @{ + */ + /** @brief Reset DMA handle state * @param __HANDLE__: DMA handle * @retval None @@ -507,24 +557,58 @@ typedef struct __DMA_HandleTypeDef */ #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ - + +/** @defgroup DMA_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ + /* Initialization and de-initialization functions *****************************/ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions + * @{ + */ + /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions + * @{ + */ /* Peripheral State and Error functions ***************************************/ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); +/** + * @} + */ + +/** + * @} + */ + /** * @} */ @@ -540,3 +624,4 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); #endif /* __STM32L0xx_HAL_DMA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.c new file mode 100644 index 00000000000..f4a58f180f1 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.c @@ -0,0 +1,311 @@ +/** + ****************************************************************************** + * @file stm32l0xx_hal_firewall.c + * @author MCD Application Team + * @version V1.2.0 + * @date 06-February-2015 + * @brief FIREWALL HAL module driver. + * + * This file provides firmware functions to manage the Firewall + * Peripheral initialization and enabling. + * + * + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The FIREWALL HAL driver can be used as follows: + + (#) Declare a FIREWALL_InitTypeDef initialization structure. + + (#) Resort to HAL_FIREWALL_Config() API to initialize the Firewall + + (#) Enable the FIREWALL in calling HAL_FIREWALL_EnableFirewall() API + + (#) To ensure that any code executed outside the protected segment closes the + FIREWALL, the user must set the flag FIREWALL_PRE_ARM_SET in calling + __HAL_FIREWALL_PREARM_ENABLE() macro if called within a protected code segment + or + HAL_FIREWALL_EnablePreArmFlag() API if called outside of protected code segment + after HAL_FIREWALL_Config() call. + + + @endverbatim + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_hal.h" + +/** @addtogroup STM32L0xx_HAL_Driver + * @{ + */ + +/** @defgroup FIREWALL FIREWALL + * @brief HAL FIREWALL module driver + * @{ + */ +#ifdef HAL_FIREWALL_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private functions ---------------------------------------------------------*/ + + +/** @defgroup FIREWALL_Exported_Functions FIREWALL Exported Functions + * @{ + */ + +/** @defgroup FIREWALL_Exported_Functions_Group1 Initialization Functions + * @brief Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides the functions allowing to initialize the Firewall. + Initialization is done by HAL_FIREWALL_Config(): + + (+) Enable the Firewall clock thru __HAL_RCC_FIREWALL_CLK_ENABLE() macro. + + (+) Set the protected code segment address start and length. + + (+) Set the protected non-volatile and/or volatile data segments + address starts and lengths if applicable. + + (+) Set the volatile data segment execution and sharing status. + + (+) Length must be set to 0 for an unprotected segment. + +@endverbatim + * @{ + */ + +/** + * @brief Initialize the Firewall according to the FIREWALL_InitTypeDef structure parameters. + * @param fw_init: Firewall initialization structure + * @note The API returns HAL_ERROR if the Firewall is already enabled. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init) +{ + /* Check the Firewall initialization structure allocation */ + if(fw_init == NULL) + { + return HAL_ERROR; + } + + /* Enable Firewall clock */ + __HAL_RCC_FIREWALL_CLK_ENABLE(); + + /* Make sure that Firewall is not enabled already */ + if (__HAL_FIREWALL_IS_ENABLED() != RESET) + { + return HAL_ERROR; + } + + /* Check Firewall configuration addresses and lengths when segment is protected */ + /* Code segment */ + if (fw_init->CodeSegmentLength != 0) + { + assert_param(IS_FIREWALL_CODE_SEGMENT_ADDRESS(fw_init->CodeSegmentStartAddress)); + assert_param(IS_FIREWALL_CODE_SEGMENT_LENGTH(fw_init->CodeSegmentStartAddress, fw_init->CodeSegmentLength)); + } + /* Non volatile data segment */ + if (fw_init->NonVDataSegmentLength != 0) + { + assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(fw_init->NonVDataSegmentStartAddress)); + assert_param(IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(fw_init->NonVDataSegmentStartAddress, fw_init->NonVDataSegmentLength)); + } + /* Volatile data segment */ + if (fw_init->VDataSegmentLength != 0) + { + assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(fw_init->VDataSegmentStartAddress)); + assert_param(IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(fw_init->VDataSegmentStartAddress, fw_init->VDataSegmentLength)); + } + + /* Check Firewall Configuration Register parameters */ + assert_param(IS_FIREWALL_VOLATILEDATA_EXECUTE(fw_init->VolatileDataExecution)); + assert_param(IS_FIREWALL_VOLATILEDATA_SHARE(fw_init->VolatileDataShared)); + + + /* Configuration */ + + /* Protected code segment start address configuration */ + WRITE_REG(FW->CSSA, (FW_CSSA_ADD & fw_init->CodeSegmentStartAddress)); + /* Protected code segment length configuration */ + WRITE_REG(FW->CSL, (FW_CSL_LENG & fw_init->CodeSegmentLength)); + + /* Protected non volatile data segment start address configuration */ + WRITE_REG(FW->NVDSSA, (FW_NVDSSA_ADD & fw_init->NonVDataSegmentStartAddress)); + /* Protected non volatile data segment length configuration */ + WRITE_REG(FW->NVDSL, (FW_NVDSL_LENG & fw_init->NonVDataSegmentLength)); + + /* Protected volatile data segment start address configuration */ + WRITE_REG(FW->VDSSA, (FW_VDSSA_ADD & fw_init->VDataSegmentStartAddress)); + /* Protected volatile data segment length configuration */ + WRITE_REG(FW->VDSL, (FW_VDSL_LENG & fw_init->VDataSegmentLength)); + + /* Set Firewall Configuration Register VDE and VDS bits + (volatile data execution and shared configuration) */ + MODIFY_REG(FW->CR, FW_CR_VDS|FW_CR_VDE, fw_init->VolatileDataExecution|fw_init->VolatileDataShared); + + return HAL_OK; +} + +/** + * @brief Retrieve the Firewall configuration. + * @param fw_config: Firewall configuration, type is same as initialization structure + * @note This API can't be executed inside a code area protected by the Firewall + * when the Firewall is enabled + * @note If NVDSL register is different from 0, that is, if the non volatile data segment + * is defined, this API can't be executed when the Firewall is enabled. + * @note User should resort to __HAL_FIREWALL_GET_PREARM() macro to retrieve FPA bit status + * @retval None + */ +void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config) +{ + + /* Enable Firewall clock, in case no Firewall configuration has been carried + out up to this point */ + __HAL_RCC_FIREWALL_CLK_ENABLE(); + + /* Retrieve code segment protection setting */ + fw_config->CodeSegmentStartAddress = (READ_REG(FW->CSSA) & FW_CSSA_ADD); + fw_config->CodeSegmentLength = (READ_REG(FW->CSL) & FW_CSL_LENG); + + /* Retrieve non volatile data segment protection setting */ + fw_config->NonVDataSegmentStartAddress = (READ_REG(FW->NVDSSA) & FW_NVDSSA_ADD); + fw_config->NonVDataSegmentLength = (READ_REG(FW->NVDSL) & FW_NVDSL_LENG); + + /* Retrieve volatile data segment protection setting */ + fw_config->VDataSegmentStartAddress = (READ_REG(FW->VDSSA) & FW_VDSSA_ADD); + fw_config->VDataSegmentLength = (READ_REG(FW->VDSL) & FW_VDSL_LENG); + + /* Retrieve volatile data execution setting */ + fw_config->VolatileDataExecution = (READ_REG(FW->CR) & FW_CR_VDE); + + /* Retrieve volatile data shared setting */ + fw_config->VolatileDataShared = (READ_REG(FW->CR) & FW_CR_VDS); + + return; +} + + + +/** + * @brief Enable FIREWALL. + * @note Firewall is enabled in clearing FWDIS bit of SYSCFG CFGR1 register. + * Once enabled, the Firewall cannot be disabled by software. Only a + * system reset can set again FWDIS bit. + * @retval None + */ +void HAL_FIREWALL_EnableFirewall(void) +{ + /* Clears FWDIS bit of SYSCFG CFGR1 register */ + CLEAR_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN); + +} + +/** + * @brief Enable FIREWALL pre arm. + * @note When FPA bit is set, any code executed outside the protected segment + * will close the Firewall. + * @note This API provides the same service as __HAL_FIREWALL_PREARM_ENABLE() macro + * but can't be executed inside a code area protected by the Firewall. + * @note -- When the Firewall is disabled, user can resort to + * HAL_FIREWALL_EnablePreArmFlag() API any time. + * -- When the Firewall is enabled and NVDSL register is equal to 0 (that is, + * when the non volatile data segment is not defined), + * ** this API can be executed when the Firewall is closed + * ** when the Firewall is opened, user should resort to + * __HAL_FIREWALL_PREARM_ENABLE() macro instead + * -- When the Firewall is enabled and NVDSL register is different from 0 + * (that is, when the non volatile data segment is defined) + * ** FW_CR register can be accessed only when the Firewall is opened: + * user should resort to __HAL_FIREWALL_PREARM_ENABLE() macro instead. + * @retval None + */ +void HAL_FIREWALL_EnablePreArmFlag(void) +{ + /* Set FPA bit */ + SET_BIT(FW->CR, FW_CR_FPA); +} + + +/** + * @brief Disable FIREWALL pre arm. + * @note When FPA bit is reset, any code executed outside the protected segment + * when the Firewall is opened will generate a system reset. + * @note This API provides the same service as __HAL_FIREWALL_PREARM_DISABLE() macro + * but can't be executed inside a code area protected by the Firewall. + * @note -- When the Firewall is disabled, user can resort to + * HAL_FIREWALL_EnablePreArmFlag() API any time. + * -- When the Firewall is enabled and NVDSL register is equal to 0 (that is, + * when the non volatile data segment is not defined), + * ** this API can be executed when the Firewall is closed + * ** when the Firewall is opened, user should resort to + * __HAL_FIREWALL_PREARM_DISABLE() macro instead + * -- When the Firewall is enabled and NVDSL register is different from 0 + * (that is, when the non volatile data segment is defined) + * ** FW_CR register can be accessed only when the Firewall is opened: + * user should resort to __HAL_FIREWALL_PREARM_DISABLE() macro instead. + + * @retval None + */ +void HAL_FIREWALL_DisablePreArmFlag(void) +{ + /* Clear FPA bit */ + CLEAR_BIT(FW->CR, FW_CR_FPA); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* HAL_FIREWALL_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.h new file mode 100644 index 00000000000..2b483a8768c --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_firewall.h @@ -0,0 +1,372 @@ +/** + ****************************************************************************** + * @file stm32l0xx_hal_firewall.h + * @author MCD Application Team + * @version V1.2.0 + * @date 06-February-2015 + * @brief Header file of FIREWALL HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_HAL_FIREWALL_H +#define __STM32L0xx_HAL_FIREWALL_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_hal_def.h" + +/** @addtogroup STM32L0xx_HAL_Driver + * @{ + */ + +/** @addtogroup FIREWALL FIREWALL + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup FIREWALL_Exported_Types FIREWALL Exported Types + * @{ + */ + +/** + * @brief FIREWALL Initialization Structure definition + */ +typedef struct +{ + uint32_t CodeSegmentStartAddress; /*!< Protected code segment start address. This value is 24-bit long, the 8 LSB bits are + reserved and forced to 0 in order to allow a 256-byte granularity. */ + + uint32_t CodeSegmentLength; /*!< Protected code segment length in bytes. This value is 22-bit long, the 8 LSB bits are + reserved and forced to 0 for the length to be a multiple of 256 bytes. */ + + uint32_t NonVDataSegmentStartAddress; /*!< Protected non-volatile data segment start address. This value is 24-bit long, the 8 LSB + bits are reserved and forced to 0 in order to allow a 256-byte granularity. */ + + uint32_t NonVDataSegmentLength; /*!< Protected non-volatile data segment length in bytes. This value is 22-bit long, the 8 LSB + bits are reserved and forced to 0 for the length to be a multiple of 256 bytes. */ + + uint32_t VDataSegmentStartAddress; /*!< Protected volatile data segment start address. This value is 17-bit long, the 6 LSB bits + are reserved and forced to 0 in order to allow a 64-byte granularity. */ + + uint32_t VDataSegmentLength; /*!< Protected volatile data segment length in bytes. This value is 17-bit long, the 6 LSB + bits are reserved and forced to 0 for the length to be a multiple of 64 bytes. */ + + uint32_t VolatileDataExecution; /*!< Set VDE bit specifying whether or not the volatile data segment can be executed. + When VDS = 1 (set by parameter VolatileDataShared), VDE bit has no meaning. + This parameter can be a value of @ref FIREWALL_VolatileData_Executable */ + + uint32_t VolatileDataShared; /*!< Set VDS bit in specifying whether or not the volatile data segment can be shared with a + non-protected application code. + This parameter can be a value of @ref FIREWALL_VolatileData_Shared */ + +}FIREWALL_InitTypeDef; + + +/** + * @} + */ + + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup FIREWALL_Exported_Constants FIREWALL Exported Constants + * @{ + */ + +/** @defgroup FIREWALL_VolatileData_Executable FIREWALL volatile data segment execution status + * @{ + */ +#define FIREWALL_VOLATILEDATA_NOT_EXECUTABLE ((uint32_t)0x0000) +#define FIREWALL_VOLATILEDATA_EXECUTABLE ((uint32_t)FW_CR_VDE) +/** + * @} + */ + +/** @defgroup FIREWALL_VolatileData_Shared FIREWALL volatile data segment share status + * @{ + */ +#define FIREWALL_VOLATILEDATA_NOT_SHARED ((uint32_t)0x0000) +#define FIREWALL_VOLATILEDATA_SHARED ((uint32_t)FW_CR_VDS) +/** + * @} + */ + +/** @defgroup FIREWALL_Pre_Arm FIREWALL pre arm status + * @{ + */ +#define FIREWALL_PRE_ARM_RESET ((uint32_t)0x0000) +#define FIREWALL_PRE_ARM_SET ((uint32_t)FW_CR_FPA) + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup FIREWALL_Private_Macros FIREWALL Private Macros + * @{ + */ +#define IS_FIREWALL_CODE_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) +#define IS_FIREWALL_CODE_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= 0x080FFFFF) + +#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x080FFFFF)) +#define IS_FIREWALL_NONVOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= 0x080FFFFF) + +#define IS_FIREWALL_VOLATILEDATA_SEGMENT_ADDRESS(ADDRESS) (((ADDRESS) >= 0x20000000) && ((ADDRESS) <= 0x20017FFF)) +#define IS_FIREWALL_VOLATILEDATA_SEGMENT_LENGTH(ADDRESS, LENGTH) (((ADDRESS) + (LENGTH)) <= 0x20017FFF) + + +#define IS_FIREWALL_VOLATILEDATA_SHARE(SHARE) (((SHARE) == FIREWALL_VOLATILEDATA_NOT_SHARED) || \ + ((SHARE) == FIREWALL_VOLATILEDATA_SHARED)) + +#define IS_FIREWALL_VOLATILEDATA_EXECUTE(EXECUTE) (((EXECUTE) == FIREWALL_VOLATILEDATA_NOT_EXECUTABLE) || \ + ((EXECUTE) == FIREWALL_VOLATILEDATA_EXECUTABLE)) +/** + * @} + */ + + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup FIREWALL_Exported_Macros FIREWALL Exported Macros + * @{ + */ + +/** @brief Check whether or not the FIREWALL is enabled + * @retval FIREWALL enabling status (TRUE or FALSE). + */ +#define __HAL_FIREWALL_IS_ENABLED() HAL_IS_BIT_CLR(SYSCFG->CFGR2, SYSCFG_CFGR2_FWDISEN) + + +/** @brief Enable FIREWALL pre arm. + * @note When FPA bit is set, any code executed outside the protected segment + * closes the Firewall, otherwise it generates a system reset. + * @note This macro provides the same service as HAL_FIREWALL_EnablePreArmFlag() API + * but can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_PREARM_ENABLE() \ + do { \ + __IO uint32_t tmpreg; \ + SET_BIT(FW->CR, FW_CR_FPA) ; \ + /* Read bit back to ensure it is taken into account by IP */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FW->CR, FW_CR_FPA) ; \ + UNUSED(tmpreg); \ + } while(0) + + + +/** @brief Disable FIREWALL pre arm. + * @note When FPA bit is set, any code executed outside the protected segment + * closes the Firewall, otherwise, it generates a system reset. + * @note This macro provides the same service as HAL_FIREWALL_DisablePreArmFlag() API + * but can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_PREARM_DISABLE() \ + do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(FW->CR, FW_CR_FPA) ; \ + /* Read bit back to ensure it is taken into account by IP */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FW->CR, FW_CR_FPA) ; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable volatile data sharing in setting VDS bit. + * @note When VDS bit is set, the volatile data segment is shared with non-protected + * application code. It can be accessed whatever the Firewall state (opened or closed). + * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_VOLATILEDATA_SHARED_ENABLE() \ + do { \ + __IO uint32_t tmpreg; \ + SET_BIT(FW->CR, FW_CR_VDS) ; \ + /* Read bit back to ensure it is taken into account by IP */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FW->CR, FW_CR_VDS) ; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Disable volatile data sharing in resetting VDS bit. + * @note When VDS bit is reset, the volatile data segment is not shared and cannot be + * hit by a non protected executable code when the Firewall is closed. If it is + * accessed in such a condition, a system reset is generated by the Firewall. + * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_VOLATILEDATA_SHARED_DISABLE() \ + do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(FW->CR, FW_CR_VDS) ; \ + /* Read bit back to ensure it is taken into account by IP */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FW->CR, FW_CR_VDS) ; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enable volatile data execution in setting VDE bit. + * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be + * executed whatever the VDE bit value. + * @note When VDE bit is set (with VDS = 0), the volatile data segment is executable. When + * the Firewall call is closed, a "call gate" entry procedure is required to open + * first the Firewall. + * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_ENABLE() \ + do { \ + __IO uint32_t tmpreg; \ + SET_BIT(FW->CR, FW_CR_VDE) ; \ + /* Read bit back to ensure it is taken into account by IP */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FW->CR, FW_CR_VDE) ; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Disable volatile data execution in resetting VDE bit. + * @note VDE bit is ignored when VDS is set. IF VDS = 1, the Volatile data segment can be + * executed whatever the VDE bit value. + * @note When VDE bit is reset (with VDS = 0), the volatile data segment cannot be executed. + * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + */ +#define __HAL_FIREWALL_VOLATILEDATA_EXECUTION_DISABLE() \ + do { \ + __IO uint32_t tmpreg; \ + CLEAR_BIT(FW->CR, FW_CR_VDE) ; \ + /* Read bit back to ensure it is taken into account by IP */ \ + /* (introduce proper delay inside macro execution) */ \ + tmpreg = READ_BIT(FW->CR, FW_CR_VDE) ; \ + UNUSED(tmpreg); \ + } while(0) + + +/** @brief Check whether or not the volatile data segment is shared. + * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + * @retval VDS bit setting status (TRUE or FALSE). + */ +#define __HAL_FIREWALL_GET_VOLATILEDATA_SHARED() ((FW->CR & FW_CR_VDS) == FW_CR_VDS) + +/** @brief Check whether or not the volatile data segment is declared executable. + * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + * @retval VDE bit setting status (TRUE or FALSE). + */ +#define __HAL_FIREWALL_GET_VOLATILEDATA_EXECUTION() ((FW->CR & FW_CR_VDE) == FW_CR_VDE) + +/** @brief Check whether or not the Firewall pre arm bit is set. + * @note This macro can be executed inside a code area protected by the Firewall. + * @note This macro can be executed whatever the Firewall state (opened or closed) when + * NVDSL register is equal to 0. Otherwise (when NVDSL register is different from + * 0, that is, when the non volatile data segment is defined), the macro can be + * executed only when the Firewall is opened. + * @retval FPA bit setting status (TRUE or FALSE). + */ +#define __HAL_FIREWALL_GET_PREARM() ((FW->CR & FW_CR_FPA) == FW_CR_FPA) + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @addtogroup FIREWALL_Exported_Functions FIREWALL Exported Functions + * @{ + */ + +/** @addtogroup FIREWALL_Exported_Functions_Group1 Initialization Functions + * @brief Initialization and Configuration Functions + * @{ + */ + +/* Initialization functions ********************************/ +HAL_StatusTypeDef HAL_FIREWALL_Config(FIREWALL_InitTypeDef * fw_init); +void HAL_FIREWALL_GetConfig(FIREWALL_InitTypeDef * fw_config); +void HAL_FIREWALL_EnableFirewall(void); +void HAL_FIREWALL_EnablePreArmFlag(void); +void HAL_FIREWALL_DisablePreArmFlag(void); + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_HAL_FIREWALL_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.c index 33db5302bc0..560ff043ce7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_flash.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: @@ -19,39 +19,73 @@ ##### FLASH peripheral features ##### ============================================================================== - [..] The Flash memory interface manages CPU accesses to the Flash memory. - It implements the erase and program Flash memory operations + [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses + to the Flash memory. It implements the erase and program Flash memory operations and the read and write protection mechanisms. + [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. + [..] The FLASH main features are: (+) Flash memory read operations (+) Flash memory program/erase operations (+) Read / write protections + (+) Prefetch on I-Code (+) Option Bytes programming ##### How to use this driver ##### ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32L0xx devices. + [..] This driver provides functions to configure and program the Flash + memory of all STM32L0xx devices. - (#) FLASH Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Program functions: byte, half word and word - (++) There Two modes of programming : - (+++) Polling mode using HAL_FLASH_Program() function - (+++) Interrupt mode using HAL_FLASH_Program_IT() function + (#) FLASH Memory Programming functions: this group includes all + needed functions to erase and program the main memory: + (++) Lock and Unlock the Flash interface. + (++) Erase function: Erase Page. + (++) Program functions: Fast Word and Half Page(should be + executed from internal SRAM). + + (#) DATA EEPROM Programming functions: this group includes all + needed functions to erase and program the DATA EEPROM memory: + (++) Lock and Unlock the DATA EEPROM interface. + (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase + Double Word (should be executed from internal SRAM). + (++) Program functions: Fast Program Byte, Fast Program Half-Word, + FastProgramWord, Program Byte, Program Half-Word, + Program Word and Program Double-Word (should be executed + from internal SRAM). + + (#) FLASH Option Bytes Programming functions: this group includes + all needed functions to: + (++) Lock and Unlock the Flash Option bytes. + (++) Set/Reset the write protection. + (++) Set the Read protection Level. + (++) Set the BOR level. + (++) Program the user option Bytes. + (++) Launch the Option Bytes loader. + (++) Get the Write protection. + (++) Get the read protection status. + (++) Get the BOR level. + (++) Get the user option bytes. (#) Interrupts and flags management functions : (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() (++) Wait for last FLASH operation according to its status (++) Get error flag status by calling HAL_GetErrorCode() - [..] - In addition to these functions, this driver includes a set of macros allowing + (#) FLASH Interface configuration functions: this group includes + the management of following features: + (++) Enable/Disable the RUN PowerDown mode. + (++) Enable/Disable the SLEEP PowerDown mode. + + (#) FLASH Peripheral State methods: this group includes + the management of following features: + (++) Wait for the FLASH operation + (++) Get the specific FLASH error flag + + [..] In addition to these function, this driver includes a set of macros allowing to handle the following operations: - (+) Set the latency + + (+) Set/Get the latency (+) Enable/Disable the prefetch buffer (+) Enable/Disable the preread buffer (+) Enable/Disable the Flash power-down @@ -101,23 +135,16 @@ [..] Proprietary code Read Out Protection (PcROP): (#) The PcROP sector is selected by using the same option bytes as the Write - protection (nWRPi bits). As a result, these 2 options are exclusive each other. - (#) In order to activate the PcROP (change the function of the nWRPi option bits), - the SPRMOD option bit must be activated. - (#) The active value of nWRPi bits is inverted when PCROP mode is active, this - means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user page "i" - is read/write protected. - (#) To activate PCROP mode for Flash page(s), you need to follow the sequence below: - (++) For page(s) within the first 64KB of the Flash, use this function - HAL_FLASHEx_AdvOBProgram with PCROPState = PCROPSTATE_ENABLE. - + protection. As a result, these 2 options are exclusive each other. + (#) To activate PCROP mode for Flash sectors(s), you need to follow the sequence below: + (++) Use this function HAL_FLASHEx_AdvOBProgram with PCROPState = OB_PCROP_STATE_ENABLE. * @endverbatim * ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -151,38 +178,40 @@ * @{ */ -/** @defgroup FLASH +#ifdef HAL_FLASH_MODULE_ENABLED + +/** @addtogroup FLASH FLASH * @brief FLASH driver modules * @{ */ -#ifdef HAL_FLASH_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)0xFFFF0) - -/* FLASH Mask */ -#define WRP01_MASK ((uint32_t)0x0000FFFF) -#define PAGESIZE ((uint32_t)0x00000080) - /* Private macro -------------------------------------------------------------*/ -/*Variables used for Erase sectors under interruption*/ -FLASH_ProcessTypeDef pFlash; +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup FLASH_Private_Variables FLASH Internal Variables + * @{ + */ +/** + * @brief Variable used for Program/Erase sectors under interruption + */ +FLASH_ProcessTypeDef ProcFlash; + +/** + * @} + */ /* Private function prototypes -----------------------------------------------*/ -static void FLASH_Program_Word(uint32_t Address, uint32_t Data); -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); static void FLASH_SetErrorCode(void); - - -/* Private functions ---------------------------------------------------------*/ +static void FLASH_Program_Word(uint32_t Address, uint32_t Data); -/** @defgroup FLASH_Private_Functions +/* functions -----------------------------------------------------------------*/ + +/** @addtogroup FLASH_Exported_Functions FLASH Exported functions * @{ */ -/** @defgroup FLASH_Group1 Programming operation functions +/** @addtogroup FLASH_Exported_Functions_Group1 * @brief Programming operation functions * @verbatim @@ -191,6 +220,10 @@ static void FLASH_SetErrorCode(void); */ /** * @brief Program word at a specified address + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). * @param TypeProgram: Indicate the way to program at a specified address. * This parameter can be a value of @ref FLASH_Type_Program * @param Address: specifies the address to be programmed. @@ -203,30 +236,25 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ - __HAL_LOCK(&pFlash); + __HAL_LOCK(&ProcFlash); /* Check the parameters */ - assert_param(IS_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - if(TypeProgram == TYPEPROGRAM_WORD) - { - /*Program word (32-bit) at a specified address.*/ - FLASH_Program_Word(Address, (uint32_t) Data); - } + /* Program word (32-bit) at a specified address */ + FLASH_Program_Word(Address, (uint32_t) Data); + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE); - - /* Reset PROG bit */ - FLASH->PECR &= ~FLASH_PECR_PROG; + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); + __HAL_UNLOCK(&ProcFlash); return status; } @@ -245,10 +273,10 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ - __HAL_LOCK(&pFlash); + __HAL_LOCK(&ProcFlash); /* Check the parameters */ - assert_param(IS_TYPEPROGRAM(TypeProgram)); + assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); /* Enable End of FLASH Operation interrupt */ __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); @@ -256,23 +284,15 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u /* Enable Error source interrupt */ __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\ - FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR); - - pFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; - pFlash.Address = Address; - - if(TypeProgram == TYPEPROGRAM_WORD) + ProcFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM; + ProcFlash.Address = Address; + + if(TypeProgram == FLASH_TYPEPROGRAM_WORD) { - /*Program word (32-bit) at a specified address.*/ + /* Program word (32-bit) at a specified address */ FLASH_Program_Word(Address, (uint32_t) Data); } - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - return status; } @@ -284,98 +304,93 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u void HAL_FLASH_IRQHandler(void) { uint32_t temp; - - /* If the program operation is completed, disable the PROG Bit */ - FLASH->PECR &= (~FLASH_PECR_PROG); - - /* If the erase operation is completed, disable the ERASE Bit */ - FLASH->PECR &= (~FLASH_PECR_ERASE); - - /* Check FLASH End of Operation flag */ - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP)) - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) - { - /*Nb of sector to erased can be decreased*/ - pFlash.NbPagesToErase--; - /* Check if there are still sectors to erase*/ - if(pFlash.NbPagesToErase != 0) - { - temp = pFlash.Page; - /*Indicate user which sector has been erased*/ - HAL_FLASH_EndOfOperationCallback(temp); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\ - FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR); - - /*Increment sector number*/ - temp = pFlash.Page + PAGESIZE; - pFlash.Page = pFlash.Page + PAGESIZE; - FLASH_Erase_Page(temp); - } - else - { - /*No more sectors to Erase, user callback can be called.*/ - /*Reset Sector and stop Erase sectors procedure*/ - pFlash.Page = temp = 0xFFFFFFFF; - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(temp); - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - } - else - { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) - { - /*Program ended. Return the selected address*/ - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(pFlash.Address); - } - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; - /* Clear FLASH End of Operation pending bit */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); - } - - } /* Check FLASH operation error flags */ - if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_ENDHV) != RESET) || \ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)|| (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || \ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET)|| (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) || \ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) != RESET)) + if (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_OPTVERR | \ + FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR | FLASH_FLAG_NOTZEROERR) != RESET) { - if(pFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) { - /*return the faulty sector*/ - temp = pFlash.Page; - pFlash.Page = 0xFFFFFFFF; + /* Return the faulty sector */ + temp = ProcFlash.Page; + ProcFlash.Page = 0xFFFFFFFF; } else { - /*retrun the faulty address*/ - temp = pFlash.Address; + /* Return the faulty address */ + temp = ProcFlash.Address; } - /*Save the Error code*/ + /* Save the Error code */ FLASH_SetErrorCode(); /* FLASH error interrupt user callback */ HAL_FLASH_OperationErrorCallback(temp); - /* Clear FLASH error pending bits */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\ - FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR); - /*Stop the procedure ongoing*/ - pFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* Stop the procedure ongoing */ + ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; } - if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE) + /* Check FLASH End of Operation flag */ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET) + { + /* Clear FLASH End of Operation pending bit */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP); + + /* Process can continue only if no error detected */ + if(ProcFlash.ProcedureOnGoing != FLASH_PROC_NONE) + { + if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE) + { + /* Nb of sector to erased can be decreased */ + ProcFlash.NbPagesToErase--; + + /* Check if there are still sectors to erase */ + if(ProcFlash.NbPagesToErase != 0) + { + temp = ProcFlash.Page; + /* Indicate user which sector has been erased */ + HAL_FLASH_EndOfOperationCallback(temp); + + /* Increment sector number */ + temp = ProcFlash.Page + FLASH_PAGE_SIZE; + ProcFlash.Page = ProcFlash.Page + FLASH_PAGE_SIZE; + + /* If the erase operation is completed, disable the ERASE Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + FLASH_ErasePage(temp); + } + else + { + /* No more sectors to Erase, user callback can be called */ + /* Reset Sector and stop Erase sectors procedure */ + ProcFlash.Page = temp = 0xFFFFFFFF; + ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(temp); + } + } + else + { + if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PROGRAM) + { + /* If the program operation is completed, disable the PROG Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + /* Program ended. Return the selected address */ + /* FLASH EOP interrupt user callback */ + HAL_FLASH_EndOfOperationCallback(ProcFlash.Address); + } + ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE; + } + } + } + + if(ProcFlash.ProcedureOnGoing == FLASH_PROC_NONE) { + /* Operation is completed, disable the PG and PER Bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE | FLASH_PECR_PROG); + /* Disable End of FLASH Operation interrupt */ __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP); @@ -383,7 +398,7 @@ void HAL_FLASH_IRQHandler(void) __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR); /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); + __HAL_UNLOCK(&ProcFlash); } } @@ -391,9 +406,9 @@ void HAL_FLASH_IRQHandler(void) /** * @brief FLASH end of operation interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * Pages_Erase: Sector which has been erased + * - Pages Erase: Sector which has been erased * (if 0xFFFFFFFF, it means that all the selected sectors have been erased) - * Program: Address which was selected for data program + * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) @@ -406,8 +421,8 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) /** * @brief FLASH operation error interrupt callback * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure - * Pages_Erase: Sector number which returned an error - * Program: Address which was selected for data program + * - Pagess Erase: Sector number which returned an error + * - Program: Address which was selected for data program * @retval none */ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) @@ -421,7 +436,7 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) * @} */ -/** @defgroup FLASH_Group2 Peripheral Control functions +/** @addtogroup FLASH_Exported_Functions_Group2 * @brief management functions * @verbatim @@ -435,18 +450,18 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) @endverbatim * @{ */ + /** * @brief Unlock the FLASH control register access - * @param None * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Unlock(void) { if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET) { + /* Unlocking FLASH_PECR register access */ if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) { - /* Unlocking the Data memory and FLASH_PECR register access*/ FLASH->PEKEYR = FLASH_PEKEY1; FLASH->PEKEYR = FLASH_PEKEY2; } @@ -465,29 +480,27 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void) /** * @brief Locks the FLASH control register access - * @param None * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_Lock(void) { /* Set the PRGLOCK Bit to lock the program memory access */ - FLASH->PECR |= FLASH_PECR_PRGLOCK; + SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK); return HAL_OK; } /** * @brief Unlock the FLASH Option Control Registers access. - * @param None * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) { if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET) { - if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) + /* Unlocking FLASH_PECR register access */ + if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) { - /* Unlocking the Data memory and FLASH_PECR register access*/ FLASH->PEKEYR = FLASH_PEKEY1; FLASH->PEKEYR = FLASH_PEKEY2; } @@ -506,36 +519,38 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) /** * @brief Lock the FLASH Option Control Registers access. - * @param None * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) { /* Set the OPTLOCK Bit to lock the option bytes block access */ - FLASH->PECR |= FLASH_PECR_OPTLOCK; + SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK); return HAL_OK; } /** * @brief Launch the option byte loading. - * @param None * @retval HAL_StatusTypeDef HAL Status */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) { + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Set the OBL_Launch bit to lauch the option byte loading */ - FLASH->PECR |= FLASH_PECR_OBL_LAUNCH; + SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH); /* Wait for last operation to be completed */ - return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + return(FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE +)); } /** * @} */ -/** @defgroup FLASH_Group3 Peripheral State and Errors functions +/** @addtogroup FLASH_Exported_Functions_Group3 * @brief Peripheral Errors functions * @verbatim @@ -551,20 +566,19 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) /** * @brief Get the specific FLASH error flag. - * @param None - * @retval FLASH_ErrorCode: The returned value can be: - * @arg FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) - * @arg FLASH_ERROR_ENDHV: FLASH Programming Sequence error flag - * @arg FLASH_ERROR_SIZE: FLASH Programming Parallelism error flag - * @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag - * @arg FLASH_ERROR_WRP: FLASH Write protected error flag - * @arg FLASH_ERROR_OPTV: FLASH Option valid error flag - * @arg FLASH_ERROR_NOTZERO: FLASH write operation is done in a not-erased region + * @retval uint32_t: The returned value can be a mixed of : + * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) + * @arg HAL_FLASH_ERROR_SIZE: FLASH Programming Parallelism error flag + * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg HAL_FLASH_ERROR_OPTV: FLASH Option valid error flag + * @arg HAL_FLASH_ERROR_FWWERR: FLASH Write or Errase operation aborted + * @arg HAL_FLASH_ERROR_NOTZERO: FLASH Write operation is done in a not-erased region */ -FLASH_ErrorTypeDef HAL_FLASH_GetError(void) +uint32_t HAL_FLASH_GetError(void) { - return pFlash.ErrorCode; -} + return ProcFlash.ErrorCode; +} /** * @} @@ -574,22 +588,24 @@ FLASH_ErrorTypeDef HAL_FLASH_GetError(void) * @} */ +/** @addtogroup FLASH_Private_Functions + * @{ + */ + /** * @brief Wait for a FLASH operation to complete. * @param Timeout: maximum flash operationtimeout - * @retval HAL_StatusTypeDef HAL Status + * @retval HAL status */ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { - uint32_t tickstart = 0; - /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - tickstart = HAL_GetTick(); + uint32_t tickstart = HAL_GetTick(); - while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) { if(Timeout != HAL_MAX_DELAY) { @@ -599,18 +615,17 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) } } } - - - if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) ||(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || \ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET)||(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) || \ - (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) ||(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) != RESET)) - { - /*Save the error code*/ + if((__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || \ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) || \ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) != RESET) || \ + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) != RESET)) + { + /* Save the error code */ FLASH_SetErrorCode(); return HAL_ERROR; } - /* If there is an error flag set */ + /* There is no error flag set */ return HAL_OK; } @@ -621,34 +636,39 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) */ static void FLASH_SetErrorCode(void) { - if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_ENDHV)) - { - pFlash.ErrorCode = FLASH_ERROR_ENDHV; - } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) { - pFlash.ErrorCode = FLASH_ERROR_WRP; + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) { - pFlash.ErrorCode = FLASH_ERROR_PGA; + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) { - pFlash.ErrorCode = FLASH_ERROR_SIZE; + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE; } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) { - pFlash.ErrorCode = FLASH_ERROR_OPTV; + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) { - pFlash.ErrorCode = FLASH_ERROR_RD; + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)) + { + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR; } if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR)) { - pFlash.ErrorCode = FLASH_ERROR_NOTZERO; + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO; } + + /* Errors are now stored, clear errors flags */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | + FLASH_FLAG_OPTVERR | FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR | + FLASH_FLAG_NOTZEROERR); } /** @@ -659,22 +679,24 @@ static void FLASH_SetErrorCode(void) * (recommended to protect the FLASH memory against possible unwanted operation) * @param Page_Address: The page address in program memory to be erased. * @note A Page is erased in the Program memory only if the address to load - * is the start address of a page (multiple of 256 bytes). + * is the start address of a page (multiple of 128 bytes). * @retval HAL_StatusTypeDef HAL Status */ -void FLASH_Erase_Page(uint32_t Page_Address) +void FLASH_ErasePage(uint32_t Page_Address) { + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Set the ERASE bit */ - FLASH->PECR |= FLASH_PECR_ERASE; - - /* Set PROG bit */ - FLASH->PECR |= FLASH_PECR_PROG; + SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + /* Set PROG bit */ + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - /* Write 00000000h to the first word of the program page to erase */ - *(__IO uint32_t *)Page_Address = 0x00000000; + /* Write 00000000h to the first word of the program page to erase */ + *(__IO uint32_t *)Page_Address = 0x00000000; } - /** * @brief Program word (32-bit) at a specified address. * @param Address: specifies the address to be programmed. @@ -686,21 +708,29 @@ static void FLASH_Program_Word(uint32_t Address, uint32_t Data) /* Check the parameters */ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - /* Set PROG bit */ - FLASH->PECR |= FLASH_PECR_PROG; + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; *(__IO uint32_t*)Address = Data; } +/** + * @} + */ + +/** + * @} + */ + #endif /* HAL_FLASH_MODULE_ENABLED */ + /** * @} */ /** * @} - */ - + */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.h index f96520cef4a..c820cfc57e7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash.h @@ -2,14 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_flash.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 - * @brief This file contains all the functions prototypes for the FLASH - * firmware library. + * @version V1.2.0 + * @date 06-February-2015 + * @brief Header file of Flash HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -51,25 +50,13 @@ * @{ */ -/** @addtogroup FLASH +/** @defgroup FLASH FLASH * @{ */ -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief FLASH Error structure definition - */ -typedef enum -{ - FLASH_ERROR_RD = 0x01, - FLASH_ERROR_ENDHV = 0x02, - FLASH_ERROR_SIZE = 0x04, - FLASH_ERROR_PGA = 0x08, - FLASH_ERROR_WRP = 0x10, - FLASH_ERROR_OPTV = 0x20, - FLASH_ERROR_NOTZERO = 0x40 -}FLASH_ErrorTypeDef; +/** @defgroup FLASH_Exported_Types FLASH Exported Types + * @{ + */ /** * @brief FLASH Procedure structure definition @@ -82,281 +69,149 @@ typedef enum } FLASH_ProcedureTypeDef; /** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< TypeErase: Mass erase or sector Erase. - This parameter can be a value of @ref FLASH_Type_Erase */ - - uint32_t Page; /*!< Sector: Initial FLASH sector to erase when Mass erase is disabled - This parameter must be an address value between 0x08000000 and 0x0800FFFF */ - - uint32_t NbPages; /*!< NbSectors: Number of sectors to be erased. - This parameter must be a value between 1 and (max number of sectors - initial sector value) */ - -} FLASH_EraseInitTypeDef; + * @brief FLASH Erase structure definition + */ + typedef struct + { + uint32_t TypeErase; /*!< TypeErase: Page Erase only. + This parameter can be a value of @ref FLASHEx_Type_Erase */ + + uint32_t PageAddress ; /*!< PageAddress : Initial FLASH address to be erased + This parameter must be a value belonging to FLASH Programm address (depending on the devices) */ + + uint32_t NbPages; /*!< NbPages: Number of pages to be erased. + This parameter must be a value between 1 and (max number of pages - value of Initial page)*/ + } FLASH_EraseInitTypeDef; /** - * @brief FLASH Option Bytes PROGRAM structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< OptionType: Option byte to be configured. - This parameter can be a value of @ref FLASH_Option_Type */ - - uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. - This parameter can be a value of @ref FLASH_WRP_State */ - - uint32_t WRPSector; /*!< WRPSector: specifies the sector(s) to be write protected. - The value of this parameter depends on device used within the same series */ - - uint32_t RDPLevel; /*!< RDPLevel: Set the read protection level.. - This parameter can be a value of @ref FLASH_Option_Bytes_Read_Protection */ - - uint32_t BORLevel; /*!< BORLevel: Set the BOR Level. - This parameter can be a value of @ref FLASH_Option_Bytes_BOR_Level */ - uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - This parameter can be a combination of @ref FLASH_Option_Bytes_IWatchdog, @ref FLASH_Option_Bytes_nRST_STOP and @ref FLASH_Option_Bytes_nRST_STDBY*/ -} FLASH_OBProgramInitTypeDef; + * @} + */ + + +/** @defgroup FLASH_Private_Types FLASH Private Types + * @{ + */ /** * @brief FLASH handle Structure definition */ typedef struct { - __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*Internal variable to indicate which procedure is ongoing or not in IT context*/ + __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing or not in IT context */ - __IO uint32_t NbPagesToErase; /*Internal variable to save the remaining sectors to erase in IT context*/ + __IO uint32_t NbPagesToErase; /* Internal variable to save the remaining sectors to erase in IT context */ - __IO uint32_t Page; /*Internal variable to define the current sector which is erasing*/ + __IO uint32_t Page; /* Internal variable to define the current sector which is erasing */ - __IO uint32_t Address; /*Internal variable to save address selected for program*/ + __IO uint32_t Address; /* Internal variable to save address selected for program */ HAL_LockTypeDef Lock; /* FLASH locking object */ - __IO FLASH_ErrorTypeDef ErrorCode; /* FLASH error code */ + __IO uint32_t ErrorCode; /* FLASH error code */ }FLASH_ProcessTypeDef; +/** + * @} + */ -/*Variables used for Erase sectors under interruption*/ -extern FLASH_ProcessTypeDef pFlash; - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants +/** @defgroup FLASH_Private_Variables FLASH Private Variables * @{ - */ + */ -/** @defgroup FLASH_Type_Erase - * @{ - */ -#define TYPEERASE_PAGEERASE ((uint32_t)0x00) /*!= DATA_EEPROM_BASE) && ((ADDRESS) <= DATA_EEPROM_END)) /* 2K */ -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END)) /* 64K */ -#define IS_NBPAGES(PAGES) (((PAGES) >= 1) && ((PAGES) <= 512)) /* 512 pages from page0 to page 511 */ -/** - * @} - */ +#define FLASH_SIZE (uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER) * 1024) +#define FLASH_PAGE_SIZE ((uint32_t)128) -/** @defgroup FLASH_Option_Bytes_Write_Protection +/** @defgroup FLASH_Type_Program * @{ */ -#define OB_WRP_Pages0to31 ((uint32_t)0x00000001) /* Write protection of Sector0 */ -#define OB_WRP_Pages32to63 ((uint32_t)0x00000002) /* Write protection of Sector1 */ -#define OB_WRP_Pages64to95 ((uint32_t)0x00000004) /* Write protection of Sector2 */ -#define OB_WRP_Pages96to127 ((uint32_t)0x00000008) /* Write protection of Sector3 */ -#define OB_WRP_Pages128to159 ((uint32_t)0x00000010) /* Write protection of Sector4 */ -#define OB_WRP_Pages160to191 ((uint32_t)0x00000020) /* Write protection of Sector5 */ -#define OB_WRP_Pages192to223 ((uint32_t)0x00000040) /* Write protection of Sector6 */ -#define OB_WRP_Pages224to255 ((uint32_t)0x00000080) /* Write protection of Sector7 */ -#define OB_WRP_Pages256to287 ((uint32_t)0x00000100) /* Write protection of Sector8 */ -#define OB_WRP_Pages288to319 ((uint32_t)0x00000200) /* Write protection of Sector9 */ -#define OB_WRP_Pages320to351 ((uint32_t)0x00000400) /* Write protection of Sector10 */ -#define OB_WRP_Pages352to383 ((uint32_t)0x00000800) /* Write protection of Sector11 */ -#define OB_WRP_Pages384to415 ((uint32_t)0x00001000) /* Write protection of Sector12 */ -#define OB_WRP_Pages416to447 ((uint32_t)0x00002000) /* Write protection of Sector13 */ -#define OB_WRP_Pages448to479 ((uint32_t)0x00004000) /* Write protection of Sector14 */ -#define OB_WRP_Pages480to511 ((uint32_t)0x00008000) /* Write protection of Sector15 */ - -#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */ - -#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) +#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!PECR |= (__INTERRUPT__)) +/** @defgroup FLASH_Exported_Macros FLASH Exported Macros + * @{ + */ + +/** @defgroup FLASH_Interrupt macros to handle FLASH interrupts + * @{ + */ /** - * @brief Disable the specified FLASH interrupt. + * @brief Enable/Disable the specified FLASH interrupt. * @param __INTERRUPT__ : FLASH interrupt - * This parameter can be any combination of the following values: + * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt * @retval none - */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) (FLASH->PECR &= ~(uint32_t)(__INTERRUPT__)) + */ +#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) ((FLASH->PECR) |= (__INTERRUPT__)) +#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) ((FLASH->PECR) &= ~(uint32_t)(__INTERRUPT__)) /** - * @brief Checks whether the specified FLASH flag is set or not. + * @brief Get the specified FLASH flag status. * @param __FLAG__: specifies the FLASH flag to check. * This parameter can be one of the following values: - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode - * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH size error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag - * @arg FLASH_FLAG_RDERR: FLASH Read protected error flag + * @arg FLASH_FLAG_BSY : FLASH Busy flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_READY: FLASH Ready flag after low power mode + * @arg FLASH_FLAG_ENDHV: FLASH End of high voltage flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_SIZERR: FLASH Size error flag + * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag + * @arg FLASH_FLAG_RDERR: FLASH Read protected error flag + * @arg FLASH_FLAG_FWWERR: FLASH Fetch While Write Error flag * @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag - * @retval The new state of FLASH_FLAG (SET or RESET). + * @retval The new state of __FLAG__ (SET or RESET). */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) ((FLASH->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) /** - * @brief Clears the FLASH's pending flags. + * @brief Clear the specified FLASH flag. * @param __FLAG__: specifies the FLASH flags to clear. * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH size error flag - * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag - * @arg FLASH_FLAG_OPTVERRUSR: FLASH Option User validity error flag - * @arg FLASH_FLAG_RDERR: FLASH Read protected error flag - * @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag + * @arg FLASH_FLAG_EOP: FLASH End of Operation flag + * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag + * @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag + * @arg FLASH_FLAG_SIZERR: FLASH size error flag + * @arg FLASH_FLAG_OPTVERR: FLASH Option validity error flag + * @arg FLASH_FLAG_RDERR: FLASH Read protected error flag + * @arg FLASH_FLAG_FWWERR: FLASH Fetch While Write Error flag + * @arg FLASH_FLAG_NOTZEROERR: Not Zero area error flag * @retval None */ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) (FLASH->SR = (__FLAG__)) /** * @} - */ + */ + +/** + * @} + */ /* Include FLASH HAL Extension module */ #include "stm32l0xx_hal_flash_ex.h" @@ -456,48 +306,102 @@ extern FLASH_ProcessTypeDef pFlash; /* Exported functions ------------------------------------------------------- */ +/** @defgroup FLASH_Exported_Functions FLASH Exported functions + * @{ + */ + +/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions + * @{ + */ + /** * @brief FLASH memory functions that can be executed from FLASH. - */ + */ /* Program operation functions ***********************************************/ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data); -/* FLASH IRQ handler function */ +/* FLASH IRQ handler function ***********************************************/ void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ +/* Callbacks in non blocking modes ******************************************/ void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); + +/** + * @} + */ + +/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ -/* Peripheral Control functions **********************************************/ +/* FLASH Memory Programming functions *****************************************/ HAL_StatusTypeDef HAL_FLASH_Unlock(void); HAL_StatusTypeDef HAL_FLASH_Lock(void); + +/* Option Bytes Programming functions *****************************************/ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); - -/* Option bytes control */ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); -/* Peripheral State functions ************************************************/ -FLASH_ErrorTypeDef HAL_FLASH_GetError(void); +/** + * @} + */ -/* Non-User functions ********************************************************/ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -void FLASH_Erase_Page(uint32_t Page_Address); +/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ +/* Peripheral State methods **************************************************/ +uint32_t HAL_FLASH_GetError(void); -#ifdef __cplusplus -} -#endif +/** + * @} + */ -#endif /* __STM32L0XX_HAL_FLASH_H */ +/** + * @} + */ +/** @defgroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ + +#define IS_FLASH_TYPEPROGRAM(VALUE) ((VALUE) == FLASH_TYPEPROGRAM_WORD) + +#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ + ((__LATENCY__) == FLASH_LATENCY_1)) /** * @} + */ + + +/** @defgroup FLASH_Private_Functions FLASH Private functions + * @{ */ +/** + * @brief Function used internally by HAL FLASH driver. + */ +HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_ErasePage(uint32_t Page_Address); +/** + * @} + */ + /** * @} */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0XX_HAL_FLASH_H */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.c index 7575dbd8e11..82e9c22050c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.c @@ -2,16 +2,16 @@ ****************************************************************************** * @file stm32l0xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the internal FLASH memory: * + FLASH Interface configuration - * + FLASH Memory Programming - * + DATA EEPROM Programming + * + FLASH Memory Erasing + * + DATA EEPROM Programming/Erasing * + Option Bytes Programming - * + Interrupts and flags management + * + Interrupts management * * @verbatim ============================================================================== @@ -20,6 +20,7 @@ [..] Comparing to other products, the FLASH interface for STM32L0xx devices contains the following additional features + (+) Erase functions (+) DATA_EEPROM memory management (+) BOOT option bit configuration (+) PCROP protection for all sectors @@ -30,13 +31,13 @@ of all STM32L0xx. It includes: (+) Full DATA_EEPROM erase and program management (+) Boot activation - (+) PCROP protection configuration and control for all pages + (+) PCROP protection configuration and control for all sectors @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -65,11 +66,12 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" -/** @addtogroup STM32L0XX_HAL_Driver + +/** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup FLASHEx HAL FLASH Driver +/** @addtogroup FLASHEx * @brief FLASH HAL Extension module driver * @{ */ @@ -78,61 +80,322 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define HAL_FLASH_TIMEOUT_VALUE ((uint32_t)0x50000 -#define WRP01_MASK ((uint32_t)0x0000FFFF) -#define PAGESIZE ((uint32_t)0x00000080) - /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState); -static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP); -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint16_t OB_BOOT); -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data); -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data); -static uint8_t FLASH_OB_GetUser(void); -static uint32_t FLASH_OB_GetWRP(void); -static FlagStatus FLASH_OB_GetRDP(void); -static uint8_t FLASH_OB_GetBOR(void); -static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState); -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t OB_RDP); +static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP); +static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR); +static uint8_t FLASH_OB_GetUser(void); +static uint8_t FLASH_OB_GetRDP(void); +static uint8_t FLASH_OB_GetBOR(void); +static uint8_t FLASH_OB_GetBOOTBit1(void); +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) +static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t Sector2, uint32_t NewState); +#else +static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t NewState); +#endif +static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint32_t WPRMOD); +static uint32_t FLASH_OB_GetWRP(void); +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) +static uint32_t FLASH_OB_GetWRP2(void); +#endif static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY); -static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t OB_BOR); +static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BOOT_Bit1); +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) +static HAL_StatusTypeDef FLASH_OB_BFB2Config(uint8_t OB_BFB2); +#endif + +/* Exported functions ---------------------------------------------------------*/ -/* Aliases for legacy HAL versions compatibility */ -#define DATA_EEPROM_FastProgramByte FLASH_DATAEEPROM_FastProgramByte -#define DATA_EEPROM_FastProgramHalfWord FLASH_DATAEEPROM_FastProgramHalfWord -#define DATA_EEPROM_FastProgramWord FLASH_DATAEEPROM_FastProgramWord -#define DATA_EEPROM_ProgramByte FLASH_DATAEEPROM_ProgramByte -#define DATA_EEPROM_ProgramHalfWord FLASH_DATAEEPROM_ProgramHalfWord -#define DATA_EEPROM_ProgramWord FLASH_DATAEEPROM_ProgramWord +/** @addtogroup FLASHEx_Exported_Functions + * @{ + */ - -/* Private functions ---------------------------------------------------------*/ +/** @addtogroup FLASHEx_Exported_Functions_Group1 + * @brief FLASH Memory Erasing functions + * +@verbatim + ============================================================================== + ##### FLASH Erasing Programming functions ##### + ============================================================================== + + [..] The FLASH Memory Erasing functions, includes the following functions: + (+) HAL_FLASHEx_Erase: return only when erase has been done + (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback is called with parameter + 0xFFFFFFFF + + [..] Any operation of erase should follow these steps: + (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and + program memory access. + (#) Call the desired function to erase page. + (#) Call the HAL_FLASH_Lock() to disable the flash program memory access + (recommended to protect the FLASH memory against possible unwanted operation). -/** @defgroup FLASHEx_Private_Functions Extended FLASH Private functions +@endverbatim * @{ */ -/** @defgroup FLASHEx_Group1 Peripheral extended features functions - * @brief Data transfers functions +/** + * @brief Erase the specified FLASH memory Pages + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @param[out] PageError: pointer to variable that + * contains the configuration information on faulty sector in case of error + * (0xFFFFFFFF means that all the sectors have been correctly erased) + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +{ + HAL_StatusTypeDef status = HAL_ERROR; + uint32_t index = 0; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if (status == HAL_OK) + { + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + /*Initialization of PageError variable*/ + *PageError = 0xFFFFFFFF; + + /* Check the parameters */ + assert_param(IS_NBPAGES(pEraseInit->NbPages)); + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + + /* Erase by sector by sector to be done*/ + for(index = pEraseInit->PageAddress; index < ((pEraseInit->NbPages * FLASH_PAGE_SIZE)+ pEraseInit->PageAddress); index += FLASH_PAGE_SIZE) + { + FLASH_ErasePage(index); + + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the erase operation is completed, disable the ERASE Bit */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + + if (status != HAL_OK) + { + /* In case of error, stop erase procedure and return the faulty sector*/ + *PageError = index; + break; + } + } + } + + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + + return status; +} + +/** + * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + End of erase is done when HAL_FLASH_EndOfOperationCallback is called with parameter + 0xFFFFFFFF + * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * contains the configuration information for the erasing. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Enable End of FLASH Operation interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); + + /* Enable Error source interrupt */ + __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); + + /* Check the parameters */ + assert_param(IS_NBPAGES(pEraseInit->NbPages)); + assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress)); + assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1)); + + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + ProcFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; + ProcFlash.NbPagesToErase = pEraseInit->NbPages; + ProcFlash.Page = pEraseInit->PageAddress; + + /* Erase 1st page and wait for IT */ + FLASH_ErasePage(pEraseInit->PageAddress); + return status; +} + +/** + * @} + */ + + +/** @addtogroup FLASHEx_Exported_Functions_Group2 + * @brief Option Bytes Programming functions * @verbatim - =============================================================================== - ##### Extended Features functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH data - transfers. + ============================================================================== + ##### Option Bytes Programming functions ##### + ============================================================================== + [..] Any operation of erase or program should follow these steps: + (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control + register access. + (#) Call following function to program the desired option bytes. + (++) HAL_FLASHEx_OBProgram: + - To Enable/Disable the desired sector write protection. + - To set the desired read Protection Level. + - To configure the user option Bytes: IWDG, STOP and the Standby. + - To Set the BOR level. + (#) Once all needed option bytes to be programmed are correctly written, call the + HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process. + (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended + to protect the option Bytes against possible unwanted operations). + + [..] Proprietary code Read Out Protection (PcROP): + (#) The PcROP sector is selected by using the same option bytes as the Write + protection (nWRPi bits). As a result, these 2 options are exclusive each other. + (#) In order to activate the PcROP (change the function of the nWRPi option bits), + the WPRMOD option bit must be activated. + (#) The active value of nWRPi bits is inverted when PCROP mode is active, this + means: if WPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i" + is read/write protected. + (#) To activate PCROP mode for Flash sector(s), you need to call the following function: + (++) HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected + (++) HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection @endverbatim * @{ */ +/** + * @brief Program option bytes + * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval HAL_StatusTypeDef HAL Status + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) +{ + HAL_StatusTypeDef status = HAL_ERROR; + + /* Process Locked */ + __HAL_LOCK(&ProcFlash); + + /* Check the parameters */ + assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); + + /* Write protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) + { + assert_param(IS_WRPSTATE(pOBInit->WRPState)); +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + status = FLASH_OB_ProtectedSectorsConfig(pOBInit->WRPSector, pOBInit->WRPSector2, pOBInit->WRPState); +#else + status = FLASH_OB_ProtectedSectorsConfig(pOBInit->WRPSector, pOBInit->WRPState); +#endif + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + return status; + } + } + + /* Read protection configuration */ + if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) + { + status = FLASH_OB_RDPConfig(pOBInit->RDPLevel); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + return status; + } + } + + /* USER configuration */ + if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) + { + status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, + pOBInit->USERConfig & OB_STOP_NORST, + pOBInit->USERConfig & OB_STDBY_NORST); + if (status != HAL_OK) + { + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + return status; + } + } + + /* BOR Level configuration */ + if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) + { + status = FLASH_OB_BORConfig(pOBInit->BORLevel); + } + + /* Program BOOT Bit1 config option byte */ + if ((pOBInit->OptionType & OPTIONBYTE_BOOT_BIT1) == OPTIONBYTE_BOOT_BIT1) + { + status = FLASH_OB_BOOTBit1Config(pOBInit->BOOTBit1Config); + } + + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); + return status; +} + +/** + * @brief Get the Option byte configuration + * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * contains the configuration information for the programming. + * + * @retval None + */ +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) +{ + pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; + + /* Get WRP sector */ + pOBInit->WRPSector = FLASH_OB_GetWRP(); + +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + pOBInit->WRPSector2 = FLASH_OB_GetWRP2(); +#endif + + /* Get RDP Level */ + pOBInit->RDPLevel = FLASH_OB_GetRDP(); + + /* Get USER */ + pOBInit->USERConfig = FLASH_OB_GetUser(); + + /* Get BOR Level */ + pOBInit->BORLevel = FLASH_OB_GetBOR(); + + /* Get BOOT bit 1 config OB */ + pOBInit->BOOTBit1Config = FLASH_OB_GetBOOTBit1(); + +} + /** * @brief Program option bytes * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that @@ -147,29 +410,23 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO /* Check the parameters */ assert_param(IS_OBEX(pAdvOBInit->OptionType)); - /*Program PCROP option byte*/ - if ((pAdvOBInit->OptionType&OBEX_PCROP) == OBEX_PCROP) + /* Program PCROP option byte */ + if ((pAdvOBInit->OptionType & OPTIONBYTE_PCROP) == OPTIONBYTE_PCROP) { /* Check the parameters */ assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState)); - if (pAdvOBInit->PCROPState == PCROPSTATE_ENABLE) - { - /*Enable of Write protection on the selected Sector*/ - status = FLASH_OB_PCROPConfig(pAdvOBInit->Pages, ENABLE); - status = FLASH_OB_PCROPSelectionConfig(OB_PCROP_SELECTED); - } - else - { - /*Disable of Write protection on the selected Sector*/ - status = FLASH_OB_PCROPConfig(pAdvOBInit->Pages, DISABLE); - status = FLASH_OB_PCROPSelectionConfig(OB_PCROP_DESELECTED); - } - } - /*Program BOOT config option byte*/ - if ((pAdvOBInit->OptionType&OBEX_BOOTCONFIG) == OBEX_BOOTCONFIG) +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + status = FLASH_OB_ProtectedSectorsConfig(pAdvOBInit->PCROPSector, pAdvOBInit->PCROPSector2, pAdvOBInit->PCROPState); +#else + status = FLASH_OB_ProtectedSectorsConfig(pAdvOBInit->PCROPSector, pAdvOBInit->PCROPState); +#endif + } +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + if ((pAdvOBInit->OptionType & OPTIONBYTE_BOOTCONFIG) == OPTIONBYTE_BOOTCONFIG) { - status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig); + status = FLASH_OB_BFB2Config(pAdvOBInit->BootConfig); } +#endif return status; } @@ -183,20 +440,54 @@ HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvO */ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit) { - pAdvOBInit->OptionType = OBEX_PCROP| OBEX_BOOTCONFIG; - /*Get PCROP state */ - pAdvOBInit->PCROPState = (FLASH->OBR & 0x00000100) >> 8; - /*Get PCROP protected Pages */ - pAdvOBInit->Pages = FLASH->WRPR; - /*Get Boot config OB*/ - pAdvOBInit->BootConfig = (FLASH->OBR & 0x80000000) >> 24; +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + pAdvOBInit->OptionType = OPTIONBYTE_PCROP| OPTIONBYTE_BOOTCONFIG; +#else + pAdvOBInit->OptionType = OPTIONBYTE_PCROP; +#endif + /* Get PCROP state */ + pAdvOBInit->PCROPState = (FLASH->OPTR & FLASH_OPTR_WPRMOD) >> 8; + /* Get PCROP protected sector */ + pAdvOBInit->PCROPSector = FLASH->WRPR; + +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + /* Get PCROP protected sector */ + pAdvOBInit->PCROPSector2 = FLASH->WRPR2; + + /* Get boot bank config */ + pAdvOBInit->BootConfig = (FLASH->OPTR & FLASH_OPTR_BFB2) >> 23; +#endif +} + +/** + * @brief Select the Protection Mode (WPRMOD). + * @note Once WPRMOD bit is active, unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @param None + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) +{ + return (FLASH_OB_PCROPSelectionConfig(1)); +} + +/** + * @brief Deselect the Protection Mode (WPRMOD). + * @note Once WPRMOD bit is active, unprotection of a protected sector is not possible + * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag + * @param None + * @retval HAL status + */ +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) +{ + return (FLASH_OB_PCROPSelectionConfig(0)); } /** * @} */ -/** @defgroup FLASHEx_Group2 DATA EEPROM Programming functions +/** @addtogroup FLASHEx_Exported_Functions_Group3 * @brief DATA EEPROM Programming functions * @verbatim @@ -230,15 +521,15 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void) { if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET) { - /* Unlocking the Data memory and FLASH_PECR register access*/ + /* Unlocking the Data memory and FLASH_PECR register access */ FLASH->PEKEYR = FLASH_PEKEY1; FLASH->PEKEYR = FLASH_PEKEY2; + return HAL_OK; } else { return HAL_ERROR; } - return HAL_OK; } /** @@ -249,8 +540,7 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void) HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void) { /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */ - FLASH->PECR |= FLASH_PECR_PELOCK; - + SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK); return HAL_OK; } @@ -262,8 +552,7 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void) * Call the HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access * and Flash program erase control register access(recommended to protect * the DATA_EEPROM against possible unwanted operation). - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * @retval HAL status */ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address) { @@ -273,294 +562,98 @@ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address) assert_param(IS_FLASH_DATA_ADDRESS(Address)); /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Write "00000000h" to valid address in the data memory" */ - *(__IO uint32_t *) Address = 0x00000000; - } - - /* Return the erase status */ + *(__IO uint32_t *) Address = 0x00000000; + } return status; } /** * @brief Program word at a specified address * @param TypeProgram: Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program + * This parameter can be a value of @ref FLASHEx_Type_Program_Data * @param Address: specifies the address to be programmed. * @param Data: specifies the data to be programmed * * @retval HAL_StatusTypeDef HAL Status */ -HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) +HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data) { HAL_StatusTypeDef status = HAL_ERROR; /* Process Locked */ - __HAL_LOCK(&pFlash); + __HAL_LOCK(&ProcFlash); /* Check the parameters */ - assert_param(IS_TYPEPROGRAM(TypeProgram)); - + assert_param(IS_TYPEPROGRAMDATA(TypeProgram)); + assert_param(IS_FLASH_DATA_ADDRESS(Address)); + /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - if(TypeProgram == TYPEPROGRAM_FASTBYTE) - { - /*Program word (8-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - } - - if(TypeProgram == TYPEPROGRAM_FASTHALFWORD) - { - /*Program word (16-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - } - if(TypeProgram == TYPEPROGRAM_FASTWORD) + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + + if(TypeProgram == FLASH_TYPEPROGRAMDATA_WORD) { - /*Program word (32-bit) at a specified address.*/ - FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + /* Program word (32-bit) at a specified address */ + *(__IO uint32_t *)Address = Data; } - if(TypeProgram == TYPEPROGRAM_WORD) + else if(TypeProgram == FLASH_TYPEPROGRAMDATA_HALFWORD) { - /*Program word (32-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + /* Program word (16-bit) at a specified address */ + *(__IO uint16_t *)Address = (uint16_t) Data; } - - if(TypeProgram == TYPEPROGRAM_HALFWORD) + else if(TypeProgram == FLASH_TYPEPROGRAMDATA_BYTE) { - /*Program word (16-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + /*Program word (8-bit) at a specified address */ + *(__IO uint8_t *)Address = (uint8_t) Data; } - - if(TypeProgram == TYPEPROGRAM_BYTE) + else { - /*Program word (8-bit) at a specified address.*/ - FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = HAL_ERROR; } - } - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + /* Process Unlocked */ + __HAL_UNLOCK(&ProcFlash); return status; } /** - * @brief Erase the specified FLASH memory Pages - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError: pointer to variable that - * contains the configuration information on faulty sector in case of error - * (0xFFFFFFFF means that all the sectors have been correctly erased) - * - * @retval HAL_StatusTypeDef HAL Status + * @brief Enable DATA EEPROM fixed Time programming (2*Tprog). + * @retval None */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) +void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void) { - HAL_StatusTypeDef status = HAL_ERROR; - uint32_t index = 0; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - if (status == HAL_OK) - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFF; - - /* Check the parameters */ - assert_param(IS_NBPAGES(pEraseInit->NbPages + pEraseInit->Page)); - - /* Erase by sector by sector to be done*/ - for(index = pEraseInit->Page; index < ((pEraseInit->NbPages*PAGESIZE)+ pEraseInit->Page); index+=PAGESIZE) - { - FLASH_Erase_Page(index); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - /* If the erase operation is completed, disable the ERASE Bit */ - FLASH->PECR &= (~FLASH_PECR_PROG); - FLASH->PECR &= (~FLASH_PECR_ERASE); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty sector*/ - *PageError = index; - break; - } - } - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; + SET_BIT(FLASH->PECR, FLASH_PECR_FIX); } /** - * @brief Perform a page erase of the specified FLASH memory pages with interrupt enabled - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL_StatusTypeDef HAL Status + * @brief Disables DATA EEPROM fixed Time programming (2*Tprog). + * @retval None */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) +void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void) { - HAL_StatusTypeDef status = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_TYPEERASE(pEraseInit->TypeErase)); - - /* Enable End of FLASH Operation interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP); - - /* Enable Error source interrupt */ - __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR); - - /* Clear pending flags (if any) */ - __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP | FLASH_FLAG_ENDHV | FLASH_FLAG_WRPERR |\ - FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR| FLASH_FLAG_OPTVERR |\ - FLASH_FLAG_RDERR | FLASH_FLAG_NOTZEROERR); - - if (pEraseInit->TypeErase == TYPEERASE_PAGEERASE) - { - /* Erase by sector to be done*/ - - /* Check the parameters */ - assert_param(IS_NBPAGES(pEraseInit->NbPages + pEraseInit->Page)); - - pFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE; - pFlash.NbPagesToErase = pEraseInit->NbPages; - pFlash.Page = pEraseInit->Page; - - /*Erase 1st page and wait for IT*/ - FLASH_Erase_Page(pEraseInit->Page); - } - - return status; -} - - -/** - * @brief Program option bytes - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval HAL_StatusTypeDef HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /*Write protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP) - { - assert_param(IS_WRPSTATE(pOBInit->WRPState)); - if (pOBInit->WRPState == WRPSTATE_ENABLE) - { - /*Enable of Write protection on the selected Sector*/ - status = FLASH_OB_WRPConfig(pOBInit->WRPSector, ENABLE); - } - else - { - /*Disable of Write protection on the selected Sector*/ - status = FLASH_OB_WRPConfig(pOBInit->WRPSector, DISABLE); - } - } - - /* Read protection configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP) - { - status = FLASH_OB_RDP_LevelConfig(pOBInit->RDPLevel); - } - - /* USER configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER) - { - status = FLASH_OB_UserConfig(pOBInit->USERConfig&OB_IWDG_SW, - pOBInit->USERConfig&OB_STOP_NoRST, - pOBInit->USERConfig&OB_STDBY_NoRST); - } - - /* BOR Level configuration*/ - if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR) - { - status = FLASH_OB_BOR_LevelConfig(pOBInit->BORLevel); - } - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option byte configuration - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR; - - /*Get WRP*/ - pOBInit->WRPSector = FLASH_OB_GetWRP(); - - /*Get RDP Level*/ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /*Get USER*/ - pOBInit->USERConfig = FLASH_OB_GetUser(); - - /*Get BOR Level*/ - pOBInit->BORLevel = FLASH_OB_GetBOR(); -} + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FIX); +} /** * @} */ - + /** * @brief Returns the FLASH User Option Bytes values. * @param None @@ -569,136 +662,65 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) static uint8_t FLASH_OB_GetUser(void) { /* Return the User Option Byte */ - return (uint8_t)(FLASH->OBR >> 20); + return (uint8_t)((FLASH->OPTR & FLASH_OPTR_USER) >> 16); } /** - * @brief Returns the FLASH Write Protection Option Bytes value. + * @brief Returns the FLASH Read out Protection Level. * @param None - * @retval The FLASH Write Protection Option Bytes value. + * @retval FLASH RDP level. */ -static uint32_t FLASH_OB_GetWRP(void) +static uint8_t FLASH_OB_GetRDP(void) { - /* Return the FLASH write protection Register value */ - return (uint32_t)(FLASH->WRPR); + return (uint8_t)(FLASH->OPTR & FLASH_OPTR_RDPROT); } /** - * @brief Checks whether the FLASH Read out Protection Status is set or not. + * @brief Returns the FLASH BOR level. * @param None - * @retval FLASH ReadOut Protection Status(SET or RESET). + * @retval The BOR level Option Bytes. */ -static FlagStatus FLASH_OB_GetRDP(void) +static uint8_t FLASH_OB_GetBOR(void) { - FlagStatus readstatus = RESET; - - if ((uint8_t)(FLASH->OBR) != (uint8_t)OB_RDP_Level_0) - { - readstatus = SET; - } - else - { - readstatus = RESET; - } - return readstatus; + /* Return the BOR level */ + return (uint8_t)((FLASH->OPTR & (uint32_t)FLASH_OPTR_BOR_LEV) >> 16); } /** - * @brief Returns the FLASH BOR level. + * @brief Returns the FLASH BOOT bit1 value. * @param None - * @retval The FLASH User Option Bytes. + * @retval The BOOT bit 1 value Option Bytes. */ -static uint8_t FLASH_OB_GetBOR(void) +static uint8_t FLASH_OB_GetBOOTBit1(void) { /* Return the BOR level */ - return (uint8_t)((FLASH->OBR & (uint32_t)0x000F0000) >> 16); + return (FLASH->OPTR & FLASH_OPTR_BOOT1) >> 31; + } /** - * @brief Write protects the desired pages of the first 64KB of the Flash. - * @param OB_WRP: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP_Pages0to31 and OB_WRP_Pages480to511 - * @arg OB_WRP_AllPages - * @param NewState: new state of the specified FLASH Pages Wtite protection. - * This parameter can be: ENABLE or DISABLE. - * @retval HAL_StatusTypeDef + * @brief Returns the FLASH Write Protection Option Bytes value. + * @param None + * @retval The FLASH Write Protection Option Bytes value. */ -static HAL_StatusTypeDef FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) +static uint32_t FLASH_OB_GetWRP(void) { - HAL_StatusTypeDef status = HAL_OK; - uint32_t WRP01_Data = 0; - uint32_t tmp1 = 0; - - /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - if(status == HAL_OK) - { - if (NewState != DISABLE) - { - WRP01_Data = (uint16_t)(((OB_WRP & WRP01_MASK) | OB->WRP01)); - tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data); - OB->WRP01 = tmp1; - } - else - { - WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01)); - tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data); - OB->WRP01 = tmp1; - } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE)); - } - - /* Return the write protection operation Status */ - return status; + /* Return the FLASH write protection Register value */ + return (uint32_t)(FLASH->WRPR); } + +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) /** - * @brief Enables or disables the read out protection. - * @note To correctly run this function, the FLASH_OB_Unlock() function - * must be called before. - * @param FLASH_ReadProtection_Level: specifies the read protection level. - * This parameter can be: - * @arg OB_RDP_Level_0: No protection - * @arg OB_RDP_Level_1: Read protection of the memory - * @arg OB_RDP_Level_2: Chip protection - * - * !!!Warning!!! When enabling OB_RDP_Level_2 it's no more possible to go back to level 1 or 0 - * - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * @brief Returns the FLASH Write Protection Option Bytes value. + * @param None + * @retval The FLASH Write Protection Option Bytes value. */ -static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t OB_RDP) +static uint32_t FLASH_OB_GetWRP2(void) { - HAL_StatusTypeDef status = HAL_OK; - uint16_t tmp1 = 0; - uint32_t tmp2 = 0; - - /* Check the parameters */ - assert_param(IS_OB_RDP(OB_RDP)); - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE)); - - /* calculate the option byte to write */ - tmp1 = ((uint16_t)(*(__IO uint16_t *)(OB_BASE)) & 0xFF00) | OB_RDP; - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(~tmp1) << 16)) | ((uint32_t)tmp1)); - - if(status == HAL_OK) - { - /* program read protection level */ - OB->RDP = tmp2; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - /* Return the Read protection operation Status */ - return status; + /* Return the FLASH write protection Register value */ + return (uint32_t)(FLASH->WRPR2); } +#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ /** * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. @@ -712,42 +734,84 @@ static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t OB_RDP) * @arg OB_STOP_RST: Reset generated when entering in STOP * @param OB_STDBY: Reset event when entering Standby mode. * This parameter can be one of the following values: - * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY + * @arg OB_STDBY_NORST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * @retval HAL status */ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0; + uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) (OB_IWDG | OB_STOP | OB_STDBY); /* Check the parameters */ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG)); assert_param(IS_OB_STOP_SOURCE(OB_STOP)); assert_param(IS_OB_STDBY_SOURCE(OB_STDBY)); + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Get the User Option byte register */ - tmp1 = (FLASH->OBR & 0x800F0000) >> 16; - + tmp1 = OB->USER & ((~FLASH_OPTR_USER) >> 16); + /* Calculate the user option byte to write */ - tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16); - tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1); + tmp = (~(OB_Bits | tmp1)) << 16; + tmp |= OB_Bits | tmp1; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - /* Write the User Option Byte */ + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Program OB */ OB->USER = tmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } + return status; +} + +/** + * @brief Enables or disables the read out protection. + * @note To correctly run this function, the FLASH_OB_Unlock() function + * must be called before. + * @param OB_RDP: specifies the read protection level. + * This parameter can be: + * @arg OB_RDP_LEVEL0: No protection + * @arg OB_RDP_LEVEL1: Read protection of the memory + * @arg OB_RDP_LEVEL2: Chip protection + * + * !!!Warning!!! When enabling OB_RDP_LEVEL2 it's no more possible to go back to level 1 or 0 + * + * @retval HAL status + */ +static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP) +{ + HAL_StatusTypeDef status; + uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) OB_RDP; + + /* Check the parameters */ + assert_param(IS_OB_RDP(OB_RDP)); + + /* Calculate the option byte to write */ + tmp = (OB->RDP & ((~FLASH_OPTR_RDPROT) & 0x0000FFFF)) | OB_Bits; + tmp1 = (~tmp << 16) | tmp; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - /* Return the Option Byte program Status */ - return status; + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Program OB */ + OB->RDP = tmp1; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + return status; } /** @@ -761,503 +825,241 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, u * @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply * @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply * @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * @retval HAL status */ -static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t OB_BOR) +static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR) { HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0; + uint32_t tmp = 0, tmp1 = 0, OB_Bits = (uint32_t) OB_BOR; /* Check the parameters */ assert_param(IS_OB_BOR_LEVEL(OB_BOR)); /* Get the User Option byte register */ - tmp1 = (FLASH->OBR & 0x000F0000) >> 16; - - /* Calculate the option byte to write */ - tmp = (uint32_t)~(OB_BOR | tmp1)<<16; - tmp |= (OB_BOR | tmp1); + tmp1 = OB->USER & ((~FLASH_OPTR_BOR_LEV) >> 16); + + /* Calculate the user option byte to write */ + tmp = (~(OB_Bits | tmp1)) << 16; + tmp |= OB_Bits | tmp1; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - /* Write the BOR Option Byte */ + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Program OB */ OB->USER = tmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - /* Return the Option Byte program Status */ return status; } - /** - * @brief Enables or disables the read/write protection (PCROP) of the desired - * sectors, for the first 64KB of the Flash. - * @param OB_WRP: specifies the address of the pages to be write protected. - * This parameter can be: - * @arg value between OB_WRP_Pages0to31 and OB_WRP_Pages480to511 - * @arg OB_WRP_AllPages - * @param NewState: new state of the specified FLASH Pages Write protection. - * This parameter can be: ENABLE or DISABLE. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * @brief Sets or resets the BOOT bit1 option bit. + * @param OB_BOOT_BIT1: Set or Reset the BOOT bit1 option bit. + * This parameter can be one of the following values: + * @arg OB_BOOT_BIT1_RESET: BOOT1 option bit reset + * @arg OB_BOOT_BIT1_SET: BOOT1 option bit set + * @retval HAL status */ -static HAL_StatusTypeDef FLASH_OB_PCROPConfig(uint32_t OB_WRP, FunctionalState NewState) +static HAL_StatusTypeDef FLASH_OB_BOOTBit1Config(uint8_t OB_BOOT_BIT1) { - HAL_StatusTypeDef status = HAL_OK; - uint32_t WRP01_Data = 0; - uint32_t tmp1 = 0; - + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) OB_BOOT_BIT1) << 15; + /* Check the parameters */ - assert_param(IS_OB_WRP(OB_WRP)); - assert_param(IS_FUNCTIONAL_STATE(NewState)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - if(status == HAL_OK) - { - if (NewState != DISABLE) - { - WRP01_Data = (uint16_t)(~OB_WRP & (WRP01_MASK & OB->WRP01)); + assert_param(IS_OB_BOOT1(OB_BOOT_BIT1)); + + /* Get the User Option byte register */ + tmp1 = OB->USER & ((~FLASH_OPTR_BOOT1) >> 16); - tmp1 = (uint32_t)((~WRP01_Data) << 16)|(WRP01_Data); - OB->WRP01 = tmp1; - } + /* Calculate the user option byte to write */ + tmp = (~(OB_Bits | tmp1)) << 16; + tmp |= OB_Bits | tmp1; - else - { - WRP01_Data = (uint16_t)((OB_WRP & WRP01_MASK) | OB->WRP01); - - tmp1 = (uint32_t)(~(WRP01_Data) << 16)|(WRP01_Data); - OB->WRP01 = tmp1; - } + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Program OB */ + OB->USER = tmp; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } - /* Return the write protection operation Status */ - return status; + return status; } /** - * @brief Select the Protection Mode (SPRMOD). - * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible + * @brief Select the Protection Mode (WPRMOD). + * @note Once WPRMOD bit is active, unprotection of a protected sector is not possible * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag * @param OB_PcROP: Select the Protection Mode of WPR bits. * This parameter can be: * @arg OB_PCROP_SELECTED: nWRP control the read&write protection (PcROP) of respective user sectors. * @arg OB_PCROP_DESELECTED: nWRP control the write protection of respective user sectors. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * @retval HAL status */ -static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint16_t OB_PcROP) +static HAL_StatusTypeDef FLASH_OB_PCROPSelectionConfig(uint32_t WPRMOD) { - HAL_StatusTypeDef status = HAL_OK; - uint16_t tmp1 = 0; - uint32_t tmp2 = 0; - uint8_t optiontmp = 0; - uint16_t optiontmp2 = 0; - - /* Check the parameters */ - assert_param(IS_OB_PCROP_SELECT(OB_PcROP)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - /* Mask RDP Byte */ - optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); - - /* Update Option Byte */ - optiontmp2 = (uint16_t)(OB_PcROP | optiontmp); - - - /* calculate the option byte to write */ - tmp1 = (uint16_t)(~(optiontmp2 )); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2)); - - if(status == HAL_OK) - { - /* program PCRop */ - OB->RDP = tmp2; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE)); - - /* Return the Read protection operation Status */ - return status; -} + HAL_StatusTypeDef status; + uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) WPRMOD) << 8; -/** - * @brief Select the Protection Mode (SPRMOD). - * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @param None - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t tmp1 = 0; - uint32_t tmp2 = 0; - uint8_t optiontmp = 0; - uint16_t optiontmp2 = 0; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - /* Mask RDP Byte */ - optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); - - /* Update Option Byte */ - optiontmp2 = (uint16_t)(FLASH_OBR_SPRMOD | optiontmp); - - - /* calculate the option byte to write */ - tmp1 = (uint16_t)(~(optiontmp2 )); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2)); - - if(status == HAL_OK) - { - /* program PCRop */ - OB->RDP = tmp2; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE)); - - /* Return the Read protection operation Status */ - return status; - -} + /* Get the User Option byte register */ + tmp1 = OB->USER & ((~FLASH_OPTR_WPRMOD) >> 16); -/** - * @brief Deselect the Protection Mode (SPRMOD). - * @note Once SPRMOD bit is active, unprotection of a protected sector is not possible - * @note Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag - * @param None - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint16_t tmp1 = 0; - uint32_t tmp2 = 0; - uint8_t optiontmp = 0; - uint16_t optiontmp2 = 0; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - /* Mask RDP Byte */ - optiontmp = (uint8_t)(*(__IO uint8_t *)(OB_BASE)); - - /* Update Option Byte */ - optiontmp2 = (uint16_t)(optiontmp); - - /* calculate the option byte to write */ - tmp1 = (uint16_t)(~(optiontmp2 )); - tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2)); + /* Calculate the user option byte to write */ + tmp = (~(OB_Bits | tmp1)) << 16; + tmp |= OB_Bits | tmp1; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + if(status == HAL_OK) { - /* program PCRop */ - OB->RDP = tmp2; + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; + /* Program OB */ + OB->RDP = tmp; + /* Wait for last operation to be completed */ + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE)); - - /* Return the Read protection operation Status */ - return status; -} + return status; +} +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) /** - * @brief Sets or resets the BOOT1 option bit. - * @param OB_BOOT1: Set or Reset the BOOT1 option bit. + * @brief Sets or resets the BFB2 option bit. + * @param BFB2: Set or Reset the BFB2 option bit. * This parameter can be one of the following values: - * @arg OB_BOOT1_RESET: BOOT1 option bit reset - * @arg OB_BOOT1_SET: BOOT1 option bit set + * @arg OB_BOOT_BANK1: BFB2 option bit reset + * @arg OB_BOOT_BANK2: BFB2 option bit set * @retval None */ -static HAL_StatusTypeDef FLASH_OB_BootConfig(uint16_t OB_BOOT) +static HAL_StatusTypeDef FLASH_OB_BFB2Config(uint8_t OB_BFB2) { - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmp = 0, tmp1 = 0; + HAL_StatusTypeDef status = HAL_OK; + uint32_t tmp = 0, tmp1 = 0, OB_Bits = ((uint32_t) OB_BFB2) << 7; /* Check the parameters */ - assert_param(IS_OB_BOOT1(OB_BOOT)); + assert_param(IS_OB_BOOT_BANK(OB_BFB2)); /* Get the User Option byte register */ - tmp1 = (FLASH->OBR & 0x007F0000) >> 16; - - /* Calculate the option byte to write */ - tmp = (uint32_t)~(OB_BOOT | tmp1)<<16; - tmp |= (OB_BOOT | tmp1); + tmp1 = OB->USER & ((~FLASH_OPTR_BFB2) >> 16); + + /* Calculate the user option byte to write */ + tmp = (~(OB_Bits | tmp1)) << 16; + tmp |= OB_Bits | tmp1; /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - /* Write the BOOT Option Byte */ - OB->USER = tmp; - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - /* Return the Option Byte program Status */ - return status; -} + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; -/** - * @brief Write a Byte at a specified address in data memory. - * @note To correctly run this function, the HAL_FLASHEx_DATAEEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that data word is already erased. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); + /* Program OB */ + OB->USER = tmp; - /* If the previous operation is completed, proceed to write the new Data */ - *(__IO uint8_t *)Address = Data; - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); } - /* Return the Write Status */ return status; } +#endif /** - * @brief Writes a half word at a specified address in data memory. - * @note To correctly run this function, the HAL_FLASHEx_DATAEEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASHEx_DATAEEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + * @brief Write Option Byte of the desired pages of the Flash. + * @param Sector: specifies the sectors to be write protected. + * @param Sector2: specifies the sectors to be write protected only stm32l07xxx and stm32l08xxx devices + * @param NewState: new state of the specified FLASH Pages Wite protection. + * This parameter can be: ENABLE or DISABLE. + * @retval HAL_StatusTypeDef */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data) +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) +static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t Sector2, uint32_t NewState) +#else +static HAL_StatusTypeDef FLASH_OB_ProtectedSectorsConfig(uint32_t Sector, uint32_t NewState) +#endif { - HAL_StatusTypeDef status = HAL_ERROR; + HAL_StatusTypeDef status = HAL_OK; + uint32_t WRP_Data = 0; + uint32_t OB_WRP = Sector; /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); - - /* If the previous operation is completed, proceed to write the new data */ - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in data memory. - * @note To correctly run this function, the HAL_FLASHEx_DATAEEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASHEx_DATAEEPROM_Lock() to the data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @note This function assumes that the is data word is already erased. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - if(status == HAL_OK) - { - /* Clear the FTDW bit */ - FLASH->PECR &= (uint32_t)(~((uint32_t)FLASH_PECR_FTDW)); - - /* If the previous operation is completed, proceed to program the new data */ - *(__IO uint32_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - } - /* Return the Write Status */ - return status; -} - -/** - * @brief Write a Byte at a specified address in data memory without erase. - * @note To correctly run this function, the HAL_FLASHEx_DATAEEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASHEx_DATAEEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; + assert_param(IS_FUNCTIONAL_STATE(NewState)); - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); if(status == HAL_OK) { - /* Set the FTDW bit */ - FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW; - - *(__IO uint8_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - } - /* Return the Write Status */ - return status; -} + /* Clean the error context */ + ProcFlash.ErrorCode = HAL_FLASH_ERROR_NONE; -/** - * @brief Writes a half word at a specified address in data memory without erase. - * @note To correctly run this function, the HAL_FLASHEx_DATAEEPROM_Unlock function - * must be called before. - * Call the HAL_FLASHEx_DATAEEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); + if (OB_WRP & 0x0000FFFF) + { + if (NewState != OB_WRPSTATE_DISABLE) + { + WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP01)); + OB->WRP01 = (uint32_t)(~(WRP_Data) << 16) | (WRP_Data); + } + else + { + WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP01)); + OB->WRP01 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data); + } + } +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + if (OB_WRP & 0xFFFF0000) + { + if (NewState != OB_WRPSTATE_DISABLE) + { + WRP_Data = (uint16_t)((((OB_WRP & WRP_MASK_HIGH) >> 16 | OB->WRP23))); + OB->WRP23 = (uint32_t)(~(WRP_Data) << 16) | (WRP_Data); + } + else + { + WRP_Data = (uint16_t)((((~OB_WRP & WRP_MASK_HIGH) >> 16 & OB->WRP23))); + OB->WRP23 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data); + } + } - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - if(status == HAL_OK) - { - /* Set the FTDW bit */ - FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW; - - *(__IO uint16_t *)Address = Data; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); + OB_WRP = Sector2; + if (OB_WRP & 0x0000FFFF) + { + if (NewState != OB_WRPSTATE_DISABLE) + { + WRP_Data = (uint16_t)(((OB_WRP & WRP_MASK_LOW) | OB->WRP45)); + OB->WRP45 =(uint32_t)(~(WRP_Data) << 16) | (WRP_Data); + } + else + { + WRP_Data = (uint16_t)(~OB_WRP & (WRP_MASK_LOW & OB->WRP45)); + OB->WRP45 = (uint32_t)((~WRP_Data) << 16) | (WRP_Data); + } + } +#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ } - /* Return the Write Status */ - return status; -} - -/** - * @brief Programs a word at a specified address in data memory without erase. - * @note To correctly run this function, the HAL_FLASHEx_DATAEEPROM_Unlock() function - * must be called before. - * Call the HAL_FLASHEx_DATAEEPROM_Lock() to he data EEPROM access - * and Flash program erase control register access(recommended to protect - * the DATA_EEPROM against possible unwanted operation). - * @param Address: specifies the address to be written. - * @param Data: specifies the data to be written. - * @retval FLASH Status: The returned value can be: - * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. - */ -static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Check the parameters */ - assert_param(IS_FLASH_DATA_ADDRESS(Address)); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - - if(status == HAL_OK) - { - /* Set the FTDW bit */ - FLASH->PECR |= (uint32_t)FLASH_PECR_FTDW; - - *(__IO uint32_t *)Address = Data; + status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE)); - } - /* Return the Write Status */ - return status; + /* Return the write protection operation Status */ + return status; } - -/** - * @} - */ -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - /** * @} */ +#endif /* HAL_FLASH_MODULE_ENABLED */ - /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.h index 01f1051ea0f..794f4ddd4ca 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 - * @brief Header file of FLASH HAL Extension module. + * @version V1.2.0 + * @date 06-February-2015 + * @brief Header file of FLash HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,243 +50,637 @@ * @{ */ -/** @addtogroup FLASHEx +/** @defgroup FLASHEx FLASHEx * @{ */ -/* Exported types ------------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Types FLASH Exported Types + * @{ + */ + /** - * @brief FLASH Advanced Option Bytes Program structure definition + * @brief FLASH Option Bytes PROGRAM structure definition */ typedef struct { - uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . - This parameter can be a value of @ref FLASHEx_Option_Type */ + uint32_t OptionType; /*!< OptionType: Option byte to be configured. + This parameter can be a value of @ref FLASHEx_Option_Type */ - uint32_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. - This parameter can be a value of @ref FLASHEx_PCROP_State */ + uint32_t WRPState; /*!< WRPState: Write protection activation or deactivation. + This parameter can be a value of @ref FLASHEx_WRP_State */ + + uint32_t WRPSector; /*!< WRPSector: This bitfield specifies the sector (s) which are write protected. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection */ + +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + uint32_t WRPSector2; /*!< WRPSector2 : This bitfield specifies the sector(s) upper Sector31 which are write protected. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */ +#endif - uint16_t Pages; /*!< Sectors: specifies the sector(s) set for PCROP - This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + uint8_t RDPLevel; /*!< RDPLevel: Set the read protection level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */ + + uint8_t BORLevel; /*!< BORLevel: Set the BOR Level. + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */ + + uint8_t USERConfig; /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, + @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY */ + + uint8_t BOOTBit1Config; /*!< BOOT1Config: Together with input pad Boot0, this bit selects the boot source, flash, ram or system memory + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOTBit1 */ + +} FLASH_OBProgramInitTypeDef; + +/** + * @brief FLASH Advanced Option Bytes Program structure definition + */ +typedef struct +{ + uint32_t OptionType; /*!< OptionType: Option byte to be configured for extension . + This parameter can be a value of @ref FLASHEx_OptionAdv_Type */ + + uint8_t PCROPState; /*!< PCROPState: PCROP activation or deactivation. + This parameter can be a value of @ref FLASHEx_PCROP_State */ - uint16_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config - This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT1 */ + uint32_t PCROPSector; /*!< PCROPSector : This bitfield specifies the sector(s) which are read/write protected. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection */ + +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) + uint32_t PCROPSector2; /*!< PCROPSector : This bitfield specifies the sector(s) upper Sector31 which are read/write protected. + This parameter can be a combination of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */ + + uint8_t BootConfig; /*!< BootConfig: specifies Option bytes for boot config. + This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT_BANK */ +#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ } FLASH_AdvOBProgramInitTypeDef; -/* Exported constants --------------------------------------------------------*/ +/** + * @} + */ -/** @defgroup FLASHEx_Exported_Constants +/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants * @{ */ -/** @defgroup FLASHEx_PCROP_State + +/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase * @{ - */ -#define PCROPSTATE_DISABLE ((uint32_t)0x00) /*!ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) + * @} + */ +/** @defgroup FLASHEx_Option_Bytes_ReadWrite_Protection2 FLASHEx Option Bytes Read Write Protection + * @{ + */ +#define OB_PCROP2_Pages1024to1055 ((uint32_t)0x00000001) /* PC Read/Write protection of Sector32 */ +#define OB_PCROP2_Pages1056to1087 ((uint32_t)0x00000002) /* PC Read/Write protection of Sector33 */ +#define OB_PCROP2_Pages1088to1119 ((uint32_t)0x00000004) /* PC Read/Write protection of Sector34 */ +#define OB_PCROP2_Pages1120to1151 ((uint32_t)0x00000008) /* PC Read/Write protection of Sector35 */ +#define OB_PCROP2_Pages1152to1183 ((uint32_t)0x00000010) /* PC Read/Write protection of Sector36 */ +#define OB_PCROP2_Pages1184to1215 ((uint32_t)0x00000020) /* PC Read/Write protection of Sector37 */ +#define OB_PCROP2_Pages1216to1247 ((uint32_t)0x00000040) /* PC Read/Write protection of Sector38 */ +#define OB_PCROP2_Pages1248to1279 ((uint32_t)0x00000080) /* PC Read/Write protection of Sector39 */ +#define OB_PCROP2_Pages1280to1311 ((uint32_t)0x00000100) /* PC Read/Write protection of Sector40 */ +#define OB_PCROP2_Pages1312to1343 ((uint32_t)0x00000200) /* PC Read/Write protection of Sector41 */ +#define OB_PCROP2_Pages1344to1375 ((uint32_t)0x00000400) /* PC Read/Write protection of Sector42 */ +#define OB_PCROP2_Pages1376to1407 ((uint32_t)0x00000800) /* PC Read/Write protection of Sector43 */ +#define OB_PCROP2_Pages1408to1439 ((uint32_t)0x00001000) /* PC Read/Write protection of Sector44 */ +#define OB_PCROP2_Pages1440to1471 ((uint32_t)0x00002000) /* PC Read/Write protection of Sector45 */ +#define OB_PCROP2_Pages1472to1503 ((uint32_t)0x00004000) /* PC Read/Write protection of Sector46 */ +#define OB_PCROP2_Pages1504to1535 ((uint32_t)0x00008000) /* PC Read/Write protection of Sector47 */ +#define OB_PCROP2_AllPages ((uint32_t)0x0000FFFF) /*!< PC Read/Write protection of all Sectors PCROP2 */ /** - * @brief Enable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTEN) + * @} + */ +#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ + +/** @defgroup FLASHEx_Option_Bytes_BOOTBit1 + * @{ + */ +#define OB_BOOT_BIT1_RESET (uint8_t)(0x00) /*!< BOOT Bit 1 Reset */ +#define OB_BOOT_BIT1_SET (uint8_t)(0x01) /*!< BOOT Bit 1 Set */ +/** + * @} + */ +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) +/** @defgroup FLASHEx_Option_Bytes_BOOT_BANK FLASHEx Option Bytes BOOT BANK + * @{ + */ +#define OB_BOOT_BANK1 ((uint8_t)0x00) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position + and this parameter is selected the device will boot from Bank 2 + or Bank 1, depending on the activation of the bank */ +#define OB_BOOT_BANK2 (uint8_t)(0x01) /*!< At startup, if boot pin 0 and BOOT1 bit are set in boot from user Flash position + and this parameter is selected the device will boot from Bank1(Default) */ /** - * @brief Disable the FLASH prefetch buffer. - * @retval none - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTEN)) + * @} + */ +#endif /* if STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ + +/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data + * @{ + */ +#define FLASH_TYPEPROGRAMDATA_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address.*/ +#define FLASH_TYPEPROGRAMDATA_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address.*/ +#define FLASH_TYPEPROGRAMDATA_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address.*/ +/* Aliases for compatibility with the V1.0.0 package */ +#define FLASH_TYPEPROGRAM_BYTE FLASH_TYPEPROGRAMDATA_BYTE +#define FLASH_TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD /** - * @brief Enable the FLASH Buffer cache. - * @retval none + * @} + */ + +/** @defgroup FLASHEx_Address FLASHEx Address + * @{ + */ +#define FLASH_NBPAGES_MAX (FLASH_SIZE / FLASH_PAGE_SIZE) +/** + * @} */ -#define __HAL_FLASH_BUFFER_CACHE_ENABLE() (FLASH->ACR &= (~FLASH_ACR_DISAB_BUF)) + +/** + * @} + */ +/** @defgroup FLASHEx_Exported_Macros macros to control FLASH features + * @brief + * @{ + */ + /** - * @brief Disable the FLASH Buffer cache. + * @brief Set the FLASH Latency. + * @param __LATENCY__: FLASH Latency + * This parameter can be one of the following values: + * @arg FLASH_LATENCY_0: FLASH Zero Latency cycle + * @arg FLASH_LATENCY_1: FLASH One Latency cycle * @retval none */ -#define __HAL_FLASH_BUFFER_CACHE_DISABLE() (FLASH->ACR |= FLASH_ACR_DISAB_BUF) +#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__)) /** - * @brief Enable the FLASH preread buffer + * @brief Enable/Disable the FLASH prefetch buffer. * @retval none */ -#define __HAL_FLASH_PREREAD_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRE_READ) +#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) +#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN) /** - * @brief Disable the FLASH preread buffer + * @brief Enable/Disable the FLASH Buffer cache. * @retval none */ -#define __HAL_FLASH_PREREAD_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRE_READ)) +#define __HAL_FLASH_BUFFER_CACHE_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF) +#define __HAL_FLASH_BUFFER_CACHE_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_DISAB_BUF) /** - * @brief Enable the FLASH power down during Sleep mode + * @brief Enable/Disable the FLASH preread buffer. * @retval none */ -#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) +#define __HAL_FLASH_PREREAD_BUFFER_ENABLE() SET_BIT((FLASH->ACR), FLASH_ACR_PRE_READ) +#define __HAL_FLASH_PREREAD_BUFFER_DISABLE() CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRE_READ) /** - * @brief Disable the FLASH power down during Sleep mode + * @brief Enable/Disable the FLASH power down during Sleep mode. * @retval none */ -#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) +#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) +#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) /** - * @brief Macro to enable or disable the Flash Run power down mode. + * @brief Enable the Flash Run power down mode. * @note Writing this bit to 0 this bit, automatically the keys are * loss and a new unlock sequence is necessary to re-write it to 1. */ - #define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ FLASH->PDKEYR = FLASH_PDKEY2; \ - SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ + SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ } while (0) +/** + * @brief Disable the Flash Run power down mode. + * @note Writing this bit to 0 this bit, automatically the keys are + * loss and a new unlock sequence is necessary to re-write it to 1. + */ #define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1; \ FLASH->PDKEYR = FLASH_PDKEY2; \ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \ + CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD); \ } while (0) + /** * @} */ -/* Exported functions --------------------------------------------------------*/ +/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported functions + * @{ + */ -/* I/O operation functions *****************************************************/ -/* Peripheral Control functions ************************************************/ +/** @defgroup FLASHEx_Exported_Functions_Group1 FLASH Memory Erasing functions + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions + * @{ + */ +HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); +void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); +void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); +HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); +HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); +/** + * @} + */ + +/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions + * @{ + */ HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void); HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void); HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t Address); HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data); +void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void); +void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void); + +/** + * @} + */ -/* Aliases for legacy HAL versions compatibility */ -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program +/** + * @} + */ + +/** @addtogroup FLASH_Private_Macros FLASH Private Macros + * @{ + */ +#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES)) -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); +#define IS_OPTIONBYTE(__VALUE__) (((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | \ + OPTIONBYTE_USER | OPTIONBYTE_BOR | OPTIONBYTE_BOOT_BIT1))) -HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void); -HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void); +#define IS_WRPSTATE(__VALUE__) (((__VALUE__) == OB_WRPSTATE_DISABLE) || \ + ((__VALUE__) == OB_WRPSTATE_ENABLE)) -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); +#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000)) -HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); -void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); +#define IS_OB_RDP(__LEVEL__) (((__LEVEL__) == OB_RDP_LEVEL0)||\ + ((__LEVEL__) == OB_RDP_LEVEL1)||\ + ((__LEVEL__) == OB_RDP_LEVEL2)) + +#define IS_OB_BOR_LEVEL(__LEVEL__) ( ((__LEVEL__) == OB_BOR_OFF) || \ + ((__LEVEL__) == OB_BOR_LEVEL1) || \ + ((__LEVEL__) == OB_BOR_LEVEL2) || \ + ((__LEVEL__) == OB_BOR_LEVEL3) || \ + ((__LEVEL__) == OB_BOR_LEVEL4) || \ + ((__LEVEL__) == OB_BOR_LEVEL5)) + +#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW)) +#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST)) +#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST)) +#define IS_PCROPSTATE(VALUE)(((VALUE) == OB_PCROP_STATE_DISABLE) || \ + ((VALUE) == OB_PCROP_STATE_ENABLE)) + +#define IS_OB_PCROP(__PAGE__) (((__PAGE__) != 0x0000000)) + +#define IS_OB_BOOT1(__BOOT_BIT1__) (((__BOOT_BIT1__) == OB_BOOT_BIT1_RESET) || ((__BOOT_BIT1__) == OB_BOOT_BIT1_SET)) + +#define IS_TYPEPROGRAMDATA(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAMDATA_BYTE) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_HALFWORD) || \ + ((__VALUE__) == FLASH_TYPEPROGRAMDATA_WORD)) + +#define IS_NBPAGES(__PAGES__) (((__PAGES__) >= 1) && ((__PAGES__) <= FLASH_NBPAGES_MAX)) + +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define IS_OBEX(__VALUE__)(((__VALUE__) <= (OPTIONBYTE_PCROP | OPTIONBYTE_BOOTCONFIG))) +#define IS_OB_BOOT_BANK(__BANK__) (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1)) +#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END)) +#define IS_FLASH_DATA_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK1_END)) +#define IS_FLASH_DATA_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BANK2_BASE) && ((__ADDRESS__) <= DATA_EEPROM_BANK2_END)) +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) +#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + (FLASH_SIZE >> 1)))) +#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) +#else +#define IS_OBEX(VALUE)((VALUE) == OPTIONBYTE_PCROP) +#define IS_FLASH_DATA_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= DATA_EEPROM_BASE) && ((__ADDRESS__) <= DATA_EEPROM_END)) +#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) < (FLASH_BASE + FLASH_SIZE))) +#endif /** * @} */ /** * @} - */ + */ + +/** + * @} + */ #ifdef __cplusplus } @@ -295,3 +689,4 @@ void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit); #endif /* __STM32L0xx_HAL_FLASH_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.c index dfa493556e6..214c95bfb19 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.c @@ -2,13 +2,11 @@ ****************************************************************************** * @file stm32l0xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief FLASH RAMFUNC driver. * This file provides a Flash firmware functions which should be * executed from internal SRAM - * + FLASH HalfPage Programming - * + FLASH Power Down in Run mode * * @verbatim @@ -29,12 +27,12 @@ -------------------- [..] RAM functions are defined using a specific toolchain attribute "__attribute__((section(".RamFunc")))". - - @endverbatim + +@endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -63,32 +61,27 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" -/** @addtogroup STM32L0XX_HAL_Driver + +#ifdef HAL_FLASH_MODULE_ENABLED +/** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup FLASHRamfunc Driver +/** @addtogroup FLASHRamfunc * @brief FLASH functions executed from RAM * @{ */ -#ifdef HAL_FLASH_MODULE_ENABLED - /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static __RAM_FUNC FLASH_Program_HalfPage(uint32_t Address, uint32_t *Data); +static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout); +static __RAM_FUNC FLASHRAM_SetErrorCode(void); -/* Private functions ---------------------------------------------------------*/ -/** @defgroup FLASHRamfunc_Private_Functions - * @{ - */ - -/** @defgroup FLASHRamfunc_Group1 Peripheral features functions - * @brief Data transfers functions +/** @addtogroup FLASHRamfunc_Exported_Functions * @verbatim =============================================================================== @@ -102,66 +95,33 @@ static __RAM_FUNC FLASH_Program_HalfPage(uint32_t Address, uint32_t *Data); * @{ */ -/** - * @brief Program a half page word at a specified address, - * @note This function should be executed from RAM - * @param Address: specifies the address to be programmed, - * the address should be half page aligned. - * @param *Data: specifies the buffer of data to be programmed, - * the size of the buffer is 16 words. - * - * @retval HAL_StatusTypeDef HAL Status - */ -__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t *Data) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t timeout = 0xFFFFFFFF; - /*Program word (32-bit) at a specified address.*/ - FLASH_Program_HalfPage(Address, Data); - - /* Wait for a FLASH operation to complete or a TIMEOUT to occur */ - while(((FLASH->SR & FLASH_FLAG_BSY) != 0x00) && (timeout != 0x00)) - { - timeout--; - } - - if(timeout == 0x00 ) - { - return HAL_TIMEOUT; - } - - /* Reset PROG bit */ - FLASH->PECR &= ~FLASH_PECR_PROG; - FLASH->PECR &= ~FLASH_PECR_FPRG; - return status; -} +/** @addtogroup FLASHRamfunc_Exported_Functions_Group1 + * @{ + */ /** - * @brief Enable the Power down in Run Mode - * @note This function should be called and executed from SRAM memory + * @brief Enable the power down mode during RUN mode. + * @note This function can be used only when the user code is running from Internal SRAM. * @param None * @retval None */ -__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) +__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void) { /* Enable the Power Down in Run mode*/ __HAL_FLASH_POWER_DOWN_ENABLE(); - return HAL_OK; - } /** - * @brief Disable the Power down in Run Mode - * @note This function should be called and executed from SRAM memory + * @brief Disable the power down mode during RUN mode. + * @note This function can be used only when the user code is running from Internal SRAM. * @param None * @retval None */ -__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) +__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) { /* Disable the Power Down in Run mode*/ __HAL_FLASH_POWER_DOWN_DISABLE(); - return HAL_OK; } @@ -169,39 +129,332 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void) * @} */ +/** @addtogroup FLASHRamfunc_Exported_Functions_Group2 + * +@verbatim +@endverbatim + * @{ + */ + +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) /** - * @brief Program a half page in program memory. - * @param Address: The Half page address in program memory to be written. - * @param Data: - * @retval None + * @brief Erases a specified 2 pages in program memory in parallel. + * @note This function can be used only for STM32L07xxx/STM32L08xxx devices. + * To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + * @param Page_Address1: The page address in program memory to be erased in + * the first Bank (BANK1). This parameter should be between FLASH_BASE + * and FLASH_BANK1_END. + * @param Page_Address2: The page address in program memory to be erased in + * the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE + * and FLASH_BANK2_END. + * @note A Page is erased in the Program memory only if the address to load + * is the start address of a page (multiple of 128 bytes). + * @retval HAL Status: The returned value can be: + * HAL_ERROR, HAL_OK or HAL_TIMEOUT. */ -static __RAM_FUNC FLASH_Program_HalfPage(uint32_t Address, uint32_t *Data) +__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2) { HAL_StatusTypeDef status = HAL_OK; - uint32_t i =0; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - /* Set PROG bit */ - FLASH->PECR |= FLASH_PECR_PROG; + if(status == HAL_OK) + { + /* Proceed to erase the page */ + SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + SET_BIT(FLASH->PECR, FLASH_PECR_ERASE); + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); - /* Set FPRG bit */ - FLASH->PECR |= FLASH_PECR_FPRG; + /* Write 00000000h to the first word of the first program page to erase */ + *(__IO uint32_t *)Page_Address1 = 0x00000000; + /* Write 00000000h to the first word of the second program page to erase */ + *(__IO uint32_t *)Page_Address2 = 0x00000000; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - *(__IO uint32_t*)Address = Data[0]; + /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + } + /* Return the erasesStatus */ + return status; +} + +/** + * @brief Programs 2 half pages in program memory in parallel. The half page size is 16 Words. + * @note This function can be used only for STM32L07xxx/STM32L08xxx devices. + * @param Address1: specifies the first address to be written in the first bank + * (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE). + * @param pBuffer1: pointer to the buffer containing the data to be written + * to the first half page in the first bank. + * @param Address2: specifies the second address to be written in the second bank + * (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE). + * @param pBuffer2: pointer to the buffer containing the data to be written + * to the second half page in the second bank. + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation). + * @note Half page write is possible only from SRAM. + * @note A half page is written to the program memory only if the first + * address to load is the start address of a half page (multiple of 64 + * bytes) and the 15 remaining words to load are in the same half page. + * @note During the Program memory half page write all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @note If a PGAERR is set during a Program memory half page write, the + * complete write operation is aborted. Software should then reset the + * FPRG and PROG/DATA bits and restart the write operation from the + * beginning. + * @retval HAL Status: The returned value can be: + * HAL_ERROR, HAL_OK or HAL_TIMEOUT. + */ +__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2) +{ + uint32_t count; + HAL_StatusTypeDef status; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - for(i = 1; i <= 15; i++) - { - *(__IO uint32_t*)(Address + 4) = Data[i]; - } + if(status == HAL_OK) + { + /* Proceed to program the new half page */ + SET_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Write one half page, + Address1 doesn't need to be increased */ + count = 0; + + /* Disable all IRQs */ + __disable_irq(); + + while(count < 16) + { + *(__IO uint32_t*) Address1 = *pBuffer1; + pBuffer1++; + count++; + } + + /* Write the second half page, + Address2 doesn't need to be increased */ + count = 0; + while(count < 16) + { + *(__IO uint32_t*) Address2 = *pBuffer2; + pBuffer2++; + count++; + } + + /* Enable IRQs */ + __enable_irq(); + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + } + /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PARALLBANK); + } + /* Return the Write Status */ + return status; +} +#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ + +/** + * @brief Program a half page in program memory. + * @param Address: specifies the address to be written. + * @param pBuffer: pointer to the buffer containing the data to be written to + * the half page. + * @note To correctly run this function, the HAL_FLASH_Unlock() function + * must be called before. + * Call the HAL_FLASH_Lock() to disable the flash memory access + * (recommended to protect the FLASH memory against possible unwanted operation) + * @note Half page write is possible only from SRAM. + * @note A half page is written to the program memory only if the first + * address to load is the start address of a half page (multiple of 64 + * bytes) and the 15 remaining words to load are in the same half page. + * @note During the Program memory half page write all read operations are + * forbidden (this includes DMA read operations and debugger read + * operations such as breakpoints, periodic updates, etc.). + * @note If a PGAERR is set during a Program memory half page write, the + * complete write operation is aborted. Software should then reset the + * FPRG and PROG/DATA bits and restart the write operation from the + * beginning. + * @retval HAL Status: The returned value can be: + * HAL_ERROR, HAL_OK or HAL_TIMEOUT. + */ +__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t *pBuffer) +{ + uint32_t count; + HAL_StatusTypeDef status; + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + if(status == HAL_OK) + { + /* Proceed to program the new half page */ + SET_BIT(FLASH->PECR, FLASH_PECR_FPRG); + SET_BIT(FLASH->PECR, FLASH_PECR_PROG); + + + count = 0; + /* Write one half page, + Address doesn't need to be increased */ + + /* Disable all IRQs */ + __disable_irq(); + + while(count < 16) + { + *(__IO uint32_t*) Address = *pBuffer; + pBuffer++; + count++; + } + + /* Enable IRQs */ + __enable_irq(); + + /* Wait for last operation to be completed */ + status = FLASHRAM_WaitForLastOperation(FLASH_TIMEOUT_VALUE); + + /* If the write operation is completed, disable the PROG and FPRG bits */ + CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG); + CLEAR_BIT(FLASH->PECR, FLASH_PECR_FPRG); + } + /* Return the write status */ return status; } +/** + * @brief Get the specific FLASH errors flag. + * @param error pointer is the error value. It can be a mixed of : + * @arg HAL_FLASH_ERROR_RD: FLASH Read Protection error flag (PCROP) + * @arg HAL_FLASH_ERROR_SIZE: FLASH Programming Parallelism error flag + * @arg HAL_FLASH_ERROR_PGA: FLASH Programming Alignment error flag + * @arg HAL_FLASH_ERROR_WRP: FLASH Write protected error flag + * @arg HAL_FLASH_ERROR_OPTV: FLASH Option valid error flag + * @arg HAL_FLASH_ERROR_FWWERR: FLASH Write or Errase operation aborted + * @arg HAL_FLASH_ERROR_NOTZERO: FLASH Write operation is done in a not-erased region + */ +__RAM_FUNC HAL_FLASHRAM_GetError(uint32_t * error) +{ + *error = ProcFlash.ErrorCode; + return HAL_OK; +} + + + /** * @} - */ -#endif /* HAL_FLASH_MODULE_ENABLED */ + */ + +/** + * @} + */ +/** @defgroup FLASHRamfunc_Private_Functions FLASH RAM Private Functions + * @{ + */ +/** + * @brief Set the specific FLASH error flag. + * @param None + * @retval None + */ +static __RAM_FUNC FLASHRAM_SetErrorCode(void) +{ + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)) + { + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_WRP; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)) + { + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_PGA; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)) + { + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_SIZE; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)) + { + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_OPTV; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)) + { + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_RD; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR)) + { + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_FWWERR; + } + if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR)) + { + ProcFlash.ErrorCode |= HAL_FLASH_ERROR_NOTZERO; + } + + /* Errors are now stored, clear errors flags */ + __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_WRPERR | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | + FLASH_FLAG_OPTVERR | FLASH_FLAG_RDERR | FLASH_FLAG_FWWERR | + FLASH_FLAG_NOTZEROERR); + return HAL_OK; +} + + +/** + * @brief Wait for a FLASH operation to complete. + * @param Timeout: maximum flash operationtimeout + * @retval HAL status + */ +static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout) +{ + /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset. + Even if the FLASH operation fails, the BUSY flag will be reset and an error + flag will be set */ + + while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00)) + { + Timeout--; + } + + if(Timeout == 0x00 ) + { + return HAL_TIMEOUT; + } + + if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_FWWERR) != RESET) || + (__HAL_FLASH_GET_FLAG(FLASH_FLAG_NOTZEROERR) != RESET) ) + { + /*Save the error code*/ + FLASHRAM_SetErrorCode(); + return HAL_ERROR; + } + /* If there is an error flag set */ + return HAL_OK; +} + /** * @} */ @@ -210,7 +463,10 @@ static __RAM_FUNC FLASH_Program_HalfPage(uint32_t Address, uint32_t *Data) * @} */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +/** + * @} + */ +#endif /* HAL_FLASH_MODULE_ENABLED */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.h index 398f181c658..44d858545bc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_flash_ramfunc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup FLASHRamfunc +/** @defgroup FLASHRamfunc FLASHRamfunc * @{ */ @@ -59,18 +59,41 @@ /* Exported functions --------------------------------------------------------*/ -/* I/O operation functions *****************************************************/ -/* Peripheral Control functions ************************************************/ +/** @defgroup FLASHRamfunc_Exported_Functions FLASH RAM Exported Functions + * @{ + */ -__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t *Data); +/* + * @brief FLASH memory functions that should be executed from internal SRAM. + * These functions are defined inside the "stm32l0xx_hal_flash_ramfunc.c" + * file. + */ + +/** @defgroup FLASHRamfunc_Exported_Functions_Group1 FLASH RAM Peripheral features functions + * @{ + */ +__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer); __RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void); __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); +__RAM_FUNC HAL_FLASHRAM_GetError(uint32_t * error); +/** + * @} + */ -/* Aliases for legacy compatibility */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) +/** @defgroup FLASHRamfunc_Exported_Functions_Group2 FLASH RAM Programming and erasing operation functions + * @{ + */ +__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2); +__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2); +/** + * @} + */ +#endif /* STM32L071xx || STM32L072xx || STM32L073xx || STM32L081xx || STM32L082xx || STM32L083xx */ +/** + * @} + */ /** * @} @@ -87,3 +110,4 @@ __RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void); #endif /* __STM32L0xx_FLASH_RAMFUNC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.c index c52999d2854..c2703424a4b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_gpio.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -41,7 +41,7 @@ lines, the port must be configured in input mode. All available GPIO pins are connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - (+) The external interrupt/event controller consists of up to 23 edge detectors + (+) The external interrupt/event controller consists of up to 28 edge detectors (16 lines are connected to GPIO) for generating event/interrupt requests (each input line can be independently configured to select the type (interrupt or event) and the corresponding trigger event (rising or falling or both). Each line can @@ -50,11 +50,8 @@ ##### How to use this driver ##### ============================================================================== [..] - (#) Enable the GPIO IOPORT clock using the following function: __GPIOx_CLK_ENABLE(). - - (#) In case of external interrupt/event mode selection, enable the SYSCFG clock - using the following function __SYSCFG_CLK_ENABLE(). - + (#) Enable the GPIO IOPORT clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). + (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef @@ -73,11 +70,18 @@ mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using HAL_NVIC_EnableIRQ(). + (#) HAL_GPIO_DeInit allows to set register values to their reset value. This function + is also to be used when unconfiguring pin which was used as an external interrupt + or in event mode. That is the only way to reset the corresponding bit in + EXTI & SYSCFG registers. + (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). (#) To set/reset the level of a pin configured in output mode use HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - + + (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). + (#) During and just after reset, the alternate functions are not active and the GPIO pins are configured in input floating mode (except JTAG pins). @@ -94,7 +98,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -128,7 +132,7 @@ * @{ */ -/** @defgroup GPIO +/** @addtogroup GPIO * @brief GPIO HAL module driver * @{ */ @@ -138,12 +142,6 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ -#define GET_GPIO_SOURCE(__GPIOx__) \ -(((uint32_t)(__GPIOx__) == ((uint32_t)GPIOA_BASE))? 0 :\ - ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0400)))? (uint32_t)1 :\ - ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0800)))? (uint32_t)2 :\ - ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x0C00)))? (uint32_t)3 :\ - ((uint32_t)(__GPIOx__) == ((uint32_t)(GPIOA_BASE + 0x1C00)))? (uint32_t)4 : (uint32_t)5) #define GPIO_MODE ((uint32_t)0x00000003) @@ -159,12 +157,12 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Functions +/** @addtogroup GPIO_Exported_Functions * @{ */ -/** @defgroup GPIO_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup GPIO_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions * @verbatim =============================================================================== @@ -177,23 +175,24 @@ /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..D and H) to select the GPIO peripheral for STM32L0XX family devices. + * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices. + * Note that GPIOE is not available on all devices. * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. + * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { - uint32_t position; + uint32_t position = 0x00; uint32_t ioposition = 0x00; uint32_t iocurrent = 0x00; uint32_t temp = 0x00; - + /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); - assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); - + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,(GPIO_Init->Pin))); + /* Configure the port pins */ for(position = 0; position < GPIO_NUMBER; position++) { @@ -210,6 +209,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { /* Check the Alternate function parameter */ assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + /* Check if the Alternate function is compliant with the GPIO in use */ + assert_param(IS_GPIO_AF_AVAILABLE(GPIOx,(GPIO_Init->Alternate))); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3]; temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; @@ -253,11 +254,11 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) { /* Enable SYSCFG Clock */ - __SYSCFG_CLK_ENABLE(); + __HAL_RCC_SYSCFG_CLK_ENABLE(); temp = SYSCFG->EXTICR[position >> 2]; - temp &= ~((uint32_t)0x0F) << (4 * (position & 0x03)); - temp |= ((uint32_t)(GET_GPIO_SOURCE(GPIOx)) << (4 * (position & 0x03))); + temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); + temp |= ((uint32_t)(GPIO_GET_INDEX(GPIOx)) << (4 * (position & 0x03))); SYSCFG->EXTICR[position >> 2] = temp; /* Clear EXTI line configuration */ @@ -300,18 +301,23 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..D and H) to select the GPIO peripheral for STM32L0XX family devices. + * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0XX family devices. + * Note that GPIOE is not available on all devices. * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15) except for GPIOD(2) and GPIOH(1:0). + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * All port bits are not necessarily available on all GPIOs. * @retval None */ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) { - uint32_t position; + uint32_t position = 0x00; uint32_t ioposition = 0x00; uint32_t iocurrent = 0x00; uint32_t tmp = 0x00; - + + /* Check the parameters */ + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); + /* Configure the port pins */ for(position = 0; position < GPIO_NUMBER; position++) { @@ -359,7 +365,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * @} */ -/** @defgroup GPIO_Group2 IO operation functions +/** @addtogroup GPIO_Exported_Functions_Group2 * @brief GPIO Read and Write * @verbatim @@ -373,9 +379,11 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) /** * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..D and H) to select the GPIO peripheral for STM32L0xx family devices. + * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices. + * Note that GPIOE is not available on all devices. * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15) except for GPIOD(2) and GPIOH(1:0). + * This parameter can be GPIO_PIN_x where x can be (0..15). + * All port bits are not necessarily available on all GPIOs. * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -383,7 +391,7 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) GPIO_PinState bitstatus; /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); if((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET) { @@ -403,19 +411,21 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..D and H) to select the GPIO peripheral for STM32L0xx family devices. + * @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices. + * Note that GPIOE is not available on all devices. * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15) except for GPIOD(2) and GPIOH(1:0). + * This parameter can be one of GPIO_PIN_x where x can be (0..15). + * All port bits are not necessarily available on all GPIOs. * @param PinState: specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * GPIO_PIN_RESET: to clear the port pin - * GPIO_PIN_SET: to set the port pin + * This parameter can be one of the GPIO_PinState enum values: + * GPIO_PIN_RESET: to clear the port pin + * GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) @@ -430,14 +440,16 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin /** * @brief Toggles the specified GPIO pins. - * @param GPIOx: Where x can be (A..D and H) to select the GPIO peripheral for STM32L0xx family devices. + * @param GPIOx: Where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family devices. + * Note that GPIOE is not available on all devices. + * All port bits are not necessarily available on all GPIOs. * @param GPIO_Pin: Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) { /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); GPIOx->ODR ^= GPIO_Pin; } @@ -448,9 +460,11 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. -* @param GPIOx: where x can be (A..D and H) to select the GPIO peripheral for STM32F3 family +* @param GPIOx: where x can be (A..E and H) to select the GPIO peripheral for STM32L0xx family. +* Note that GPIOE is not available on all devices. * @param GPIO_Pin: specifies the port bit to be locked. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). +* All port bits are not necessarily available on all GPIOs. * @retval None */ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -458,7 +472,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) __IO uint32_t tmp = GPIO_LCKR_LCKK; /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_AVAILABLE(GPIOx,GPIO_Pin)); /* Apply lock key write sequence */ tmp |= GPIO_Pin; @@ -482,7 +496,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) } /** * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin: Specifies the pins connected to the EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -497,7 +511,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) /** * @brief EXTI line detection callbacks. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin: Specifies the pins connected to the EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) @@ -526,3 +540,4 @@ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.h index 8f398e8072b..137191228a2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_gpio.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,19 +50,27 @@ * @{ */ -/** @addtogroup GPIO +/** @defgroup GPIO GPIO * @{ */ - +/******************************************************************************/ /* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ + +/** @defgroup GPIO_Exported_Types GPIO Exported Types + * @{ + */ +/** @defgroup GPIO_Init_Configuration GPIO init configuration structure + * @{ + */ /** * @brief GPIO Init structure definition */ typedef struct { uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_pins_define */ + This parameter can be a combination of @ref GPIO_pins_define */ uint32_t Mode; /*!< Specifies the operating mode for the selected pins. This parameter can be a value of @ref GPIO_mode_define */ @@ -76,7 +84,13 @@ typedef struct uint32_t Alternate; /*!< Peripheral to be connected to the selected pins This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ }GPIO_InitTypeDef; +/** + * @} + */ +/** @defgroup GPIO_SetReset_Definition GPIO set reset definition + * @{ + */ /** * @brief GPIO Bit SET and Bit RESET enumeration */ @@ -85,15 +99,24 @@ typedef enum GPIO_PIN_RESET = 0, GPIO_PIN_SET }GPIO_PinState; -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) +/** + * @} + */ +/** + * @} + */ + +#define IS_GPIO_PIN_ACTION(__ACTION__) (((__ACTION__) == GPIO_PIN_RESET) || ((__ACTION__) == GPIO_PIN_SET)) +/******************************************************************************/ /* Exported constants --------------------------------------------------------*/ +/******************************************************************************/ -/** @defgroup GPIO_Exported_Constants +/** @defgroup GPIO_Exported_Constants GPIO Exported Constants * @{ */ -/** @defgroup GPIO_pins_define +/** @defgroup GPIO_pins_define Pin definition * @{ */ #define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */ @@ -113,14 +136,14 @@ typedef enum #define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */ #define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */ #define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */ - -#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ -#define IS_GPIO_PIN(PIN) (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00) /** * @} */ -/** @defgroup GPIO_mode_define +#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */ +#define IS_GPIO_PIN(__PIN__) (((__PIN__) & GPIO_PIN_MASK ) != (uint32_t)0x00) + +/** @defgroup GPIO_mode_define Mode definition * @brief GPIO Configuration Mode * Elements values convention: 0xX0yz00YZ * - X : GPIO mode or EXTI Mode @@ -145,24 +168,26 @@ typedef enum #define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */ #define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */ #define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */ - -#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) ||\ - ((MODE) == GPIO_MODE_OUTPUT_PP) ||\ - ((MODE) == GPIO_MODE_OUTPUT_OD) ||\ - ((MODE) == GPIO_MODE_AF_PP) ||\ - ((MODE) == GPIO_MODE_AF_OD) ||\ - ((MODE) == GPIO_MODE_IT_RISING) ||\ - ((MODE) == GPIO_MODE_IT_FALLING) ||\ - ((MODE) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING) ||\ - ((MODE) == GPIO_MODE_EVT_FALLING) ||\ - ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((MODE) == GPIO_MODE_ANALOG)) /** * @} */ -/** @defgroup GPIO_speed_define + +#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ + ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ + ((__MODE__) == GPIO_MODE_AF_PP) ||\ + ((__MODE__) == GPIO_MODE_AF_OD) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING) ||\ + ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ + ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ + ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ + ((__MODE__) == GPIO_MODE_ANALOG)) + + +/** @defgroup GPIO_speed_define Speed definition * @brief GPIO Output Maximum frequency * @{ */ @@ -171,13 +196,15 @@ typedef enum #define GPIO_SPEED_FAST ((uint32_t)0x00000002) /*!< Fast speed */ #define GPIO_SPEED_HIGH ((uint32_t)0x00000003) /*!< High speed */ -#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_LOW) || ((SPEED) == GPIO_SPEED_MEDIUM) || \ - ((SPEED) == GPIO_SPEED_FAST) || ((SPEED) == GPIO_SPEED_HIGH)) /** * @} */ - /** @defgroup GPIO_pull_define +#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_LOW) || ((__SPEED__) == GPIO_SPEED_MEDIUM) || \ + ((__SPEED__) == GPIO_SPEED_FAST) || ((__SPEED__) == GPIO_SPEED_HIGH)) + + + /** @defgroup GPIO_pull_define Pull definition * @brief GPIO Pull-Up or Pull-Down Activation * @{ */ @@ -185,18 +212,24 @@ typedef enum #define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */ #define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */ -#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \ - ((PULL) == GPIO_PULLDOWN)) /** * @} */ + +#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) || ((__PULL__) == GPIO_PULLUP) || \ + ((__PULL__) == GPIO_PULLDOWN)) + /** * @} */ - +/******************************************************************************/ /* Exported macro ------------------------------------------------------------*/ - +/******************************************************************************/ +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Macro GPIO Exported Macro + * @{ + */ /** * @brief Checks whether the specified EXTI line flag is set or not. * @param __EXTI_LINE__: specifies the EXTI line flag to check. @@ -237,23 +270,48 @@ typedef enum */ #define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +/** + * @} + */ /* Include GPIO HAL Extension module */ #include "stm32l0xx_hal_gpio_ex.h" -/* Exported functions --------------------------------------------------------*/ +/******************************************************************************/ +/* Exported functions --------------------------------------------------------*/ +/******************************************************************************/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_Exported_Functions GPIO Exported Functions + * @{ + */ /* Initialization and de-initialization functions *******************************/ +/** @defgroup GPIO_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); +/** + * @} + */ /* IO operation functions *******************************************************/ +/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions + * @{ + */ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); +/** + * @} + */ +/** + * @} + */ /** * @} */ @@ -269,3 +327,4 @@ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin); #endif /* __STM32L0xx_HAL_GPIO_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio_ex.h index 725380ec4ca..95ad19587b1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_gpio_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,34 +50,974 @@ * @{ */ -/** @addtogroup GPIOEx +/** @defgroup GPIOEx GPIOx * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants +/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants * @{ */ -/** @defgroup GPIOEx_Alternate_function_selection - * @{ + +/*----------------------------------------------------------------------------*/ +/*------------------------- STM32L083xx/STM32L073xx---------------------------*/ +/*----------------------------------------------------------------------------*/ + +#if defined (STM32L083xx) || defined (STM32L073xx) + +/* The table below gives an overview of the different alternate functions per port. + * For more details refer yourself to the product data sheet. + * + */ + +/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | + *______________________________________________________________________________ + * PA0 | | |TIM2_C1 |TSC |USART2 |TIM2_TR |USART4 |COMP1 | + * PA1 |EVENTOUT|LCD |TIM2_C2 |TSC |USART2 |TIM21_TR|USART4 | | + * PA2 |TIM21_C1|LCD |TIM2_C3 |TSC |USART2 | |LPUART1 |COMP2 | + * PA3 |TIM21_C2|LCD |TIM2_C4 |TSC |USART2 | |LPUART1 | | + * PA4 |SPI1 | | |TSC |USART2 |TIM22_TR| | | + * PA5 |SPI1 | |TIM2_TR |TSC | |TIM2_C1 | | | + * PA6 |SPI1 |LCD |TIM3_C1 |TSC |LPUART1 |TIM22_C1|EVENTOUT|COMP1 | + * PA7 |SPI1 |LCD |TIM3_C2 |TSC | |TIM22_C2|EVENTOUT|COMP2 | + * PA8 |MCO |LCD |USB |EVENTOUT|USART1 | | |I2C3 | + * PA9 |MCO |LCD | |TSC |USART1 | |I2C1 |I2C3 | + * PA10| |LCD | |TSC |USART1 | |I2C1 | | + * PA11|SPI1 | |EVENTOUT|TSC |USART1 | |I2C2 |COMP1 | + * PA12|SPI1 | |EVENTOUT|TSC |USART1 | |I2C2 |COMP2 | + * PA13|SWDIO | |USB | | | |LPUART1 | | + * PA14|SWCLK | | | |USART2 | |LPUART1 | | + * PA15|SPI1 |LCD |TIM2_TR |EVENTOUT|USART2 |TIM2_C1 |USART4 | | + *______________________________________________________________________________ + * PB0 |EVENTOUT|LCD |TIM3_C3 |TSC | | | | | + * PB1 | |LCD |TIM3_C4 |TSC |LPUART1 | | | | + * PB2 | | |LPTIM1_O|TSC | | | |I2C3 | + * PB3 |SPI1 |LCD |TIM2_C2 |TSC |EVENTOUT|USART1 |USART5 | | + * PB4 |SPI1 |LCD |TIM3_C1 |TSC |TIM22_C1|USART1 |USART5 |I2C3 | + * PB5 |SPI1 |LCD |LPTIM1_I|I2C1 |TIM3_C2 |USART1 |USART5 | | + * | | | | |TIM22_C2| | | | + * PB6 |USART1 |I2C1 |LPTIM1_T|TSC | | | | | + * PB7 |USART1 |I2C1 |LPTIM1_I|TSC | | |USART4 | | + * PB8 | |LCD | |TSC |I2C1 | | | | + * PB9 | |LCD |EVENTOUT| |I2C1 |SPI2 | | | + * PB10| |LCD |TIM2_C3 |TSC |LPUART1 |SPI2 |I2C2 |LPUART1 | + * PB11|EVENTOUT|LCD |TIM2_C4 |TSC |LPUART1 | |I2C2 |LPUART1 | + * PB12|SPI2 |LCD |LPUART1 |TSC | |I2C2 |EVENTOUT| | + * PB13|SPI2 |LCD |MCO |TSC |LPUART1 |I2C2 |TIM21_C1| | + * PB14|SPI2 |LCD |RTC |TSC |LPUART1 |I2C2 |TIM21_C2| | + * PB15|SPI2 |LCD |RTC | | | | | | + *______________________________________________________________________________ + * PC0 |LPTIM1_I|LCD |EVENTOUT|TSC | | |LPUART1 |I2C3 | + * PC1 |LPTIM1_O|LCD |EVENTOUT|TSC | | |LPUART1 |I2C3 | + * PC2 |LPTIM1_I|LCD |SPI2 |TSC | | | | | + * PC3 |LPTIM1_T|LCD |SPI2 |TSC | | | | | + * PC4 |EVENTOUT|LCD |LPUART1 | | | | | | + * PC5 | |LCD |LPUART1 |TSC | | | | | + * PC6 |TIM22_C1|LCD |TIM3_C1 |TSC | | | | | + * PC7 |TIM22_C2|LCD |TIM3_C2 |TSC | | | | | + * PC8 |TIM22_TR|LCD |TIM3_C3 |TSC | | | | | + * PC9 |TIM21_TR|LCD |USB |TSC | | | |I2C3 | + * | | |TIM3_C4 | | | | | | + * PC10|LPUART1 |LCD | | | | |USART4 | | + * PC11|LPUART1 |LCD | | | | |USART4 | | + * PC12| |LCD |USART5 | | | |USART4 | | + * PC13| | | | | | | | | + * PC14| | | | | | | | | + * PC15| | | | | | | | | + *______________________________________________________________________________ + * PD0 |TIM21_C1|SPI2 | | | | | | | + * PD1 | |SPI2 | | | | | | | + * PD2 |LPUART1 |LCD |TIM3_TR | | | |USART5 | | + * PD3 |USART2 |LCD |SPI2 | | | | | | + * PD4 |USART2 |SPI2 | | | | | | | + * PD5 |USART2 | | | | | | | | + * PD6 |USART2 | | | | | | | | + * PD7 |USART2 |TIM21_C2| | | | | | | + * PD8 |LPUART1 |LCD | | | | | | | + * PD9 |LPUART1 |LCD | | | | | | | + * PD10| |LCD | | | | | | | + * PD11|LPUART1 |LCD | | | | | | | + * PD12|LPUART1 |LCD | | | | | | | + * PD13| |LCD | | | | | | | + * PD14| |LCD | | | | | | | + * PD15|USB |LCD | | | | | | | + *______________________________________________________________________________ + * PE0 | |LCD |EVENTOUT| | | | | | + * PE1 | |LCD |EVENTOUT| | | | | | + * PE2 | |LCD |TIM3_TR | | | | | | + * PE3 |TIM22_C1|LCD |TIM3_C1 | | | | | | + * PE4 |TIM22_C2| |TIM3_C2 | | | | | | + * PE5 |TIM21_C1| |TIM3_C3 | | | | | | + * PE6 |TIM21_C2| |TIM3_C4 | | | | | | + * PE7 | |LCD | | | | |USART5 | | + * PE8 | |LCD | | | | |USART4 | | + * PE9 |TIM2_C1 |LCD |TIM2_TR | | | |USART4 | | + * PE10|TIM2_C2 |LCD | | | | |USART5 | | + * PE11|TIM2_C3 | | | | | |USART5 | | + * PE12|TIM2_C4 | |SPI1 | | | | | | + * PE13| |LCD |SPI1 | | | | | | + * PE14| |LCD |SPI1 | | | | | | + * PE15| |LCD |SPI1 | | | | | | + *______________________________________________________________________________ + * PH0 |USB | | | | | | | | + * PH1 | | | | | | | | | + * PH9 | | | | | | | | | + * PH10| | | | | | | | | + * + */ + +/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0 + * @{ + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1 + * @{ + */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ +#define GPIO_AF1_LCD ((uint8_t)0x01) /* LCD Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2 + * @{ + */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */ +#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3 + * @{ + */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4 + * @{ + */ +#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping*/ +#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5 + * @{ + */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_USART1 ((uint8_t)0x05) /* USART1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6 + * @{ + */ + +#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7 + * @{ + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */ +#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */ +/** + * @} */ - -/*------------------------- STM32L053xx/STM32L063xx---------------------------*/ + +/** + * @} + */ + +/** + * @brief IS_GPIO_AF macro definition + */ +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF0_TIM21) || ((__AF__) == GPIO_AF1_SPI2) || \ + ((__AF__) == GPIO_AF0_MCO) || ((__AF__) == GPIO_AF1_TIM21) || \ + ((__AF__) == GPIO_AF0_SWDIO) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF0_SWCLK) || ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF2_USB) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_EVENTOUT) || \ + ((__AF__) == GPIO_AF0_LPTIM1) || ((__AF__) == GPIO_AF2_LPTIM1) || \ + ((__AF__) == GPIO_AF0_TIM2) || ((__AF__) == GPIO_AF2_LPUART1) || \ + ((__AF__) == GPIO_AF0_LPUART1) || ((__AF__) == GPIO_AF2_MCO) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF2_RTC) || \ + ((__AF__) == GPIO_AF0_USB) || ((__AF__) == GPIO_AF2_SPI2) || \ + ((__AF__) == GPIO_AF0_TIM2) || ((__AF__) == GPIO_AF2_USART5) || \ + ((__AF__) == GPIO_AF3_TSC) || ((__AF__) == GPIO_AF2_SPI1) || \ + ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF3_I2C1) || ((__AF__) == GPIO_AF4_LPUART1) || \ + ((__AF__) == GPIO_AF5_TIM21) || ((__AF__) == GPIO_AF4_EVENTOUT) || \ + ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF5_USART1) || ((__AF__) == GPIO_AF4_TIM22) || \ + ((__AF__) == GPIO_AF5_TIM22) || ((__AF__) == GPIO_AF4_TIM3) || \ + ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_COMP2) || ((__AF__) == GPIO_AF6_LPUART1) || \ + ((__AF__) == GPIO_AF7_COMP1) || ((__AF__) == GPIO_AF6_I2C1) || \ + ((__AF__) == GPIO_AF7_I2C3) || ((__AF__) == GPIO_AF6_EVENTOUT) || \ + ((__AF__) == GPIO_AF7_LPUART1) || ((__AF__) == GPIO_AF6_I2C2) || \ + ((__AF__) == GPIO_AF6_USART5) || ((__AF__) == GPIO_AF6_TIM21)) + + +#define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \ + ((((__INSTANCE__) == GPIOA) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_I2C3))) || \ + (((__INSTANCE__) == GPIOB) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF4_TIM3) || \ + ((__AF__) == GPIO_AF5_I2C2) || \ + ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_LPUART1))) || \ + (((__INSTANCE__) == GPIOC) && (((__AF__) == GPIO_AF0_LPTIM1) || \ + ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_I2C3))) || \ + (((__INSTANCE__) == GPIOD) && (((__AF__) == GPIO_AF0_LPUART1) || \ + ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF6_USART5))) || \ + (((__INSTANCE__) == GPIOE) && (((__AF__) == GPIO_AF0_TIM22) || \ + ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF6_USART4))) || \ + (((__INSTANCE__) == GPIOH) && (((__AF__) == GPIO_AF0_USB)))) + +#endif /* (STM32L083xx) || (STM32L073xx) */ + +/*----------------------------------------------------------------------------*/ +/*------------------------- STM32L082xx and STM32L072xx-----------------------*/ +/*----------------------------------------------------------------------------*/ +#if defined (STM32L082xx) || defined (STM32L072xx) + +/* The table below gives an overview of the different alternate functions per port. + * For more details refer yourself to the product data sheet. + */ + + +/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | + *______________________________________________________________________________ + * PA0 | | |TIM2_C1 |TSC |USART2 |TIM2_TR |USART4 |COMP1 | + * PA1 |EVENTOUT| |TIM2_C2 |TSC |USART2 |TIM21_TR|USART4 | | + * PA2 |TIM21_C1| |TIM2_C3 |TSC |USART2 | |LPUART1 |COMP2 | + * PA3 |TIM21_C2| |TIM2_C4 |TSC |USART2 | |LPUART1 | | + * PA4 |SPI1 | | |TSC |USART2 |TIM22_TR| | | + * PA5 |SPI1 | |TIM2_TR |TSC | |TIM2_C1 | | | + * PA6 |SPI1 | |TIM3_C1 |TSC |LPUART1 |TIM22_C1|EVENTOUT|COMP1 | + * PA7 |SPI1 | |TIM3_C2 |TSC | |TIM22_C2|EVENTOUT|COMP2 | + * PA8 |MCO | |USB |EVENTOUT|USART1 | | |I2C3 | + * PA9 |MCO | | |TSC |USART1 | |I2C1 |I2C3 | + * PA10| | | |TSC |USART1 | |I2C1 | | + * PA11|SPI1 | |EVENTOUT|TSC |USART1 | |I2C2 |COMP1 | + * PA12|SPI1 | |EVENTOUT|TSC |USART1 | |I2C2 |COMP2 | + * PA13|SWDIO | |USB | | | |LPUART1 | | + * PA14|SWCLK | | | |USART2 | |LPUART1 | | + * PA15|SPI1 | |TIM2_TR |EVENTOUT|USART2 |TIM2_C1 |USART4 | | + *______________________________________________________________________________ + * PB0 |EVENTOUT| |TIM3_C3 |TSC | | | | | + * PB1 | | |TIM3_C4 |TSC |LPUART1 | | | | + * PB2 | | |LPTIM1_O|TSC | | | |I2C3 | + * PB3 |SPI1 | |TIM2_C2 |TSC |EVENTOUT|USART1 |USART5 | | + * PB4 |SPI1 | |TIM3_C1 |TSC |TIM22_C1|USART1 |USART5 |I2C3 | + * PB5 |SPI1 | |LPTIM1_I|I2C1 |TIM3_C2 |USART1 |USART5 | | + * | | | | |TIM22_C2| | | | + * PB6 |USART1 |I2C1 |LPTIM1_T|TSC | | | | | + * PB7 |USART1 |I2C1 |LPTIM1_I|TSC | | |USART4 | | + * PB8 | | | |TSC |I2C1 | | | | + * PB9 | | |EVENTOUT| |I2C1 |SPI2 | | | + * PB10| | |TIM2_C3 |TSC |LPUART1 |SPI2 |I2C2 |LPUART1 | + * PB11|EVENTOUT| |TIM2_C4 |TSC |LPUART1 | |I2C2 |LPUART1 | + * PB12|SPI2 | |LPUART1 |TSC | |I2C2 |EVENTOUT| | + * PB13|SPI2 | |MCO |TSC |LPUART1 |I2C2 |TIM21_C1| | + * PB14|SPI2 | |RTC |TSC |LPUART1 |I2C2 |TIM21_C2| | + * PB15|SPI2 | |RTC | | | | | | + *______________________________________________________________________________ + * PC0 |LPTIM1_I| |EVENTOUT|TSC | | |LPUART1 |I2C3 | + * PC1 |LPTIM1_O| |EVENTOUT|TSC | | |LPUART1 |I2C3 | + * PC2 |LPTIM1_I| |SPI2 |TSC | | | | | + * PC3 |LPTIM1_T| |SPI2 |TSC | | | | | + * PC4 |EVENTOUT| |LPUART1 | | | | | | + * PC5 | | |LPUART1 |TSC | | | | | + * PC6 |TIM22_C1| |TIM3_C1 |TSC | | | | | + * PC7 |TIM22_C2| |TIM3_C2 |TSC | | | | | + * PC8 |TIM22_TR| |TIM3_C3 |TSC | | | | | + * PC9 |TIM21_TR| |USB |TSC | | | |I2C3 | + * | | |TIM3_C4 | | | | | | + * PC10|LPUART1 | | | | | |USART4 | | + * PC11|LPUART1 | | | | | |USART4 | | + * PC12| | |USART5 | | | |USART4 | | + * PC13| | | | | | | | | + * PC14| | | | | | | | | + * PC15| | | | | | | | | + *______________________________________________________________________________ + * PD0 |TIM21_C1|SPI2 | | | | | | | + * PD1 | |SPI2 | | | | | | | + * PD2 |LPUART1 | |TIM3_TR | | | |USART5 | | + * PD3 |USART2 | |SPI2 | | | | | | + * PD4 |USART2 |SPI2 | | | | | | | + * PD5 |USART2 | | | | | | | | + * PD6 |USART2 | | | | | | | | + * PD7 |USART2 |TIM21_C2| | | | | | | + * PD8 |LPUART1 | | | | | | | | + * PD9 |LPUART1 | | | | | | | | + * PD10| | | | | | | | | + * PD11|LPUART1 | | | | | | | | + * PD12|LPUART1 | | | | | | | | + * PD13| | | | | | | | | + * PD14| | | | | | | | | + * PD15|USB | | | | | | | | + *______________________________________________________________________________ + * PE0 | | |EVENTOUT| | | | | | + * PE1 | | |EVENTOUT| | | | | | + * PE2 | | |TIM3_TR | | | | | | + * PE3 |TIM22_C1| |TIM3_C1 | | | | | | + * PE4 |TIM22_C2| |TIM3_C2 | | | | | | + * PE5 |TIM21_C1| |TIM3_C3 | | | | | | + * PE6 |TIM21_C2| |TIM3_C4 | | | | | | + * PE7 | | | | | | |USART5 | | + * PE8 | | | | | | |USART4 | | + * PE9 |TIM2_C1 | |TIM2_TR | | | |USART4 | | + * PE10|TIM2_C2 | | | | | |USART5 | | + * PE11|TIM2_C3 | | | | | |USART5 | | + * PE12|TIM2_C4 | |SPI1 | | | | | | + * PE13| | |SPI1 | | | | | | + * PE14| | |SPI1 | | | | | | + * PE15| | |SPI1 | | | | | | + *______________________________________________________________________________ + * PH0 |USB | | | | | | | | + * PH1 | | | | | | | | | + * PH9 | | | | | | | | | + * PH10| | | | | | | | | + * + */ + +/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1 + * @{ + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0 + * @{ + */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2 + * @{ + */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */ +#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3 + * @{ + */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4 + * @{ + */ +#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5 + * @{ + */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_USART1 ((uint8_t)0x05) /* USART1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +/** + * @} + */ + + /** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6 + * @{ + */ +#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ +/** + * @} + */ + + /** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7 + * @{ + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */ +#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */ +/** + * @} + */ + +/** + * @} + */ + +/** + * IS_GPIO_AF macro definition + */ +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF6_TIM21) || \ + ((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF0_TIM21) || ((__AF__) == GPIO_AF1_SPI2) || \ + ((__AF__) == GPIO_AF0_MCO) || ((__AF__) == GPIO_AF1_TIM21) || \ + ((__AF__) == GPIO_AF0_SWDIO) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF0_SWCLK) || ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF2_USB) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_EVENTOUT) || \ + ((__AF__) == GPIO_AF0_LPTIM1) || ((__AF__) == GPIO_AF2_LPTIM1) || \ + ((__AF__) == GPIO_AF0_TIM2) || ((__AF__) == GPIO_AF2_LPUART1) || \ + ((__AF__) == GPIO_AF0_LPUART1) || ((__AF__) == GPIO_AF2_MCO) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF2_RTC) || \ + ((__AF__) == GPIO_AF0_USB) || ((__AF__) == GPIO_AF2_SPI2) || \ + ((__AF__) == GPIO_AF0_TIM2) || ((__AF__) == GPIO_AF2_USART5) || \ + ((__AF__) == GPIO_AF3_TSC) || ((__AF__) == GPIO_AF2_SPI1) || \ + ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF3_I2C1) || ((__AF__) == GPIO_AF4_LPUART1) || \ + ((__AF__) == GPIO_AF5_TIM21) || ((__AF__) == GPIO_AF4_EVENTOUT) || \ + ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF5_USART1) || ((__AF__) == GPIO_AF4_TIM22) || \ + ((__AF__) == GPIO_AF5_TIM22) || ((__AF__) == GPIO_AF4_TIM3) || \ + ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_COMP2) || ((__AF__) == GPIO_AF6_LPUART1) || \ + ((__AF__) == GPIO_AF7_COMP1) || ((__AF__) == GPIO_AF6_I2C1) || \ + ((__AF__) == GPIO_AF7_I2C3) || ((__AF__) == GPIO_AF6_EVENTOUT) || \ + ((__AF__) == GPIO_AF7_LPUART1) || ((__AF__) == GPIO_AF6_I2C2) || \ + ((__AF__) == GPIO_AF6_USART5)) + +#define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \ + ((((__INSTANCE__) == GPIOA) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_EVENTOUT) || \ + ((__AF__) == GPIO_AF7_COMP1))) || \ + (((__INSTANCE__) == GPIOB) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF4_TIM22) || \ + ((__AF__) == GPIO_AF5_I2C2) || \ + ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_LPUART1))) || \ + (((__INSTANCE__) == GPIOC) && (((__AF__) == GPIO_AF0_TIM22) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_I2C3))) || \ + (((__INSTANCE__) == GPIOD) && (((__AF__) == GPIO_AF0_TIM21) || \ + ((__AF__) == GPIO_AF1_TIM21) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF6_USART5))) || \ + (((__INSTANCE__) == GPIOE) && (((__AF__) == GPIO_AF0_TIM22) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF6_USART4))) || \ + (((__INSTANCE__) == GPIOH) && (((__AF__) == GPIO_AF0_USB)))) + + +#endif /* (STM32L082xx) || (STM32L072xx) */ + + +/*----------------------------------------------------------------------------*/ +/*------------------------- STM32L081xx and STM32L071xx-----------------------*/ +/*----------------------------------------------------------------------------*/ +#if defined (STM32L081xx) || defined (STM32L071xx) + +/* The table below gives an overview of the different alternate functions per port. + * For more details refer yourself to the product data sheet. + * + */ + + +/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | + *______________________________________________________________________________ + * PA0 | | |TIM2_C1 | |USART2 |TIM2_TR |USART4 |COMP1 | + * PA1 |EVENTOUT| |TIM2_C2 | |USART2 |TIM21_TR|USART4 | | + * PA2 |TIM21_C1| |TIM2_C3 | |USART2 | |LPUART1 |COMP2 | + * PA3 |TIM21_C2| |TIM2_C4 | |USART2 | |LPUART1 | | + * PA4 |SPI1 | | | |USART2 |TIM22_TR| | | + * PA5 |SPI1 | |TIM2_TR | | |TIM2_C1 | | | + * PA6 |SPI1 | |TIM3_C1 | |LPUART1 |TIM22_C1|EVENTOUT|COMP1 | + * PA7 |SPI1 | |TIM3_C2 | | |TIM22_C2|EVENTOUT|COMP2 | + * PA8 |MCO | | |EVENTOUT|USART1 | | |I2C3 | + * PA9 |MCO | | | |USART1 | |I2C1 |I2C3 | + * PA10| | | | |USART1 | |I2C1 | | + * PA11|SPI1 | |EVENTOUT| |USART1 | |I2C2 |COMP1 | + * PA12|SPI1 | |EVENTOUT| |USART1 | |I2C2 |COMP2 | + * PA13|SWDIO | | | | | |LPUART1 | | + * PA14|SWCLK | | | |USART2 | |LPUART1 | | + * PA15|SPI1 | |TIM2_TR |EVENTOUT|USART2 |TIM2_C1 |USART4 | | + *______________________________________________________________________________ + * PB0 |EVENTOUT| |TIM3_C3 | | | | | | + * PB1 | | |TIM3_C4 | |LPUART1 | | | | + * PB2 | | |LPTIM1_O| | | | |I2C3 | + * PB3 |SPI1 | |TIM2_C2 | |EVENTOUT|USART1 |USART5 | | + * PB4 |SPI1 | |TIM3_C1 | |TIM22_C1|USART1 |USART5 |I2C3 | + * PB5 |SPI1 | |LPTIM1_I|I2C1 |TIM3_C2 |USART1 |USART5 | | + * | | | | |TIM22_C2| | | | + * PB6 |USART1 |I2C1 |LPTIM1_T| | | | | | + * PB7 |USART1 |I2C1 |LPTIM1_I| | | |USART4 | | + * PB8 | | | | |I2C1 | | | | + * PB9 | | |EVENTOUT| |I2C1 |SPI2 | | | + * PB10| | |TIM2_C3 | |LPUART1 |SPI2 |I2C2 |LPUART1 | + * PB11|EVENTOUT| |TIM2_C4 | |LPUART1 | |I2C2 |LPUART1 | + * PB12|SPI2 | |LPUART1 | | |I2C2 |EVENTOUT| | + * PB13|SPI2 | |MCO | |LPUART1 |I2C2 |TIM21_C1| | + * PB14|SPI2 | |RTC | |LPUART1 |I2C2 |TIM21_C2| | + * PB15|SPI2 | |RTC | | | | | | + *______________________________________________________________________________ + * PC0 |LPTIM1_I| |EVENTOUT| | | |LPUART1 |I2C3 | + * PC1 |LPTIM1_O| |EVENTOUT| | | |LPUART1 |I2C3 | + * PC2 |LPTIM1_I| |SPI2 | | | | | | + * PC3 |LPTIM1_T| |SPI2 | | | | | | + * PC4 |EVENTOUT| |LPUART1 | | | | | | + * PC5 | | |LPUART1 | | | | | | + * PC6 |TIM22_C1| |TIM3_C1 | | | | | | + * PC7 |TIM22_C2| |TIM3_C2 | | | | | | + * PC8 |TIM22_TR| |TIM3_C3 | | | | | | + * PC9 |TIM21_TR| | | | | | |I2C3 | + * | | |TIM3_C4 | | | | | | + * PC10|LPUART1 | | | | | |USART4 | | + * PC11|LPUART1 | | | | | |USART4 | | + * PC12| | |USART5 | | | |USART4 | | + * PC13| | | | | | | | | + * PC14| | | | | | | | | + * PC15| | | | | | | | | + *______________________________________________________________________________ + * PD0 |TIM21_C1|SPI2 | | | | | | | + * PD1 | |SPI2 | | | | | | | + * PD2 |LPUART1 | |TIM3_TR | | | |USART5 | | + * PD3 |USART2 | |SPI2 | | | | | | + * PD4 |USART2 |SPI2 | | | | | | | + * PD5 |USART2 | | | | | | | | + * PD6 |USART2 | | | | | | | | + * PD7 |USART2 |TIM21_C2| | | | | | | + * PD8 |LPUART1 | | | | | | | | + * PD9 |LPUART1 | | | | | | | | + * PD10| | | | | | | | | + * PD11|LPUART1 | | | | | | | | + * PD12|LPUART1 | | | | | | | | + * PD13| | | | | | | | | + * PD14| | | | | | | | | + * PD15| | | | | | | | | + *______________________________________________________________________________ + * PE0 | | |EVENTOUT| | | | | | + * PE1 | | |EVENTOUT| | | | | | + * PE2 | | |TIM3_TR | | | | | | + * PE3 |TIM22_C1| |TIM3_C1 | | | | | | + * PE4 |TIM22_C2| |TIM3_C2 | | | | | | + * PE5 |TIM21_C1| |TIM3_C3 | | | | | | + * PE6 |TIM21_C2| |TIM3_C4 | | | | | | + * PE7 | | | | | | |USART5 | | + * PE8 | | | | | | |USART4 | | + * PE9 |TIM2_C1 | |TIM2_TR | | | |USART4 | | + * PE10|TIM2_C2 | | | | | |USART5 | | + * PE11|TIM2_C3 | | | | | |USART5 | | + * PE12|TIM2_C4 | |SPI1 | | | | | | + * PE13| | |SPI1 | | | | | | + * PE14| | |SPI1 | | | | | | + * PE15| | |SPI1 | | | | | | + *______________________________________________________________________________ + * PH0 | | | | | | | | | + * PH1 | | | | | | | | | + * PH9 | | | | | | | | | + * PH10| | | | | | | | | + * + */ + +/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0 + * @{ + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1 + * @{ + */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2 + * @{ + */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_MCO ((uint8_t)0x02) /* MCO Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_USART5 ((uint8_t)0x02) /* USART5 Alternate Function mapping */ +#define GPIO_AF2_SPI1 ((uint8_t)0x02) /* SPI1 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3 + * @{ + */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4 + * @{ + */ +#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_TIM3 ((uint8_t)0x04) /* TIM3 Alternate Function mapping */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5 + * @{ + */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +#define GPIO_AF5_USART1 ((uint8_t)0x05) /* USART1 Alternate Function mapping */ +#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ +#define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6 + * @{ + */ +#define GPIO_AF6_USART4 ((uint8_t)0x06) /* USART4 Alternate Function mapping */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF6_I2C1 ((uint8_t)0x06) /* I2C1 Alternate Function mapping */ +#define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ +#define GPIO_AF6_USART5 ((uint8_t)0x06) /* USART5 Alternate Function mapping */ +#define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ +/** + * @} + */ + + /** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7 + * @{ + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +#define GPIO_AF7_I2C3 ((uint8_t)0x07) /* I2C3 Alternate Function mapping */ +#define GPIO_AF7_LPUART1 ((uint8_t)0x07) /* LPUART1 Alternate Function mapping */ +/** + * @} + */ + +/** + * @} + */ + + /** + * IS_GPIO_AF macro definition + */ +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF7_LPUART1) || \ + ((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF0_TIM21) || ((__AF__) == GPIO_AF1_SPI2) || \ + ((__AF__) == GPIO_AF0_MCO) || ((__AF__) == GPIO_AF1_TIM21) || \ + ((__AF__) == GPIO_AF0_SWDIO) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF0_SWCLK) || ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF6_TIM21) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_EVENTOUT) || \ + ((__AF__) == GPIO_AF0_LPTIM1) || ((__AF__) == GPIO_AF2_LPTIM1) || \ + ((__AF__) == GPIO_AF0_TIM2) || ((__AF__) == GPIO_AF2_LPUART1) || \ + ((__AF__) == GPIO_AF0_LPUART1) || ((__AF__) == GPIO_AF2_MCO) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF2_RTC) || \ + ((__AF__) == GPIO_AF2_SPI2) || ((__AF__) == GPIO_AF6_USART5) || \ + ((__AF__) == GPIO_AF0_TIM2) || ((__AF__) == GPIO_AF2_USART5) || \ + ((__AF__) == GPIO_AF2_SPI1) || ((__AF__) == GPIO_AF6_I2C2) || \ + ((__AF__) == GPIO_AF3_EVENTOUT) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF3_I2C1) || ((__AF__) == GPIO_AF4_LPUART1) || \ + ((__AF__) == GPIO_AF5_TIM21) || ((__AF__) == GPIO_AF4_EVENTOUT) || \ + ((__AF__) == GPIO_AF5_TIM2) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF5_USART1) || ((__AF__) == GPIO_AF4_TIM22) || \ + ((__AF__) == GPIO_AF5_TIM22) || ((__AF__) == GPIO_AF4_TIM3) || \ + ((__AF__) == GPIO_AF5_SPI2) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_COMP2) || ((__AF__) == GPIO_AF6_LPUART1) || \ + ((__AF__) == GPIO_AF7_COMP1) || ((__AF__) == GPIO_AF6_I2C1) || \ + ((__AF__) == GPIO_AF7_I2C3) || ((__AF__) == GPIO_AF6_EVENTOUT)) + + +#define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \ + ((((__INSTANCE__) == GPIOA) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_EVENTOUT) || \ + ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_COMP1))) || \ + (((__INSTANCE__) == GPIOB) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_I2C1) || \ + ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF5_I2C2) || \ + ((__AF__) == GPIO_AF6_USART4) || \ + ((__AF__) == GPIO_AF7_LPUART1))) || \ + (((__INSTANCE__) == GPIOC) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF6_LPUART1) || \ + ((__AF__) == GPIO_AF7_I2C3))) || \ + (((__INSTANCE__) == GPIOD) && (((__AF__) == GPIO_AF0_LPUART1) || \ + ((__AF__) == GPIO_AF1_SPI2) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF6_USART5))) || \ + (((__INSTANCE__) == GPIOE) && (((__AF__) == GPIO_AF0_TIM22) || \ + ((__AF__) == GPIO_AF2_TIM3) || \ + ((__AF__) == GPIO_AF6_USART4)))) + + +#endif /* (STM32L081xx) || (STM32L071xx) */ + +/*----------------------------------------------------------------------------*/ +/*------------------------- STM32L053xx/STM32L063xx---------------------------*/ +/*----------------------------------------------------------------------------*/ #if defined (STM32L053xx) || defined (STM32L063xx) -/** - * @brief AF 0 selection - */ + +/* The table below gives an overview of the different alternate functions per port. + * For more details refer yourself to the product data sheet. + * + */ +/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | + *______________________________________________________________________________ + * PA0 | | |TIM2_C1 |TSC |USART2 |TIM2_TR | |COMP1 | + * PA1 |EVENTOUT|LCD |TIM2_C2 |TSC |USART2 |TIM21_TR| | | + * PA2 |TIM21_C1|LCD |TIM2_C3 |TSC |USART2 | | |COMP2 | + * PA3 |TIM21_C2|LCD |TIM2_C4 |TSC |USART2 | | | | + * PA4 |SPI1 | | |TSC |USART2 |TIM22_TR| | | + * PA5 |SPI1 | |TIM2_TR |TSC | |TIM2_C1 | | | + * PA6 |SPI1 |LCD | |TSC |LPUART |TIM22_C1|EVENTOUT|COMP1 | + * PA7 |SPI1 |LCD | |TSC | |TIM22_C2|EVENTOUT|COMP2 | + * PA8 |MCO |LCD |USB |EVENTOUT|USART1 | | | | + * PA9 |MCO |LCD | |TSC |USART1 | | | | + * PA10| |LCD | |TSC |USART1 | | | | + * PA11|SPI1 | |EVENTOUT|TSC |USART1 | | |COMP1 | + * PA12|SPI1 | |EVENTOUT|TSC |USART1 | | |COMP2 | + * PA13|SWDIO | |USB | | | | | | + * PA14|SWCLK | | | |USART2 | | | | + * PA15|SPI1 |LCD |TIM2_TR |EVENTOUT|USART2 |TIM2_C1 | | | + *______________________________________________________________________________ + * PB0 |EVENTOUT|LCD | |TSC | | | | | + * PB1 | |LCD | |TSC |LPUART1 | | | | + * PB2 | | |LPTIM1_O|TSC | | | | | + * PB3 |SPI1 |LCD |TIM2_C2 |TSC |EVENTOUT| | | | + * PB4 |SPI1 |LCD |EVENTOUT|TSC |TIM22_C1| | | | + * PB5 |SPI1 |LCD |LPTIM1_I|I2C1 |TIM22_C2| | | | + * PB6 |USART1 |I2C1 |LPTIM1_T|TSC | | | | | + * PB7 |USART1 |I2C1 |LPTIM1_I|TSC | | | | | + * PB8 | |LCD | |TSC |I2C1 | | | | + * PB9 | |LCD |EVENTOUT| |I2C1 |SPI2 | | | + * PB10| |LCD |TIM2_C3 |TSC |LPUART1 |SPI2 |I2C2 | | + * PB11|EVENTOUT|LCD |TIM2_C4 |TSC |LPUART1 | |I2C2 | | + * PB12|SPI2 |LCD |LPUART1 |TSC | |I2C2 |EVENTOUT| | + * PB13|SPI2 |LCD | |TSC |LPUART1 |I2C2 |TIM21_C1| | + * PB14|SPI2 |LCD |RTC |TSC |LPUART1 |I2C2 |TIM21_C2| | + * PB15|SPI2 |LCD |RTC | | | | | | + *______________________________________________________________________________ + * PC0 |LPTIM1_I|LCD |EVENTOUT|TSC | | | | | + * PC1 |LPTIM1_O|LCD |EVENTOUT|TSC | | | | | + * PC2 |LPTIM1_I|LCD |SPI2 |TSC | | | | | + * PC3 |LPTIM1_T|LCD |SPI2 |TSC | | | | | + * PC4 |EVENTOUT|LCD |LPUART | | | | | | + * PC5 | |LCD |LPUART |TSC | | | | | + * PC6 |TIM22_C1|LCD | |TSC | | | | | + * PC7 |TIM22_C2|LCD | |TSC | | | | | + * PC8 |TIM22_TR|LCD | |TSC | | | | | + * PC9 |TIM21_TR|LCD |USB |TSC | | | | | + * PC10|LPUART |LCD | | | | | | | + * PC11|LPUART |LCD | | | | | | | + * PC12| |LCD | | | | | | | + * PC13| | | | | | | | | + * PC14| | | | | | | | | + * PC15| | | | | | | | | + *______________________________________________________________________________ + * PD2 |LPUART |LCD | | | | | | | + *______________________________________________________________________________ + * PH0 |USB | | | | | | | | + * PH1 | | | | | | | | | + * * + */ + +/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0 + * @{ + */ #define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ #define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ #define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ #define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ #define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ #define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ -#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF0_TSC ((uint8_t)0x00) /* TSC Alternate Function mapping */ #define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ #define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ @@ -86,339 +1026,882 @@ #define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ #define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ #define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 1 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1 + * @{ + */ #define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ #define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ #define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ #define GPIO_AF1_LCD ((uint8_t)0x01) /* LCD Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ +/** + * @} + */ + + /** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2 + * @{ + */ #define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ #define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ #define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */ -#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ #define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM22 ((uint8_t)0x02) /* TIM22 Alternate Function mapping */ #define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_RTC_50Hz ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 3 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3 + * @{ + */ #define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ #define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ #define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 4 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4 + * @{ + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ #define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ #define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ #define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ #define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 5 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5 + * @{ + */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ #define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ #define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ #define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ #define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 6 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6 + * @{ + */ #define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ #define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ #define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 7 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7 + * @{ + */ #define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ #define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +/** + * @} + */ + +/** + * @} + */ + + + +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF2_SPI2) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_LPUART1) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF2_USB) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF2_LPTIM1) || \ + ((__AF__) == GPIO_AF0_LPUART1) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF0_USB) || ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF0_LPTIM1) || ((__AF__) == GPIO_AF2_EVENTOUT) || \ + ((__AF__) == GPIO_AF0_TSC) || ((__AF__) == GPIO_AF2_RTC) || \ + ((__AF__) == GPIO_AF3_I2C1) || ((__AF__) == GPIO_AF7_COMP2) || \ + ((__AF__) == GPIO_AF0_TIM22) || ((__AF__) == GPIO_AF3_EVENTOUT) || \ + ((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF0_MCO) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF0_SWDIO) || ((__AF__) == GPIO_AF0_SWCLK) || \ + ((__AF__) == GPIO_AF1_SPI1) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF1_SPI2) || ((__AF__) == GPIO_AF4_LPUART1) || \ + ((__AF__) == GPIO_AF7_COMP2) || ((__AF__) == GPIO_AF4_TIM22) || \ + ((__AF__) == GPIO_AF1_I2C1) || ((__AF__) == GPIO_AF4_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_LCD) || ((__AF__) == GPIO_AF5_SPI2) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF5_TIM2) || \ + ((__AF__) == GPIO_AF5_TIM21) || ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF6_TIM21) || \ + ((__AF__) == GPIO_AF6_EVENTOUT) || ((__AF__) == GPIO_AF7_COMP1)) + -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_SPI1) || ((AF) == GPIO_AF2_SPI2) || \ - ((AF) == GPIO_AF0_SPI2) || ((AF) == GPIO_AF2_LPUART1) || \ - ((AF) == GPIO_AF0_USART1) || ((AF) == GPIO_AF2_USB) || \ - ((AF) == GPIO_AF0_USART2) || ((AF) == GPIO_AF2_LPTIM) || \ - ((AF) == GPIO_AF0_LPUART1) || ((AF) == GPIO_AF2_TIM2) || \ - ((AF) == GPIO_AF0_USB) || ((AF) == GPIO_AF2_TIM22) || \ - ((AF) == GPIO_AF0_LPTIM) || ((AF) == GPIO_AF2_EVENTOUT) || \ - ((AF) == GPIO_AF0_TSC) || ((AF) == GPIO_AF2_RTC_50Hz) || \ - ((AF) == GPIO_AF0_TIM2) || ((AF) == GPIO_AF3_I2C1) || \ - ((AF) == GPIO_AF0_TIM21) || ((AF) == GPIO_AF3_TSC) || \ - ((AF) == GPIO_AF0_TIM22) || ((AF) == GPIO_AF3_EVENTOUT) || \ - ((AF) == GPIO_AF0_EVENTOUT) || ((AF) == GPIO_AF4_I2C1) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF4_USART1) || \ - ((AF) == GPIO_AF0_SWDIO) || ((AF) == GPIO_AF0_SWCLK) || \ - ((AF) == GPIO_AF1_SPI1) || ((AF) == GPIO_AF4_USART2) || \ - ((AF) == GPIO_AF1_SPI2) || ((AF) == GPIO_AF4_LPUART1) || \ - ((AF) == GPIO_AF1_TIM2) || ((AF) == GPIO_AF4_TIM22) || \ - ((AF) == GPIO_AF1_I2C1) || ((AF) == GPIO_AF4_EVENTOUT) || \ - ((AF) == GPIO_AF1_LCD) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_I2C2) || ((AF) == GPIO_AF5_TIM2) || \ - ((AF) == GPIO_AF5_TIM21) || ((AF) == GPIO_AF5_TIM22) || \ - ((AF) == GPIO_AF6_I2C2) || ((AF) == GPIO_AF6_TIM21) || \ - ((AF) == GPIO_AF6_EVENTOUT) || ((AF) == GPIO_AF7_COMP1) || \ - ((AF) == GPIO_AF7_COMP2) || ((AF) == GPIO_AF1_TIM21)) +#define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \ + ((((__INSTANCE__) == GPIOA) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_EVENTOUT) || \ + ((__AF__) == GPIO_AF7_COMP1))) || \ + (((__INSTANCE__) == GPIOB) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF4_EVENTOUT) || \ + ((__AF__) == GPIO_AF5_I2C2) || \ + ((__AF__) == GPIO_AF6_TIM21))) || \ + (((__INSTANCE__) == GPIOC) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_LCD) || \ + ((__AF__) == GPIO_AF2_EVENTOUT) || \ + ((__AF__) == GPIO_AF3_TSC))) || \ + (((__INSTANCE__) == GPIOD) && (((__AF__) == GPIO_AF0_LPUART1) || \ + ((__AF__) == GPIO_AF1_LCD))) || \ + (((__INSTANCE__) == GPIOH) && (((__AF__) == GPIO_AF0_USB)))) + #endif /* STM32L053xx || STM32L063xx */ /*------------------------------------------------------------------------------------------*/ -/*------------------------- STM32L052xx/STM32L062xx---------------------------*/ +/*----------------------------------------------------------------------------*/ +/*------------------------- STM32L052xx/STM32L062xx---------------------------*/ +/*----------------------------------------------------------------------------*/ #if defined (STM32L052xx) || defined (STM32L062xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ -#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00) /* TSC Alternate Function mapping */ -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ - - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ -#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */ -#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM22 ((uint8_t)0x02) /* TIM22 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_RTC_50Hz ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ + +/* The table below gives an overview of the different alternate functions per port. + * For more details refer yourself to the product data sheet. + * + */ +/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | + *______________________________________________________________________________ + * PA0 | | |TIM2_C1 |TSC |USART2 |TIM2_TR | |COMP1 | + * PA1 |EVENTOUT| |TIM2_C2 |TSC |USART2 |TIM21_TR| | | + * PA2 |TIM21_C1| |TIM2_C3 |TSC |USART2 | | |COMP2 | + * PA3 |TIM21_C2| |TIM2_C4 |TSC |USART2 | | | | + * PA4 |SPI1 | | |TSC |USART2 |TIM22_TR| | | + * PA5 |SPI1 | |TIM2_TR |TSC | |TIM2_C1 | | | + * PA6 |SPI1 | | |TSC |LPUART |TIM22_C1|EVENTOUT|COMP1 | + * PA7 |SPI1 | | |TSC | |TIM22_C2|EVENTOUT|COMP2 | + * PA8 |MCO | |USB |EVENTOUT|USART1 | | | | + * PA9 |MCO | | |TSC |USART1 | | | | + * PA10| | | |TSC |USART1 | | | | + * PA11|SPI1 | |EVENTOUT|TSC |USART1 | | |COMP1 | + * PA12|SPI1 | |EVENTOUT|TSC |USART1 | | |COMP2 | + * PA13|SWDIO | |USB | | | | | | + * PA14|SWCLK | | | |USART2 | | | | + * PA15|SPI1 | |TIM2_TR |EVENTOUT|USART2 |TIM2_C1 | | | + *______________________________________________________________________________ + * PB0 |EVENTOUT| | |TSC | | | | | + * PB1 | | | |TSC |LPUART1 | | | | + * PB2 | | |LPTIM1_O|TSC | | | | | + * PB3 |SPI1 | |TIM2_C2 |TSC |EVENTOUT| | | | + * PB4 |SPI1 | |EVENTOUT|TSC |TIM22_C1| | | | + * PB5 |SPI1 | |LPTIM1_I|I2C1 |TIM22_C2| | | | + * PB6 |USART1 |I2C1 |LPTIM1_T|TSC | | | | | + * PB7 |USART1 |I2C1 |LPTIM1_I|TSC | | | | | + * PB8 | | | |TSC |I2C1 | | | | + * PB9 | | |EVENTOUT| |I2C1 |SPI2 | | | + * PB10| | |TIM2_C3 |TSC |LPUART1 |SPI2 |I2C2 | | + * PB11|EVENTOUT| |TIM2_C4 |TSC |LPUART1 | |I2C2 | | + * PB12|SPI2 | |LPUART1 |TSC | |I2C2 |EVENTOUT| | + * PB13|SPI2 | | |TSC |LPUART1 |I2C2 |TIM21_C1| | + * PB14|SPI2 | |RTC |TSC |LPUART1 |I2C2 |TIM21_C2| | + * PB15|SPI2 | |RTC | | | | | | + *______________________________________________________________________________ + * PC0 |LPTIM1_I| |EVENTOUT|TSC | | | | | + * PC1 |LPTIM1_O| |EVENTOUT|TSC | | | | | + * PC2 |LPTIM1_I| |SPI2 |TSC | | | | | + * PC3 |LPTIM1_T| |SPI2 |TSC | | | | | + * PC4 |EVENTOUT| |LPUART | | | | | | + * PC5 | | |LPUART |TSC | | | | | + * PC6 |TIM22_C1| | |TSC | | | | | + * PC7 |TIM22_C2| | |TSC | | | | | + * PC8 |TIM22_TR| | |TSC | | | | | + * PC9 |TIM21_TR| |USB |TSC | | | | | + * PC10|LPUART | | | | | | | | + * PC11|LPUART | | | | | | | | + * PC12| | | | | | | | | + * PC13| | | | | | | | | + * PC14| | | | | | | | | + * PC15| | | | | | | | | + *______________________________________________________________________________ + * PD2 |LPUART | | | | | | | | + *______________________________________________________________________________ + * PH0 |USB | | | | | | | | + * PH1 | | | | | | | | | + * * + */ + +/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0 + * @{ + */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_USB ((uint8_t)0x00) /* USB Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TSC ((uint8_t)0x00) /* TSC Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1 + * @{ + */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2 + * @{ + */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ +/** + * @} + */ + + /** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3 + * @{ + */ #define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ #define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ #define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 4 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4 + * @{ + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ #define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ #define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ #define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ #define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 5 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5 + * @{ + */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ #define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ #define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ #define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ #define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 6 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6 + * @{ + */ #define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ #define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ #define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 7 selection - */ + /** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7 + * @{ + */ #define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ #define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +/** + * @} + */ + +/** + * @} + */ + +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF2_SPI2) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_LPUART1) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF2_USB) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF2_LPTIM1) || \ + ((__AF__) == GPIO_AF0_LPUART1) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF0_USB) || ((__AF__) == GPIO_AF4_TIM22) || \ + ((__AF__) == GPIO_AF0_LPTIM1) || ((__AF__) == GPIO_AF2_EVENTOUT) || \ + ((__AF__) == GPIO_AF0_TSC) || ((__AF__) == GPIO_AF2_RTC) || \ + ((__AF__) == GPIO_AF0_TIM2) || ((__AF__) == GPIO_AF3_I2C1) || \ + ((__AF__) == GPIO_AF0_TIM21) || ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF0_TIM22) || ((__AF__) == GPIO_AF3_EVENTOUT) || \ + ((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF0_MCO) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF0_SWDIO) || ((__AF__) == GPIO_AF0_SWCLK) || \ + ((__AF__) == GPIO_AF1_SPI1) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF1_SPI2) || ((__AF__) == GPIO_AF4_LPUART1) || \ + ((__AF__) == GPIO_AF1_I2C1) || ((__AF__) == GPIO_AF4_EVENTOUT) || \ + ((__AF__) == GPIO_AF6_EVENTOUT) || ((__AF__) == GPIO_AF5_SPI2) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF5_TIM2) || \ + ((__AF__) == GPIO_AF5_TIM21) || ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF6_TIM21) || \ + ((__AF__) == GPIO_AF7_COMP2) || ((__AF__) == GPIO_AF7_COMP1)) + + +#define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \ + ((((__INSTANCE__) == GPIOA) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_EVENTOUT) || \ + ((__AF__) == GPIO_AF7_COMP1))) || \ + (((__INSTANCE__) == GPIOB) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_TSC) || \ + ((__AF__) == GPIO_AF4_LPUART1) || \ + ((__AF__) == GPIO_AF5_I2C2) || \ + ((__AF__) == GPIO_AF6_EVENTOUT))) || \ + (((__INSTANCE__) == GPIOC) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF2_EVENTOUT) || \ + ((__AF__) == GPIO_AF3_TSC))) || \ + (((__INSTANCE__) == GPIOD) && (((__AF__) == GPIO_AF0_LPUART1))) || \ + (((__INSTANCE__) == GPIOH) && (((__AF__) == GPIO_AF0_USB)))) -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_SPI1) || ((AF) == GPIO_AF2_SPI2) || \ - ((AF) == GPIO_AF0_SPI2) || ((AF) == GPIO_AF2_LPUART1) || \ - ((AF) == GPIO_AF0_USART1) || ((AF) == GPIO_AF2_USB) || \ - ((AF) == GPIO_AF0_USART2) || ((AF) == GPIO_AF2_LPTIM) || \ - ((AF) == GPIO_AF0_LPUART1) || ((AF) == GPIO_AF2_TIM2) || \ - ((AF) == GPIO_AF0_USB) || ((AF) == GPIO_AF2_TIM22) || \ - ((AF) == GPIO_AF0_LPTIM) || ((AF) == GPIO_AF2_EVENTOUT) || \ - ((AF) == GPIO_AF0_TSC) || ((AF) == GPIO_AF2_RTC_50Hz) || \ - ((AF) == GPIO_AF0_TIM2) || ((AF) == GPIO_AF3_I2C1) || \ - ((AF) == GPIO_AF0_TIM21) || ((AF) == GPIO_AF3_TSC) || \ - ((AF) == GPIO_AF0_TIM22) || ((AF) == GPIO_AF3_EVENTOUT) || \ - ((AF) == GPIO_AF0_EVENTOUT) || ((AF) == GPIO_AF4_I2C1) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF4_USART1) || \ - ((AF) == GPIO_AF0_SWDIO) || ((AF) == GPIO_AF0_SWCLK) || \ - ((AF) == GPIO_AF1_SPI1) || ((AF) == GPIO_AF4_USART2) || \ - ((AF) == GPIO_AF1_SPI2) || ((AF) == GPIO_AF4_LPUART1) || \ - ((AF) == GPIO_AF1_TIM2) || ((AF) == GPIO_AF4_TIM22) || \ - ((AF) == GPIO_AF1_I2C1) || ((AF) == GPIO_AF4_EVENTOUT) || \ - ((AF) == GPIO_AF6_EVENTOUT) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_I2C2) || ((AF) == GPIO_AF5_TIM2) || \ - ((AF) == GPIO_AF5_TIM21) || ((AF) == GPIO_AF5_TIM22) || \ - ((AF) == GPIO_AF6_I2C2) || ((AF) == GPIO_AF6_TIM21) || \ - ((AF) == GPIO_AF7_COMP2) || ((AF) == GPIO_AF7_COMP1) || \ - ((AF) == GPIO_AF1_TIM21)) #endif /* STM32L052xx || STM32L062xx */ /*------------------------------------------------------------------------------------------*/ -/*------------------------- STM32L051xx/STM32L061xx---------------------------*/ +/*----------------------------------------------------------------------------*/ +/*------------------------- STM32L051xx/STM32L061xx---------------------------*/ +/*----------------------------------------------------------------------------*/ #if defined (STM32L051xx)|| defined (STM32L061xx) -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ -#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ -#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ -#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ -#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF0_LPTIM ((uint8_t)0x00) /* LPTIM Alternate Function mapping */ -#define GPIO_AF0_TSC ((uint8_t)0x00) /* TSC Alternate Function mapping */ -#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ -#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ -#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ -#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ -#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ -#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ - - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ -#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ -#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM21 ((uint8_t)0x01) /* TIM21 Alternate Function mapping */ -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ -#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF2_LPTIM ((uint8_t)0x02) /* LPTIM Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM22 ((uint8_t)0x02) /* TIM22 Alternate Function mapping */ -#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ -#define GPIO_AF2_RTC_50Hz ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ +/* The table below gives an overview of the different alternate functions per port. + * For more details refer yourself to the product data sheet. + * + */ +/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | + *______________________________________________________________________________ + * PA0 | | |TIM2_C1 | |USART2 |TIM2_TR | |COMP1 | + * PA1 |EVENTOUT| |TIM2_C2 | |USART2 |TIM21_TR| | | + * PA2 |TIM21_C1| |TIM2_C3 | |USART2 | | |COMP2 | + * PA3 |TIM21_C2| |TIM2_C4 | |USART2 | | | | + * PA4 |SPI1 | | | |USART2 |TIM22_TR| | | + * PA5 |SPI1 | |TIM2_TR | | |TIM2_C1 | | | + * PA6 |SPI1 | | | |LPUART |TIM22_C1|EVENTOUT|COMP1 | + * PA7 |SPI1 | | | | |TIM22_C2|EVENTOUT|COMP2 | + * PA8 |MCO | | |EVENTOUT|USART1 | | | | + * PA9 |MCO | | | |USART1 | | | | + * PA10| | | | |USART1 | | | | + * PA11|SPI1 | |EVENTOUT| |USART1 | | |COMP1 | + * PA12|SPI1 | |EVENTOUT| |USART1 | | |COMP2 | + * PA13|SWDIO | | | | | | | | + * PA14|SWCLK | | | |USART2 | | | | + * PA15|SPI1 | |TIM2_TR |EVENTOUT|USART2 |TIM2_C1 | | | + *______________________________________________________________________________ + * PB0 |EVENTOUT| | | | | | | | + * PB1 | | | | |LPUART1 | | | | + * PB2 | | |LPTIM1_O| | | | | | + * PB3 |SPI1 | |TIM2_C2 | |EVENTOUT| | | | + * PB4 |SPI1 | |EVENTOUT| |TIM22_C1| | | | + * PB5 |SPI1 | |LPTIM1_I|I2C1 |TIM22_C2| | | | + * PB6 |USART1 |I2C1 |LPTIM1_T| | | | | | + * PB7 |USART1 |I2C1 |LPTIM1_I| | | | | | + * PB8 | | | | |I2C1 | | | | + * PB9 | | |EVENTOUT| |I2C1 |SPI2 | | | + * PB10| | |TIM2_C3 | |LPUART1 |SPI2 |I2C2 | | + * PB11|EVENTOUT| |TIM2_C4 | |LPUART1 | |I2C2 | | + * PB12|SPI2 | |LPUART1 | | |I2C2 |EVENTOUT| | + * PB13|SPI2 | | | |LPUART1 |I2C2 |TIM21_C1| | + * PB14|SPI2 | |RTC | |LPUART1 |I2C2 |TIM21_C2| | + * PB15|SPI2 | |RTC | | | | | | + *______________________________________________________________________________ + * PC0 |LPTIM1_I| |EVENTOUT| | | | | | + * PC1 |LPTIM1_O| |EVENTOUT| | | | | | + * PC2 |LPTIM1_I| |SPI2 | | | | | | + * PC3 |LPTIM1_T| |SPI2 | | | | | | + * PC4 |EVENTOUT| |LPUART | | | | | | + * PC5 | | |LPUART | | | | | | + * PC6 |TIM22_C1| | | | | | | | + * PC7 |TIM22_C2| | | | | | | | + * PC8 |TIM22_TR| | | | | | | | + * PC9 |TIM21_TR| | | | | | | | + * PC10|LPUART | | | | | | | | + * PC11|LPUART | | | | | | | | + * PC12| | | | | | | | | + * PC13| | | | | | | | | + * PC14| | | | | | | | | + * PC15| | | | | | | | | + *______________________________________________________________________________ + * PD2 |LPUART | | | | | | | | + *______________________________________________________________________________ + * PH0 | | | | | | | | | + * PH1 | | | | | | | | | + * * + */ + +/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0 + * @{ + */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_SPI2 ((uint8_t)0x00) /* SPI2 Alternate Function mapping */ +#define GPIO_AF0_USART1 ((uint8_t)0x00) /* USART1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_LPUART1 ((uint8_t)0x00) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM2 ((uint8_t)0x00) /* TIM2 Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_TIM22 ((uint8_t)0x00) /* TIM22 Alternate Function mapping */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1 + * @{ + */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_SPI2 ((uint8_t)0x01) /* SPI2 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +/** + * @} + */ + + /** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2 + * @{ + */ +#define GPIO_AF2_SPI2 ((uint8_t)0x02) /* SPI2 Alternate Function mapping */ +#define GPIO_AF2_LPUART1 ((uint8_t)0x02) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF2_USB ((uint8_t)0x02) /* USB Alternate Function mapping */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3 + * @{ + */ #define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ -#define GPIO_AF3_TSC ((uint8_t)0x03) /* TSC Alternate Function mapping */ #define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ - -/** - * @brief AF 4 selection - */ +/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4 + * @{ + */ #define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ #define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */ #define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ #define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ #define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ #define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 5 selection - */ +/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5 + * @{ + */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ #define GPIO_AF5_I2C2 ((uint8_t)0x05) /* I2C2 Alternate Function mapping */ #define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ #define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ #define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 6 selection - */ +/** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6 + * @{ + */ #define GPIO_AF6_I2C2 ((uint8_t)0x06) /* I2C2 Alternate Function mapping */ #define GPIO_AF6_TIM21 ((uint8_t)0x06) /* TIM21 Alternate Function mapping */ #define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ -/** - * @brief AF 7 selection - */ +/** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7 + * @{ + */ #define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ #define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +/** + * @} + */ + +/** + * @} + */ -#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_SPI1) || ((AF) == GPIO_AF2_SPI2) || \ - ((AF) == GPIO_AF0_SPI2) || ((AF) == GPIO_AF2_LPUART1) || \ - ((AF) == GPIO_AF0_USART1) || ((AF) == GPIO_AF2_TIM22) || \ - ((AF) == GPIO_AF0_USART2) || ((AF) == GPIO_AF2_LPTIM) || \ - ((AF) == GPIO_AF0_LPUART1) || ((AF) == GPIO_AF2_TIM2) || \ - ((AF) == GPIO_AF0_LPTIM) || ((AF) == GPIO_AF2_EVENTOUT) || \ - ((AF) == GPIO_AF1_TIM21) || ((AF) == GPIO_AF2_RTC_50Hz) || \ - ((AF) == GPIO_AF0_TIM2) || ((AF) == GPIO_AF3_I2C1) || \ - ((AF) == GPIO_AF0_TIM21) || ((AF) == GPIO_AF3_TSC) || \ - ((AF) == GPIO_AF0_TIM22) || ((AF) == GPIO_AF3_EVENTOUT) || \ - ((AF) == GPIO_AF0_EVENTOUT) || ((AF) == GPIO_AF4_I2C1) || \ - ((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF4_USART1) || \ - ((AF) == GPIO_AF0_SWDIO) || ((AF) == GPIO_AF0_SWCLK) || \ - ((AF) == GPIO_AF1_SPI1) || ((AF) == GPIO_AF4_USART2) || \ - ((AF) == GPIO_AF1_SPI2) || ((AF) == GPIO_AF4_LPUART1) || \ - ((AF) == GPIO_AF1_TIM2) || ((AF) == GPIO_AF4_TIM22) || \ - ((AF) == GPIO_AF1_I2C1) || ((AF) == GPIO_AF4_EVENTOUT) || \ - ((AF) == GPIO_AF6_EVENTOUT) || ((AF) == GPIO_AF5_SPI2) || \ - ((AF) == GPIO_AF5_I2C2) || ((AF) == GPIO_AF5_TIM2) || \ - ((AF) == GPIO_AF5_TIM21) || ((AF) == GPIO_AF5_TIM22) || \ - ((AF) == GPIO_AF6_I2C2) || ((AF) == GPIO_AF6_TIM21) || \ - ((AF) == GPIO_AF7_COMP2) || ((AF) == GPIO_AF7_COMP1)) +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_SPI1) || ((__AF__) == GPIO_AF2_SPI2) || \ + ((__AF__) == GPIO_AF0_SPI2) || ((__AF__) == GPIO_AF2_LPUART1) || \ + ((__AF__) == GPIO_AF0_USART1) || ((__AF__) == GPIO_AF7_COMP1) || \ + ((__AF__) == GPIO_AF0_USART2) || ((__AF__) == GPIO_AF2_LPTIM1) || \ + ((__AF__) == GPIO_AF0_LPUART1) || ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF0_LPTIM1) || ((__AF__) == GPIO_AF2_EVENTOUT) || \ + ((__AF__) == GPIO_AF2_RTC) || ((__AF__) == GPIO_AF4_TIM22) || \ + ((__AF__) == GPIO_AF0_TIM2) || ((__AF__) == GPIO_AF3_I2C1) || \ + ((__AF__) == GPIO_AF0_TIM21) || ((__AF__) == GPIO_AF7_COMP2) || \ + ((__AF__) == GPIO_AF0_TIM22) || ((__AF__) == GPIO_AF3_EVENTOUT) || \ + ((__AF__) == GPIO_AF0_EVENTOUT) || ((__AF__) == GPIO_AF4_I2C1) || \ + ((__AF__) == GPIO_AF0_MCO) || ((__AF__) == GPIO_AF4_USART1) || \ + ((__AF__) == GPIO_AF0_SWDIO) || ((__AF__) == GPIO_AF0_SWCLK) || \ + ((__AF__) == GPIO_AF1_SPI1) || ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF1_SPI2) || ((__AF__) == GPIO_AF4_LPUART1) || \ + ((__AF__) == GPIO_AF1_I2C1) || ((__AF__) == GPIO_AF4_EVENTOUT) || \ + ((__AF__) == GPIO_AF6_EVENTOUT) || ((__AF__) == GPIO_AF5_SPI2) || \ + ((__AF__) == GPIO_AF5_I2C2) || ((__AF__) == GPIO_AF5_TIM2) || \ + ((__AF__) == GPIO_AF5_TIM21) || ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_I2C2) || ((__AF__) == GPIO_AF6_TIM21)) + + #define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \ + ((((__INSTANCE__) == GPIOA) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_EVENTOUT) || \ + ((__AF__) == GPIO_AF4_USART2) || \ + ((__AF__) == GPIO_AF5_TIM22) || \ + ((__AF__) == GPIO_AF6_EVENTOUT) || \ + ((__AF__) == GPIO_AF7_COMP2))) || \ + (((__INSTANCE__) == GPIOB) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF1_I2C1) || \ + ((__AF__) == GPIO_AF2_TIM2) || \ + ((__AF__) == GPIO_AF3_I2C1) || \ + ((__AF__) == GPIO_AF4_LPUART1) || \ + ((__AF__) == GPIO_AF5_I2C2) || \ + ((__AF__) == GPIO_AF6_TIM21))) || \ + (((__INSTANCE__) == GPIOC) && (((__AF__) == GPIO_AF0_EVENTOUT) || \ + ((__AF__) == GPIO_AF2_LPUART1))) || \ + (((__INSTANCE__) == GPIOD) && (((__AF__) == GPIO_AF0_LPUART1)))) + + #endif /* STM32L051xx/STM32L061xx*/ +/*------------------------------------------------------------------------------------------*/ + +/*----------------------------------------------------------------------------*/ +/*------------------------- STM32L031xx/STM32L041xx---------------------------*/ +/*----------------------------------------------------------------------------*/ +#if defined (STM32L031xx)|| defined (STM32L041xx) +/* The table below gives an overview of the different alternate functions per port. + * For more details refer yourself to the product data sheet. + * + */ +/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | + *______________________________________________________________________________ + * PA0 | |LPTIM1 |TIM2_C1 | |USART2 |TIM2_TR | |COMP1 | + * PA1 |EVENTOUT|LPTIM1 |TIM2_C2 |I2C1 |USART2 |TIM21_TR| | | + * PA2 |TIM21_C1| |TIM2_C3 | |USART2 | |LPUART1 |COMP2 | + * PA3 |TIM21_C2| |TIM2_C4 | |USART2 | |LPUART1 | | + * PA4 |SPI1 |LPTIM1 | | |USART2 |TIM22_TR| | | + * PA5 |SPI1 |LPTIM1 |TIM2_TR | | |TIM2_C1 | | | + * PA6 |SPI1 |LPTIM1 | | |LPUART |TIM22_C1|EVENTOUT|COMP1 | + * PA7 |SPI1 |LPTIM1 | | |USART2 |TIM22_C2|EVENTOUT|COMP2 | + * PA8 |MCO | |LPTIM1 |EVENTOUT|USART2 | | | | + * PA9 |MCO |I2C1 | | |USART2 |TIM22_C1| | | + * PA10| |I2C1 | | |USART2 |TIM22_C2| | | + * PA11|SPI1 | |EVENTOUT| |USART2 | | |COMP1 | + * PA12|SPI1 | |EVENTOUT| |USART2 | | |COMP2 | + * PA13|SWDIO |LPTIM1 | | | | |LPUART1 | | + * PA14|SWCLK |LPTIM1 | |I2C1 |USART2 | |LPUART1 | | + * PA15|SPI1 | |TIM2_TR |EVENTOUT|USART2 |TIM2_C1 | | | + *_____________________________________________________________________________| + * PB0 |EVENTOUT|SPI1 | | |USART2 |TIM2_C3 | | | + * PB1 |USART2 |SPI1 | | |LPUART1 |TIM2_C4 | | | + * PB2 | | |LPTIM1_O| | | | | | + * PB3 |SPI1 | |TIM2_C2 | |EVENTOUT| | | | + * PB4 |SPI1 | |EVENTOUT| |TIM22_C1| | | | + * PB5 |SPI1 | |LPTIM1_I|I2C1 |TIM22_C2| | | | + * PB6 |USART2 |I2C1 |LPTIM1_T| | | | | | + * PB7 |USART2 |I2C1 |LPTIM1_I| | | | | | + * PB8 | | | | |I2C1 | | | | + * PB9 | | |EVENTOUT| |I2C1 | | | | + * PB10| | |TIM2_C3 | | | |LPUART1 | | + * PB11|EVENTOUT| |TIM2_C4 | | | |LPUART1 | | + * PB12|SPI2 | | | | | |EVENTOUT| | + * PB13|SPI2 | |MCO | | |TIM21_C1|LPUART1 | | + * PB14|SPI2 | |RTC | | |TIM21_C2|LPUART1 | | + * PB15|SPI2 | |RTC | | | | | | + *_____________________________________________________________________________| + * PC0 |LPTIM1_I| |EVENTOUT| | | |LPUART1 | | + * PC1 | | | | | | | | | + * PC13| | | | | | | | | + * PC14| | | | | | | | | + * PC15| | | | | | | | | + *_____________________________________________________________________________| + * PH0 | | | | | | | | | + * PH1 | | | | | | | | | + *_____________________________________________________________________________| + */ + +/** @defgroup GPIOEx_Alternate_function_selection Alternate function selection + * @{ + */ + +/** @defgroup GPIOEx_Alternate_function_AF0 Alternate function AF0 + * @{ + */ +#define GPIO_AF0_EVENTOUT ((uint8_t)0x00) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF0_TIM21 ((uint8_t)0x00) /* TIM21 Alternate Function mapping */ +#define GPIO_AF0_SPI1 ((uint8_t)0x00) /* SPI1 Alternate Function mapping */ +#define GPIO_AF0_USART2 ((uint8_t)0x00) /* USART2 Alternate Function mapping */ +#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO Alternate Function mapping */ +#define GPIO_AF0_SWDIO ((uint8_t)0x00) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK ((uint8_t)0x00) /* SWCLK Alternate Function mapping */ +/** + * @} + */ -/* Aliases define maintained for legacy */ -#define GPIO_AF0_EVENOUT GPIO_AF0_EVENTOUT -#define GPIO_AF2_EVENOUT GPIO_AF2_EVENTOUT -#define GPIO_AF3_EVENOUT GPIO_AF3_EVENTOUT -#define GPIO_AF6_EVENOUT GPIO_AF6_EVENTOUT +/** @defgroup GPIOEx_Alternate_function_AF1 Alternate function AF1 + * @{ + */ +#define GPIO_AF1_SPI1 ((uint8_t)0x01) /* SPI1 Alternate Function mapping */ +#define GPIO_AF1_I2C1 ((uint8_t)0x01) /* I2C1 Alternate Function mapping */ +#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ +/** + * @} + */ + + /** @defgroup GPIOEx_Alternate_function_AF2 Alternate function AF2 + * @{ + */ +#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ +#define GPIO_AF2_EVENTOUT ((uint8_t)0x02) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF2_RTC ((uint8_t)0x02) /* RTC_OUT Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF3 Alternate function AF3 + * @{ + */ +#define GPIO_AF3_I2C1 ((uint8_t)0x03) /* I2C1 Alternate Function mapping */ +#define GPIO_AF3_EVENTOUT ((uint8_t)0x03) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF4 Alternate function AF4 + * @{ + */ +#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ +#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */ +#define GPIO_AF4_LPUART1 ((uint8_t)0x04) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF4_TIM22 ((uint8_t)0x04) /* TIM22 Alternate Function mapping */ +#define GPIO_AF4_EVENTOUT ((uint8_t)0x04) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF5 Alternate function AF5 + * @{ + */ +#define GPIO_AF5_TIM2 ((uint8_t)0x05) /* TIM2 Alternate Function mapping */ +#define GPIO_AF5_TIM21 ((uint8_t)0x05) /* TIM21 Alternate Function mapping */ +#define GPIO_AF5_TIM22 ((uint8_t)0x05) /* TIM22 Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF6 Alternate function AF6 + * @{ + */ +#define GPIO_AF6_LPUART1 ((uint8_t)0x06) /* LPUART1 Alternate Function mapping */ +#define GPIO_AF6_EVENTOUT ((uint8_t)0x06) /* EVENTOUT Alternate Function mapping */ +/** + * @} + */ + +/** @defgroup GPIOEx_Alternate_function_AF7 Alternate function AF7 + * @{ + */ +#define GPIO_AF7_COMP1 ((uint8_t)0x07) /* COMP1 Alternate Function mapping */ +#define GPIO_AF7_COMP2 ((uint8_t)0x07) /* COMP2 Alternate Function mapping */ +/** + * @} + */ + +/** + * @} + */ + +#define IS_GPIO_AF(__AF__) (((__AF__) == GPIO_AF0_EVENTOUT ) || \ + ((__AF__) == GPIO_AF0_TIM21 ) || \ + ((__AF__) == GPIO_AF0_SPI1 ) || \ + ((__AF__) == GPIO_AF0_USART2 ) || \ + ((__AF__) == GPIO_AF0_LPTIM1 ) || \ + ((__AF__) == GPIO_AF0_MCO ) || \ + ((__AF__) == GPIO_AF0_SWDIO ) || \ + ((__AF__) == GPIO_AF0_SWCLK ) || \ + ((__AF__) == GPIO_AF1_SPI1 ) || \ + ((__AF__) == GPIO_AF1_I2C1 ) || \ + ((__AF__) == GPIO_AF1_LPTIM1 ) || \ + ((__AF__) == GPIO_AF2_LPTIM1 ) || \ + ((__AF__) == GPIO_AF2_TIM2 ) || \ + ((__AF__) == GPIO_AF2_EVENTOUT ) || \ + ((__AF__) == GPIO_AF2_RTC ) || \ + ((__AF__) == GPIO_AF3_I2C1 ) || \ + ((__AF__) == GPIO_AF3_EVENTOUT ) || \ + ((__AF__) == GPIO_AF4_I2C1 ) || \ + ((__AF__) == GPIO_AF4_USART2 ) || \ + ((__AF__) == GPIO_AF4_LPUART1 ) || \ + ((__AF__) == GPIO_AF4_TIM22 ) || \ + ((__AF__) == GPIO_AF4_EVENTOUT ) || \ + ((__AF__) == GPIO_AF5_TIM2 ) || \ + ((__AF__) == GPIO_AF5_TIM21 ) || \ + ((__AF__) == GPIO_AF5_TIM22 ) || \ + ((__AF__) == GPIO_AF6_LPUART1 ) || \ + ((__AF__) == GPIO_AF6_EVENTOUT ) || \ + ((__AF__) == GPIO_AF7_COMP1 ) || \ + ((__AF__) == GPIO_AF7_COMP2 )) + + + +#define IS_GPIO_AF_AVAILABLE(__INSTANCE__,__AF__) \ + (1) + + +#endif /* STM32L031xx/STM32L041xx*/ /*------------------------------------------------------------------------------------------*/ + + + +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOE))? 4U :\ + ((__GPIOx__) == (GPIOH))? 5U : 6U) + +/** @defgroup GPIOEx_Pin_Available Pin available + * @{ + */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE GPIO_PIN_All +#define GPIOD_PIN_AVAILABLE GPIO_PIN_All +#define GPIOE_PIN_AVAILABLE GPIO_PIN_All +#define GPIOH_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_9 | GPIO_PIN_10) /** * @} - */ + */ + +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOE) && (((__PIN__) & (GPIOE_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOE_PIN_AVAILABLE)) == (GPIOE_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) + +#elif defined (STM32L031xx) || defined (STM32L041xx) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOH))? 5U : 6U) + +/** @defgroup GPIOEx_Pin_Available Pin available + * @{ + */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15) +#define GPIOH_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1) /** * @} */ -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) + +#elif defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) +#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\ + ((__GPIOx__) == (GPIOB))? 1U :\ + ((__GPIOx__) == (GPIOC))? 2U :\ + ((__GPIOx__) == (GPIOD))? 3U :\ + ((__GPIOx__) == (GPIOH))? 5U : 6U) +/** @defgroup GPIOEx_Pin_Available Pin available + * @{ + */ +#define GPIOA_PIN_AVAILABLE GPIO_PIN_All +#define GPIOB_PIN_AVAILABLE GPIO_PIN_All +#define GPIOC_PIN_AVAILABLE GPIO_PIN_All +#define GPIOD_PIN_AVAILABLE GPIO_PIN_2 +#define GPIOH_PIN_AVAILABLE GPIO_PIN_0 | GPIO_PIN_1 /** * @} - */ + */ + +#define IS_GPIO_PIN_AVAILABLE(__INSTANCE__,__PIN__) \ + ((((__INSTANCE__) == GPIOA) && (((__PIN__) & (GPIOA_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOA_PIN_AVAILABLE)) == (GPIOA_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOB) && (((__PIN__) & (GPIOB_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOB_PIN_AVAILABLE)) == (GPIOB_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOC) && (((__PIN__) & (GPIOC_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOC_PIN_AVAILABLE)) == (GPIOC_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOD) && (((__PIN__) & (GPIOD_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOD_PIN_AVAILABLE)) == (GPIOD_PIN_AVAILABLE))) || \ + (((__INSTANCE__) == GPIOH) && (((__PIN__) & (GPIOH_PIN_AVAILABLE)) != 0) && (((__PIN__) | (GPIOH_PIN_AVAILABLE)) == (GPIOH_PIN_AVAILABLE)))) + + +#endif /* STM32L083xx || STM32L082xx || STM32L081xx || STM32L073xx || STM32L072xx || STM32L071xx*/ + /** * @} */ - + +/** + * @} + */ + +/** + * @} + */ #ifdef __cplusplus } #endif @@ -426,3 +1909,4 @@ #endif /* __STM32L0xx_HAL_GPIO_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c index faac2d09a8b..23e0288dfba 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.c @@ -2,15 +2,14 @@ ****************************************************************************** * @file stm32l0xx_hal_i2c.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief I2C HAL module driver. - * * This file provides firmware functions to manage the following * functionalities of the Inter Integrated Circuit (I2C) peripheral: * + Initialization and de-initialization functions * + IO operation functions - * + Peripheral State functions + * + Peripheral State and Errors functions * @verbatim ============================================================================== @@ -31,23 +30,23 @@ (+++) Configure the I2Cx interrupt priority (+++) Enable the NVIC I2C IRQ Channel (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel (+++) Enable the DMAx interface clock using (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Stream + (+++) Configure the DMA Tx or Rx channel (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on + the DMA Tx or Rx channel (#) Configure the Communication Clock Timing, Own Address1, Master Adressing Mode, Dual Addressing mode, Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - (#) Initialize the I2C registers by calling the HAL_I2C_Init() API: - (+++) These API's configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_I2C_MspInit(&hi2c) API. + (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware + (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API. (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - (#) For I2C IO and IO MEM operations, three mode of operations are available within this driver : + (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : *** Polling mode IO operation *** ================================= @@ -140,10 +139,10 @@ (+) __HAL_I2C_ENABLE: Enable the I2C peripheral (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG : Clears the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enables the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disables the specified I2C interrupt + (+) __HAL_I2C_GET_FLAG : Check whether the specified I2C flag is set or not + (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag + (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt + (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt [..] (@) You can refer to the I2C HAL driver header file for more useful macros @@ -152,7 +151,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -186,7 +185,7 @@ * @{ */ -/** @defgroup I2C +/** @defgroup I2C I2C * @brief I2C HAL module driver * @{ */ @@ -194,7 +193,10 @@ #ifdef HAL_I2C_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup I2C_Private_Constants I2C Private Constants + * @{ + */ #define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*ErrorCode = HAL_I2C_ERROR_NONE; + hi2c->State = HAL_I2C_STATE_RESET; /* Release Lock */ @@ -414,7 +427,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) * @} */ -/** @defgroup HAL_I2C_Group2 I/O operation functions +/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions * @brief Data transfers functions * @verbatim @@ -425,7 +438,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) This subsection provides a set of functions allowing to manage the I2C data transfers. - (#) There is two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. @@ -460,7 +473,7 @@ HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) (++) HAL_I2C_Mem_Write_DMA() (++) HAL_I2C_Mem_Read_DMA() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_I2C_MemTxCpltCallback() (++) HAL_I2C_MemRxCpltCallback() (++) HAL_I2C_MasterTxCpltCallback() @@ -489,7 +502,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -578,7 +591,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -609,7 +622,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -692,7 +705,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -720,7 +733,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -849,7 +862,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -961,7 +974,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1033,7 +1046,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1103,7 +1116,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1153,7 +1166,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1204,7 +1217,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1295,7 +1308,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1375,7 +1388,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1461,7 +1474,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD { if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1519,6 +1532,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD return HAL_BUSY; } } + /** * @brief Write an amount of data in blocking mode to a specific memory address * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains @@ -1540,7 +1554,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1647,7 +1661,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -1683,7 +1697,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1785,7 +1799,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -1799,6 +1813,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, return HAL_BUSY; } } + /** * @brief Write an amount of data in no-blocking mode with Interrupt to a specific memory address * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains @@ -1817,7 +1832,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1910,7 +1925,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1983,6 +1998,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre return HAL_BUSY; } } + /** * @brief Write an amount of data in no-blocking mode with DMA to a specific memory address * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains @@ -2001,7 +2017,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -2110,7 +2126,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddr if(hi2c->State == HAL_I2C_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -2224,7 +2240,7 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd do { /* Generate Start */ - hi2c->Instance->CR2 = __HAL_I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); + hi2c->Instance->CR2 = __I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ @@ -2308,6 +2324,13 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd return HAL_BUSY; } } +/** + * @} + */ + +/** @defgroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /** * @brief This function handles I2C event interrupt request. @@ -2493,7 +2516,8 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) * @} */ -/** @defgroup I2C_Group3 Peripheral State and Errors functions + +/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State and Errors functions * @verbatim @@ -2510,7 +2534,8 @@ __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) /** * @brief Returns the I2C state. - * @param hi2c : I2C handle + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains + * the configuration information for the specified I2C. * @retval HAL state */ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) @@ -2520,7 +2545,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) /** * @brief Return the I2C error code -* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2C. * @retval I2C Error Code */ @@ -2533,6 +2558,14 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) * @} */ +/** + * @} + */ + +/** @addtogroup I2C_Private_Functions + * @{ + */ + /** * @brief Handle Interrupt Flags Master Transmit Mode * @param hi2c : Pointer to a I2C_HandleTypeDef structure that contains @@ -2606,7 +2639,7 @@ static HAL_StatusTypeDef I2C_MasterTransmit_ISR(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -2713,7 +2746,7 @@ static HAL_StatusTypeDef I2C_MasterReceive_ISR(I2C_HandleTypeDef *hi2c) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->State = HAL_I2C_STATE_READY; @@ -2924,13 +2957,13 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress); } /* If Memory address size is 16Bit */ else { /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress); + hi2c->Instance->TXDR = __I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) @@ -2946,7 +2979,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_ } /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TCR flag is set */ @@ -2989,13 +3022,13 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t if(MemAddSize == I2C_MEMADD_SIZE_8BIT) { /* Send Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress); } /* If Mememory address size is 16Bit */ else { /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_MSB(MemAddress); + hi2c->Instance->TXDR = __I2C_MEM_ADD_MSB(MemAddress); /* Wait until TXIS flag is set */ if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout) != HAL_OK) @@ -3011,7 +3044,7 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t } /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = __HAL_I2C_MEM_ADD_LSB(MemAddress); + hi2c->Instance->TXDR = __I2C_MEM_ADD_LSB(MemAddress); } /* Wait until TC flag is set */ @@ -3023,7 +3056,6 @@ static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t return HAL_OK; } - /** * @brief DMA I2C master transmit process complete callback. * @param hdma: DMA handle @@ -3068,7 +3100,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3125,7 +3157,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3159,7 +3191,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -3275,7 +3307,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3338,7 +3370,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3373,7 +3405,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -3490,7 +3522,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3547,7 +3579,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3581,7 +3613,7 @@ static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; @@ -3646,7 +3678,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3709,7 +3741,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->XferCount = 0; @@ -3743,7 +3775,7 @@ static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma) __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); /* Disable DMA Request */ hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; @@ -3929,7 +3961,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_NONE; hi2c->State= HAL_I2C_STATE_READY; @@ -4006,7 +4038,7 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_I2C_RESET_CR2(hi2c); + __I2C_RESET_CR2(hi2c); hi2c->ErrorCode = HAL_I2C_ERROR_AF; hi2c->State= HAL_I2C_STATE_READY; @@ -4061,10 +4093,6 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui hi2c->Instance->CR2 = tmpreg; } -/** - * @} - */ - /** * @} */ @@ -4079,3 +4107,4 @@ static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, ui */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.h index d25a49c6c05..35b2522f8b4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_i2c.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of I2C HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,9 +55,13 @@ */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup I2C_Exported_Types I2C Exported Types + * @{ + */ -/** +/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition * @brief I2C Configuration Structure definition + * @{ */ typedef struct { @@ -89,8 +93,14 @@ typedef struct }I2C_InitTypeDef; /** - * @brief HAL State structures definition + * @} + */ + +/** @defgroup HAL_state_structure_definition HAL state structure definition + * @brief HAL State structure definition + * @{ */ + typedef enum { HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */ @@ -107,82 +117,86 @@ typedef enum }HAL_I2C_StateTypeDef; /** - * @brief HAL I2C Error Code structure definition - */ -typedef enum -{ - HAL_I2C_ERROR_NONE = 0x00, /*!< No error */ - HAL_I2C_ERROR_BERR = 0x01, /*!< BERR error */ - HAL_I2C_ERROR_ARLO = 0x02, /*!< ARLO error */ - HAL_I2C_ERROR_AF = 0x04, /*!< ACKF error */ - HAL_I2C_ERROR_OVR = 0x08, /*!< OVR error */ - HAL_I2C_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_I2C_ERROR_TIMEOUT = 0x20, /*!< Timeout error */ - HAL_I2C_ERROR_SIZE = 0x40 /*!< Size Management error */ -}HAL_I2C_ErrorTypeDef; + * @} + */ +/** @defgroup I2C_Error_Code I2C Error Code + * @brief I2C Error Code + * @{ + */ +#define HAL_I2C_ERROR_NONE 0x00 /*!< No error */ +#define HAL_I2C_ERROR_BERR 0x01 /*!< BERR error */ +#define HAL_I2C_ERROR_ARLO 0x02 /*!< ARLO error */ +#define HAL_I2C_ERROR_AF 0x04 /*!< ACKF error */ +#define HAL_I2C_ERROR_OVR 0x08 /*!< OVR error */ +#define HAL_I2C_ERROR_DMA 0x10 /*!< DMA transfer error */ +#define HAL_I2C_ERROR_TIMEOUT 0x20 /*!< Timeout error */ +#define HAL_I2C_ERROR_SIZE 0x40 /*!< Size Management error */ /** + * @} + */ + +/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition * @brief I2C handle Structure definition + * @{ */ typedef struct { - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ErrorTypeDef ErrorCode; /* I2C Error code */ + I2C_TypeDef *Instance; /*!< I2C registers base address */ + + I2C_InitTypeDef Init; /*!< I2C communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ + + uint16_t XferSize; /*!< I2C transfer size */ + + __IO uint16_t XferCount; /*!< I2C transfer counter */ + + DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ + + HAL_LockTypeDef Lock; /*!< I2C locking object */ + + __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ + + __IO uint32_t ErrorCode; /*!< I2C Error code, see I2C_Error_Code */ }I2C_HandleTypeDef; +/** + * @} + */ +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup I2C_Exported_Constants +/** @defgroup I2C_Exported_Constants I2C Exported Constants * @{ */ -/** @defgroup I2C_addressing_mode +/** @defgroup I2C_addressing_mode I2C addressing mode * @{ */ #define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001) #define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002) - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) /** * @} */ -/** @defgroup I2C_dual_addressing_mode +/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode * @{ */ - -#define I2C_DUALADDRESS_DISABLED ((uint32_t)0x00000000) -#define I2C_DUALADDRESS_ENABLED I2C_OAR2_OA2EN - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLED)) +#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN /** * @} */ -/** @defgroup I2C_own_address2_masks +/** @defgroup I2C_own_address2_masks I2C own address2 masks * @{ */ - #define I2C_OA2_NOMASK ((uint8_t)0x00) #define I2C_OA2_MASK01 ((uint8_t)0x01) #define I2C_OA2_MASK02 ((uint8_t)0x02) @@ -191,89 +205,59 @@ typedef struct #define I2C_OA2_MASK05 ((uint8_t)0x05) #define I2C_OA2_MASK06 ((uint8_t)0x06) #define I2C_OA2_MASK07 ((uint8_t)0x07) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) /** * @} */ -/** @defgroup I2C_general_call_addressing_mode +/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode * @{ */ -#define I2C_GENERALCALL_DISABLED ((uint32_t)0x00000000) -#define I2C_GENERALCALL_ENABLED I2C_CR1_GCEN - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \ - ((CALL) == I2C_GENERALCALL_ENABLED)) +#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN /** * @} */ -/** @defgroup I2C_nostretch_mode +/** @defgroup I2C_nostretch_mode I2C nostretch mode * @{ */ -#define I2C_NOSTRETCH_DISABLED ((uint32_t)0x00000000) -#define I2C_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLED)) +#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH /** * @} */ -/** @defgroup I2C_Memory_Address_Size +/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size * @{ */ #define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001) #define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) /** * @} */ -/** @defgroup I2C_ReloadEndMode_definition +/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition * @{ */ - #define I2C_RELOAD_MODE I2C_CR2_RELOAD #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND #define I2C_SOFTEND_MODE ((uint32_t)0x00000000) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) /** * @} */ -/** @defgroup I2C_StartStopMode_definition +/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition * @{ */ - #define I2C_NO_STARTSTOP ((uint32_t)0x00000000) #define I2C_GENERATE_STOP I2C_CR2_STOP #define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) #define I2C_GENERATE_START_WRITE I2C_CR2_START - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_NO_STARTSTOP)) - /** * @} */ -/** @defgroup I2C_Interrupt_configuration_definition +/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition * @brief I2C Interrupt definition * Elements values convention: 0xXXXXXXXX * - XXXXXXXX : Interrupt control mask @@ -292,10 +276,9 @@ typedef struct */ -/** @defgroup I2C_Flag_definition +/** @defgroup I2C_Flag_definition I2C Flag definition * @{ */ - #define I2C_FLAG_TXE I2C_ISR_TXE #define I2C_FLAG_TXIS I2C_ISR_TXIS #define I2C_FLAG_RXNE I2C_ISR_RXNE @@ -312,28 +295,25 @@ typedef struct #define I2C_FLAG_ALERT I2C_ISR_ALERT #define I2C_FLAG_BUSY I2C_ISR_BUSY #define I2C_FLAG_DIR I2C_ISR_DIR - /** * @} */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ + +/** @defgroup I2C_Exported_Macros I2C Exported Macros + * @{ + */ /** @brief Reset I2C handle state * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. * @retval None */ #define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -/** @brief Enables or disables the specified I2C interrupts. +/** @brief Enable the specified I2C interrupts. * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__: specifies the interrupt source to enable. * This parameter can be one of the following values: * @arg I2C_IT_ERRI: Errors interrupt enable * @arg I2C_IT_TCI: Transfer complete interrupt enable @@ -347,11 +327,25 @@ typedef struct */ #define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) + +/** @brief Disable the specified I2C interrupts. + * @param __HANDLE__: specifies the I2C Handle. + * @param __INTERRUPT__: specifies the interrupt source to disable. + * This parameter can be one of the following values: + * @arg I2C_IT_ERRI: Errors interrupt enable + * @arg I2C_IT_TCI: Transfer complete interrupt enable + * @arg I2C_IT_STOPI: STOP detection interrupt enable + * @arg I2C_IT_NACKI: NACK received interrupt enable + * @arg I2C_IT_ADDRI: Address match interrupt enable + * @arg I2C_IT_RXI: RX interrupt enable + * @arg I2C_IT_TXI: TX interrupt enable + * + * @retval None + */ #define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) /** @brief Checks if the specified I2C interrupt source is enabled or disabled. * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. * @param __INTERRUPT__: specifies the I2C interrupt source to check. * This parameter can be one of the following values: * @arg I2C_IT_ERRI: Errors interrupt enable @@ -362,13 +356,12 @@ typedef struct * @arg I2C_IT_RXI: RX interrupt enable * @arg I2C_IT_TXI: TX interrupt enable * - * @retval The new state of __IT__ (TRUE or FALSE). + * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ #define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2C flag is set or not. * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg I2C_FLAG_TXE: Transmit data register empty @@ -391,11 +384,10 @@ typedef struct * @retval The new state of __FLAG__ (TRUE or FALSE). */ #define I2C_FLAG_MASK ((uint32_t)0x0001FFFF) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) +#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK))) /** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit. * @param __HANDLE__: specifies the I2C Handle. - * This parameter can be I2C where x: 1 or 2 to select the I2C peripheral. * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg I2C_FLAG_ADDR: Address matched (slave mode) @@ -410,34 +402,48 @@ typedef struct * * @retval None */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK)) +#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK)) +/** @brief Enable the specified I2C peripheral. + * @param __HANDLE__: specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) -#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) -#define __HAL_I2C_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) - -#define __HAL_I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) - -#define __HAL_I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) -#define __HAL_I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) - -#define __HAL_I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +/** @brief Disable the specified I2C peripheral. + * @param __HANDLE__: specifies the I2C Handle. + * @retval None + */ +#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) +/** + * @} + */ /* Include I2C HAL Extension module */ #include "stm32l0xx_hal_i2c_ex.h" /* Exported functions --------------------------------------------------------*/ -/* Initialization/de-initialization functions**********************************/ +/** @addtogroup I2C_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ +/* Initialization and de-initialization functions******************************/ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c); void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); +/** + * @} + */ -/* I/O operation functions ***************************************************/ +/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions + * @{ + */ +/* IO operation functions ****************************************************/ /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -462,7 +468,13 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *p HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size); +/** + * @} + */ +/** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks + * @{ + */ /******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); @@ -473,11 +485,97 @@ void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); +/** + * @} + */ -/* Peripheral State functions ************************************************/ +/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions + * @{ + */ +/* Peripheral State and Errors functions *************************************/ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c); uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); +/** + * @} + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ + +#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ + ((MODE) == I2C_ADDRESSINGMODE_10BIT)) + +#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) + +#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ + ((MASK) == I2C_OA2_MASK01) || \ + ((MASK) == I2C_OA2_MASK02) || \ + ((MASK) == I2C_OA2_MASK03) || \ + ((MASK) == I2C_OA2_MASK04) || \ + ((MASK) == I2C_OA2_MASK05) || \ + ((MASK) == I2C_OA2_MASK06) || \ + ((MASK) == I2C_OA2_MASK07)) + +#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ + ((CALL) == I2C_GENERALCALL_ENABLE)) + +#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ + ((STRETCH) == I2C_NOSTRETCH_ENABLE)) + +#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ + ((SIZE) == I2C_MEMADD_SIZE_16BIT)) + + +#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ + ((MODE) == I2C_AUTOEND_MODE) || \ + ((MODE) == I2C_SOFTEND_MODE)) + +#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ + ((REQUEST) == I2C_GENERATE_START_READ) || \ + ((REQUEST) == I2C_GENERATE_START_WRITE) || \ + ((REQUEST) == I2C_NO_STARTSTOP)) + + +#define __I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) + +#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) +#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF) + +#define __I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8))) +#define __I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) + +#define __I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ + (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) +/** + * @} + */ + +/* Private Fonctions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32l0xx_hal_i2c.c file */ +/** + * @} + */ + /** * @} */ @@ -494,3 +592,4 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c); #endif /* __STM32L0xx_HAL_I2C_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.c index c4ae751b082..a85bdd62726 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.c @@ -2,17 +2,16 @@ ****************************************************************************** * @file stm32l0xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 - * @brief Extended I2C HAL module driver. - * + * @version V1.2.0 + * @date 06-February-2015 + * @brief I2C Extended HAL module driver. * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Extended Control methods + * functionalities of I2C Extended peripheral: + * + Extended features functions * @verbatim ============================================================================== - ##### I2C peripheral extended features ##### + ##### I2C peripheral Extended features ##### ============================================================================== [..] Comparing to other previous devices, the I2C interface for STM32L0XX @@ -25,12 +24,19 @@ ##### How to use this driver ##### ============================================================================== [..] This driver provides functions to configure Noise Filter - + (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() + (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() + (#) Configure the enable or disable of I2C Wake Up Mode using the functions : + + HAL_I2CEx_EnableWakeUp() + + HAL_I2CEx_DisableWakeUp() + (#) Configure the enable or disable of fast mode plus driving capability using the functions : + + HAL_I2CEx_EnableFastModePlus() + + HAL_I2CEx_DisbleFastModePlus() @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,8 +70,8 @@ * @{ */ -/** @defgroup I2CEx - * @brief I2C HAL module driver +/** @defgroup I2CEx I2C Extended HAL module driver + * @brief I2C Extended HAL module driver * @{ */ @@ -78,17 +84,16 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup I2CEX_Private_Functions +/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions * @{ */ - -/** @defgroup I2CEX_Group1 Peripheral Control methods - * @brief management functions +/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions + * @brief Extended features functions * @verbatim =============================================================================== - ##### Peripheral Control methods ##### + ##### Extended features functions ##### =============================================================================== [..] This section provides functions allowing to: (+) Configure Noise Filters @@ -104,7 +109,7 @@ * @param AnalogFilter : new state of the Analog filter. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) { /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); @@ -147,7 +152,7 @@ HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_ * @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ -HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) { uint32_t tmpreg = 0; @@ -268,6 +273,60 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) return HAL_OK; } +/** + * @brief Enable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus: selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be enabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be enabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Enable fast mode plus driving capability for selected pin */ + SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + +/** + * @brief Disable the I2C fast mode plus driving capability. + * @param ConfigFastModePlus: selects the pin. + * This parameter can be one of the @ref I2CEx_FastModePlus values + * @note For I2C1, fast mode plus driving capability can be disabled on all selected + * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently + * on each one of the following pins PB6, PB7, PB8 and PB9. + * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability + * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. + * @note For all I2C2 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C2 parameter. + * @note For all I2C3 pins fast mode plus driving capability can be disabled + * only by using I2C_FASTMODEPLUS_I2C3 parameter. + * @retval None + */ +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) +{ + /* Check the parameter */ + assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); + + /* Enable SYSCFG clock */ + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + /* Disable fast mode plus driving capability for selected pin */ + CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); +} + /** * @} */ @@ -286,3 +345,4 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.h index 726655eda9c..9d63353ae24 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2c_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,19 +64,26 @@ /** @defgroup I2CEx_Analog_Filter * @{ */ -#define I2C_ANALOGFILTER_ENABLED ((uint32_t)0x00000000) -#define I2C_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF - -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLED) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLED)) +#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /** * @} */ -/** @defgroup I2CEx_Digital_Filter +/** @defgroup I2CEx_FastModePlus * @{ */ -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR2_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ +#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR2_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ +#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR2_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ +#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR2_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ +#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR2_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ +#if !defined(STM32L031xx) && !defined(STM32L041xx) +#define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR2_I2C2_FMP /*!< Enable Fast Mode Plus on I2C2 pins */ +#endif +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) +#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR2_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ +#endif /** * @} */ @@ -89,19 +96,74 @@ /* Exported functions --------------------------------------------------------*/ /* Peripheral Control methods ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_AnalogFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_DigitalFilter_Config(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp (I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); +HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); +HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); +HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); +void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); +void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Constants I2C Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2C_Private_Macro I2C Private Macros + * @{ + */ +#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ + ((FILTER) == I2C_ANALOGFILTER_DISABLE)) + +#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F) +#if defined(STM32L031xx) || defined(STM32L041xx) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1)) +#elif defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)) +#else +#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ + (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2)) +#endif /** * @} */ +/* Private Fonctions ---------------------------------------------------------*/ +/** @defgroup I2C_Private_Functions I2C Private Functions + * @{ + */ +/* Private functions are defined in stm32l0xx_hal_i2c_ex.c file */ /** * @} */ +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif @@ -110,3 +172,4 @@ HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp (I2C_HandleTypeDef *hi2c); /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c index fd16faa4bb0..f2773565e7f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.c @@ -2,10 +2,9 @@ ****************************************************************************** * @file stm32l0xx_hal_i2s.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief I2S HAL module driver. - * * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: * + Initialization and de-initialization functions @@ -17,34 +16,38 @@ =============================================================================== [..] The I2S HAL driver can be used as follow: - + (#) Declare a I2S_HandleTypeDef handle structure. (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: - (##) Enable the SPIx interface clock. + (##) Enable the SPIx interface clock. (##) I2S pins configuration: (+++) Enable the clock for the I2S GPIOs. - (+++) Configure these I2S pins as alternate function pull-up. + (+++) Configure these I2S pins as alternate function. (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() and HAL_I2S_Receive_IT() APIs). (+++) Configure the I2Sx interrupt priority. (+++) Enable the NVIC I2S IRQ handle. (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() and HAL_I2S_Receive_DMA() APIs: - (+++) Declare a DMA handle structure for the Tx/Rx stream. + (+++) Declare a DMA handle structure for the Tx/Rx Channel. (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx Stream. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx Channel. (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle. (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the - DMA Tx/Rx Stream. + DMA Tx/Rx Channel. (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity using HAL_I2S_Init() function. -@- The specific I2S interrupts (Transmission complete interrupt, RXNE interrupt and Error Interrupts) will be managed using the macros - __I2S_ENABLE_IT() and __I2S_DISABLE_IT() inside the transmit and receive process. - (#) Three mode of operations are available within this driver : + __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. + -@- Make sure that either: + (+@) External clock source is configured after setting correctly + the define constant HSE_VALUE in the stm32l0xx_hal_conf.h file. + + (#) Three mode of operations are available within this driver : *** Polling mode IO operation *** ================================= @@ -56,12 +59,16 @@ =================================== [..] (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() - (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can + (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback + (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_I2S_TxCpltCallback - (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() - (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can + (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() + (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can + add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback + (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can add his own code by customization of function pointer HAL_I2S_RxCpltCallback - (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can + (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can add his own code by customization of function pointer HAL_I2S_ErrorCallback *** DMA mode IO operation *** @@ -101,7 +108,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -128,34 +135,48 @@ ****************************************************************************** */ +#if !defined(STM32L031xx) && !defined(STM32L041xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#ifdef HAL_I2S_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup I2S +/** @defgroup I2S I2S * @brief I2S HAL module driver * @{ */ -#ifdef HAL_I2S_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); -static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s); -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2S_Private_Functions +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void I2S_DMAError(DMA_HandleTypeDef *hdma); +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout); +/** + * @} + */ + +/* Exported functions ---------------------------------------------------------*/ +/** @defgroup I2S_Exported_Functions I2S Exported Functions * @{ */ -/** @defgroup I2S_Group1 Initialization and de-initialization functions +/** @defgroup I2S_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -177,9 +198,9 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s); (++) Audio frequency (++) Polarity - (+) Call the function HAL_I2S_DeInit() to restore the default configuration - of the selected I2Sx periperal. -@endverbatim + (+) Call the function HAL_I2S_DeInit() to restore the default configuration + of the selected I2Sx periperal. + @endverbatim * @{ */ @@ -192,16 +213,17 @@ static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s); */ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) { - uint32_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; - uint32_t tmp = 0, i2sclk = 0; + uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0, i2sclk = 0, tmpreg = 0; /* Check the I2S handle allocation */ - if(hi2s == HAL_NULL) + if(hi2s == NULL) { return HAL_ERROR; } /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); assert_param(IS_I2S_MODE(hi2s->Init.Mode)); assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); @@ -216,33 +238,31 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) } hi2s->State = HAL_I2S_STATE_BUSY; - - /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/ - /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ - hi2s->Instance->I2SCFGR &= (uint32_t)~((uint32_t)SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ - SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ - SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD); - hi2s->Instance->I2SPR = 0x0002; - /* Get the I2SCFGR register value */ - tmpreg = hi2s->Instance->I2SCFGR; - - /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */ + /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/ + if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT) + { + i2sodd = (uint32_t)0; + i2sdiv = (uint32_t)2; + } /* If the requested audio frequency is not the default, compute the prescaler */ - if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) + else { /* Check the frame length (For the Prescaler computing) *******************/ - if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) + if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B) + { + /* Packet length is 16 bits */ + packetlength = 1; + } + else { /* Packet length is 32 bits */ packetlength = 2; } - /* Get I2S source Clock frequency ****************************************/ - /* I2S clock source is SystemClock for stm32l0xx devices */ - - i2sclk = HAL_RCC_GetSysClockFreq(); - + /* Get the source clock value: based on System Clock value */ + i2sclk = HAL_RCC_GetSysClockFreq(); + /* Compute the Real divider depending on the MCLK output state, with a floating point */ if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) { @@ -275,19 +295,44 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) i2sdiv = 2; i2sodd = 0; } - + + /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/ + /* Write to SPIx I2SPR register the computed value */ hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); - /* Configure the I2S with the I2S_InitStruct values */ - tmpreg |= (uint32_t)(SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode | hi2s->Init.Standard | hi2s->Init.DataFormat | hi2s->Init.CPOL); + /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ + /* And configure the I2S with the I2S_InitStruct values */ + MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\ + SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\ + SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD),\ + (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\ + hi2s->Init.Standard | hi2s->Init.DataFormat |\ + hi2s->Init.CPOL)); + + /* Get the I2SCFGR register value */ + tmpreg = hi2s->Instance->I2SCFGR; +#if defined(SPI_I2SCFGR_ASTRTEN) + if (hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) + { + /* Write to SPIx I2SCFGR */ + hi2s->Instance->I2SCFGR = tmpreg | SPI_I2SCFGR_ASTRTEN; + } + else + { + /* Write to SPIx I2SCFGR */ + hi2s->Instance->I2SCFGR = tmpreg; + } +#else /* Write to SPIx I2SCFGR */ hi2s->Instance->I2SCFGR = tmpreg; - +#endif + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; hi2s->State= HAL_I2S_STATE_READY; - + return HAL_OK; } @@ -300,16 +345,19 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) { /* Check the I2S handle allocation */ - if(hi2s == HAL_NULL) + if(hi2s == NULL) { return HAL_ERROR; } hi2s->State = HAL_I2S_STATE_BUSY; + /* Disable the I2S Peripheral Clock */ + __HAL_I2S_DISABLE(hi2s); + /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ HAL_I2S_MspDeInit(hi2s); - + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; hi2s->State = HAL_I2S_STATE_RESET; @@ -328,7 +376,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspInit could be implenetd in the user file + the HAL_I2S_MspInit could be implemented in the user file */ } @@ -341,7 +389,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_MspDeInit could be implenetd in the user file + the HAL_I2S_MspDeInit could be implemented in the user file */ } @@ -349,7 +397,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) * @} */ -/** @defgroup I2S_Group2 IO operation functions +/** @defgroup I2S_Exported_Functions_Group2 IO operation functions * @brief Data transfers functions * @verbatim @@ -360,7 +408,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) This subsection provides a set of functions allowing to manage the I2S data transfers. - (#) There is two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode : The communication is performed in the polling mode. The status of all data processing is returned by the same function after finishing transfer. @@ -382,7 +430,7 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) (++) HAL_I2S_Transmit_DMA() (++) HAL_I2S_Receive_DMA() - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_I2S_TxCpltCallback() (++) HAL_I2S_RxCpltCallback() (++) HAL_I2S_ErrorCallback() @@ -404,40 +452,40 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) * @param Timeout: Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). - * @note This function can use an Audio Frequency up to 44KHz when I2S Clock Source is 32MHz + * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tmp1 = 0, tmp2 = 0; - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { - return HAL_ERROR; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hi2s); + if(hi2s->State == HAL_I2S_STATE_READY) { - tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - if((tmp1 == I2S_DATAFORMAT_24B)|| \ - (tmp2 == I2S_DATAFORMAT_32B)) + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = Size*2; - hi2s->TxXferCount = Size*2; + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); } else { hi2s->TxXferSize = Size; hi2s->TxXferCount = Size; } - - /* Process Locked */ - __HAL_LOCK(hi2s); - + + /* Set state and reset error code */ + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; hi2s->State = HAL_I2S_STATE_BUSY_TX; - + hi2s->pTxBuffPtr = pData; + /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); @@ -445,13 +493,19 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin while(hi2s->TxXferCount > 0) { - hi2s->Instance->DR = (*pData++); - hi2s->TxXferCount--; /* Wait until TXE flag is set */ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) { return HAL_TIMEOUT; } + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; + } + + /* Wait until TXE flag is set, to confirm the end of the transaction */ + if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; } /* Wait until Busy flag is reset */ if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK) @@ -468,6 +522,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); return HAL_BUSY; } } @@ -492,32 +548,33 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin */ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) { - uint32_t tmp1 = 0, tmp2 = 0; - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hi2s); + if(hi2s->State == HAL_I2S_STATE_READY) { - tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - if((tmp1 == I2S_DATAFORMAT_24B)|| \ - (tmp2 == I2S_DATAFORMAT_32B)) + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = Size*2; - hi2s->RxXferCount = Size*2; + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); } else { hi2s->RxXferSize = Size; hi2s->RxXferCount = Size; } - /* Process Locked */ - __HAL_LOCK(hi2s); - + + /* Set state and reset error code */ + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; hi2s->State = HAL_I2S_STATE_BUSY_RX; - + hi2s->pRxBuffPtr = pData; + /* Check if the I2S is already enabled */ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) { @@ -541,11 +598,11 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint { return HAL_TIMEOUT; } - - (*pData++) = hi2s->Instance->DR; + + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; hi2s->RxXferCount--; } - + hi2s->State = HAL_I2S_STATE_READY; /* Process Unlocked */ @@ -555,6 +612,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); return HAL_BUSY; } } @@ -571,27 +630,30 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint * the Size parameter means the number of 16-bit data length. * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). - * @note This function can use an Audio Frequency up to 32KHz when I2S Clock Source is 32MHz + * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - uint32_t tmp1 = 0, tmp2 = 0; + if((pData == NULL) || (Size == 0)) + { + return HAL_ERROR; + } + + /* Process Locked */ + __HAL_LOCK(hi2s); + if(hi2s->State == HAL_I2S_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) - { - return HAL_ERROR; - } - hi2s->pTxBuffPtr = pData; - tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - if((tmp1 == I2S_DATAFORMAT_24B)|| \ - (tmp2 == I2S_DATAFORMAT_32B)) + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = Size*2; - hi2s->TxXferCount = Size*2; + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); } else { @@ -599,12 +661,6 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->TxXferCount = Size; } - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - /* Enable TXE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); @@ -622,6 +678,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); return HAL_BUSY; } } @@ -640,40 +698,38 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, * between Master and Slave(example: audio streaming). * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation * between Master and Slave otherwise the I2S interrupt should be optimized. - * @note This function can use an Audio Frequency up to 32KHz when I2S Clock Source is 32MHz + * @note This function can use an Audio Frequency up to 48KHz when I2S Clock Source is 32MHz * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - uint32_t tmp1 = 0, tmp2 = 0; - if(hi2s->State == HAL_I2S_STATE_READY) - { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hi2s); + + if(hi2s->State == HAL_I2S_STATE_READY) + { hi2s->pRxBuffPtr = pData; - tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - if((tmp1 == I2S_DATAFORMAT_24B)||\ - (tmp2 == I2S_DATAFORMAT_32B)) + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = Size*2; - hi2s->RxXferCount = Size*2; - } + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); + } else { hi2s->RxXferSize = Size; hi2s->RxXferCount = Size; } - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - /* Enable TXE and ERR interrupt */ + /* Enable RXNE and ERR interrupt */ __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); /* Check if the I2S is already enabled */ @@ -688,9 +744,10 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u return HAL_OK; } - else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); return HAL_BUSY; } } @@ -711,24 +768,25 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u */ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - uint32_t *tmp; - uint32_t tmp1 = 0, tmp2 = 0; - - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hi2s); + if(hi2s->State == HAL_I2S_STATE_READY) { hi2s->pTxBuffPtr = pData; - tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - if((tmp1 == I2S_DATAFORMAT_24B)|| \ - (tmp2 == I2S_DATAFORMAT_32B)) + hi2s->State = HAL_I2S_STATE_BUSY_TX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->TxXferSize = Size*2; - hi2s->TxXferCount = Size*2; + hi2s->TxXferSize = (Size << 1); + hi2s->TxXferCount = (Size << 1); } else { @@ -736,12 +794,6 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, hi2s->TxXferCount = Size; } - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->State = HAL_I2S_STATE_BUSY_TX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - /* Set the I2S Tx DMA Half transfert complete callback */ hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; @@ -751,22 +803,21 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, /* Set the DMA error callback */ hi2s->hdmatx->XferErrorCallback = I2S_DMAError; - /* Enable the Tx DMA Stream */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); + /* Enable the Tx DMA Channel */ + HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); } - /* Check if the I2S Tx request is already enabled */ - if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN) + /* Check if the I2S Tx request is already enabled */ + if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_TXDMAEN)) { /* Enable Tx DMA Request */ - hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } /* Process Unlocked */ @@ -776,6 +827,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); return HAL_BUSY; } } @@ -796,45 +849,42 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, */ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) { - uint32_t *tmp; - uint32_t tmp1 = 0, tmp2 = 0; - - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hi2s); + if(hi2s->State == HAL_I2S_STATE_READY) { hi2s->pRxBuffPtr = pData; - tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - tmp2 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); - if((tmp1 == I2S_DATAFORMAT_24B)|| \ - (tmp2 == I2S_DATAFORMAT_32B)) + hi2s->State = HAL_I2S_STATE_BUSY_RX; + hi2s->ErrorCode = HAL_I2S_ERROR_NONE; + + if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\ + ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B)) { - hi2s->RxXferSize = Size*2; - hi2s->RxXferCount = Size*2; + hi2s->RxXferSize = (Size << 1); + hi2s->RxXferCount = (Size << 1); } else { hi2s->RxXferSize = Size; hi2s->RxXferCount = Size; } - /* Process Locked */ - __HAL_LOCK(hi2s); - - hi2s->State = HAL_I2S_STATE_BUSY_RX; - hi2s->ErrorCode = HAL_I2S_ERROR_NONE; - + + /* Set the I2S Rx DMA Half transfert complete callback */ hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; - + /* Set the I2S Rx DMA transfert complete callback */ hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; - + /* Set the DMA error callback */ hi2s->hdmarx->XferErrorCallback = I2S_DMAError; - + /* Check if Master Receiver mode is selected */ if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) { @@ -842,23 +892,22 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, access to the SPI_SR register. */ __HAL_I2S_CLEAR_OVRFLAG(hi2s); } - - /* Enable the Rx DMA Stream */ - tmp = (uint32_t*)&pData; - HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize); - + + /* Enable the Rx DMA Channel */ + HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize); + /* Check if the I2S is already enabled */ - if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) + if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); } /* Check if the I2S Rx request is already enabled */ - if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN) + if(HAL_IS_BIT_CLR(hi2s->Instance->CR2, SPI_CR2_RXDMAEN)) { /* Enable Rx DMA Request */ - hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); } /* Process Unlocked */ @@ -868,6 +917,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, } else { + /* Process Unlocked */ + __HAL_UNLOCK(hi2s); return HAL_BUSY; } } @@ -876,7 +927,7 @@ HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, * @brief Pauses the audio stream playing from the Media. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) { @@ -886,12 +937,12 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) if(hi2s->State == HAL_I2S_STATE_BUSY_TX) { /* Disable the I2S DMA Tx request */ - hi2s->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) { /* Disable the I2S DMA Rx request */ - hi2s->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_RXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); } /* Process Unlocked */ @@ -904,7 +955,7 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) * @brief Resumes the audio stream playing from the Media. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) { @@ -914,16 +965,16 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) if(hi2s->State == HAL_I2S_STATE_BUSY_TX) { /* Enable the I2S DMA Tx request */ - hi2s->Instance->CR2 |= SPI_CR2_TXDMAEN; + SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); } else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) { /* Enable the I2S DMA Rx request */ - hi2s->Instance->CR2 |= SPI_CR2_RXDMAEN; + SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); } - + /* If the I2S peripheral is still not enabled, enable it */ - if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0) + if(HAL_IS_BIT_CLR(hi2s->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) { /* Enable I2S peripheral */ __HAL_I2S_ENABLE(hi2s); @@ -936,10 +987,10 @@ HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) } /** - * @brief Resumes the audio stream playing from the Media. + * @brief Stops the audio stream playing from the Media. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @retval None + * @retval HAL status */ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) { @@ -947,17 +998,21 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) __HAL_LOCK(hi2s); /* Disable the I2S Tx/Rx DMA requests */ - hi2s->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_TXDMAEN); - hi2s->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_RXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); - /* Abort the I2S DMA Stream tx */ - if(hi2s->hdmatx != HAL_NULL) + /* Abort the I2S DMA Channel tx */ + if(hi2s->hdmatx != NULL) { + /* Disable the I2S DMA channel */ + __HAL_DMA_DISABLE(hi2s->hdmatx); HAL_DMA_Abort(hi2s->hdmatx); } - /* Abort the I2S DMA Stream rx */ - if(hi2s->hdmarx != HAL_NULL) + /* Abort the I2S DMA Channel rx */ + if(hi2s->hdmarx != NULL) { + /* Disable the I2S DMA channel */ + __HAL_DMA_DISABLE(hi2s->hdmarx); HAL_DMA_Abort(hi2s->hdmarx); } @@ -976,55 +1031,53 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) * @brief This function handles I2S interrupt request. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @retval HAL status + * @retval None */ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) -{ - uint32_t tmp1 = 0, tmp2 = 0; - if(hi2s->State == HAL_I2S_STATE_BUSY_RX) +{ + uint32_t i2ssr = hi2s->Instance->SR; + + /* I2S in mode Receiver ------------------------------------------------*/ + if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) && + ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) { - tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_RXNE); - tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE); - /* I2S in mode Receiver --------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - I2S_Receive_IT(hi2s); - } - tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR); - tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); - /* I2S Overrun error interrupt occured -----------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) - { - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - hi2s->ErrorCode |= HAL_I2S_ERROR_OVR; - } + I2S_Receive_IT(hi2s); + return; } - if(hi2s->State == HAL_I2S_STATE_BUSY_TX) + /* I2S in mode Tramitter -----------------------------------------------*/ + if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) + { + I2S_Transmit_IT(hi2s); + return; + } + + /* I2S interrupt error -------------------------------------------------*/ + if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET) { - tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_TXE); - tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE); - /* I2S in mode Tramitter -------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + /* I2S Overrun error interrupt occured ---------------------------------*/ + if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) { - I2S_Transmit_IT(hi2s); + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); } - - tmp1 = __HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR); - tmp2 = __HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR); - /* I2S Underrun error interrupt occured ----------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + + /* I2S Underrun error interrupt occured --------------------------------*/ + if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) { - __HAL_I2S_CLEAR_UDRFLAG(hi2s); - hi2s->ErrorCode |= HAL_I2S_ERROR_UDR; + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); } - } - - /* Call the Error call Back in case of Errors */ - if(hi2s->ErrorCode != HAL_I2S_ERROR_NONE) - { - /* Set the I2S state ready to be able to start again the process */ - hi2s->State= HAL_I2S_STATE_READY; + + /* Set the I2S State ready */ + hi2s->State = HAL_I2S_STATE_READY; + /* Call the Error Callback */ HAL_I2S_ErrorCallback(hi2s); } } @@ -1038,7 +1091,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxHalfCpltCallback could be implenetd in the user file + the HAL_I2S_TxHalfCpltCallback could be implemented in the user file */ } @@ -1051,7 +1104,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_TxCpltCallback could be implenetd in the user file + the HAL_I2S_TxCpltCallback could be implemented in the user file */ } @@ -1064,7 +1117,7 @@ void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxCpltCallback could be implenetd in the user file + the HAL_I2S_RxHalfCpltCallback could be implemented in the user file */ } @@ -1077,7 +1130,7 @@ __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_RxCpltCallback could be implenetd in the user file + the HAL_I2S_RxCpltCallback could be implemented in the user file */ } @@ -1090,7 +1143,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_I2S_ErrorCallback could be implenetd in the user file + the HAL_I2S_ErrorCallback could be implemented in the user file */ } @@ -1098,7 +1151,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) * @} */ -/** @defgroup I2S_Group3 Peripheral State and Errors functions +/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions * @brief Peripheral State functions * @verbatim @@ -1106,7 +1159,7 @@ __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) ##### Peripheral State and Errors functions ##### =============================================================================== [..] - This subsection permit to get in run-time the status of the peripheral + This subsection permits to get in run-time the status of the peripheral and the data flow. @endverbatim @@ -1130,42 +1183,50 @@ HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) * the configuration information for I2S module * @retval I2S Error Code */ -HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) { return hi2s->ErrorCode; } +/** + * @} + */ /** * @} */ +/* Private functions ---------------------------------------------------------*/ +/** @addtogroup I2S_Private_Functions I2S Private Functions + * @{ + */ /** * @brief DMA I2S transmit process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) +static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - hi2s->TxXferCount = 0; - /* Disable Tx DMA Request */ - hi2s->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_TXDMAEN); + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); - hi2s->State = HAL_I2S_STATE_READY; + hi2s->TxXferCount = 0; + hi2s->State = HAL_I2S_STATE_READY; } HAL_I2S_TxCpltCallback(hi2s); } /** * @brief DMA I2S transmit process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; @@ -1174,31 +1235,31 @@ void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S receive process complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) +static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if(HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { /* Disable Rx DMA Request */ - hi2s->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_RXDMAEN); - + CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN); hi2s->RxXferCount = 0; - - hi2s->State = HAL_I2S_STATE_READY; + hi2s->State = HAL_I2S_STATE_READY; } HAL_I2S_RxCpltCallback(hi2s); } /** * @brief DMA I2S receive process half complete callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; @@ -1207,19 +1268,23 @@ void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) /** * @brief DMA I2S communication error callback - * @param hdma : DMA handle + * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA module. * @retval None */ -void I2S_DMAError(DMA_HandleTypeDef *hdma) +static void I2S_DMAError(DMA_HandleTypeDef *hdma) { I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; + /* Disable Rx and Tx DMA Request */ + CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); hi2s->TxXferCount = 0; hi2s->RxXferCount = 0; hi2s->State= HAL_I2S_STATE_READY; - hi2s->ErrorCode |= HAL_I2S_ERROR_DMA; + /* Set the error code and execute error callback*/ + SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA); HAL_I2S_ErrorCallback(hi2s); } @@ -1227,87 +1292,60 @@ void I2S_DMAError(DMA_HandleTypeDef *hdma) * @brief Transmit an amount of data in non-blocking mode with Interrupt * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @retval HAL status + * @retval None */ -static HAL_StatusTypeDef I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) +static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) { - if(hi2s->State == HAL_I2S_STATE_BUSY_TX) - { - /* Transmit data */ - hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); - - hi2s->TxXferCount--; + /* Transmit data */ + hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); + hi2s->TxXferCount--; - if(hi2s->TxXferCount == 0) - { - /* Disable TXE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (uint32_t)(I2S_IT_TXE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; - - HAL_I2S_TxCpltCallback(hi2s); - } - return HAL_OK; - } - else + if(hi2s->TxXferCount == 0) { - return HAL_BUSY; + /* Disable TXE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); + + hi2s->State = HAL_I2S_STATE_READY; + HAL_I2S_TxCpltCallback(hi2s); } } /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains - * the configuration information for I2S module - * @retval HAL status + * @param hi2s: I2S handle + * @retval None */ -static HAL_StatusTypeDef I2S_Receive_IT(I2S_HandleTypeDef *hi2s) +static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) { - if(hi2s->State == HAL_I2S_STATE_BUSY_RX) + /* Receive data */ + (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; + hi2s->RxXferCount--; + + if(hi2s->RxXferCount == 0) { - /* Receive data */ - (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; - - hi2s->RxXferCount--; - - /* Check if Master Receiver mode is selected */ - if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) - { - /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read - access to the SPI_SR register. */ - __HAL_I2S_CLEAR_OVRFLAG(hi2s); - } - - if(hi2s->RxXferCount == 0) - { - /* Disable RXNE and ERR interrupt */ - __HAL_I2S_DISABLE_IT(hi2s, (uint32_t)(I2S_IT_RXNE | I2S_IT_ERR)); - - hi2s->State = HAL_I2S_STATE_READY; + /* Disable RXNE and ERR interrupt */ + __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); - HAL_I2S_RxCpltCallback(hi2s); - } - - return HAL_OK; + hi2s->State = HAL_I2S_STATE_READY; + HAL_I2S_RxCpltCallback(hi2s); } - else - { - return HAL_BUSY; - } } + /** * @brief This function handles I2S Communication Timeout. * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @param Flag: Flag checked - * @param State: Value of the flag expected + * @param Status: Value of the flag expected * @param Timeout: Duration of the timeout * @retval HAL status */ -HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout) +static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0; + + /* Get tick */ tickstart = HAL_GetTick(); /* Wait until flag is set */ @@ -1315,15 +1353,16 @@ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_ { while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET) { - /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hi2s); + return HAL_TIMEOUT; } } @@ -1333,15 +1372,16 @@ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_ { while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET) { - /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Set the I2S State ready */ hi2s->State= HAL_I2S_STATE_READY; + /* Process Unlocked */ __HAL_UNLOCK(hi2s); + return HAL_TIMEOUT; } } @@ -1354,7 +1394,6 @@ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_ * @} */ -#endif /* HAL_I2S_MODULE_ENABLED */ /** * @} */ @@ -1363,4 +1402,8 @@ HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_ * @} */ +#endif /* HAL_I2S_MODULE_ENABLED */ +#endif /* #if !defined(STM32L031xx) && !defined(STM32L041xx) */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.h index 573a6e9de65..ed0af6c0fa7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_i2s.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_i2s.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,6 +43,7 @@ extern "C" { #endif +#if !defined (STM32L031xx) && !defined (STM32L041xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" @@ -55,6 +56,10 @@ */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_Types I2S Exported Types + * @{ + */ + /** * @brief I2S Init structure definition */ @@ -85,130 +90,130 @@ typedef struct */ typedef enum { - HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ - HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ - HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ - HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ - HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ - HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */ - HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ - + HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */ + HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */ + HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */ + HAL_I2S_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */ + HAL_I2S_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */ + HAL_I2S_STATE_TIMEOUT = 0x03, /*!< I2S timeout state */ + HAL_I2S_STATE_ERROR = 0x04 /*!< I2S error state */ }HAL_I2S_StateTypeDef; -/** - * @brief HAL I2S Error Code structure definition - */ -typedef enum -{ - HAL_I2S_ERROR_NONE = 0x00, /*!< No error */ - HAL_I2S_ERROR_UDR = 0x01, /*!< I2S Underrun error */ - HAL_I2S_ERROR_OVR = 0x02, /*!< I2S Overrun error */ - HAL_I2S_ERROR_FRE = 0x10, /*!< I2S Frame format error */ - HAL_I2S_ERROR_DMA = 0x20 /*!< DMA transfer error */ -}HAL_I2S_ErrorTypeDef; - /** * @brief I2S handle Structure definition */ typedef struct { - SPI_TypeDef *Instance; /* I2S registers base address */ - - I2S_InitTypeDef Init; /* I2S communication parameters */ + SPI_TypeDef *Instance; /* I2S registers base address */ - uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer*/ - - __IO uint16_t TxXferSize; /* I2S Tx transfer size */ - - __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */ - - uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer*/ - - __IO uint16_t RxXferSize; /* I2S Rx transfer size */ - - __IO uint16_t RxXferCount; /* I2S Rx transfer counter */ - - DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */ + I2S_InitTypeDef Init; /* I2S communication parameters */ + + uint16_t *pTxBuffPtr; /* Pointer to I2S Tx transfer buffer */ + + __IO uint16_t TxXferSize; /* I2S Tx transfer size */ + + __IO uint16_t TxXferCount; /* I2S Tx transfer Counter */ + + uint16_t *pRxBuffPtr; /* Pointer to I2S Rx transfer buffer */ + + __IO uint16_t RxXferSize; /* I2S Rx transfer size */ + + __IO uint16_t RxXferCount; /* I2S Rx transfer counter + (This field is initialized at the + same value as transfer size at the + beginning of the transfer and + decremented when a sample is received. + NbSamplesReceived = RxBufferSize-RxBufferCount) */ - __IO HAL_LockTypeDef Lock; /* I2S locking object */ + DMA_HandleTypeDef *hdmatx; /* I2S Tx DMA handle parameters */ - __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ + DMA_HandleTypeDef *hdmarx; /* I2S Rx DMA handle parameters */ + + __IO HAL_LockTypeDef Lock; /* I2S locking object */ + + __IO HAL_I2S_StateTypeDef State; /* I2S communication state */ - __IO HAL_I2S_ErrorTypeDef ErrorCode; /* I2S Error code */ + __IO uint32_t ErrorCode; /* I2S Error code */ }I2S_HandleTypeDef; +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2S_Exported_Constants +/** @defgroup I2S_Exported_Constants I2S Exported Constants * @{ - */ + */ -/** @defgroup I2S_Mode +/** + * @defgroup I2S_ErrorCode I2S Error Code * @{ */ -#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000) -#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100) -#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200) -#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300) - -#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ - ((MODE) == I2S_MODE_SLAVE_RX) || \ - ((MODE) == I2S_MODE_MASTER_TX) || \ - ((MODE) == I2S_MODE_MASTER_RX)) +#define HAL_I2S_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_I2S_ERROR_UDR ((uint32_t)0x01) /*!< I2S Underrun error */ +#define HAL_I2S_ERROR_OVR ((uint32_t)0x02) /*!< I2S Overrun error */ +#define HAL_I2S_ERROR_FRE ((uint32_t)0x04) /*!< I2S Frame format error */ +#define HAL_I2S_ERROR_DMA ((uint32_t)0x08) /*!< DMA transfer error */ + /** + * @} + */ + +/** @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MODE_SLAVE_TX ((uint32_t) 0x00000000) +#define I2S_MODE_SLAVE_RX ((uint32_t) SPI_I2SCFGR_I2SCFG_0) +#define I2S_MODE_MASTER_TX ((uint32_t) SPI_I2SCFGR_I2SCFG_1) +#define I2S_MODE_MASTER_RX ((uint32_t)(SPI_I2SCFGR_I2SCFG_0 |\ + SPI_I2SCFGR_I2SCFG_1)) /** * @} */ -/** @defgroup I2S_Standard +/** @defgroup I2S_Standard I2S Standard * @{ */ -#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000) -#define I2S_STANDARD_MSB ((uint32_t)0x00000010) -#define I2S_STANDARD_LSB ((uint32_t)0x00000020) -#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030) -#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0) +#define I2S_STANDARD_PHILIPS ((uint32_t) 0x00000000) +#define I2S_STANDARD_MSB ((uint32_t) SPI_I2SCFGR_I2SSTD_0) +#define I2S_STANDARD_LSB ((uint32_t) SPI_I2SCFGR_I2SSTD_1) +#define I2S_STANDARD_PCM_SHORT ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ + SPI_I2SCFGR_I2SSTD_1)) +#define I2S_STANDARD_PCM_LONG ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\ + SPI_I2SCFGR_I2SSTD_1 |\ + SPI_I2SCFGR_PCMSYNC)) +/** @defgroup I2S_Legacy I2S Legacy + * @{ + */ +#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS +/** + * @} + */ -#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ - ((STANDARD) == I2S_STANDARD_MSB) || \ - ((STANDARD) == I2S_STANDARD_LSB) || \ - ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ - ((STANDARD) == I2S_STANDARD_PCM_LONG)) /** * @} */ -/** @defgroup I2S_Data_Format +/** @defgroup I2S_Data_Format I2S Data Format * @{ */ -#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000) -#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001) -#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003) -#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005) - -#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ - ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ - ((FORMAT) == I2S_DATAFORMAT_24B) || \ - ((FORMAT) == I2S_DATAFORMAT_32B)) +#define I2S_DATAFORMAT_16B ((uint32_t) 0x00000000) +#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t) SPI_I2SCFGR_CHLEN) +#define I2S_DATAFORMAT_24B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)) +#define I2S_DATAFORMAT_32B ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)) /** * @} */ -/** @defgroup I2S_MCLK_Output +/** @defgroup I2S_MCLK_Output I2S MCLK Output * @{ */ #define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE) #define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000) - -#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ - ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) /** * @} */ -/** @defgroup I2S_Audio_Frequency +/** @defgroup I2S_Audio_Frequency I2S Audio Frequency * @{ */ #define I2S_AUDIOFREQ_192K ((uint32_t)192000) @@ -221,27 +226,20 @@ typedef struct #define I2S_AUDIOFREQ_11K ((uint32_t)11025) #define I2S_AUDIOFREQ_8K ((uint32_t)8000) #define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2) - -#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ - ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ - ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) /** * @} */ -/** @defgroup I2S_Clock_Polarity +/** @defgroup I2S_Clock_Polarity I2S Clock Polarity * @{ */ #define I2S_CPOL_LOW ((uint32_t)0x00000000) #define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL) - -#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ - ((CPOL) == I2S_CPOL_HIGH)) /** * @} */ -/** @defgroup I2S_Interrupt_configuration_definition +/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition * @{ */ #define I2S_IT_TXE SPI_CR2_TXEIE @@ -251,7 +249,7 @@ typedef struct * @} */ -/** @defgroup I2S_Flag_definition +/** @defgroup I2S_Flag_definition I2S Flag definition * @{ */ #define I2S_FLAG_TXE SPI_SR_TXE @@ -272,21 +270,29 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2S_Exported_macros I2S Exported Macros + * @{ + */ -/** @brief Reset I2S handle state +/** @brief Reset I2S handle state * @param __HANDLE__: specifies the I2S Handle. * @retval None */ #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) -/** @brief Enable or disable the specified SPI peripheral (in I2S mode). +/** @brief Enable the specified SPI peripheral (in I2S mode). + * @param __HANDLE__: specifies the I2S Handle. + * @retval None + */ +#define __HAL_I2S_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) + +/** @brief Disable the specified SPI peripheral (in I2S mode). * @param __HANDLE__: specifies the I2S Handle. * @retval None */ -#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) -#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint32_t)~((uint32_t)SPI_I2SCFGR_I2SE)) +#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE)) -/** @brief Enable or disable the specified I2S interrupts. +/** @brief Enable the specified I2S interrupts. * @param __HANDLE__: specifies the I2S Handle. * @param __INTERRUPT__: specifies the interrupt source to enable or disable. * This parameter can be one of the following values: @@ -295,8 +301,18 @@ typedef struct * @arg I2S_IT_ERR: Error interrupt enable * @retval None */ -#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__)) +#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) + +/** @brief Disable the specified I2S interrupts. + * @param __HANDLE__: specifies the I2S Handle. + * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be one of the following values: + * @arg I2S_IT_TXE: Tx buffer empty interrupt enable + * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable + * @arg I2S_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))) /** @brief Checks if the specified I2S interrupt source is enabled or disabled. * @param __HANDLE__: specifies the I2S Handle. @@ -318,7 +334,6 @@ typedef struct * @arg I2S_FLAG_TXE: Transmit buffer empty flag * @arg I2S_FLAG_UDR: Underrun flag * @arg I2S_FLAG_OVR: Overrun flag - * @arg I2S_FLAG_FRE: Frame error flag * @arg I2S_FLAG_CHSIDE: Channel Side flag * @arg I2S_FLAG_BSY: Busy flag * @retval The new state of __FLAG__ (TRUE or FALSE). @@ -328,24 +343,41 @@ typedef struct /** @brief Clears the I2S OVR pending flag. * @param __HANDLE__: specifies the I2S Handle. * @retval None - */ -#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ - (__HANDLE__)->Instance->SR;}while(0) + */ +#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\ + tmpreg = (__HANDLE__)->Instance->SR;\ + UNUSED(tmpreg);\ + }while(0) /** @brief Clears the I2S UDR pending flag. * @param __HANDLE__: specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR) - +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ - -/* Initialization/de-initialization functions **********************************/ +/** @addtogroup I2S_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_Exported_Functions_Group1 + * @{ + */ +/* Initialization/de-initialization functions ********************************/ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s); void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s); void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s); +/** + * @} + */ -/* I/O operation functions *****************************************************/ +/** @addtogroup I2S_Exported_Functions_Group2 + * @{ + */ +/* I/O operation functions ***************************************************/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout); @@ -363,36 +395,84 @@ HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s); HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s); -/* Peripheral Control and State functions **************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); - /* Callbacks used in non blocking modes (Interrupt and DMA) *******************/ void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s); void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); +/** + * @} + */ -void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); -void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); -void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -void I2S_DMAError(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout); +/** @addtogroup I2S_Exported_Functions_Group3 + * @{ + */ +/* Peripheral Control and State functions ************************************/ +HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +/** + * @} + */ /** * @} - */ + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_Private_Macros I2S Private Macros + * @{ + */ +#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \ + ((MODE) == I2S_MODE_SLAVE_RX) || \ + ((MODE) == I2S_MODE_MASTER_TX) || \ + ((MODE) == I2S_MODE_MASTER_RX)) + +#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS) || \ + ((STANDARD) == I2S_STANDARD_MSB) || \ + ((STANDARD) == I2S_STANDARD_LSB) || \ + ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \ + ((STANDARD) == I2S_STANDARD_PCM_LONG)) + +#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B) || \ + ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \ + ((FORMAT) == I2S_DATAFORMAT_24B) || \ + ((FORMAT) == I2S_DATAFORMAT_32B)) + +#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \ + ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE)) +#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K) && \ + ((FREQ) <= I2S_AUDIOFREQ_192K)) || \ + ((FREQ) == I2S_AUDIOFREQ_DEFAULT)) + +#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \ + ((CPOL) == I2S_CPOL_HIGH)) +/** + * @} + */ + +/* Private Fonctions ---------------------------------------------------------*/ +/** @defgroup I2S_Private_Functions I2S Private Functions + * @{ + */ +/* Private functions are defined in stm32f1xx_hal_i2s.c file */ /** * @} */ +/** + * @} + */ + +/** + * @} + */ #ifdef __cplusplus } #endif +#endif /* !STM32L031xx && !STM32L041xx */ #endif /* __STM32L0xx_HAL_I2S_H */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.c index 99a70978532..05f3fae82cf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_irda.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief IRDA HAL module driver. * * This file provides firmware functions to manage the following @@ -101,7 +101,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -135,7 +135,7 @@ * @{ */ -/** @defgroup IRDA +/** @addtogroup IRDA * @brief IRDA HAL module driver * @{ */ @@ -159,15 +159,15 @@ static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_CheckIdleState(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout); static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda); - +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda); static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); /* Private functions ---------------------------------------------------------*/ -/** @defgroup IRDA_Private_Functions +/** @addtogroup IRDA_Exported_Functions * @{ */ -/** @defgroup IRDA_Group1 Initialization/de-initialization functions +/** @addtogroup IRDA_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim @@ -222,7 +222,7 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) { /* Check the IRDA handle allocation */ - if(hirda == HAL_NULL) + if(hirda == NULL) { return HAL_ERROR; } @@ -268,7 +268,7 @@ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda) HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) { /* Check the IRDA handle allocation */ - if(hirda == HAL_NULL) + if(hirda == NULL) { return HAL_ERROR; } @@ -320,7 +320,7 @@ HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda) * @} */ -/** @defgroup IRDA_Group2 IO operation functions +/** @addtogroup IRDA_Exported_Functions_Group2 * @brief IRDA Transmit-Receive functions * @verbatim @@ -382,7 +382,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -462,7 +462,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -485,7 +485,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui /* Computation of the mask to apply to the RDR register of the UART associated to the IRDA */ - __HAL_IRDA_MASK_COMPUTATION(hirda); + IRDA_MASK_COMPUTATION(hirda); uhMask = hirda->Mask; /* Check data remaining to be received */ @@ -540,7 +540,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData { if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -568,8 +568,8 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData /* Process Unlocked */ __HAL_UNLOCK(hirda); - /* Enable the IRDA Transmit Complete Interrupt */ - __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); + /* Enable the IRDA Transmit Data Register Empty Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE); return HAL_OK; } @@ -590,7 +590,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, { if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -604,7 +604,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, /* Computation of the mask to apply to the RDR register of the UART associated to the IRDA */ - __HAL_IRDA_MASK_COMPUTATION(hirda); + IRDA_MASK_COMPUTATION(hirda); hirda->ErrorCode = HAL_IRDA_ERROR_NONE; if(hirda->State == HAL_IRDA_STATE_BUSY_TX) @@ -649,7 +649,7 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -685,6 +685,9 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->TDR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_IRDA_CLEAR_FLAG(hirda, IRDA_FLAG_TC); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the IRDA CR3 register */ hirda->Instance->CR3 |= USART_CR3_DMAT; @@ -715,7 +718,7 @@ HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData if ((hirda->State == HAL_IRDA_STATE_READY) || (hirda->State == HAL_IRDA_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -857,12 +860,12 @@ HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda) hirda->Instance->CR3 &= ~USART_CR3_DMAR; /* Abort the UART DMA tx channel */ - if(hirda->hdmatx != HAL_NULL) + if(hirda->hdmatx != NULL) { HAL_DMA_Abort(hirda->hdmatx); } /* Abort the UART DMA rx channel */ - if(hirda->hdmarx != HAL_NULL) + if(hirda->hdmarx != NULL) { HAL_DMA_Abort(hirda->hdmarx); } @@ -882,7 +885,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA parity error interrupt occurred -------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_PE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE) != RESET)) { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_PEF); + __HAL_IRDA_CLEAR_PEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_PE; /* Set the IRDA state ready to be able to start again the process */ @@ -892,7 +895,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA frame error interrupt occured --------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_FE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_FEF); + __HAL_IRDA_CLEAR_FEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_FE; /* Set the IRDA state ready to be able to start again the process */ @@ -902,7 +905,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA noise error interrupt occured --------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_NE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_NEF); + __HAL_IRDA_CLEAR_NEFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_NE; /* Set the IRDA state ready to be able to start again the process */ @@ -912,7 +915,7 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) /* IRDA Over-Run interrupt occured -----------------------------------------*/ if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_ORE) != RESET) && (__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR) != RESET)) { - __HAL_IRDA_CLEAR_IT(hirda, IRDA_CLEAR_OREF); + __HAL_IRDA_CLEAR_OREFLAG(hirda); hirda->ErrorCode |= HAL_IRDA_ERROR_ORE; /* Set the IRDA state ready to be able to start again the process */ @@ -938,7 +941,13 @@ void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda) { IRDA_Transmit_IT(hirda); } - + + /* IRDA in mode Transmitter (transmission end) -----------------------------*/ + if((__HAL_IRDA_GET_IT(hirda, IRDA_IT_TC) != RESET) &&(__HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC) != RESET)) + { + IRDA_EndTransmit_IT(hirda); + } + } /** @@ -1005,7 +1014,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda) * @} */ -/** @defgroup IRDA_Group3 Peripheral Control functions +/** @addtogroup IRDA_Exported_Functions_Group3 * @brief IRDA control functions * @verbatim @@ -1078,7 +1087,7 @@ static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda) MODIFY_REG(hirda->Instance->GTPR, (uint32_t)USART_GTPR_PSC, hirda->Init.Prescaler); /*-------------------------- USART BRR Configuration -----------------------*/ - __HAL_IRDA_GETCLOCKSOURCE(hirda, clocksource); + IRDA_GETCLOCKSOURCE(hirda, clocksource); switch (clocksource) { case IRDA_CLOCKSOURCE_PCLK1: @@ -1168,7 +1177,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - hirda->State= HAL_IRDA_STATE_TIMEOUT; + hirda->State= HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -1193,7 +1202,7 @@ static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE); __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - hirda->State= HAL_IRDA_STATE_TIMEOUT; + hirda->State= HAL_IRDA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hirda); @@ -1219,24 +1228,14 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) if((hirda->State == HAL_IRDA_STATE_BUSY_TX) || (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)) { + if(hirda->TxXferCount == 0) { - /* Disable the IRDA Transmit Complete Interrupt */ + /* Disable the IRDA Transmit Data Register Empty Interrupt */ __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE); - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); - - hirda->State = HAL_IRDA_STATE_READY; - } - - HAL_IRDA_TxCpltCallback(hirda); + + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); return HAL_OK; } @@ -1261,6 +1260,34 @@ static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda) return HAL_BUSY; } } +/** + * @brief Wraps up transmission in non blocking mode. + * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains + * the configuration information for the specified IRDA module. + * @retval HAL status + */ +static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda) +{ + /* Disable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) + { + hirda->State = HAL_IRDA_STATE_BUSY_RX; + } + else + { + /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR); + + hirda->State = HAL_IRDA_STATE_READY; + } + + HAL_IRDA_TxCpltCallback(hirda); + + return HAL_OK; +} /** * @brief Receive an amount of data in non blocking mode. @@ -1330,37 +1357,18 @@ static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda) static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma) { IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - + /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + if ( HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC) ) { hirda->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the IRDA CR3 register */ - hirda->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); - - /* Wait for IRDA TC Flag */ - if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, HAL_IRDA_TXDMA_TIMEOUTVALUE) != HAL_OK) - { - /* Timeout Occured */ - hirda->State = HAL_IRDA_STATE_TIMEOUT; - HAL_IRDA_ErrorCallback(hirda); - } - else - { - /* No Timeout */ - - if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) - { - hirda->State = HAL_IRDA_STATE_BUSY_RX; - } - else - { - hirda->State = HAL_IRDA_STATE_READY; - } - HAL_IRDA_TxCpltCallback(hirda); - } + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the IRDA CR3 register */ + hirda->Instance->CR3 &= ~(USART_CR3_DMAT); + + /* Enable the IRDA Transmit Complete Interrupt */ + __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC); } /* DMA Circular mode */ else @@ -1454,3 +1462,4 @@ static void IRDA_DMAError(DMA_HandleTypeDef *hdma) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.h index 4252fed19b6..1bd0501a7a5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_irda.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of IRDA HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup IRDA +/** @defgroup IRDA IRDA * @{ */ @@ -102,17 +102,15 @@ typedef enum }HAL_IRDA_StateTypeDef; /** - * @brief HAL IRDA Error Code structure definition + * @brief HAL IRDA Error Code definition */ -typedef enum -{ - HAL_IRDA_ERROR_NONE = 0x00, /*!< No error */ - HAL_IRDA_ERROR_PE = 0x01, /*!< Parity error */ - HAL_IRDA_ERROR_NE = 0x02, /*!< Noise error */ - HAL_IRDA_ERROR_FE = 0x04, /*!< frame error */ - HAL_IRDA_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_IRDA_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_IRDA_ErrorTypeDef; + +#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_IRDA_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE ((uint32_t)0x04) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ /** * @brief IRDA clock sources definition @@ -157,7 +155,7 @@ typedef struct __IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */ - __IO HAL_IRDA_ErrorTypeDef ErrorCode; /* IRDA Error code */ + __IO uint32_t ErrorCode; /* IRDA Error code */ }IRDA_HandleTypeDef; @@ -170,7 +168,7 @@ typedef struct * @{ */ -/** @defgroup IRDA_Parity +/** @defgroup IRDA_Parity IRDA Parity * @{ */ #define IRDA_PARITY_NONE ((uint32_t)0x0000) @@ -184,7 +182,7 @@ typedef struct */ -/** @defgroup IRDA_Transfer_Mode +/** @defgroup IRDA_Transfer_Mode IRDA transfer mode * @{ */ #define IRDA_MODE_RX ((uint32_t)USART_CR1_RE) @@ -195,7 +193,7 @@ typedef struct * @} */ -/** @defgroup IRDA_Low_Power +/** @defgroup IRDA_Low_Power IRDA low power * @{ */ #define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000) @@ -206,7 +204,7 @@ typedef struct * @} */ - /** @defgroup IRDA_State + /** @defgroup IRDA_State IRDA State * @{ */ #define IRDA_STATE_DISABLE ((uint32_t)0x0000) @@ -217,7 +215,7 @@ typedef struct * @} */ - /** @defgroup IRDA_Mode + /** @defgroup IRDA_Mode IRDA Mode * @{ */ #define IRDA_MODE_DISABLE ((uint32_t)0x0000) @@ -228,18 +226,18 @@ typedef struct * @} */ -/** @defgroup IRDA_One_Bit +/** @defgroup IRDA_One_Bit IRDA One bit * @{ */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED ((uint32_t)0x00000000) -#define IRDA_ONE_BIT_SAMPLE_ENABLED ((uint32_t)USART_CR3_ONEBIT) -#define IS_IRDA_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLED) || \ - ((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLED)) +#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) +#define IS_IRDA_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \ + ((ONEBIT) == IRDA_ONE_BIT_SAMPLE_ENABLE)) /** * @} */ -/** @defgroup IRDA_DMA_Tx +/** @defgroup IRDA_DMA_Tx IRDA DMA TX * @{ */ #define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000) @@ -250,7 +248,7 @@ typedef struct * @} */ -/** @defgroup IRDA_DMA_Rx +/** @defgroup IRDA_DMA_Rx IRDA DMA RX * @{ */ #define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000) @@ -261,7 +259,7 @@ typedef struct * @} */ -/** @defgroup IRDA_Flags +/** @defgroup IRDA_Flags IRDA Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ @@ -282,7 +280,7 @@ typedef struct * @} */ -/** @defgroup IRDA_Interrupt_definition +/** @defgroup IRDA_Interrupt_definition IRDA Interrupt definition * Elements values convention: 0000ZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) @@ -319,26 +317,27 @@ typedef struct * @} */ -/** @defgroup IRDA_IT_CLEAR_Flags +/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interrupt clear flag * @{ */ #define IRDA_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define IRDA_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ #define IRDA_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ #define IRDA_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ -#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define IRDA_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define IRDA_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ /** * @} */ -/** @defgroup IRDA_Request_Parameters +/** @defgroup IRDA_Request_Parameters IRDA Request parameters * @{ */ -#define IRDA_AUTOBAUD_REQUEST ((uint16_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ -#define IRDA_RXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ -#define IRDA_TXDATA_FLUSH_REQUEST ((uint16_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ +#define IRDA_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ +#define IRDA_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ +#define IRDA_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /*!< Transmit data flush Request */ #define IS_IRDA_REQUEST_PARAMETER(PARAM) (((PARAM) == IRDA_AUTOBAUD_REQUEST) || \ ((PARAM) == IRDA_SENDBREAK_REQUEST) || \ ((PARAM) == IRDA_MUTE_MODE_REQUEST) || \ @@ -348,7 +347,7 @@ typedef struct * @} */ -/** @defgroup IRDA_Interruption_Mask +/** @defgroup IRDA_Interruption_Mask IRDA Interruption mask * @{ */ #define IRDA_IT_MASK ((uint16_t)0x001F) @@ -362,7 +361,7 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ -/** @defgroup IRDA_Exported_Macros +/** @defgroup IRDA_Exported_Macros IRDA Exported Macros * @{ */ @@ -373,6 +372,63 @@ typedef struct */ #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET) +/** @brief Flushs the IRDA DR register + * @param __HANDLE__: specifies the IRDA Handle. + * The Handle Instance which can be USART1 or USART2. + * @retval None + */ +#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \ + } while(0) + + +/** @brief Clears the specified IRDA pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg IRDA_CLEAR_PEF + * @arg IRDA_CLEAR_FEF + * @arg IRDA_CLEAR_NEF + * @arg IRDA_CLEAR_OREF + * @arg IRDA_CLEAR_TCF + * @arg IRDA_CLEAR_IDLEF + * @retval None + */ +#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__)) + +/** @brief Clear the IRDA PE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG(__HANDLE__, IRDA_CLEAR_PEF) + + +/** @brief Clear the IRDA FE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG(__HANDLE__, IRDA_CLEAR_FEF) + +/** @brief Clear the IRDA NE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG(__HANDLE__, IRDA_CLEAR_NEF) + +/** @brief Clear the IRDA ORE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG(__HANDLE__, IRDA_CLEAR_OREF) + +/** @brief Clear the IRDA IDLE pending flag. + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG(__HANDLE__, IRDA_CLEAR_IDLEF) + /** @brief Check whether the specified IRDA flag is set or not. * @param __HANDLE__: specifies the IRDA Handle. * The Handle Instance which can be USART1 or USART2. @@ -492,7 +548,19 @@ typedef struct * * @retval None */ -#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) +#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) + +/** @brief Enables the IRDA one bit sample method + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disables the IRDA one bit sample method + * @param __HANDLE__: specifies the IRDA Handle. + * @retval None + */ +#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART/USART associated to IRDA Handle * @param __HANDLE__: specifies the IRDA Handle. @@ -527,12 +595,27 @@ typedef struct /* Include IRDA HAL Extension module */ #include "stm32l0xx_hal_irda_ex.h" +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IRDA_Exported_Functions IRDA Exported Functions + * @{ + */ + +/** @defgroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ /* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization methods **********************************/ HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda); HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda); void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda); +/** + * @} + */ + +/** @defgroup IRDA_Exported_Functions_Group2 IRDA IO operationfunctions + * @{ + */ /* IO operation methods *******************************************************/ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout); @@ -550,7 +633,13 @@ void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda); void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda); +/** + * @} + */ +/** @defgroup IRDA_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ /* Peripheral State methods **************************************************/ HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda); uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); @@ -562,7 +651,14 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); /** * @} */ - + +/** + * @} + */ + +/** + * @} + */ #ifdef __cplusplus } #endif @@ -570,3 +666,4 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda); #endif /* __STM32L0xx_HAL_IRDA_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda_ex.h index da9301c4190..07a51a2039e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_irda_ex.h @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_irda_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of IRDA HAL Extension module. ****************************************************************************** * @attention @@ -56,11 +56,11 @@ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/** @defgroup IRDAEx_Extended_Exported_Constants +/** @defgroup IRDAEx_Extended_Exported_Constants IRDA Extended Exported Constants * @{ */ -/** @defgroup IRDAEx_Word_Length +/** @defgroup IRDAEx_Word_Length IRDAEx Word length * @{ */ #define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) @@ -80,7 +80,7 @@ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup IRDAEx_Extended_Exported_Macros +/** @defgroup IRDAEx_Extended_Exported_Macros IRDA Extended Exported Macros * @{ */ /** @brief Reports the IRDA clock source. @@ -88,7 +88,54 @@ * @param __CLOCKSOURCE__ : output variable * @retval IRDA clocking source, written in __CLOCKSOURCE__. */ -#define __HAL_IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#if defined (STM32L031xx) || defined (STM32L041xx) +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE; \ + break; \ + default: \ + break; \ + } \ + } \ + } while(0) + +#else /* (STM32L031xx) || defined (STM32L041xx) */ + +#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -110,7 +157,7 @@ break; \ } \ } \ - else if((__HANDLE__)->Instance == USART2) \ + else if((__HANDLE__)->Instance == USART2) \ { \ switch(__HAL_RCC_GET_USART2_SOURCE()) \ { \ @@ -151,13 +198,14 @@ } \ } \ } while(0) - +#endif /* (STM32L031xx) || (STM32L041xx) */ + /** @brief Reports the mask to apply to retrieve the received data * according to the word length and to the parity bits activation. * @param __HANDLE__: specifies the IRDA Handle * @retval mask to apply to USART RDR register value. */ -#define __HAL_IRDA_MASK_COMPUTATION(__HANDLE__) \ +#define IRDA_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B) \ { \ @@ -219,3 +267,4 @@ #endif /* __STM32L0xx_HAL_IRDA_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.c index fddf4299aea..8cfda67a8fa 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_iwdg.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral: @@ -76,7 +76,7 @@ (+) __HAL_IWDG_START: Enable the IWDG peripheral (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register - (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers + (+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status @@ -84,7 +84,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -118,25 +118,24 @@ * @{ */ -/** @defgroup IWDG +/** @addtogroup IWDG * @brief IWDG HAL module driver. * @{ */ #ifdef HAL_IWDG_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* TimeOut value */ +#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000 -/** @defgroup IWDG_Private_Functions +/* Local define used to check the SR status register */ +#define IWDG_SR_FLAGS (IWDG_FLAG_PVU | IWDG_FLAG_RVU | IWDG_FLAG_WVU) + +/** @addtogroup IWDG_Exported_Functions * @{ */ -/** @defgroup IWDG_Group1 Initialization and de-initialization functions +/** @addtogroup IWDG_Exported_Functions_Group1 * @brief Initialization and Configuration functions. * @verbatim @@ -156,16 +155,21 @@ /** * @brief Initializes the IWDG according to the specified * parameters in the IWDG_InitTypeDef and creates the associated handle. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. + * + * When using the 'window option', the function HAL_IWDG_Start() must + * be called before calling this function + * + * @param hiwdg : pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ + HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) { uint32_t tickstart = 0; /* Check the IWDG handle allocation */ - if(hiwdg == HAL_NULL) + if(hiwdg == NULL) { return HAL_ERROR; } @@ -176,17 +180,15 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); /* Check pending flag, if previous update not done, return error */ - if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET)) + if(((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) { return HAL_ERROR; } if(hiwdg->State == HAL_IWDG_STATE_RESET) { - /* Init the low level hardware */ - HAL_IWDG_MspInit(hiwdg); + /* Init the low level hardware */ + HAL_IWDG_MspInit(hiwdg); } /* Change IWDG peripheral state */ @@ -194,7 +196,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */ /* by writing 0x5555 in KR */ - __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg); + IWDG_ENABLE_WRITE_ACCESS(hiwdg); /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */ MODIFY_REG(hiwdg->Instance->PR, (uint32_t)IWDG_PR_PR, hiwdg->Init.Prescaler); @@ -206,14 +208,14 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg) tickstart = HAL_GetTick(); /* Wait for register to be updated */ - while((uint32_t)(hiwdg->Instance->SR) != RESET) - { - if((HAL_GetTick() - tickstart ) > 1000) - { - /* Set IWDG state */ - hiwdg->State = HAL_IWDG_STATE_TIMEOUT; - return HAL_TIMEOUT; - } + while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) + { + if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { + /* Set IWDG state */ + hiwdg->State = HAL_IWDG_STATE_TIMEOUT; + return HAL_TIMEOUT; + } } /* Write to IWDG WINR the IWDG_Window value to compare with */ @@ -244,7 +246,7 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) * @} */ -/** @defgroup IWDG_Group2 IO operation functions +/** @addtogroup IWDG_Exported_Functions_Group2 * @brief IO operation functions * @verbatim @@ -261,8 +263,8 @@ __weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg) /** * @brief Starts the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. + * @param hiwdg : pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) @@ -275,35 +277,31 @@ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_BUSY; + /* Enable the IWDG peripheral */ + __HAL_IWDG_START(hiwdg); + /* Reload IWDG counter with value defined in the RLR register */ if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE) { __HAL_IWDG_RELOAD_COUNTER(hiwdg); } - /* Enable the IWDG peripheral */ - __HAL_IWDG_START(hiwdg); - tickstart = HAL_GetTick(); - - /* Wait until PVU, RVU, WVU flag are RESET */ - while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) - &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) ) + + /* Wait until PVU, RVU, WVU flag are RESET */ + while (((hiwdg->Instance->SR) & IWDG_SR_FLAGS) != 0) { - - if((HAL_GetTick() - tickstart ) > 1000) - { + if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { /* Set IWDG state */ hiwdg->State = HAL_IWDG_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hiwdg); - return HAL_TIMEOUT; } } - + /* Change IWDG peripheral state */ hiwdg->State = HAL_IWDG_STATE_READY; @@ -316,8 +314,8 @@ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg) /** * @brief Refreshes the IWDG. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. + * @param hiwdg : pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) @@ -335,8 +333,8 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) /* Wait until RVU flag is RESET */ while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET) { - if((HAL_GetTick() - tickstart ) > 1000) - { + if((HAL_GetTick()-tickstart) > HAL_IWDG_DEFAULT_TIMEOUT) + { /* Set IWDG state */ hiwdg->State = HAL_IWDG_STATE_TIMEOUT; @@ -364,7 +362,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) * @} */ -/** @defgroup IWDG_Group3 Peripheral State functions +/** @addtogroup IWDG_Exported_Functions_Group3 * @brief Peripheral State functions. * @verbatim @@ -381,8 +379,8 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg) /** * @brief Returns the IWDG state. - * @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains - * the configuration information for the specified IWDG module. + * @param hiwdg : pointer to a IWDG_HandleTypeDef structure that contains + * the configuration information for the specified IWDG module. * @retval HAL state */ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) @@ -408,3 +406,4 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.h index 9363b815d95..b35f981aa16 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_iwdg.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_iwdg.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup IWDG +/** @defgroup IWDG * @{ */ @@ -60,6 +60,9 @@ * @{ */ +/** @defgroup IWDG_State IWDG state definition + * @{ + */ /** * @brief IWDG HAL State Structure definition */ @@ -72,7 +75,12 @@ typedef enum HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */ }HAL_IWDG_StateTypeDef; - +/** + * @} + */ +/** @defgroup IWDG_Init IWDG init configuration structure + * @{ + */ /** * @brief IWDG Init structure definition */ @@ -88,7 +96,13 @@ typedef struct This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */ } IWDG_InitTypeDef; +/** + * @} + */ +/** @defgroup IWDG_handle IWDG handler + * @{ + */ /** * @brief IWDG Handle Structure definition */ @@ -104,6 +118,10 @@ typedef struct }IWDG_HandleTypeDef; +/** + * @} + */ + /** * @} */ @@ -114,41 +132,41 @@ typedef struct * @{ */ -/** @defgroup IWDG_Registers_BitMask IWDG_Registers_BitMask +/** @defgroup IWDG_Registers_Key IWDG key * @brief IWDG registers bit mask * @{ */ /* --- KR Register ---*/ /* KR register bit mask */ -#define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ -#define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ -#define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ -#define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ - -#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \ - ((__KR__) == KR_KEY_ENABLE))|| \ - ((__KR__) == KR_KEY_EWA)) || \ - ((__KR__) == KR_KEY_DWA)) +#define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */ +#define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */ +#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */ +#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */ /** * @} */ -/** @defgroup IWDG_Flag_definition IWDG_Flag_definition +#define IS_IWDG_KR(__KR__) (((__KR__) == IWDG_KEY_RELOAD) || \ + ((__KR__) == IWDG_KEY_ENABLE))|| \ + ((__KR__) == IWDG_KEY_WRITE_ACCESS_ENABLE)) || \ + ((__KR__) == IWDG_KEY_WRITE_ACCESS_DISABLE)) + + +/** @defgroup IWDG_Flag_definition IWDG Flag definition * @{ */ #define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */ #define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */ #define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update Flag */ - -#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \ - ((FLAG) == IWDG_FLAG_RVU) || \ - ((FLAG) == IWDG_FLAG_WVU)) - /** * @} */ +#define IS_IWDG_FLAG(__FLAG__) (((__FLAG__) == IWDG_FLAG_PVU) || \ + ((__FLAG__) == IWDG_FLAG_RVU) || \ + ((__FLAG__) == IWDG_FLAG_WVU)) + -/** @defgroup IWDG_Prescaler IWDG_Prescaler +/** @defgroup IWDG_Prescaler IWDG Prescaler * @{ */ #define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */ @@ -158,7 +176,9 @@ typedef struct #define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */ #define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */ #define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */ - +/** + * @} + */ #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ ((__PRESCALER__) == IWDG_PRESCALER_8) || \ ((__PRESCALER__) == IWDG_PRESCALER_16) || \ @@ -167,32 +187,16 @@ typedef struct ((__PRESCALER__) == IWDG_PRESCALER_128)|| \ ((__PRESCALER__) == IWDG_PRESCALER_256)) -/** - * @} - */ - -/** @defgroup IWDG_Reload_Value IWDG_Reload_Value - * @{ - */ +/* Check for reload value */ #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF) -/** - * @} - */ - -/** @defgroup IWDG_CounterWindow_Value - * @{ - */ -#define IS_IWDG_WINDOW(VALUE) ((VALUE) <= 0xFFF) +/* Check for window value */ +#define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFF) -/** - * @} - */ -/** @defgroup IWDG_Window +/** @defgroup IWDG_Disable IWDG Disable * @{ */ - #define IWDG_WINDOW_DISABLE 0xFFF /** * @} @@ -201,51 +205,50 @@ typedef struct /** * @} */ - /* Exported macro ------------------------------------------------------------*/ -/** @defgroup IWDG_Exported_Macro +/** @defgroup IWDG_Exported_Macro IWDG Exported Macro * @{ */ /** @brief Reset IWDG handle state - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ : IWDG handle * @retval None */ #define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET) /** * @brief Enables the IWDG peripheral. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ : IWDG handle * @retval None */ -#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE) +#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) /** * @brief Reloads IWDG counter with value defined in the reload register * (write access to IWDG_PR and IWDG_RLR registers disabled). - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ : IWDG handle * @retval None */ -#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD) +#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) /** * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ : IWDG handle * @retval None */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA) +#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ : IWDG handle * @retval None */ -#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA) +#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) /** * @brief Gets the selected IWDG's flag status. - * @param __HANDLE__: IWDG handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ : IWDG handle + * @param __FLAG__ : specifies the flag to check. * This parameter can be one of the following values: * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag @@ -259,25 +262,39 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ - -/** @addtogroup IWDG_Exported_Functions +/** @defgroup IWDG_Exported_Functions * @{ */ -/* Initialization/de-initialization functions ********************************/ +/** @defgroup IWDG_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg); void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg); +/** + * @} + */ -/* I/O operation functions ****************************************************/ +/** @defgroup IWDG_Exported_Functions_Group2 I/O operation functions + * @{ + */ HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg); HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg); +/** + * @} + */ -/* Peripheral State functions ************************************************/ +/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions + * @{ + */ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); +/** + * @} + */ /** * @} - */ + */ /** * @} @@ -286,7 +303,7 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); /** * @} */ - + #ifdef __cplusplus } #endif @@ -294,3 +311,4 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg); #endif /* __STM32L0xx_HAL_IWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.c index 8a7e4c6830f..68f8100c4ea 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_lcd.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief LCD Controller HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LCD Controller (LCD) peripheral: @@ -21,10 +21,8 @@ (#) Initialize the LCD low level resources by implement the HAL_LCD_MspInit() API: (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. - (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. + (+) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and + selected clock source (HSE, LSI or LSE) -@- The frequency generator allows you to achieve various LCD frame rates starting from an LCD input clock frequency (LCDCLK) which can vary @@ -66,7 +64,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -96,30 +94,38 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) + /** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup LCD +#ifdef HAL_LCD_MODULE_ENABLED + +/** @defgroup LCD LCD * @brief LCD HAL module driver * @{ */ -#ifdef HAL_LCD_MODULE_ENABLED -#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L062xx) && !defined (STM32L061xx) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ +/** @defgroup LCD_Private_Defines LCD Private Defines + * @{ + */ #define LCD_TIMEOUT_VALUE 1000 +/** + * @} + */ /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup LCD_Private_Functions +/** @defgroup LCD_Exported_Functions LCD Exported Functions * @{ */ -/** @defgroup LCD_Group1 Initialization/de-initialization methods +/** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods * @brief Initialization and Configuration functions * @verbatim @@ -140,7 +146,7 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) { /* Check the LCD handle allocation */ - if(hlcd == HAL_NULL) + if(hlcd == NULL) { return HAL_ERROR; } @@ -148,8 +154,20 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) /* Check the parameters */ assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance)); + /* Check the LCD peripheral state */ + if(hlcd->State == HAL_LCD_STATE_BUSY) + { + return HAL_BUSY; + } + hlcd->State = HAL_LCD_STATE_BUSY; + /* Disable the peripheral */ + __HAL_LCD_DISABLE(hlcd); + + /*Disable Highdrive by default*/ + __HAL_LCD_HIGHDRIVER_DISABLE(hlcd); + /* DeInit the low level hardware */ HAL_LCD_MspDeInit(hlcd); @@ -165,7 +183,8 @@ HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd) /** * @brief Initializes the LCD peripheral according to the specified parameters * in the LCD_InitStruct. - * @note This function can be used only when the LCD is disabled. + * @note This function can be used only when the LCD is disabled. + * The LCD HighDrive can be enabled/disabled using related macros up to user. * @param hlcd: LCD handle * @retval None */ @@ -175,7 +194,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) uint8_t counter = 0; /* Check the LCD handle allocation */ - if(hlcd == HAL_NULL) + if(hlcd == NULL) { return HAL_ERROR; } @@ -188,12 +207,12 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) assert_param(IS_LCD_BIAS(hlcd->Init.Bias)); assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource)); assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration)); + assert_param(IS_LCD_HIGHDRIVE(hlcd->Init.HighDrive)); assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime)); assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); - if(hlcd->State == HAL_LCD_STATE_RESET) { /* Initialize the low level hardware (MSP) */ @@ -212,7 +231,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) hlcd->Instance->RAM[counter] = 0; } /* Enable the display request */ - hlcd->Instance->SR |= LCD_SR_UDR; + SET_BIT(hlcd->Instance->SR, LCD_SR_UDR); /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: Set PS[3:0] bits according to hlcd->Init.Prescaler value @@ -221,22 +240,27 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value Set DEAD[2:0] bits according to hlcd->Init.DeadTime value Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value - Set CC[2:0] bits according to hlcd->Init.Contrast value */ - hlcd->Instance->FCR = (uint32_t)(hlcd->Init.Prescaler | hlcd->Init.Divider | \ - hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ - hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | \ - hlcd->Init.Contrast); + Set CC[2:0] bits according to hlcd->Init.Contrast value + Set HD[0] bit according to hlcd->Init.HighDrive value*/ + + MODIFY_REG(hlcd->Instance->FCR, \ + (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \ + LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \ + (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ + hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive)); + /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register.*/ LCD_WaitForSynchro(hlcd); - /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast: + /* Configure the LCD Duty, Bias, Voltage Source, Dead Time: Set DUTY[2:0] bits according to hlcd->Init.Duty value Set BIAS[1:0] bits according to hlcd->Init.Bias value Set VSEL bits according to hlcd->Init.VoltageSource value */ - hlcd->Instance->CR = (uint32_t)(hlcd->Init.Duty | hlcd->Init.Bias | \ - hlcd->Init.VoltageSource); + MODIFY_REG(hlcd->Instance->CR, \ + (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL), \ + (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource)); /* Enable the peripheral */ __HAL_LCD_ENABLE(hlcd); @@ -245,11 +269,11 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /* Wait Until the LCD is enabled */ - while((hlcd->Instance->SR & LCD_FLAG_ENS) == (uint32_t)RESET) + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET) { if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) { - hlcd->ErrorCode = HAL_LCD_ERROR_ENS; + hlcd->ErrorCode = HAL_LCD_ERROR_ENS; return HAL_TIMEOUT; } } @@ -258,11 +282,11 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /*!< Wait Until the LCD Booster is ready */ - while((hlcd->Instance->SR & LCD_FLAG_RDY) == (uint32_t)RESET) + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET) { if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) { - hlcd->ErrorCode = HAL_LCD_ERROR_RDY; + hlcd->ErrorCode = HAL_LCD_ERROR_RDY; return HAL_TIMEOUT; } } @@ -302,7 +326,7 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) * @} */ -/** @defgroup LCD_Group2 IO operation methods +/** @defgroup LCD_Exported_Functions_Group2 IO operation methods * @brief LCD RAM functions * @verbatim @@ -354,6 +378,11 @@ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) * @arg LCD_RAM_REGISTER15: LCD RAM Register 15 * @param RAMRegisterMask: specifies the LCD RAM Register Data Mask. * @param Data: specifies LCD Data Value to be written. + * @note For LCD glass COM*SEG as 8*40 for example, the LCD common terminals COM[0,7] + * are mapped on 32bits LCD_RAM_REGISTER[0,14] according to rules: COM(n) spread + * on LCD_RAM_REGISTER(2*n) and LCD_RAM_REGISTER(2*n+1).The segment terminals + * SEG[0,39] of COM(n) correspond to LSB bits of related LCD_RAM_REGISTER(2*n)[0,31] + * and LCD_RAM_REGISTER(2*n+1)[0,7] * @retval None */ HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data) @@ -375,21 +404,19 @@ HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterInd tickstart = HAL_GetTick(); /*!< Wait Until the LCD is ready */ - while((hlcd->Instance->SR & LCD_FLAG_UDR) != (uint32_t)RESET) + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) { if((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_UDR; + /* Process Unlocked */ + __HAL_UNLOCK(hlcd); return HAL_TIMEOUT; } } } - - /* Clear the data bytes position into LCD RAM register */ - hlcd->Instance->RAM[RAMRegisterIndex] &= (uint32_t)RAMRegisterMask; - - /* Copy the new Data bytes to LCD RAM register */ - hlcd->Instance->RAM[RAMRegisterIndex] |= (uint32_t)Data; +/* Copy the new Data bytes to LCD RAM register */ + MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data); return HAL_OK; } @@ -420,11 +447,15 @@ HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /*!< Wait Until the LCD is ready */ - while((hlcd->Instance->SR & LCD_FLAG_UDR) != (uint32_t)RESET) + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET) { if( (HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { - hlcd->ErrorCode = HAL_LCD_ERROR_UDR; + hlcd->ErrorCode = HAL_LCD_ERROR_UDR; + + /* Process Unlocked */ + __HAL_UNLOCK(hlcd); + return HAL_TIMEOUT; } } @@ -473,13 +504,17 @@ HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /*!< Wait Until the LCD display is done */ - while((hlcd->Instance->SR & LCD_FLAG_UDD) == (uint32_t)RESET) + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET) { - if( (HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) { - hlcd->ErrorCode = HAL_LCD_ERROR_UDD; + hlcd->ErrorCode = HAL_LCD_ERROR_UDD; + + /* Process Unlocked */ + __HAL_UNLOCK(hlcd); + return HAL_TIMEOUT; - } + } } hlcd->State = HAL_LCD_STATE_READY; @@ -494,7 +529,7 @@ HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd) * @} */ -/** @defgroup LCD_Group3 Peripheral State methods +/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods * @brief LCD State functions * @verbatim @@ -533,10 +568,18 @@ uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd) * @} */ +/** + * @} + */ + +/** @defgroup LCD_Private_Functions LCD Private Functions + * @{ + */ + /** * @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain. * This function must be called after any write operation to LCD_FCR register. - * @param None + * @param hlcd: LCD handle * @retval None */ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) @@ -547,7 +590,7 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) tickstart = HAL_GetTick(); /* Loop until FCRSF flag is set */ - while((hlcd->Instance->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET) + while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET) { if((HAL_GetTick() - tickstart) > LCD_TIMEOUT_VALUE) { @@ -562,16 +605,16 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd) /** * @} */ -#endif /* STM32L051xx && STM32L052xx && STM32L062xx && STM32L061xx*/ -#endif /* HAL_LCD_MODULE_ENABLED */ + /** * @} */ +#endif /* HAL_LCD_MODULE_ENABLED */ /** * @} */ - +#endif /* #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.h index a8f189ccbad..8c9f23cb7f2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lcd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_lcd.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of LCD Controller HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -35,6 +35,8 @@ ****************************************************************************** */ +#if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) + /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L0xx_HAL_LCD_H #define __STM32L0xx_HAL_LCD_H @@ -43,7 +45,6 @@ extern "C" { #endif -#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L062xx) && !defined (STM32L061xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" @@ -52,11 +53,14 @@ * @{ */ -/** @addtogroup LCD +/** @addtogroup LCD LCD * @{ */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup LCD_Exported_Types LCD Exported Types + * @{ + */ /** * @brief LCD Init structure definition @@ -80,8 +84,8 @@ typedef struct This parameter can be one value of @ref LCD_DeadTime */ uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration. This parameter can be one value of @ref LCD_PulseOnDuration */ - uint32_t HighDrive; /*!< Enable or disable the low resistance divider. - This parameter can be set to ENABLE or DISABLE. */ + uint32_t HighDrive; /*!< Configures the LCD High Drive. + This parameter can be one value of @ref LCD_HighDrive */ uint32_t BlinkMode; /*!< Configures the LCD Blink Mode. This parameter can be one value of @ref LCD_BlinkMode */ uint32_t BlinkFrequency; /*!< Configures the LCD Blink frequency. @@ -100,45 +104,47 @@ typedef enum HAL_LCD_STATE_ERROR = 0x04 /*!< Error */ }HAL_LCD_StateTypeDef; -/** - * @brief HAL LCD Error Code structure definition - */ -typedef enum -{ - HAL_LCD_ERROR_NONE = 0x00, /*!< No error */ - HAL_LCD_ERROR_FCRSF = 0x01, /*!< Synchro flag timeout error */ - HAL_LCD_ERROR_UDR = 0x02, /*!< Update display request flag timeout error */ - HAL_LCD_ERROR_UDD = 0x04, /*!< Update display done flag timeout error */ - HAL_LCD_ERROR_ENS = 0x08, /*!< LCD enabled status flag timeout error */ - HAL_LCD_ERROR_RDY = 0x10 /*!< LCD Booster ready timeout error */ -}HAL_LCD_ErrorTypeDef; - /** * @brief UART handle Structure definition */ typedef struct { - LCD_TypeDef *Instance; /* LCD registers base address */ + LCD_TypeDef *Instance; /* LCD registers base address */ - LCD_InitTypeDef Init; /* LCD communication parameters */ + LCD_InitTypeDef Init; /* LCD communication parameters */ - HAL_LockTypeDef Lock; /* Locking object */ + HAL_LockTypeDef Lock; /* Locking object */ - __IO HAL_LCD_StateTypeDef State; /* LCD communication state */ + __IO HAL_LCD_StateTypeDef State; /* LCD communication state */ - __IO HAL_LCD_ErrorTypeDef ErrorCode; /* LCD Error code */ + __IO uint32_t ErrorCode; /* LCD Error code */ }LCD_HandleTypeDef; +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ -/** @defgroup LCD_Exported_Constants +/** @defgroup LCD_Exported_Constants LCD Exported Constants * @{ */ -#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD) - -/** @defgroup LCD_Prescaler +/** @defgroup LCD_ErrorCode LCD Error Code + * @{ + */ +#define HAL_LCD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_LCD_ERROR_FCRSF ((uint32_t)0x01) /*!< Synchro flag timeout error */ +#define HAL_LCD_ERROR_UDR ((uint32_t)0x02) /*!< Update display request flag timeout error */ +#define HAL_LCD_ERROR_UDD ((uint32_t)0x04) /*!< Update display done flag timeout error */ +#define HAL_LCD_ERROR_ENS ((uint32_t)0x08) /*!< LCD enabled status flag timeout error */ +#define HAL_LCD_ERROR_RDY ((uint32_t)0x10) /*!< LCD Booster ready timeout error */ +/** + * @} + */ + +/** @defgroup LCD_Prescaler LCD Prescaler * @{ */ @@ -157,30 +163,30 @@ typedef struct #define LCD_PRESCALER_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */ #define LCD_PRESCALER_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */ #define LCD_PRESCALER_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */ -#define LCD_PRESCALER_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */ - -#define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_PRESCALER_1) || \ - ((PRESCALER) == LCD_PRESCALER_2) || \ - ((PRESCALER) == LCD_PRESCALER_4) || \ - ((PRESCALER) == LCD_PRESCALER_8) || \ - ((PRESCALER) == LCD_PRESCALER_16) || \ - ((PRESCALER) == LCD_PRESCALER_32) || \ - ((PRESCALER) == LCD_PRESCALER_64) || \ - ((PRESCALER) == LCD_PRESCALER_128) || \ - ((PRESCALER) == LCD_PRESCALER_256) || \ - ((PRESCALER) == LCD_PRESCALER_512) || \ - ((PRESCALER) == LCD_PRESCALER_1024) || \ - ((PRESCALER) == LCD_PRESCALER_2048) || \ - ((PRESCALER) == LCD_PRESCALER_4096) || \ - ((PRESCALER) == LCD_PRESCALER_8192) || \ - ((PRESCALER) == LCD_PRESCALER_16384) || \ - ((PRESCALER) == LCD_PRESCALER_32768)) +#define LCD_PRESCALER_32768 ((uint32_t)LCD_FCR_PS) /*!< CLKPS = LCDCLK/32768 */ + +#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1) || \ + ((__PRESCALER__) == LCD_PRESCALER_2) || \ + ((__PRESCALER__) == LCD_PRESCALER_4) || \ + ((__PRESCALER__) == LCD_PRESCALER_8) || \ + ((__PRESCALER__) == LCD_PRESCALER_16) || \ + ((__PRESCALER__) == LCD_PRESCALER_32) || \ + ((__PRESCALER__) == LCD_PRESCALER_64) || \ + ((__PRESCALER__) == LCD_PRESCALER_128) || \ + ((__PRESCALER__) == LCD_PRESCALER_256) || \ + ((__PRESCALER__) == LCD_PRESCALER_512) || \ + ((__PRESCALER__) == LCD_PRESCALER_1024) || \ + ((__PRESCALER__) == LCD_PRESCALER_2048) || \ + ((__PRESCALER__) == LCD_PRESCALER_4096) || \ + ((__PRESCALER__) == LCD_PRESCALER_8192) || \ + ((__PRESCALER__) == LCD_PRESCALER_16384) || \ + ((__PRESCALER__) == LCD_PRESCALER_32768)) /** * @} */ -/** @defgroup LCD_Divider +/** @defgroup LCD_Divider LCD Divider * @{ */ @@ -199,52 +205,52 @@ typedef struct #define LCD_DIVIDER_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */ #define LCD_DIVIDER_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */ #define LCD_DIVIDER_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */ -#define LCD_DIVIDER_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */ - -#define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_DIVIDER_16) || \ - ((DIVIDER) == LCD_DIVIDER_17) || \ - ((DIVIDER) == LCD_DIVIDER_18) || \ - ((DIVIDER) == LCD_DIVIDER_19) || \ - ((DIVIDER) == LCD_DIVIDER_20) || \ - ((DIVIDER) == LCD_DIVIDER_21) || \ - ((DIVIDER) == LCD_DIVIDER_22) || \ - ((DIVIDER) == LCD_DIVIDER_23) || \ - ((DIVIDER) == LCD_DIVIDER_24) || \ - ((DIVIDER) == LCD_DIVIDER_25) || \ - ((DIVIDER) == LCD_DIVIDER_26) || \ - ((DIVIDER) == LCD_DIVIDER_27) || \ - ((DIVIDER) == LCD_DIVIDER_28) || \ - ((DIVIDER) == LCD_DIVIDER_29) || \ - ((DIVIDER) == LCD_DIVIDER_30) || \ - ((DIVIDER) == LCD_DIVIDER_31)) +#define LCD_DIVIDER_31 ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */ + +#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \ + ((__DIVIDER__) == LCD_DIVIDER_17) || \ + ((__DIVIDER__) == LCD_DIVIDER_18) || \ + ((__DIVIDER__) == LCD_DIVIDER_19) || \ + ((__DIVIDER__) == LCD_DIVIDER_20) || \ + ((__DIVIDER__) == LCD_DIVIDER_21) || \ + ((__DIVIDER__) == LCD_DIVIDER_22) || \ + ((__DIVIDER__) == LCD_DIVIDER_23) || \ + ((__DIVIDER__) == LCD_DIVIDER_24) || \ + ((__DIVIDER__) == LCD_DIVIDER_25) || \ + ((__DIVIDER__) == LCD_DIVIDER_26) || \ + ((__DIVIDER__) == LCD_DIVIDER_27) || \ + ((__DIVIDER__) == LCD_DIVIDER_28) || \ + ((__DIVIDER__) == LCD_DIVIDER_29) || \ + ((__DIVIDER__) == LCD_DIVIDER_30) || \ + ((__DIVIDER__) == LCD_DIVIDER_31)) /** * @} */ -/** @defgroup LCD_Duty +/** @defgroup LCD_Duty LCD Duty * @{ */ -#define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */ -#define LCD_DUTY_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */ -#define LCD_DUTY_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */ -#define LCD_DUTY_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */ -#define LCD_DUTY_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */ - -#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_DUTY_STATIC) || \ - ((DUTY) == LCD_DUTY_1_2) || \ - ((DUTY) == LCD_DUTY_1_3) || \ - ((DUTY) == LCD_DUTY_1_4) || \ - ((DUTY) == LCD_DUTY_1_8)) +#define LCD_DUTY_STATIC ((uint32_t)0x00000000) /*!< Static duty */ +#define LCD_DUTY_1_2 (LCD_CR_DUTY_0) /*!< 1/2 duty */ +#define LCD_DUTY_1_3 (LCD_CR_DUTY_1) /*!< 1/3 duty */ +#define LCD_DUTY_1_4 ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty */ +#define LCD_DUTY_1_8 (LCD_CR_DUTY_2) /*!< 1/8 duty */ + +#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC) || \ + ((__DUTY__) == LCD_DUTY_1_2) || \ + ((__DUTY__) == LCD_DUTY_1_3) || \ + ((__DUTY__) == LCD_DUTY_1_4) || \ + ((__DUTY__) == LCD_DUTY_1_8)) /** * @} */ -/** @defgroup LCD_Bias +/** @defgroup LCD_Bias LCD Bias * @{ */ @@ -252,14 +258,14 @@ typedef struct #define LCD_BIAS_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */ #define LCD_BIAS_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */ -#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_BIAS_1_4) || \ - ((BIAS) == LCD_BIAS_1_2) || \ - ((BIAS) == LCD_BIAS_1_3)) +#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \ + ((__BIAS__) == LCD_BIAS_1_2) || \ + ((__BIAS__) == LCD_BIAS_1_3)) /** * @} */ -/** @defgroup LCD_Voltage_Source +/** @defgroup LCD_Voltage_Source LCD Voltage Source * @{ */ @@ -273,140 +279,148 @@ typedef struct * @} */ -/** @defgroup LCD_Interrupts +/** @defgroup LCD_Interrupts LCD Interrupts * @{ */ #define LCD_IT_SOF LCD_FCR_SOFIE #define LCD_IT_UDD LCD_FCR_UDDIE -#define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00)) - -#define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD)) - /** * @} */ -/** @defgroup LCD_PulseOnDuration +/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration * @{ */ -#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ -#define LCD_PULSEONDURATION_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */ -#define LCD_PULSEONDURATION_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */ -#define LCD_PULSEONDURATION_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */ -#define LCD_PULSEONDURATION_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */ -#define LCD_PULSEONDURATION_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */ -#define LCD_PULSEONDURATION_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */ -#define LCD_PULSEONDURATION_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */ - -#define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PULSEONDURATION_0) || \ - ((DURATION) == LCD_PULSEONDURATION_1) || \ - ((DURATION) == LCD_PULSEONDURATION_2) || \ - ((DURATION) == LCD_PULSEONDURATION_3) || \ - ((DURATION) == LCD_PULSEONDURATION_4) || \ - ((DURATION) == LCD_PULSEONDURATION_5) || \ - ((DURATION) == LCD_PULSEONDURATION_6) || \ - ((DURATION) == LCD_PULSEONDURATION_7)) +#define LCD_PULSEONDURATION_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */ +#define LCD_PULSEONDURATION_1 (LCD_FCR_PON_0) /*!< Pulse ON duration = 1/CK_PS */ +#define LCD_PULSEONDURATION_2 (LCD_FCR_PON_1) /*!< Pulse ON duration = 2/CK_PS */ +#define LCD_PULSEONDURATION_3 (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS */ +#define LCD_PULSEONDURATION_4 (LCD_FCR_PON_2) /*!< Pulse ON duration = 4/CK_PS */ +#define LCD_PULSEONDURATION_5 (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS */ +#define LCD_PULSEONDURATION_6 (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS */ +#define LCD_PULSEONDURATION_7 (LCD_FCR_PON) /*!< Pulse ON duration = 7/CK_PS */ + +#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \ + ((__DURATION__) == LCD_PULSEONDURATION_1) || \ + ((__DURATION__) == LCD_PULSEONDURATION_2) || \ + ((__DURATION__) == LCD_PULSEONDURATION_3) || \ + ((__DURATION__) == LCD_PULSEONDURATION_4) || \ + ((__DURATION__) == LCD_PULSEONDURATION_5) || \ + ((__DURATION__) == LCD_PULSEONDURATION_6) || \ + ((__DURATION__) == LCD_PULSEONDURATION_7)) /** * @} */ +/** @defgroup LCD_HighDrive LCD HighDrive + * @{ + */ + +#define LCD_HIGHDRIVE_0 ((uint32_t)0x00000000) /*!< Low resistance Drive */ +#define LCD_HIGHDRIVE_1 (LCD_FCR_HD) /*!< High resistance Drive */ + +#define IS_LCD_HIGHDRIVE(__HIGHDRIVE__) (((__HIGHDRIVE__) == LCD_HIGHDRIVE_0) || \ + ((__HIGHDRIVE__) == LCD_HIGHDRIVE_1)) +/** + * @} + */ -/** @defgroup LCD_DeadTime +/** @defgroup LCD_DeadTime LCD Dead Time * @{ */ -#define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */ -#define LCD_DEADTIME_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */ -#define LCD_DEADTIME_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */ -#define LCD_DEADTIME_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */ -#define LCD_DEADTIME_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */ -#define LCD_DEADTIME_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */ -#define LCD_DEADTIME_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */ -#define LCD_DEADTIME_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */ - -#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DEADTIME_0) || \ - ((TIME) == LCD_DEADTIME_1) || \ - ((TIME) == LCD_DEADTIME_2) || \ - ((TIME) == LCD_DEADTIME_3) || \ - ((TIME) == LCD_DEADTIME_4) || \ - ((TIME) == LCD_DEADTIME_5) || \ - ((TIME) == LCD_DEADTIME_6) || \ - ((TIME) == LCD_DEADTIME_7)) +#define LCD_DEADTIME_0 ((uint32_t)0x00000000) /*!< No dead Time */ +#define LCD_DEADTIME_1 (LCD_FCR_DEAD_0) /*!< One Phase between different couple of Frame */ +#define LCD_DEADTIME_2 (LCD_FCR_DEAD_1) /*!< Two Phase between different couple of Frame */ +#define LCD_DEADTIME_3 (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */ +#define LCD_DEADTIME_4 (LCD_FCR_DEAD_2) /*!< Four Phase between different couple of Frame */ +#define LCD_DEADTIME_5 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame */ +#define LCD_DEADTIME_6 (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame */ +#define LCD_DEADTIME_7 (LCD_FCR_DEAD) /*!< Seven Phase between different couple of Frame */ + +#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \ + ((__TIME__) == LCD_DEADTIME_1) || \ + ((__TIME__) == LCD_DEADTIME_2) || \ + ((__TIME__) == LCD_DEADTIME_3) || \ + ((__TIME__) == LCD_DEADTIME_4) || \ + ((__TIME__) == LCD_DEADTIME_5) || \ + ((__TIME__) == LCD_DEADTIME_6) || \ + ((__TIME__) == LCD_DEADTIME_7)) /** * @} */ -/** @defgroup LCD_BlinkMode +/** @defgroup LCD_BlinkMode LCD Blink Mode * @{ */ -#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */ -#define LCD_BLINKMODE_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ -#define LCD_BLINKMODE_SEG0_ALLCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to +#define LCD_BLINKMODE_OFF ((uint32_t)0x00000000) /*!< Blink disabled */ +#define LCD_BLINKMODE_SEG0_COM0 (LCD_FCR_BLINK_0) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */ +#define LCD_BLINKMODE_SEG0_ALLCOM (LCD_FCR_BLINK_1) /*!< Blink enabled on SEG[0], all COM (up to 8 pixels according to the programmed duty) */ -#define LCD_BLINKMODE_ALLSEG_ALLCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */ +#define LCD_BLINKMODE_ALLSEG_ALLCOM (LCD_FCR_BLINK) /*!< Blink enabled on all SEG and all COM (all pixels) */ -#define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BLINKMODE_OFF) || \ - ((MODE) == LCD_BLINKMODE_SEG0_COM0) || \ - ((MODE) == LCD_BLINKMODE_SEG0_ALLCOM) || \ - ((MODE) == LCD_BLINKMODE_ALLSEG_ALLCOM)) +#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF) || \ + ((__MODE__) == LCD_BLINKMODE_SEG0_COM0) || \ + ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM) || \ + ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM)) /** * @} */ -/** @defgroup LCD_BlinkFrequency +/** @defgroup LCD_BlinkFrequency LCD Blink Frequency * @{ */ -#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ -#define LCD_BLINKFREQUENCY_DIV16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */ -#define LCD_BLINKFREQUENCY_DIV32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */ -#define LCD_BLINKFREQUENCY_DIV64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */ -#define LCD_BLINKFREQUENCY_DIV128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */ -#define LCD_BLINKFREQUENCY_DIV256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */ -#define LCD_BLINKFREQUENCY_DIV512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */ -#define LCD_BLINKFREQUENCY_DIV1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */ - -#define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BLINKFREQUENCY_DIV8) || \ - ((FREQUENCY) == LCD_BLINKFREQUENCY_DIV16) || \ - ((FREQUENCY) == LCD_BLINKFREQUENCY_DIV32) || \ - ((FREQUENCY) == LCD_BLINKFREQUENCY_DIV64) || \ - ((FREQUENCY) == LCD_BLINKFREQUENCY_DIV128) || \ - ((FREQUENCY) == LCD_BLINKFREQUENCY_DIV256) || \ - ((FREQUENCY) == LCD_BLINKFREQUENCY_DIV512) || \ - ((FREQUENCY) == LCD_BLINKFREQUENCY_DIV1024)) +#define LCD_BLINKFREQUENCY_DIV8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */ +#define LCD_BLINKFREQUENCY_DIV16 (LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/16 */ +#define LCD_BLINKFREQUENCY_DIV32 (LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/32 */ +#define LCD_BLINKFREQUENCY_DIV64 (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64 */ +#define LCD_BLINKFREQUENCY_DIV128 (LCD_FCR_BLINKF_2) /*!< The Blink frequency = fLCD/128 */ +#define LCD_BLINKFREQUENCY_DIV256 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/256 */ +#define LCD_BLINKFREQUENCY_DIV512 (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1) /*!< The Blink frequency = fLCD/512 */ +#define LCD_BLINKFREQUENCY_DIV1024 (LCD_FCR_BLINKF) /*!< The Blink frequency = fLCD/1024 */ + +#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \ + ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024)) /** * @} */ -/** @defgroup LCD_Contrast +/** @defgroup LCD_Contrast LCD Contrast * @{ */ -#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ -#define LCD_CONTRASTLEVEL_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */ -#define LCD_CONTRASTLEVEL_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */ -#define LCD_CONTRASTLEVEL_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */ -#define LCD_CONTRASTLEVEL_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */ -#define LCD_CONTRASTLEVEL_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */ -#define LCD_CONTRASTLEVEL_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */ -#define LCD_CONTRASTLEVEL_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */ - -#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_CONTRASTLEVEL_0) || \ - ((CONTRAST) == LCD_CONTRASTLEVEL_1) || \ - ((CONTRAST) == LCD_CONTRASTLEVEL_2) || \ - ((CONTRAST) == LCD_CONTRASTLEVEL_3) || \ - ((CONTRAST) == LCD_CONTRASTLEVEL_4) || \ - ((CONTRAST) == LCD_CONTRASTLEVEL_5) || \ - ((CONTRAST) == LCD_CONTRASTLEVEL_6) || \ - ((CONTRAST) == LCD_CONTRASTLEVEL_7)) +#define LCD_CONTRASTLEVEL_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */ +#define LCD_CONTRASTLEVEL_1 (LCD_FCR_CC_0) /*!< Maximum Voltage = 2.73V */ +#define LCD_CONTRASTLEVEL_2 (LCD_FCR_CC_1) /*!< Maximum Voltage = 2.86V */ +#define LCD_CONTRASTLEVEL_3 (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V */ +#define LCD_CONTRASTLEVEL_4 (LCD_FCR_CC_2) /*!< Maximum Voltage = 3.12V */ +#define LCD_CONTRASTLEVEL_5 (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V */ +#define LCD_CONTRASTLEVEL_6 (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V */ +#define LCD_CONTRASTLEVEL_7 (LCD_FCR_CC) /*!< Maximum Voltage = 3.51V */ + +#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \ + ((__CONTRAST__) == LCD_CONTRASTLEVEL_7)) /** * @} */ -/** @defgroup LCD_Flag +/** @defgroup LCD_Flag LCD Flag * @{ */ @@ -417,16 +431,11 @@ typedef struct #define LCD_FLAG_RDY LCD_SR_RDY #define LCD_FLAG_FCRSF LCD_SR_FCRSR -#define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \ - ((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \ - ((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF)) - -#define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00)) /** * @} */ -/** @defgroup LCD_RAMRegister +/** @defgroup LCD_RAMRegister LCD RAMRegister * @{ */ @@ -447,22 +456,22 @@ typedef struct #define LCD_RAM_REGISTER14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */ #define LCD_RAM_REGISTER15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */ -#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAM_REGISTER0) || \ - ((REGISTER) == LCD_RAM_REGISTER1) || \ - ((REGISTER) == LCD_RAM_REGISTER2) || \ - ((REGISTER) == LCD_RAM_REGISTER3) || \ - ((REGISTER) == LCD_RAM_REGISTER4) || \ - ((REGISTER) == LCD_RAM_REGISTER5) || \ - ((REGISTER) == LCD_RAM_REGISTER6) || \ - ((REGISTER) == LCD_RAM_REGISTER7) || \ - ((REGISTER) == LCD_RAM_REGISTER8) || \ - ((REGISTER) == LCD_RAM_REGISTER9) || \ - ((REGISTER) == LCD_RAM_REGISTER10) || \ - ((REGISTER) == LCD_RAM_REGISTER11) || \ - ((REGISTER) == LCD_RAM_REGISTER12) || \ - ((REGISTER) == LCD_RAM_REGISTER13) || \ - ((REGISTER) == LCD_RAM_REGISTER14) || \ - ((REGISTER) == LCD_RAM_REGISTER15)) +#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0) || \ + ((__REGISTER__) == LCD_RAM_REGISTER1) || \ + ((__REGISTER__) == LCD_RAM_REGISTER2) || \ + ((__REGISTER__) == LCD_RAM_REGISTER3) || \ + ((__REGISTER__) == LCD_RAM_REGISTER4) || \ + ((__REGISTER__) == LCD_RAM_REGISTER5) || \ + ((__REGISTER__) == LCD_RAM_REGISTER6) || \ + ((__REGISTER__) == LCD_RAM_REGISTER7) || \ + ((__REGISTER__) == LCD_RAM_REGISTER8) || \ + ((__REGISTER__) == LCD_RAM_REGISTER9) || \ + ((__REGISTER__) == LCD_RAM_REGISTER10) || \ + ((__REGISTER__) == LCD_RAM_REGISTER11) || \ + ((__REGISTER__) == LCD_RAM_REGISTER12) || \ + ((__REGISTER__) == LCD_RAM_REGISTER13) || \ + ((__REGISTER__) == LCD_RAM_REGISTER14) || \ + ((__REGISTER__) == LCD_RAM_REGISTER15)) /** * @} @@ -474,7 +483,7 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ -/** @defgroup LCD_Exported_Macros +/** @defgroup LCD_Exported_Macros LCD Exported Macros * @{ */ @@ -482,14 +491,14 @@ typedef struct * @param __HANDLE__: specifies the LCD Handle. * @retval None */ -#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET) +#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LCD_STATE_RESET) /** @brief macros to enables or disables the LCD * @param __HANDLE__: specifies the LCD Handle. * @retval None */ -#define __HAL_LCD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= LCD_CR_LCDEN) -#define __HAL_LCD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~LCD_CR_LCDEN) +#define __HAL_LCD_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)) +#define __HAL_LCD_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN)) /** @brief Macros to enable or disable the low resistance divider. Displays with high * internal resistance may need a longer drive time to achieve @@ -502,15 +511,16 @@ typedef struct */ #define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__) \ do{ \ - ((__HANDLE__)->Instance->FCR |= LCD_FCR_HD); \ + SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \ LCD_WaitForSynchro(__HANDLE__); \ }while(0) #define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__) \ do{ \ - ((__HANDLE__)->Instance->FCR &= ~LCD_FCR_HD); \ + CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \ LCD_WaitForSynchro(__HANDLE__); \ }while(0) + /** * @brief Macro to configure the LCD pulses on duration. * @param __HANDLE__: specifies the LCD Handle. @@ -574,6 +584,7 @@ typedef struct MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__)); \ LCD_WaitForSynchro(__HANDLE__); \ } while(0) + /** * @brief Macro to configure the LCD Blink mode and Blink frequency. * @param __HANDLE__: specifies the LCD Handle. @@ -610,16 +621,17 @@ typedef struct * @arg LCD_IT_UDD: Update Display Done Interrupt * @retval None */ -#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - do{ \ - ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)); \ - LCD_WaitForSynchro(__HANDLE__); \ +#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \ + LCD_WaitForSynchro(__HANDLE__); \ }while(0) -#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - do{ \ - ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__));\ - LCD_WaitForSynchro(__HANDLE__); \ - }while(0) +#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \ + LCD_WaitForSynchro(__HANDLE__); \ + }while(0) + /** @brief Checks whether the specified LCD interrupt is enabled or not. * @param __HANDLE__: specifies the LCD Handle. * @param __IT__: specifies the LCD interrupt source to check. @@ -653,48 +665,81 @@ typedef struct * in the LCDCLK domain. * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) +#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified LCD pending flag. * @param __HANDLE__: specifies the LCD Handle. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__: specifies the flag to clear. * This parameter can be any combination of the following values: * @arg LCD_FLAG_SOF: Start of Frame Interrupt * @arg LCD_FLAG_UDD: Update Display Done Interrupt * @retval None */ -#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLR = (__FLAG__)) +#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLR = (__FLAG__)) /** * @} */ /* Exported functions ------------------------------------------------------- */ + +/** @addtogroup LCD_Exported_Functions + * @{ + */ + +/** @addtogroup LCD_Exported_Functions_Group1 + * @{ + */ + /* Initialization/de-initialization methods **********************************/ -HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd); -HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd); -void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd); -void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd); - +HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd); +HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd); +void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd); +void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd); + +/** + * @} + */ + +/** @addtogroup LCD_Exported_Functions_Group2 + * @{ + */ + /* IO operation methods *******************************************************/ -HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data); -HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd); -HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd); +HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data); +HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd); +HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd); + +/** + * @} + */ + +/** @addtogroup LCD_Exported_Functions_Group3 + * @{ + */ /* Peripheral State methods **************************************************/ -HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd); -uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd); +HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd); +uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd); -/* Private functions ---------------------------------------------------------*/ -HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); +/** + * @} + */ + +/** + * @} + */ -#endif /* STM32L051xx && STM32L052xx && STM32L062xx && STM32L061xx*/ +/** @addtogroup LCD_Private_Functions + * @{ + */ -#ifdef __cplusplus -} -#endif +/* Private functions ---------------------------------------------------------*/ +HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); -#endif /* __STM32L0xx_HAL_LCD_H */ +/** + * @} + */ /** * @} @@ -704,4 +749,14 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd); * @} */ -/******************* (C) COPYRIGHT 2014 STMicroelectronics *****END OF FILE****/ +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_HAL_LCD_H */ + + +#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ + +/******************* (C) COPYRIGHT 2015 STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.c index 9fb54814adc..76fa2678465 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_lptim.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief LPTIM HAL module driver. * * This file provides firmware functions to manage the following @@ -23,7 +23,7 @@ (#)Initialize the LPTIM low level resources by implementing the HAL_LPTIM_MspInit(): - (##) Enable the LPTIM interface clock using __LPTIM1_CLK_ENABLE(). + (##) Enable the LPTIM interface clock using __HAL_RCC_LPTIM1_CLK_ENABLE(). (##) In case of using interrupts (e.g. HAL_LPTIM_PWM_Start_IT()): (+) Configure the LPTIM interrupt priority using HAL_NVIC_SetPriority(). (+) Enable the LPTIM IRQ handler using HAL_NVIC_EnableIRQ(). @@ -94,7 +94,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -128,24 +128,18 @@ * @{ */ -/** @defgroup LPTIM +/** @addtogroup LPTIM * @brief LPTIM HAL module driver. * @{ */ #ifdef HAL_LPTIM_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup LPTIM_Private_Functions + +/** @addtogroup LPTIM_Exported_Functions * @{ */ -/** @defgroup LPTIM_Group1 Initialization/de-initialization functions +/** @addtogroup LPTIM_Exported_Functions_Group1 * @brief Initialization and Configuration functions. * @verbatim @@ -166,7 +160,7 @@ /** * @brief Initializes the LPTIM according to the specified parameters in the * LPTIM_InitTypeDef and creates the associated handle. - * @param hlptim: LPTIM handle + * @param hlptim : LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) @@ -174,7 +168,7 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) uint32_t tmpcfgr = 0; /* Check the LPTIM handle allocation */ - if(hlptim == HAL_NULL) + if(hlptim == NULL) { return HAL_ERROR; } @@ -257,13 +251,13 @@ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim) /** * @brief DeInitializes the LPTIM peripheral. - * @param hlptim: LPTIM handle + * @param hlptim : LPTIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) { /* Check the LPTIM handle allocation */ - if(hlptim == HAL_NULL) + if(hlptim == NULL) { return HAL_ERROR; } @@ -289,7 +283,7 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim) /** * @brief Initializes the LPTIM MSP. - * @param hlptim: LPTIM handle + * @param hlptim : LPTIM handle * @retval None */ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) @@ -301,7 +295,7 @@ __weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim) /** * @brief DeInitializes LPTIM MSP. - * @param hlptim: LPTIM handle + * @param hlptim : LPTIM handle * @retval None */ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) @@ -315,7 +309,7 @@ __weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Group2 LPTIM Start-Stop operation functions +/** @addtogroup LPTIM_Exported_Functions_Group2 * @brief Start-Stop operation functions. * @verbatim @@ -428,22 +422,22 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_ARROK); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_CMPOK); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_ARRM); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_CMPM); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then enable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_EXTTRIG); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Enable the Peripheral */ @@ -482,22 +476,22 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE(hlptim); /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_ARROK); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_CMPOK); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_ARRM); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_CMPM); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then disable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_EXTTRIG); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Change the TIM state*/ @@ -538,7 +532,7 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t /* Load the pulse value in the compare register */ __HAL_LPTIM_COMPARE_SET(hlptim, Pulse); - /* Start timer in continuous mode */ + /* Start timer in single mode */ __HAL_LPTIM_START_SINGLE(hlptim); /* Change the TIM state*/ @@ -594,22 +588,22 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3 hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_ARROK); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_CMPOK); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_ARRM); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_CMPM); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then enable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_EXTTRIG); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Enable the Peripheral */ @@ -648,22 +642,22 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE(hlptim); /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_ARROK); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_CMPOK); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_ARRM); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_CMPM); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then disable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_EXTTRIG); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Change the TIM state*/ @@ -760,22 +754,22 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_ARROK); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); /* Enable Compare write complete interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_CMPOK); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPOK); /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_ARRM); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_CMPM); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then enable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Enable external trigger interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_EXTTRIG); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Enable the Peripheral */ @@ -814,22 +808,22 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE(hlptim); /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_ARROK); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Compare write complete interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_CMPOK); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPOK); /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_ARRM); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_CMPM); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); /* If external trigger source is used, then disable external trigger interrupt */ if ((hlptim->Init.Trigger.Source) != LPTIM_TRIGSOURCE_SOFTWARE) { /* Disable external trigger interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_EXTTRIG); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_EXTTRIG); } /* Change the TIM state*/ @@ -956,10 +950,10 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; /* Enable "switch to down direction" interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_DOWN); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); /* Enable "switch to up direction" interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_UP); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_UP); /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -997,10 +991,10 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim) hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; /* Disable "switch to down direction" interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_DOWN); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_DOWN); /* Disable "switch to up direction" interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_UP); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_UP); /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; @@ -1103,7 +1097,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; /* Enable Compare match interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_CMPM); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -1144,7 +1138,7 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim) hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; /* Disable Compare match interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_CMPM); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_CMPM); /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; @@ -1243,10 +1237,10 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32 } /* Enable Autoreload write complete interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_ARROK); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); /* Enable Autoreload match interrupt */ - __HAL_LPTIM_ENABLE_INTERRUPT(hlptim, LPTIM_IT_ARRM); + __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARRM); /* Enable the Peripheral */ __HAL_LPTIM_ENABLE(hlptim); @@ -1281,10 +1275,10 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) __HAL_LPTIM_DISABLE(hlptim); /* Disable Autoreload write complete interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_ARROK); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); /* Disable Autoreload match interrupt */ - __HAL_LPTIM_DISABLE_INTERRUPT(hlptim, LPTIM_IT_ARRM); + __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); /* Change the TIM state*/ hlptim->State= HAL_LPTIM_STATE_READY; @@ -1297,7 +1291,7 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Group3 LPTIM Read operation functions +/** @addtogroup LPTIM_Exported_Functions_Group3 * @brief Read operation functions. * @verbatim @@ -1357,7 +1351,7 @@ uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim) -/** @defgroup LPTIM_Group4 LPTIM IRQ handler +/** @addtogroup LPTIM_Exported_Functions_Group4 * @brief LPTIM IRQ handler. * @verbatim @@ -1380,7 +1374,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Compare match interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPM) != RESET) { - if(__HAL_LPTIM_GET_ITSTATUS(hlptim, LPTIM_IT_CMPM) !=RESET) + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPM) !=RESET) { /* Clear Compare match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM); @@ -1393,7 +1387,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Autoreload match interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARRM) != RESET) { - if(__HAL_LPTIM_GET_ITSTATUS(hlptim, LPTIM_IT_ARRM) !=RESET) + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARRM) !=RESET) { /* Clear Autoreload match flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM); @@ -1406,7 +1400,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Trigger detected interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_EXTTRIG) != RESET) { - if(__HAL_LPTIM_GET_ITSTATUS(hlptim, LPTIM_IT_EXTTRIG) !=RESET) + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_EXTTRIG) !=RESET) { /* Clear Trigger detected flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG); @@ -1419,7 +1413,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Compare write interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_CMPOK) != RESET) { - if(__HAL_LPTIM_GET_ITSTATUS(hlptim, LPTIM_IT_CMPOK) !=RESET) + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_CMPOK) !=RESET) { /* Clear Compare write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK); @@ -1432,7 +1426,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Autoreload write interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_ARROK) != RESET) { - if(__HAL_LPTIM_GET_ITSTATUS(hlptim, LPTIM_IT_ARROK) !=RESET) + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_ARROK) !=RESET) { /* Clear Autoreload write flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK); @@ -1445,7 +1439,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Direction counter changed from Down to Up interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_UP) != RESET) { - if(__HAL_LPTIM_GET_ITSTATUS(hlptim, LPTIM_IT_UP) !=RESET) + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_UP) !=RESET) { /* Clear Direction counter changed from Down to Up flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP); @@ -1458,7 +1452,7 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim) /* Direction counter changed from Up to Down interrupt */ if(__HAL_LPTIM_GET_FLAG(hlptim, LPTIM_FLAG_DOWN) != RESET) { - if(__HAL_LPTIM_GET_ITSTATUS(hlptim, LPTIM_IT_DOWN) !=RESET) + if(__HAL_LPTIM_GET_IT_SOURCE(hlptim, LPTIM_IT_DOWN) !=RESET) { /* Clear Direction counter changed from Up to Down flag */ __HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN); @@ -1557,7 +1551,7 @@ __weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim) * @} */ -/** @defgroup LPTIM_Group5 Peripheral State functions +/** @addtogroup LPTIM_Exported_Functions_Group5 * @brief Peripheral State functions. * @verbatim @@ -1585,12 +1579,17 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) * @} */ +/** + * @} + */ /** * @} */ #endif /* HAL_LPTIM_MODULE_ENABLED */ + + /** * @} */ @@ -1600,3 +1599,4 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.h index 6188cab0392..7f1abbadfac 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_lptim.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of LPTIM HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,12 +50,18 @@ * @{ */ -/** @addtogroup LPTIM +/** @defgroup LPTIM LPTIM (Low power timer) * @{ */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ +/** @defgroup LPTIM_Clock_Configuration LPTIM Clock configuration structure + * @{ + */ /** * @brief LPTIM Clock configuration definition */ @@ -68,9 +74,15 @@ typedef struct This parameter can be a value of @ref LPTIM_Clock_Prescaler */ }LPTIM_ClockConfigTypeDef; +/** + * @} + */ +/** @defgroup LPTIM_ULPClock_Configuration LPTIM ULP Clock configuration structure + * @{ + */ /** - * @brief LPTIM Clock configuration definition + * @brief LPTIM ULP Clock configuration definition */ typedef struct { @@ -86,9 +98,15 @@ typedef struct This parameter can be a value of @ref LPTIM_Clock_Sample_Time */ }LPTIM_ULPClockConfigTypeDef; +/** + * @} + */ +/** @defgroup LPTIM_Trigger_Configuration LPTIM Trigger configuration structure + * @{ + */ /** - * @brief LPTIM Trigger configuration definition + * @brief LPTIM Trigger configuration structure */ typedef struct { @@ -103,7 +121,13 @@ typedef struct Note: This parameter is used only when an external trigger is used. This parameter can be a value of @ref LPTIM_Trigger_Sample_Time */ }LPTIM_TriggerConfigTypeDef; +/** + * @} + */ +/** @defgroup LPTIM_Init_Configuration LPTIM Initialization configuration structure + * @{ + */ /** * @brief LPTIM Initialization Structure definition */ @@ -127,7 +151,12 @@ typedef struct This parameter can be a value of @ref LPTIM_Counter_Source */ }LPTIM_InitTypeDef; - +/** + * @} + */ +/** @defgroup LPTIM_State_structure LPTIM state definition + * @{ + */ /** * @brief HAL LPTIM State structure definition */ @@ -139,7 +168,13 @@ typedef enum __HAL_LPTIM_StateTypeDef HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */ }HAL_LPTIM_StateTypeDef; +/** + * @} + */ +/** @defgroup LPTIM_Handle LPTIM handler + * @{ + */ /** * @brief LPTIM handle Structure definition */ @@ -157,41 +192,38 @@ typedef struct }LPTIM_HandleTypeDef; -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup LPTIM_Exported_Constants - * @{ - */ - -/** @defgroup LPTIM_Autorelaod_Value - * @{ +/** + * @} */ -#define IS_LPTIM_AUTORELOAD(AUTORELOAD) ((AUTORELOAD) <= 0x0000FFFF) /** * @} */ -/** @defgroup LPTIM_Compare_Value +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup LPTIM_Exported_Constants LPTIM Exported constants * @{ */ -#define IS_LPTIM_COMPARE(COMPARE) ((COMPARE) <= 0x0000FFFF) -/** - * @} - */ -/** @defgroup LPTIM_Clock_Source +/* Check autoreload value */ +#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF) + +/* Check compare value */ +#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF) + +/** @defgroup LPTIM_Clock_Source Clock source * @{ */ #define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00) #define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL - -#define IS_LPTIM_CLOCK_SOURCE(SOURCE) (((SOURCE) == LPTIM_CLOCKSOURCE_ULPTIM) || \ - ((SOURCE) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) /** * @} */ +#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \ + ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC)) + -/** @defgroup LPTIM_Clock_Prescaler +/** @defgroup LPTIM_Clock_Prescaler Prescaler * @{ */ #define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000) @@ -202,160 +234,127 @@ typedef struct #define LPTIM_PRESCALER_DIV32 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)) #define LPTIM_PRESCALER_DIV64 ((uint32_t)(LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)) #define LPTIM_PRESCALER_DIV128 ((uint32_t)LPTIM_CFGR_PRESC) - -#define IS_LPTIM_CLOCK_PRESCALER(PRESCALER) (((PRESCALER) == LPTIM_PRESCALER_DIV1 ) || \ - ((PRESCALER) == LPTIM_PRESCALER_DIV2 ) || \ - ((PRESCALER) == LPTIM_PRESCALER_DIV4 ) || \ - ((PRESCALER) == LPTIM_PRESCALER_DIV8 ) || \ - ((PRESCALER) == LPTIM_PRESCALER_DIV16 ) || \ - ((PRESCALER) == LPTIM_PRESCALER_DIV32 ) || \ - ((PRESCALER) == LPTIM_PRESCALER_DIV64 ) || \ - ((PRESCALER) == LPTIM_PRESCALER_DIV128)) -#define IS_LPTIM_CLOCK_PRESCALERDIV1(PRESCALER) ((PRESCALER) == LPTIM_PRESCALER_DIV1) /** * @} - */ + */ + +#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LPTIM_PRESCALER_DIV1 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV2 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV4 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV8 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV16 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV32 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV64 ) || \ + ((__PRESCALER__) == LPTIM_PRESCALER_DIV128)) + +#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) == LPTIM_PRESCALER_DIV1) -/** @defgroup LPTIM_Output_Polarity + +/** @defgroup LPTIM_Output_Polarity Output polarity * @{ */ - #define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000) #define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL) -#define IS_LPTIM_OUTPUT_POLARITY(POLARITY) (((POLARITY) == LPTIM_OUTPUTPOLARITY_LOW ) || \ - ((POLARITY) == LPTIM_OUTPUTPOLARITY_HIGH)) /** * @} */ +#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \ + ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH)) -/** @defgroup LPTIM_Clock_Sample_Time +/** @defgroup LPTIM_Clock_Sample_Time Clock sample time * @{ */ -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION ((uint32_t)0x00000000) -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CFGR_CKFLT_0 -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CFGR_CKFLT_1 -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CFGR_CKFLT -#define IS_LPTIM_CLOCK_SAMPLE_TIME(SAMPLETIME) (((SAMPLETIME) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION) || \ - ((SAMPLETIME) == LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS) || \ - ((SAMPLETIME) == LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS) || \ - ((SAMPLETIME) == LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS)) +#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0 +#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1 +#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT /** * @} */ +#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS) || \ + ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS)) -/** @defgroup LPTIM_Clock_Polarity +/** @defgroup LPTIM_Clock_Polarity Clock polarity * @{ */ - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE ((uint32_t)0x00000000) -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CFGR_CKPOL_0 -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CFGR_CKPOL_1 -#define IS_LPTIM_CLOCK_POLARITY(POLARITY) (((POLARITY) == LPTIM_CLOCKPOLARITY_RISINGEDGE) || \ - ((POLARITY) == LPTIM_CLOCKPOLARITY_FALLINGEDGE) || \ - ((POLARITY) == LPTIM_CLOCKPOLARITY_BOTHEDGES)) - +#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000) +#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0 +#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1 /** * @} */ -/** @defgroup LPTIM_Trigger_Source - * @{ - */ -#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF) -#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000) -#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0) -#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 -#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) -#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 -#define LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2) -#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL -#define IS_LPTIM_TRG_SOURCE(TRIG) (((TRIG) == LPTIM_TRIGSOURCE_SOFTWARE) || \ - ((TRIG) == LPTIM_TRIGSOURCE_0) || \ - ((TRIG) == LPTIM_TRIGSOURCE_1) || \ - ((TRIG) == LPTIM_TRIGSOURCE_2) || \ - ((TRIG) == LPTIM_TRIGSOURCE_3) || \ - ((TRIG) == LPTIM_TRIGSOURCE_4) || \ - ((TRIG) == LPTIM_TRIGSOURCE_6) || \ - ((TRIG) == LPTIM_TRIGSOURCE_7)) -/** - * @} - */ +#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING)) -/** @defgroup LPTIM_External_Trigger_Polarity +/** @defgroup LPTIM_External_Trigger_Polarity Trigger polarity * @{ */ #define LPTIM_ACTIVEEDGE_RISING LPTIM_CFGR_TRIGEN_0 #define LPTIM_ACTIVEEDGE_FALLING LPTIM_CFGR_TRIGEN_1 #define LPTIM_ACTIVEEDGE_RISING_FALLING LPTIM_CFGR_TRIGEN -#define IS_LPTIM_EXT_TRG_POLARITY(POLAR) (((POLAR) == LPTIM_ACTIVEEDGE_RISING ) || \ - ((POLAR) == LPTIM_ACTIVEEDGE_FALLING ) || \ - ((POLAR) == LPTIM_ACTIVEEDGE_RISING_FALLING )) - /** * @} */ +#define IS_LPTIM_EXT_TRG_POLARITY(__POLAR__) (((__POLAR__) == LPTIM_ACTIVEEDGE_RISING ) || \ + ((__POLAR__) == LPTIM_ACTIVEEDGE_FALLING ) || \ + ((__POLAR__) == LPTIM_ACTIVEEDGE_RISING_FALLING )) -/** @defgroup LPTIM_Trigger_Sample_Time +/** @defgroup LPTIM_Trigger_Sample_Time Trigger sample time * @{ */ -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION ((uint32_t)0x00000000) -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_CFGR_TRGFLT_0 -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_CFGR_TRGFLT_1 -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_CFGR_TRGFLT -#define IS_LPTIM_TRIG_SAMPLE_TIME(SAMPLETIME) (((SAMPLETIME) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION) || \ - ((SAMPLETIME) == LPTIM_TRIGSAMPLETIME_2TRANSISTIONS ) || \ - ((SAMPLETIME) == LPTIM_TRIGSAMPLETIME_4TRANSISTIONS ) || \ - ((SAMPLETIME) == LPTIM_TRIGSAMPLETIME_8TRANSISTIONS )) +#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000) +#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0 +#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1 +#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT /** * @} */ +#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS ) || \ + ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS )) -/** @defgroup LPTIM_Updating_Mode + +/** @defgroup LPTIM_Updating_Mode Updating mode * @{ */ #define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000) #define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD -#define IS_LPTIM_UPDATE_MODE(MODE) (((MODE) == LPTIM_UPDATE_IMMEDIATE) || \ - ((MODE) == LPTIM_UPDATE_ENDOFPERIOD)) - /** * @} */ +#define IS_LPTIM_UPDATE_MODE(__MODE__) (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \ + ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD)) -/** @defgroup LPTIM_Counter_Source + + +/** @defgroup LPTIM_Counter_Source Counter source * @{ */ - #define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000) #define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE -#define IS_LPTIM_COUNTER_SOURCE(SOURCE) (((SOURCE) == LPTIM_COUNTERSOURCE_INTERNAL) || \ - ((SOURCE) == LPTIM_COUNTERSOURCE_EXTERNAL)) - /** * @} */ +#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ + ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -/** @defgroup LPTIM_Autorelaod_Value - * @{ - */ -#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF) -/** - * @} - */ -/** @defgroup LPTIM_Compare_Value - * @{ - */ -#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF) -/** - * @} - */ - -/** @defgroup LPTIM_Flag_Definition + +/* Check for period value */ +#define IS_LPTIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0x0000FFFF) + +/* Check for pulse value */ +#define IS_LPTIM_PULSE(__PULSE__) ((__PULSE__) <= 0x0000FFFF) + +/** @defgroup LPTIM_Flag_Definition Flag definition * @{ */ - #define LPTIM_FLAG_DOWN LPTIM_ISR_DOWN #define LPTIM_FLAG_UP LPTIM_ISR_UP #define LPTIM_FLAG_ARROK LPTIM_ISR_ARROK @@ -363,20 +362,13 @@ typedef struct #define LPTIM_FLAG_EXTTRIG LPTIM_ISR_EXTTRIG #define LPTIM_FLAG_ARRM LPTIM_ISR_ARRM #define LPTIM_FLAG_CMPM LPTIM_ISR_CMPM -#define IS_LPTIM_FLAG_(FLAG) (((FLAG) == LPTIM_FLAG_DOWN) || \ - ((FLAG) == LPTIM_FLAG_UP) || \ - ((FLAG) == LPTIM_FLAG_ARROK) || \ - ((FLAG) == LPTIM_FLAG_CMPOK) || \ - ((FLAG) == LPTIM_FLAG_EXTTRIG) || \ - ((FLAG) == LPTIM_FLAG_ARRM) || \ - ((FLAG) == LPTIM_FLAG_CMPM)) /** * @} */ -/** @defgroup LPTIM_Interrupts_Definition + +/** @defgroup LPTIM_Interrupts_Definition Interrupts definition * @{ */ - #define LPTIM_IT_DOWN LPTIM_IER_DOWNIE #define LPTIM_IT_UP LPTIM_IER_UPIE #define LPTIM_IT_ARROK LPTIM_IER_ARROKIE @@ -384,13 +376,6 @@ typedef struct #define LPTIM_IT_EXTTRIG LPTIM_IER_EXTTRIGIE #define LPTIM_IT_ARRM LPTIM_IER_ARRMIE #define LPTIM_IT_CMPM LPTIM_IER_CMPMIE -#define IS_LPTIM_IT(IT) (((IT) == LPTIM_IT_DOWN) || \ - ((IT) == LPTIM_IT_UP) || \ - ((IT) == LPTIM_IT_ARROK) || \ - ((IT) == LPTIM_IT_CMPOK) || \ - ((IT) == LPTIM_IT_EXTTRIG) || \ - ((IT) == LPTIM_IT_ARRM) || \ - ((IT) == LPTIM_IT_CMPM)) /** * @} */ @@ -401,7 +386,7 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ -/** @defgroup LPTIM_Exported_Macros +/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros * @{ */ @@ -490,7 +475,7 @@ typedef struct * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. */ -#define __HAL_LPTIM_ENABLE_INTERRUPT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) +#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) /** * @brief Disable the specified LPTIM interrupt. @@ -506,9 +491,9 @@ typedef struct * @arg LPTIM_IT_CMPM : Compare match Interrupt. * @retval None. */ -#define __HAL_LPTIM_DISABLE_INTERRUPT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) +#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) - /** + /** * @brief Checks whether the specified LPTIM interrupt is set or not. * @param __HANDLE__ : LPTIM handle. * @param __INTERRUPT__ : LPTIM interrupt to check. @@ -523,22 +508,45 @@ typedef struct * @retval Interrupt status. */ -#define __HAL_LPTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** * @} */ - + + +/* Include LPTIM HAL Extension module */ +#include "stm32l0xx_hal_lptim_ex.h" + /* Exported functions --------------------------------------------------------*/ + +/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions + * @{ + */ /* Initialization/de-initialization functions ********************************/ + +/** @defgroup LPTIM_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); + /* MSP functions *************************************************************/ + void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ + /* Start/Stop operation functions *********************************************/ + +/** @defgroup LPTIM_Exported_Functions_Group2 LPTIM Start-Stop operation functions + * @{ + */ + /* ################################# PWM Mode ################################*/ /* Blocking mode: Polling */ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse); @@ -587,12 +595,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ + /* Reading operation functions ************************************************/ + +/** @defgroup LPTIM_Exported_Functions_Group3 LPTIM Read operation functions + * @{ + */ uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); +/** + * @} + */ /* LPTIM IRQ functions *******************************************************/ +/** @defgroup LPTIM_Exported_Functions_Group4 LPTIM IRQ handler + * @{ + */ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); /* CallBack functions ********************************************************/ @@ -603,8 +625,14 @@ void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim); - +/** + * @} + */ /* Peripheral State functions ************************************************/ +/** @defgroup LPTIM_Exported_Functions_Group5 Peripheral State functions + * @{ + */ + HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** @@ -614,7 +642,15 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); /** * @} */ - + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif @@ -622,3 +658,4 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #endif /* __STM32L0xx_HAL_LPTIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim_ex.h new file mode 100644 index 00000000000..52cfc137c15 --- /dev/null +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_lptim_ex.h @@ -0,0 +1,127 @@ +/** + ****************************************************************************** + * @file stm32l0xx_hal_lptim_ex.h + * @author MCD Application Team + * @version V1.2.0 + * @date 06-February-2015 + * @brief Header file of LPTIM Extended HAL module. + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2015 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32L0xx_HAL_LPTIM_EX_H +#define __STM32L0xx_HAL_LPTIM_EX_H + +#ifdef __cplusplus + extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32l0xx_hal_def.h" + +/** @addtogroup STM32L0xx_HAL_Driver + * @{ + */ + +/** @defgroup LPTIMEx LPTIMEx + * @{ + */ + +/* Exported constants --------------------------------------------------------*/ + +/** @defgroup LPTIMEx_Exported_Constants LPTIM Extended Exported constants + * @{ + */ + + +/** @defgroup LPTIM_Trigger_Source Trigger source + * @{ + */ +#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF) +#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000) +#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0) +#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1 +#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1) +#define LPTIM_TRIGSOURCE_4 LPTIM_CFGR_TRIGSEL_2 + +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) +#define LPTIM_TRIGSOURCE_5 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2) +#endif + +#define LPTIM_TRIGSOURCE_6 ((uint32_t)LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2) +#define LPTIM_TRIGSOURCE_7 LPTIM_CFGR_TRIGSEL +/** + * @} + */ + +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_7)) +#else +#define IS_LPTIM_TRG_SOURCE(__TRIG__) (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \ + ((__TRIG__) == LPTIM_TRIGSOURCE_7)) +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32L0xx_HAL_LPTIM_EX_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.c index 6c9ff157c36..3f29c89f412 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pcd.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -28,7 +28,7 @@ (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: (##) Enable the PCD/USB Low Level interface clock using - (+++) __USB_CLK_ENABLE; + (+++) __HAL_RCC_USB_CLK_ENABLE; (##) Initialize the related GPIO clocks (##) Configure PCD pin-out @@ -44,7 +44,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -74,6 +74,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) +#ifdef HAL_PCD_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ @@ -83,7 +85,7 @@ * @{ */ -#ifdef HAL_PCD_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -127,7 +129,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) uint32_t wInterrupt_Mask = 0; /* Check the PCD handle allocation */ - if(hpcd == HAL_NULL) + if(hpcd == NULL) { return HAL_ERROR; } @@ -198,7 +200,7 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) { /* Check the PCD handle allocation */ - if(hpcd == HAL_NULL) + if(hpcd == NULL) { return HAL_ERROR; } @@ -989,22 +991,22 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) } /** - * @brief HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling + * @brief HAL_PCD_ActivateRemoteWakeup : active remote wakeup signalling * @param hpcd: PCD handle * @retval status */ -HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { hpcd->Instance->CNTR |= USB_CNTR_RESUME; return HAL_OK; } /** - * @brief HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling + * @brief HAL_PCD_DeActivateRemoteWakeup : de-active remote wakeup signalling * @param hpcd: PCD handle * @retval status */ -HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd) +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) { hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME); return HAL_OK; @@ -1297,7 +1299,6 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui * @} */ -#endif /* HAL_PCD_MODULE_ENABLED */ /** * @} */ @@ -1305,5 +1306,7 @@ void PCD_ReadPMA(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, ui /** * @} */ - +#endif /* HAL_PCD_MODULE_ENABLED */ +#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.h index 9700adcda6b..ec04658c7e3 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_pcd.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -35,6 +35,8 @@ ****************************************************************************** */ + + /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L0xx_HAL_PCD_H #define __STM32L0xx_HAL_PCD_H @@ -43,6 +45,8 @@ extern "C" { #endif +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" /** @addtogroup STM32L0xx_HAL_Driver @@ -179,8 +183,8 @@ typedef struct PCD_TypeDef *Instance; /*!< Register base address */ PCD_InitTypeDef Init; /*!< PCD required parameters */ __IO uint8_t USB_Address; /*!< USB Address */ - PCD_EPTypeDef IN_ep[5]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[5]; /*!< OUT endpoint parameters */ + PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ + PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ HAL_LockTypeDef Lock; /*!< PCD peripheral status */ __IO PCD_StateTypeDef State; /*!< PCD communication state */ uint32_t Setup[12]; /*!< Setup packet buffer */ @@ -251,11 +255,11 @@ typedef struct #define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__)) #define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR) = ~(__INTERRUPT__)) -#define USB_EXTI_LINE_WAKEUP ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ +#define USB_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */ -#define __HAL_USB_EXTI_ENABLE_IT() EXTI->IMR |= USB_EXTI_LINE_WAKEUP -#define __HAL_USB_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP) -#define __HAL_USB_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_EXTI_LINE_WAKEUP) +#define __HAL_USB_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= USB_WAKEUP_EXTI_LINE +#define __HAL_USB_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_WAKEUP_EXTI_LINE) +#define __HAL_USB_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_WAKEUP_EXTI_LINE) /* Internal macros -----------------------------------------------------------*/ @@ -667,8 +671,8 @@ uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); +HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); /* Peripheral State functions **************************************************/ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); @@ -680,6 +684,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); * @} */ +#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */ + #ifdef __cplusplus } #endif @@ -688,3 +694,4 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd); #endif /* __STM32L0xx_HAL_PCD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.c index f171ae0ece2..1dfd138e393 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Extended PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -12,7 +12,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -39,9 +39,10 @@ ****************************************************************************** */ +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" - +#ifdef HAL_PCD_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ @@ -51,7 +52,7 @@ * @{ */ -#ifdef HAL_PCD_MODULE_ENABLED + /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -139,7 +140,6 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, * @} */ -#endif /* HAL_PCD_MODULE_ENABLED */ /** * @} */ @@ -147,5 +147,6 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, /** * @} */ - +#endif /* HAL_PCD_MODULE_ENABLED */ +#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.h index 3f1d4cc776e..15eadfcca43 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pcd_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_pcd.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -80,3 +80,4 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, #endif /* __STM32L0xx_HAL_PCD_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.c index 6d319221dc6..b0083d949bb 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pwr.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief PWR HAL module driver. * * This file provides firmware functions to manage the following @@ -11,11 +11,10 @@ * + Initialization/de-initialization functions * + Peripheral Control functions * - @verbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -45,43 +44,46 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#ifdef HAL_PWR_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup PWR - * @brief PWR HAL module driver +/** @addtogroup PWR * @{ */ -#ifdef HAL_PWR_MODULE_ENABLED +/** @addtogroup PWR_Private_Defines + * @{ + */ + +/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask + * @{ + */ +#define PVD_MODE_IT ((uint32_t)0x00010000) +#define PVD_MODE_EVT ((uint32_t)0x00020000) +#define PVD_RISING_EDGE ((uint32_t)0x00000001) +#define PVD_FALLING_EDGE ((uint32_t)0x00000002) +/** + * @} + */ -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ + -/** @defgroup PWR_Private_Functions +/** @addtogroup PWR_Exported_Functions * @{ */ -/** @defgroup PWR_Group1 Initialization and De-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup PWR_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions * @verbatim =============================================================================== ##### Initialization and de-initialization functions ##### =============================================================================== - [..] - After reset, the backup domain (RTC registers, RTC backup data - registers) is protected against possible unwanted - write accesses. - To enable access to the RTC Domain and RTC registers, proceed as follows: - (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() macro. - (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. @endverbatim * @{ @@ -89,49 +91,20 @@ /** * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. - * @param None * @retval None */ void HAL_PWR_DeInit(void) { - __PWR_FORCE_RESET(); - __PWR_RELEASE_RESET(); -} - -/** - * @brief Enables access to the backup domain (RTC registers, RTC - * backup data registers ). - * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param None - * @retval None - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - /* Enable access to RTC and backup registers */ - PWR->CR |= PWR_CR_DBP; -} - -/** - * @brief Disables access to the backup domain (RTC registers, RTC - * backup data registers). - * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the - * Backup Domain Access should be kept enabled. - * @param None - * @retval None - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - /* Disable access to RTC and backup registers */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP); + __HAL_RCC_PWR_FORCE_RESET(); + __HAL_RCC_PWR_RELEASE_RESET(); } /** * @} */ -/** @defgroup PWR_Group2 Peripheral Control functions - * @brief Low Power modes configuration functions +/** @addtogroup PWR_Exported_Functions_Group2 + * @brief Low Power modes configuration functions * @verbatim @@ -139,6 +112,17 @@ void HAL_PWR_DisableBkUpAccess(void) ##### Peripheral Control functions ##### =============================================================================== + *** Backup domain *** + ========================= + [..] + After reset, the backup domain (RTC registers, RTC backup data + registers) is protected against possible unwanted + write accesses. + To enable access to the RTC Domain and RTC registers, proceed as follows: + (+) Enable the Power Controller (PWR) APB1 interface clock using the + __HAL_RCC_PWR_CLK_ENABLE() macro. + (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. + *** PVD configuration *** ========================= [..] @@ -151,7 +135,7 @@ void HAL_PWR_DisableBkUpAccess(void) (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled. This is done through - __HAL_PVD_EXTI_ENABLE_IT() macro. + __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. (+) The PVD is stopped in Standby mode. *** WakeUp pin configuration *** @@ -162,6 +146,8 @@ void HAL_PWR_DisableBkUpAccess(void) (+) There are two WakeUp pins: WakeUp Pin 1 on PA.00. WakeUp Pin 2 on PC.13. + WakeUp Pin 3 on PE.06 . + [..] *** Main and Backup Regulators configuration *** @@ -170,12 +156,12 @@ void HAL_PWR_DisableBkUpAccess(void) (+) The main internal regulator can be configured to have a tradeoff between performance and power consumption when the device does not operate at the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG() - macro which configure VOS bit in PWR_CR register: - (++) When this bit is set (Regulator voltage output Scale 1 mode selected) + macro which configures the two VOS bits in PWR_CR register: + (++) PWR_REGULATOR_VOLTAGE_SCALE1 (VOS bits = 01), the regulator voltage output Scale 1 mode selected and the System frequency can go up to 32 MHz. - (++) When this bit is reset (Regulator voltage output Scale 2 mode selected) + (++) PWR_REGULATOR_VOLTAGE_SCALE2 (VOS bits = 10), the regulator voltage output Scale 2 mode selected and the System frequency can go up to 16 MHz. - (++) When this bit is reset (Regulator voltage output Scale 3 mode selected) + (++) PWR_REGULATOR_VOLTAGE_SCALE3 (VOS bits = 11), the regulator voltage output Scale 3 mode selected and the System frequency can go up to 4.2 MHz. Refer to the datasheets for more details. @@ -202,7 +188,7 @@ void HAL_PWR_DisableBkUpAccess(void) (+) Entry: (++) VCORE in range2 - (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1. + (++) Decrease the system frequency not to exceed the frequency of MSI frequency range1. (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode() function. (+) Exit: @@ -221,7 +207,8 @@ void HAL_PWR_DisableBkUpAccess(void) (+) Exit: (++) Any peripheral interrupt acknowledged by the nested vectored interrupt - controller (NVIC) can wake up the device from Sleep mode. + controller (NVIC) can wake up the device from Sleep mode. If the WFE instruction was used to enter sleep mode, + the MCU exits Sleep mode as soon as an event occurs. *** Low power sleep mode *** ============================ @@ -256,7 +243,7 @@ void HAL_PWR_DisableBkUpAccess(void) In Stop mode, all I/O pins keep the same state as in Run mode. (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI ) + The Stop mode is entered using the HAL_PWR_EnterSTOPMode function with: (++) Main regulator ON. (++) Low Power regulator ON. @@ -341,84 +328,102 @@ void HAL_PWR_DisableBkUpAccess(void) to be sensitive to to the selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using the EXTI_Init() function. (+++) Configure the comparator to generate the event. - @endverbatim * @{ */ /** - * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). - * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration - * information for the PVD. - * @note Refer to the electrical characteristics of your device datasheet for + * @brief Enables access to the backup domain (RTC registers, RTC + * backup data registers ). + * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + /* Enable access to RTC and backup registers */ + SET_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Disables access to the backup domain + * @note Applies to RTC registers, RTC backup data registers. + * @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the + * Backup Domain Access should be kept enabled. + * @retval None + */ +void HAL_PWR_DisableBkUpAccess(void) +{ + /* Disable access to RTC and backup registers */ + CLEAR_BIT(PWR->CR, PWR_CR_DBP); +} + +/** + * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). + * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration + * information for the PVD. + * @note Refer to the electrical characteristics of your device datasheet for * more details about the voltage threshold corresponding to each * detection level. * @retval None */ -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD) +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) { - uint32_t tmpreg = 0; - /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); - - tmpreg = PWR->CR; - - /* Clear PLS[7:5] bits */ - tmpreg &= ~ (uint32_t)PWR_CR_PLS; + assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); /* Set PLS[7:5] bits according to PVDLevel value */ - tmpreg |= sConfigPVD->PVDLevel; - - /* Store the new value */ - PWR->CR = tmpreg; - - /* Configure the EXTI 16 interrupt */ - if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\ - (sConfigPVD->Mode == PWR_MODE_IT_FALLING) ||\ - (sConfigPVD->Mode == PWR_MODE_IT_RISING)) + MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); + + /* Clear any previous config. Keep it clear if no event or IT mode is selected */ + __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); + __HAL_PWR_PVD_EXTI_DISABLE_IT(); + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); + __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); + + /* Configure interrupt mode */ + if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) { - __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD); + __HAL_PWR_PVD_EXTI_ENABLE_IT(); } - /* Clear the edge trigger for the EXTI Line 16 (PVD) */ - EXTI->RTSR &= ~EXTI_RTSR_TR16; - EXTI->FTSR &= ~EXTI_FTSR_TR16; - - /* Configure the rising edge */ - if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\ - (sConfigPVD->Mode == PWR_MODE_IT_RISING)) + /* Configure event mode */ + if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) { - EXTI->RTSR |= PWR_EXTI_LINE_PVD; + __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); } - /* Configure the falling edge */ - if((sConfigPVD->Mode == PWR_MODE_IT_RISING_FALLING) ||\ - (sConfigPVD->Mode == PWR_MODE_IT_FALLING)) + + /* Configure the edge */ + if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) { - EXTI->FTSR |= PWR_EXTI_LINE_PVD; + __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); + } + + if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) + { + __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } } /** * @brief Enables the Power Voltage Detector(PVD). - * @param None * @retval None */ void HAL_PWR_EnablePVD(void) { /* Enable the power voltage detector */ - PWR->CR |= PWR_CR_PVDE; + SET_BIT(PWR->CR, PWR_CR_PVDE); } /** * @brief Disables the Power Voltage Detector(PVD). - * @param None * @retval None */ void HAL_PWR_DisablePVD(void) { /* Disable the power voltage detector */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE); + CLEAR_BIT(PWR->CR, PWR_CR_PVDE); } /** @@ -427,6 +432,7 @@ void HAL_PWR_DisablePVD(void) * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only. * @retval None */ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) @@ -434,7 +440,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) /* Check the parameter */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Enable the EWUPx pin */ - PWR->CSR |= WakeUpPinx; + SET_BIT(PWR->CSR, WakeUpPinx); } /** @@ -443,6 +449,7 @@ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN1 * @arg PWR_WAKEUP_PIN2 + * @arg PWR_WAKEUP_PIN3 for stm32l07xxx and stm32l08xxx devices only. * @retval None */ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) @@ -450,7 +457,7 @@ void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) /* Check the parameter */ assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); /* Disable the EWUPx pin */ - PWR->CSR &= ~WakeUpPinx; + CLEAR_BIT(PWR->CSR, WakeUpPinx); } /** @@ -475,19 +482,20 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) assert_param(IS_PWR_REGULATOR(Regulator)); assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); - /* Select the regulator state in Sleep mode ---------------------------------*/ + /* Select the regulator state in Sleep mode ---------------------------------*/ tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ - tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPSDSR); + CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR)); /* Set LPSDSR bit according to PWR_Regulator value */ - tmpreg |= Regulator; + SET_BIT(tmpreg, Regulator); /* Store the new value */ PWR->CR = tmpreg; /* Clear SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); /* Select SLEEP mode entry -------------------------------------------------*/ if(SLEEPEntry == PWR_SLEEPENTRY_WFI) @@ -534,17 +542,18 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) /* Select the regulator state in Stop mode ---------------------------------*/ tmpreg = PWR->CR; + /* Clear PDDS and LPDS bits */ - tmpreg &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPSDSR); + CLEAR_BIT(tmpreg, (PWR_CR_PDDS | PWR_CR_LPSDSR)); /* Set LPSDSR bit according to PWR_Regulator value */ - tmpreg |= Regulator; + SET_BIT(tmpreg, Regulator); /* Store the new value */ PWR->CR = tmpreg; /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); /* Select Stop mode entry --------------------------------------------------*/ if(STOPEntry == PWR_STOPENTRY_WFI) @@ -561,7 +570,8 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) } /* Reset SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); + CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); + } /** @@ -571,18 +581,19 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC * Alarm out, or RTC clock calibration out. * - RTC_AF2 pin (PC13) if configured for tamper. - * - WKUP pin 1 (PA0) if enabled. + * - WKUP pin 1 (PA00) if enabled. * - WKUP pin 2 (PC13) if enabled. - * @param None + * - WKUP pin 3 (PE06) if enabled, for stm32l07xxx and stm32l08xxx devices only. + * - WKUP pin 3 (PA02) if enabled, for stm32l031xx devices only. * @retval None */ void HAL_PWR_EnterSTANDBYMode(void) { /* Select Standby mode */ - PWR->CR |= PWR_CR_PDDS; + SET_BIT(PWR->CR, PWR_CR_PDDS); /* Set SLEEPDEEP bit of Cortex System Control Register */ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk); /* This option is used to ensure that store operations are completed */ #if defined ( __CC_ARM) @@ -592,28 +603,79 @@ void HAL_PWR_EnterSTANDBYMode(void) __WFI(); } +/** + * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. + * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * Setting this bit is useful when the processor is expected to run only on + * interruptions handling. + * @retval None + */ +void HAL_PWR_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. + * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor + * re-enters SLEEP mode when an interruption handling is over. + * @retval None + */ +void HAL_PWR_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + + +/** + * @brief Enables CORTEX M0+ SEVONPEND bit. + * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_EnableSEVOnPend(void) +{ + /* Set SEVONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + + +/** + * @brief Disables CORTEX M0+ SEVONPEND bit. + * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes + * WFE to wake up when an interrupt moves from inactive to pended. + * @retval None + */ +void HAL_PWR_DisableSEVOnPend(void) +{ + /* Clear SEVONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + /** * @brief This function handles the PWR PVD interrupt request. * @note This API should be called under the PVD_IRQHandler(). - * @param None * @retval None */ void HAL_PWR_PVD_IRQHandler(void) { /* Check PWR exti flag */ - if(__HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) != RESET) + if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) { /* PWR PVD interrupt user callback */ HAL_PWR_PVDCallback(); /* Clear PWR Exti pending bit */ - __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD); + __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); } } /** * @brief PWR PVD interrupt callback - * @param None * @retval None */ __weak void HAL_PWR_PVDCallback(void) @@ -641,3 +703,4 @@ __weak void HAL_PWR_PVDCallback(void) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h index aae3f9ea4fb..910513bb557 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_pwr.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,11 +50,14 @@ * @{ */ -/** @addtogroup PWR +/** @defgroup PWR * @{ */ -/* Exported types ------------------------------------------------------------*/ +/** @defgroup PWR_Exported_Types PWR Exported Types + * @{ + */ + /** * @brief PWR PVD configuration structure definition */ @@ -63,100 +66,106 @@ typedef struct uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This parameter can be a value of @ref PWR_PVD_detection_level */ - uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode */ + uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. + This parameter can be a value of @ref PWR_PVD_Mode */ }PWR_PVDTypeDef; -/* Exported constants --------------------------------------------------------*/ +/** + * @} + */ -/** @defgroup PWR_Exported_Constants +/** @defgroup PWR_Private_Defines PWR Private Defines * @{ + */ + +#define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ + +/** + * @} */ -/** @defgroup PWR_WakeUp_Pins +/** @defgroup PWR_Exported_Constants PWR Exported Constants * @{ */ -#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 -#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 -#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ - ((PIN) == PWR_WAKEUP_PIN2)) +/** @defgroup PWR_register_alias_address PWR Register alias address + * @{ + */ +#define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 +#define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 +#endif /** * @} */ -/** @defgroup PWR_PVD_detection_level +/** @defgroup PWR_PVD_detection_level PVD detection level * @{ */ -#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 -#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 -#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 -#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 -#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 -#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 -#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 -#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage - (Compare internally to VREFINT) */ -#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) +#define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 +#define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 +#define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 +#define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 +#define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 +#define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 +#define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 +#define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage + (Compare internally to VREFINT) */ /** * @} */ -/** @defgroup PWR_PVD_Mode +/** @defgroup PWR_PVD_Mode PWR PVD Mode * @{ */ -#define PWR_MODE_EVT ((uint32_t)0x00000000) /*!< No Interrupt */ -#define PWR_MODE_IT_RISING ((uint32_t)0x00000001) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_MODE_IT_FALLING ((uint32_t)0x00000002) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_MODE_IT_RISING_FALLING ((uint32_t)0x00000003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_MODE_EVT) || ((MODE) == PWR_MODE_IT_RISING)|| \ - ((MODE) == PWR_MODE_IT_FALLING) || ((MODE) == PWR_MODE_IT_RISING_FALLING)) +#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ +#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ +#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ +#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ + /** * @} */ -/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode +/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode * @{ */ -#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) -#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR +#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) +#define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR -#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ - ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) /** * @} */ -/** @defgroup PWR_SLEEP_mode_entry +/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry * @{ */ -#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) -#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) +#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) +#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) /** * @} */ -/** @defgroup PWR_STOP_mode_entry +/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry * @{ */ -#define PWR_STOPENTRY_WFI ((uint8_t)0x01) -#define PWR_STOPENTRY_WFE ((uint8_t)0x02) -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) ) +#define PWR_STOPENTRY_WFI ((uint8_t)0x01) +#define PWR_STOPENTRY_WFE ((uint8_t)0x02) /** * @} */ -/** @defgroup PWR_Regulator_Voltage_Scale +/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale * @{ */ -#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 -#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS +#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 +#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 +#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ @@ -165,16 +174,19 @@ typedef struct * @} */ -/** @defgroup PWR_Flag +/** @defgroup PWR_Flag PWR Flag * @{ */ -#define PWR_FLAG_WU PWR_CSR_WUF -#define PWR_FLAG_SB PWR_CSR_SBF -#define PWR_FLAG_PVDO PWR_CSR_PVDO -#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF -#define PWR_FLAG_VOS PWR_CSR_VOSF -#define PWR_FLAG_REGLP PWR_CSR_REGLPF +#define PWR_FLAG_WU PWR_CSR_WUF +#define PWR_FLAG_SB PWR_CSR_SBF +#define PWR_FLAG_PVDO PWR_CSR_PVDO +#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF +#define PWR_FLAG_VOS PWR_CSR_VOSF +#define PWR_FLAG_REGLP PWR_CSR_REGLPF +#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ + ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \ + ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP)) /** * @} */ @@ -183,11 +195,9 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWR_Exported_Macro +/** @defgroup PWR_Exported_Macro PWR Exported Macro * @{ */ - /** @brief macros configure the main internal regulator output voltage. * @param __REGULATOR__: specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does @@ -214,7 +224,7 @@ typedef struct * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was * resumed from StandBy mode. * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled - * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode + * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. * For this reason, this bit is equal to 0 after Standby or reset * until the PVDE bit is set. * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. @@ -229,7 +239,7 @@ typedef struct * This bit is reset by hardware when the regulator is ready. * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) +#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. * @param __FLAG__: specifies the flag to clear. @@ -237,53 +247,133 @@ typedef struct * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2) +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2) -#define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */ /** - * @brief Enable the PVD Exti Line. - * @param __EXTILINE__: specifies the PVD Exti sources to be enabled. - * This parameter can be: - * @arg PWR_EXTI_LINE_PVD + * @brief Enable interrupt on PVD Exti Line 16. * @retval None. */ -#define __HAL_PVD_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) +#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) /** - * @brief Disable the PVD EXTI Line. - * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled. - * This parameter can be: - * @arg PWR_EXTI_LINE_PVD + * @brief Disable interrupt on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Enable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + +/** + * @brief Disable event on PVD Exti Line 16. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief Disable the PVD Extended Interrupt Falling Trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) + + +/** + * @brief PVD EXTI line configuration: set rising edge trigger. * @retval None. */ -#define __HAL_PVD_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) /** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTILINE__: specifies the PVD EXTI sources to be disabled. + * @brief Disable the PVD Extended Interrupt Rising Trigger. * This parameter can be: - * @arg PWR_EXTI_LINE_PVD - * @retval None + * @retval None. */ -#define __HAL_PVD_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) /** - * @brief checks whether the specified PVD Exti interrupt flag is set or not. - * @param __EXTILINE__: specifies the PVD Exti sources to be cleared. + * @brief PVD EXTI line configuration: set rising & falling edge trigger. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. * This parameter can be: - * @arg PWR_EXTI_LINE_PVD + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()(); + + + +/** + * @brief Check whether the specified PVD EXTI interrupt flag is set or not. * @retval EXTI PVD Line Status. */ -#define __HAL_PVD_EXTI_GET_FLAG(__EXTILINE__) (EXTI->PR & (__EXTILINE__)) +#define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) /** - * @brief Clear the PVD Exti flag. - * @param __EXTILINE__: specifies the PVD Exti sources to be cleared. - * This parameter can be: - * @arg PWR_EXTI_LINE_PVD + * @brief Clear the PVD EXTI flag. * @retval None. */ -#define __HAL_PVD_EXTI_CLEAR_FLAG(__EXTILINE__) (EXTI->PR = (__EXTILINE__)) +#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) +/** + * @} + */ + +/** + * @brief Generate a Software interrupt on selected EXTI line. + * @retval None. + */ +#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) + +/** + * @} + */ + +/** @defgroup PWR_Private_Macros PWR Private Macros + * @{ + */ +#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ + ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ + ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ + ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) + +#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ + ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ + ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ + ((MODE) == PWR_PVD_MODE_NORMAL)) + +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2) || \ + ((PIN) == PWR_WAKEUP_PIN3)) +#else +#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ + ((PIN) == PWR_WAKEUP_PIN2)) +#endif + +#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ + ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) +#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) + +#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) /** * @} @@ -292,17 +382,30 @@ typedef struct /* Include PWR HAL Extension module */ #include "stm32l0xx_hal_pwr_ex.h" -/* Exported functions --------------------------------------------------------*/ - -/* Initialization and de-initialization functions *******************************/ +/** @defgroup PWR_Exported_Functions PWR Exported Functions + * @{ + */ + +/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ void HAL_PWR_DeInit(void); void HAL_PWR_EnableBkUpAccess(void); void HAL_PWR_DisableBkUpAccess(void); +/** + * @} + */ -/* Peripheral Control functions ************************************************/ -void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD); +/** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions + * @{ + */ + +/* PVD control functions ************************************************/ +void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); +void HAL_PWR_PVD_IRQHandler(void); +void HAL_PWR_PVDCallback(void); /* WakeUp pins configuration functions ****************************************/ void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); @@ -313,8 +416,18 @@ void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); void HAL_PWR_EnterSTANDBYMode(void); -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); +void HAL_PWR_EnableSleepOnExit(void); +void HAL_PWR_DisableSleepOnExit(void); +void HAL_PWR_EnableSEVOnPend(void); +void HAL_PWR_DisableSEVOnPend(void); + +/** + * @} + */ + +/** + * @} + */ /** * @} @@ -332,3 +445,4 @@ void HAL_PWR_PVDCallback(void); #endif /* __STM32L0xx_HAL_PWR_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.c index dc873832115..958bb01067c 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Power Controller (PWR) peripheral: @@ -13,7 +13,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,30 +43,26 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal.h" +#ifdef HAL_PWR_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @defgroup PWREx - * @brief PWR HAL module driver +/** @addtogroup PWREx * @{ */ -#ifdef HAL_PWR_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup PWREx_Private_Functions +/** @defgroup PWR_Extended_TimeOut_Value PWR Extended Flag Setting Time Out Value * @{ + */ +#define PWR_FLAG_SETTING_DELAY_US 50 +/** + * @} */ -/** @defgroup PWREx_Group1 Peripheral Extended features functions - * @brief Low Power modes configuration functions + +/** @addtogroup PWREx_Exported_Functions + * @brief Low Power modes configuration functions * @verbatim @@ -82,76 +78,93 @@ * @note This bit works in conjunction with ULP bit. * Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when * exiting from low power mode. - * @param None * @retval None */ void HAL_PWREx_EnableFastWakeUp(void) { /* Enable the fast wake up */ - PWR->CR |= PWR_CR_FWU; + SET_BIT(PWR->CR, PWR_CR_FWU); } /** * @brief Disables the Fast WakeUp from Ultra Low Power mode. - * @param None * @retval None */ void HAL_PWREx_DisableFastWakeUp(void) { /* Disable the fast wake up */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_FWU); + CLEAR_BIT(PWR->CR, PWR_CR_FWU); } /** * @brief Enables the Ultra Low Power mode - * @param None * @retval None */ void HAL_PWREx_EnableUltraLowPower(void) { /* Enable the Ultra Low Power mode */ - PWR->CR |= PWR_CR_ULP; + SET_BIT(PWR->CR, PWR_CR_ULP); } /** * @brief Disables the Ultra Low Power mode - * @param None * @retval None */ void HAL_PWREx_DisableUltraLowPower(void) { /* Disable the Ultra Low Power mode */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_ULP); + CLEAR_BIT(PWR->CR, PWR_CR_ULP); } /** - * @brief Enters the Low Power Run mode. + * @brief Enable the Low Power Run mode. * @note Low power run mode can only be entered when VCORE is in range 2. * In addition, the dynamic voltage scaling must not be used when Low * power run mode is selected. Only Stop and Sleep modes with regulator * configured in Low power mode is allowed when Low power run mode is * selected. + * @note The frequency of the system clock must be decreased to not exceed the + * frequency of RCC_MSIRANGE_1. * @note In Low power run mode, all I/O pins keep the same state as in Run mode. - * @param None * @retval None */ void HAL_PWREx_EnableLowPowerRunMode(void) { /* Enters the Low Power Run mode */ - PWR->CR |= PWR_CR_LPSDSR; - PWR->CR |= PWR_CR_LPRUN; + SET_BIT(PWR->CR, PWR_CR_LPSDSR); + SET_BIT(PWR->CR, PWR_CR_LPRUN); } /** - * @brief Exits the Low Power Run mode. - * @param None - * @retval None + * @brief Disable the Low Power Run mode. + * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that + * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode + * returns HAL_TIMEOUT status). The system clock frequency can then be + * increased above 2 MHz. + * @retval HAL_StatusTypeDef */ -void HAL_PWREx_DisableLowPowerRunMode(void) +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) { - /* Exits the Low Power Run mode */ - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN); - PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR); + uint32_t wait_loop_index = 0; + + /* Exit the Low Power Run mode */ + CLEAR_BIT(PWR->CR, PWR_CR_LPRUN); + CLEAR_BIT(PWR->CR, PWR_CR_LPSDSR); + + /* Wait until REGLPF is reset */ + wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); + + while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF))) + { + wait_loop_index--; + } + + if (HAL_IS_BIT_SET(PWR->CSR, PWR_CSR_REGLPF)) + { + return HAL_TIMEOUT; + } + + return HAL_OK; } /** @@ -162,13 +175,10 @@ void HAL_PWREx_DisableLowPowerRunMode(void) * @} */ -#endif /* HAL_PWR_MODULE_ENABLED */ -/** - * @} - */ - /** * @} */ +#endif /* HAL_PWR_MODULE_ENABLED */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.h index 092e89ecbcf..c60758d672a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_pwr_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,39 +50,43 @@ * @{ */ -/** @addtogroup PWREx +/** @defgroup PWREx PWR extented module * @{ */ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup PWREx_Exported macro +/** @defgroup PWREx_Exported_Macros PWRex exported macros * @{ */ -/** @brief Macros to enable or disable the Deep-sleep mode with Flash memory kept off. +/** @brief Macros to enable the Deep-sleep mode with Flash memory kept off. + * @note When entering low power mode (stop or standby only), if DS_EE_KOFF and RUN_PD of + * FLASH_ACR register are both set , the Flash memory will not be woken up + * when exiting from deep-sleep mode. + */ +#define __HAL_PWR_FLASHWAKEUP_ENABLE() CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF) + +/** @brief Macros to disable the Deep-sleep mode with Flash memory kept off. * @note When entering low power mode (stop or standby only), if DS_EE_KOFF and RUN_PD of * FLASH_ACR register are both set , the Flash memory will not be woken up * when exiting from deep-sleep mode. */ -#define __HAL_PWR_FLASHWAKEUP_ENABLE() CLEAR_BIT(PWR->CR, PWR_CR_DSEEKOFF) -#define __HAL_PWR_FLASHWAKEUP_DISABLE() SET_BIT(PWR->CR, PWR_CR_DSEEKOFF) +#define __HAL_PWR_FLASHWAKEUP_DISABLE() SET_BIT(PWR->CR, PWR_CR_DSEEKOFF) /** * @} */ -/* Exported functions --------------------------------------------------------*/ - -/* Peripheral Control methods ************************************************/ +/** @defgroup PWREx_Exported_Functions PWRex exported functions + * @{ + */ void HAL_PWREx_EnableFastWakeUp(void); void HAL_PWREx_DisableFastWakeUp(void); void HAL_PWREx_EnableUltraLowPower(void); void HAL_PWREx_DisableUltraLowPower(void); void HAL_PWREx_EnableLowPowerRunMode(void); -void HAL_PWREx_DisableLowPowerRunMode(void); - +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void); +/** + * @} + */ /** * @} @@ -96,7 +100,7 @@ void HAL_PWREx_DisableLowPowerRunMode(void); } #endif - #endif /* __STM32L0xx_HAL_PWR_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c index 17a1efc2249..01a586c3f76 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rcc.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief RCC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Reset and Clock Control (RCC) peripheral: @@ -30,11 +30,31 @@ (+) Enable the clock for the peripheral(s) to be used (+) Configure the clock source(s) for peripherals whose clocks are not derived from the System clock (ADC, RTC/LCD, RNG and IWDG) + + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registeres. + (+) This delay depends on the peripheral mapping. + (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle + after the clock enable bit is set on the hardware register + (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle + after the clock enable bit is set on the hardware register + + [..] + Possible Workarounds: + (#) Enable the peripheral clock sometimes before the peripheral read/write + register is required. + (#) For AHB peripheral, insert two dummy read to the peripheral register. + (#) For APB peripheral, insert a dummy read to the peripheral register. + @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -68,42 +88,48 @@ * @{ */ -/** @defgroup RCC +/** @addtogroup RCC * @brief RCC HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ -#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ +/** @defgroup RCC_Private_Constants RCC Private constants + * @{ + */ +#define RCC_HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT +#define RCC_HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define RCC_LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define RCC_PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define RCC_HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define RCC_MSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define RCC_CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */ -/* Private macro -------------------------------------------------------------*/ -#define __MCO1_CLK_ENABLE() __GPIOA_CLK_ENABLE() +#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() #define MCO1_GPIO_PORT GPIOA #define MCO1_PIN GPIO_PIN_8 #define MCO2_PIN GPIO_PIN_9 -/* Private variables ---------------------------------------------------------*/ +/** + * @} + */ + +/** @defgroup RCC_Private_Vatiables RCC Private Data + * @{ + */ static __IO const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; static __IO const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint32_t MSIRangeTable[7] = {64000, 128000, 256000, 512000, 1000000, 2000000, 4000000}; -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ -/** @defgroup RCC_Private_Functions +/** @addtogroup RCC_Exported_Functions * @{ */ -/** @defgroup RCC_Group1 Initialization and de-initialization functions +/** @addtogroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -183,28 +209,15 @@ const uint32_t MSIRangeTable[7] = {64000, 128000, 256000, 512000, 1000000, 20000 * - AHB, APB1 and APB2 prescaler set to 1. * - CSS and MCO OFF * - All interrupts disabled - * @note This function doesn't modify the configuration of the + * @note This function does not modify the configuration of the * @note -Peripheral clocks * @note -HSI48, LSI, LSE and RTC clocks * @param None * @retval None */ -void HAL_RCC_DeInit(void) +__weak void HAL_RCC_DeInit(void) { - /* Set MSION bit */ - SET_BIT(RCC->CR, RCC_CR_MSION); - - /* Reset HSION, HSEON, CSSON, PLLON */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_CSSHSEON | RCC_CR_PLLON); - - /* Reset CFGR register */ - CLEAR_REG(RCC->CFGR); - - /* Reset HSEBYP bit */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIER); + /* This function is now defined in the file stm32L0xx_rcc_ex.c */ } /** @@ -228,9 +241,9 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases HSE will not disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSE))) + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSE))) { - if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON)) + if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) { return HAL_ERROR; } @@ -246,7 +259,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -256,7 +269,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); /* Check the HSE State */ - if((RCC_OscInitStruct->HSEState) == RCC_HSE_ON) + if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF) { /* Get timeout */ tickstart = HAL_GetTick(); @@ -264,7 +277,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till HSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET) { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -275,10 +288,10 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Get timeout */ tickstart = HAL_GetTick(); - /* Wait till HSE is bypassed or disabled */ + /* Wait till HSE is disabled */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) { - if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_HSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -294,7 +307,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* When the HSI is used as system clock it will not disabled */ - if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSI))) + if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->CFGR & RCC_CFGR_PLLSRC) == RCC_CFGR_PLLSRC_HSI))) { /* When HSI is used as system clock it will not disabled */ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON)) @@ -322,7 +335,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET) { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -342,7 +355,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till HSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_HSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -389,7 +402,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET) { - if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_MSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -411,7 +424,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till MSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_MSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -437,7 +450,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET) { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -454,7 +467,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till LSI is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_LSI_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -462,7 +475,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } } - +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /*------------------------------ HSI48 Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) { @@ -481,7 +494,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) == RESET) { - if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_HSI48_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -498,13 +511,15 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till HSI48 is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSI48RDY) != RESET) { - if((HAL_GetTick() - tickstart ) > HSI48_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_HSI48_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } } } +#endif /* !(STM32L031xx) && !(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)*/ + /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) { @@ -512,7 +527,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Enable Power Clock*/ - __PWR_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; @@ -522,7 +537,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) while((PWR->CR & PWR_CR_DBP) == RESET) { - if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -537,7 +552,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -546,7 +561,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); /* Check the LSE State */ - if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON) + if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF) { /* Get timeout */ tickstart = HAL_GetTick(); @@ -554,7 +569,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -568,7 +583,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET) { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -581,7 +596,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) { /* Check if the PLL is used as system clock or not */ - if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) { @@ -600,7 +615,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -619,7 +634,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -635,7 +650,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) /* Wait till PLL is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) { - if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_PLL_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -753,9 +768,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -763,9 +778,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -775,7 +790,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -783,9 +798,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } else { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -852,9 +867,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -862,9 +877,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) + while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -874,7 +889,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -882,9 +897,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui } else { - while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) + while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) { - if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -927,7 +942,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @} */ -/** @defgroup RCC_Group2 Peripheral Control functions +/** @addtogroup RCC_Exported_Functions_Group2 Peripheral Control functions * @brief RCC clocks control functions * @verbatim @@ -958,7 +973,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected * @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected * @arg RCC_MCO1SOURCE_LSI: LSI clock selected - * @arg RCC_MCO1SOURCE_LSE: LSE clock selected + * @arg RCC_MCO1SOURCE_LSE: LSE clock selected + * and in STM32L052xx,STM32L053xx,STM32L062xx, STM32L063xx + * STM32L072xx,STM32L073xx,STM32L082xx, STM32L083xx * @arg RCC_MCO1SOURCE_HSI48: HSI48 clock selected * @param RCC_MCODIV: specifies the MCO DIV. * This parameter can be one of the following values: @@ -996,7 +1013,7 @@ void HAL_RCC_MCOConfig( uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_ HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct); /* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */ - MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((RCC_MCOSource << 24 | RCC_MCODiv ))); + MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCO_PRE), ((RCC_MCOSource | RCC_MCODiv ))); } /** @@ -1057,16 +1074,15 @@ uint32_t HAL_RCC_GetSysClockFreq(void) /*MSI frequency range in HZ*/ msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - msirange = MSIRangeTable[msirange]; switch (RCC->CFGR & RCC_CFGR_SWS) { case RCC_CFGR_SWS_MSI: /* MSI used as system clock */ { - sysclockfreq = msirange; + sysclockfreq = (32768 * (1 << (msirange + 1))); break; } - case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock */ { if ((RCC->CR & RCC_CR_HSIDIVF) != 0) { @@ -1078,12 +1094,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void) } break; } - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */ { sysclockfreq = HSE_VALUE; break; } - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */ { /* Get PLL clock source and multiplication factor ----------------------*/ pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; @@ -1096,7 +1112,14 @@ uint32_t HAL_RCC_GetSysClockFreq(void) if (pllsource == RCC_CFGR_PLLSRC_HSI) { /* HSI oscillator clock selected as PLL clock source */ - sysclockfreq =(((HSI_VALUE) * pllmul) / plldiv); + if ((RCC->CR & RCC_CR_HSIDIVF) != 0) + { + sysclockfreq = (HSI_VALUE >> 2) * (pllmul / plldiv); + } + else + { + sysclockfreq =(((HSI_VALUE) * pllmul) / plldiv); + } } else { @@ -1107,7 +1130,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void) } default: /* MSI used as system clock */ { - sysclockfreq = msirange; + sysclockfreq = (32768 * (1 << (msirange + 1))); break; } } @@ -1171,8 +1194,11 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { /* Set all possible values for the Oscillator type parameter ---------------*/ RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | \ - RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; - + RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI; +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) + RCC_OscInitStruct->OscillatorType |= RCC_OSCILLATORTYPE_HSI48; +#endif + /* Get the HSE configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP) { @@ -1199,7 +1225,8 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->CR &RCC_ICSCR_MSITRIM) >> 24); RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR &RCC_ICSCR_MSIRANGE) >> 13); - + +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /* Get the HSI48 configuration -----------------------------------------------*/ if((RCC->CRRCR &RCC_CRRCR_HSI48ON) == RCC_CRRCR_HSI48ON) { @@ -1209,6 +1236,7 @@ void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { RCC_OscInitStruct->HSI48State = RCC_HSI48_OFF; } +#endif /* Get the HSI configuration -----------------------------------------------*/ if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION) @@ -1299,10 +1327,10 @@ void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pF void HAL_RCC_NMI_IRQHandler(void) { /* Check RCC CSSF flag */ - if(__HAL_RCC_GET_IT(RCC_IT_CSS)) + if(__HAL_RCC_GET_IT_SOURCE(RCC_IT_CSS)) { /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CCSCallback(); + HAL_RCC_CSSCallback(); /* Clear RCC CSS pending bit */ __HAL_RCC_CLEAR_IT(RCC_IT_CSS); @@ -1314,10 +1342,10 @@ void HAL_RCC_NMI_IRQHandler(void) * @param none * @retval none */ -__weak void HAL_RCC_CCSCallback(void) +__weak void HAL_RCC_CSSCallback(void) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RCC_CCSCallback could be implemented in the user file + the HAL_RCC_CSSCallback could be implemented in the user file */ } @@ -1339,3 +1367,4 @@ __weak void HAL_RCC_CCSCallback(void) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h index ae7034d322a..319f2e95656 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_rcc.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of RCC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup RCC +/** @defgroup RCC RCC * @{ */ @@ -98,8 +98,10 @@ typedef struct uint32_t LSIState; /*!< The new state of the LSI. This parameter can be a value of @ref RCC_LSI_Config */ +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) uint32_t HSI48State; /*!< The new state of the HSI48. This parameter can be a value of @ref RCC_HSI48_Config */ +#endif uint32_t MSIState; /*!< The new state of the MSI. This parameter can be a value of @ref RCC_MSI_Config */ @@ -136,12 +138,8 @@ typedef struct }RCC_ClkInitTypeDef; -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants - * @{ - */ -/** @defgroup RCC_BitAddress_AliasRegion +/** @defgroup RCC_Private_Constants RCC Private constatnts * @brief RCC registers bit address in the alias region * @{ */ @@ -156,19 +154,23 @@ typedef struct #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74) /* CR register byte 3 (Bits[23:16]) base address */ -#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802) +#define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802) /* CIER register byte 0 (Bits[0:8]) base address */ #define CIER_BYTE0_ADDRESS ((uint32_t)(RCC_BASE + 0x10 + 0x00)) -#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ +#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT +#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */ /** * @} */ -/** @defgroup RCC_Oscillator_Type +/** @defgroup RCC_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_Oscillator_Type RCC Oscillator Type * @{ */ #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000) @@ -177,54 +179,46 @@ typedef struct #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004) #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008) #define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010) +#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) #define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020) - -#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 0x3F) +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x3F) +#else +#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) ((__OSCILLATOR__) <= 0x1F) +#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ /** * @} */ -/** @defgroup RCC_HSE_Config +/** @defgroup RCC_HSE_Config RCC HSE Config * @{ */ #define RCC_HSE_OFF ((uint32_t)0x00000000) #define RCC_HSE_ON RCC_CR_HSEON #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) -#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ - ((HSE) == RCC_HSE_BYPASS)) +#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ + ((__HSE__) == RCC_HSE_BYPASS)) /** * @} */ -/** @defgroup RCC_LSE_Config +/** @defgroup RCC_LSE_Config RCC LSE Config * @{ */ #define RCC_LSE_OFF ((uint32_t)0x00000000) #define RCC_LSE_ON RCC_CSR_LSEON #define RCC_LSE_BYPASS ((uint32_t)(RCC_CSR_LSEBYP | RCC_CSR_LSEON)) -#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ - ((LSE) == RCC_LSE_BYPASS)) +#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ + ((__LSE__) == RCC_LSE_BYPASS)) /** * @} */ -/** @defgroup RCC_HSI_Config - * @{ - */ -#define RCC_HSI_OFF ((uint8_t)0x00) -#define RCC_HSI_ON ((uint8_t)0x01) -#define RCC_HSI_DIV4 ((uint8_t)0x09) -#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON) || \ - ((HSI) == RCC_HSI_DIV4)) -/** - * @} - */ -/** @defgroup RCC_MSI_Clock_Range +/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range * @{ */ @@ -236,78 +230,84 @@ typedef struct #define RCC_MSIRANGE_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */ #define RCC_MSIRANGE_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */ -#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRANGE_0) || \ - ((RANGE) == RCC_MSIRANGE_1) || \ - ((RANGE) == RCC_MSIRANGE_2) || \ - ((RANGE) == RCC_MSIRANGE_3) || \ - ((RANGE) == RCC_MSIRANGE_4) || \ - ((RANGE) == RCC_MSIRANGE_5) || \ - ((RANGE) == RCC_MSIRANGE_6)) +#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ + ((__RANGE__) == RCC_MSIRANGE_1) || \ + ((__RANGE__) == RCC_MSIRANGE_2) || \ + ((__RANGE__) == RCC_MSIRANGE_3) || \ + ((__RANGE__) == RCC_MSIRANGE_4) || \ + ((__RANGE__) == RCC_MSIRANGE_5) || \ + ((__RANGE__) == RCC_MSIRANGE_6)) /** * @} */ -/** @defgroup RCC_LSI_Config +/** @defgroup RCC_LSI_Config RCC LSI Config * @{ */ #define RCC_LSI_OFF ((uint8_t)0x00) #define RCC_LSI_ON ((uint8_t)0x01) -#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON)) +#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0) /* Default MSI calibration trimming value */ + +#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) /** * @} */ -/** @defgroup RCC_MSI_Config +/** @defgroup RCC_MSI_Config RCC MSI Config * @{ */ #define RCC_MSI_OFF ((uint8_t)0x00) #define RCC_MSI_ON ((uint8_t)0x01) -#define IS_RCC_MSI(MSI) (((MSI) == RCC_MSI_OFF) || ((MSI) == RCC_MSI_ON)) +#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */ + +#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) /** * @} */ +#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /** @defgroup RCC_HSI48_Config * @{ */ #define RCC_HSI48_OFF ((uint8_t)0x00) #define RCC_HSI48_ON ((uint8_t)0x01) -#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON)) +#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) /** * @} */ +#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ -/** @defgroup RCC_PLL_Config +/** @defgroup RCC_PLL_Config RCC PLL Config * @{ */ #define RCC_PLL_NONE ((uint8_t)0x00) #define RCC_PLL_OFF ((uint8_t)0x01) #define RCC_PLL_ON ((uint8_t)0x02) -#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON)) +#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) ||((__PLL__) == RCC_PLL_OFF) || ((__PLL__) == RCC_PLL_ON)) /** * @} */ -/** @defgroup RCC_PLL_Clock_Source +/** @defgroup RCC_PLL_Clock_Source PCC PLL Clock Source * @{ */ #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) +#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \ + ((__SOURCE__) == RCC_PLLSOURCE_HSE)) /** * @} */ -/** @defgroup RCC_PLLMultiplication_Factor +/** @defgroup RCC_PLLMultiplication_Factor RCC PLL Multipliers * @{ */ @@ -320,29 +320,29 @@ typedef struct #define RCC_PLLMUL_24 RCC_CFGR_PLLMUL24 #define RCC_PLLMUL_32 RCC_CFGR_PLLMUL32 #define RCC_PLLMUL_48 RCC_CFGR_PLLMUL48 -#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMUL_3) || ((MUL) == RCC_PLLMUL_4) || \ - ((MUL) == RCC_PLLMUL_6) || ((MUL) == RCC_PLLMUL_8) || \ - ((MUL) == RCC_PLLMUL_12) || ((MUL) == RCC_PLLMUL_16) || \ - ((MUL) == RCC_PLLMUL_24) || ((MUL) == RCC_PLLMUL_32) || \ - ((MUL) == RCC_PLLMUL_48)) +#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLLMUL_3) || ((__MUL__) == RCC_PLLMUL_4) || \ + ((__MUL__) == RCC_PLLMUL_6) || ((__MUL__) == RCC_PLLMUL_8) || \ + ((__MUL__) == RCC_PLLMUL_12) || ((__MUL__) == RCC_PLLMUL_16) || \ + ((__MUL__) == RCC_PLLMUL_24) || ((__MUL__) == RCC_PLLMUL_32) || \ + ((__MUL__) == RCC_PLLMUL_48)) /** * @} */ -/** @defgroup RCC_PLLDivider_Factor +/** @defgroup RCC_PLLDivider_Factor RCC PLL Dividers * @{ */ #define RCC_PLLDIV_2 RCC_CFGR_PLLDIV2 #define RCC_PLLDIV_3 RCC_CFGR_PLLDIV3 #define RCC_PLLDIV_4 RCC_CFGR_PLLDIV4 -#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDIV_2) || ((DIV) == RCC_PLLDIV_3) || \ - ((DIV) == RCC_PLLDIV_4)) +#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLLDIV_2) || ((__DIV__) == RCC_PLLDIV_3) || \ + ((__DIV__) == RCC_PLLDIV_4)) /** * @} */ -/** @defgroup RCC_System_Clock_Type +/** @defgroup RCC_System_Clock_Type RCC System Clock Type * @{ */ #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001) @@ -350,12 +350,12 @@ typedef struct #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004) #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008) -#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15)) +#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15)) /** * @} */ -/** @defgroup RCC_System_Clock_Source +/** @defgroup RCC_System_Clock_Source RCC System Clock Source * @{ */ #define RCC_SYSCLKSOURCE_MSI RCC_CFGR_SW_MSI @@ -363,15 +363,26 @@ typedef struct #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL -#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_MSI) || \ - ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK)) +#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ + ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) /** * @} */ -/** @defgroup RCC_AHB_Clock_Source +/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status + * @{ + */ +#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI +#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE +#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL + +/** + * @} + */ + +/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock SOurce * @{ */ #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 @@ -384,16 +395,16 @@ typedef struct #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 -#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \ - ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \ - ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \ - ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \ - ((HCLK) == RCC_SYSCLK_DIV512)) +#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ + ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ + ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ + ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ + ((__HCLK__) == RCC_SYSCLK_DIV512)) /** * @} */ -/** @defgroup RCC_APB1_APB2_Clock_Source +/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 Clock Source * @{ */ #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 @@ -402,55 +413,67 @@ typedef struct #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 -#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \ - ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \ - ((PCLK) == RCC_HCLK_DIV16)) +#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ + ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ + ((__PCLK__) == RCC_HCLK_DIV16)) /** * @} */ -/** @defgroup RCC_RTC_Clock_Source +/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source * @{ */ +#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000) #define RCC_RTCCLKSOURCE_LSE RCC_CSR_RTCSEL_LSE #define RCC_RTCCLKSOURCE_LSI RCC_CSR_RTCSEL_LSI #define RCC_RTCCLKSOURCE_HSE_DIV2 RCC_CSR_RTCSEL_HSE #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0) #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1) #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE) -#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_LSI) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ - ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16)) +#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV2) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV4) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV8) || \ + ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV16)) /** * @} */ -/** @defgroup RCC_MCO_Clock_Source +/** @defgroup RCC_MCO_Clock_Source RCC MCo Clock Source * @{ */ -#define RCC_MCO1SOURCE_NOCLOCK ((uint8_t)0x00) -#define RCC_MCO1SOURCE_SYSCLK ((uint8_t)0x01) -#define RCC_MCO1SOURCE_HSI ((uint8_t)0x02) -#define RCC_MCO1SOURCE_MSI ((uint8_t)0x03) -#define RCC_MCO1SOURCE_HSE ((uint8_t)0x04) -#define RCC_MCO1SOURCE_PLLCLK ((uint8_t)0x05) -#define RCC_MCO1SOURCE_LSI ((uint8_t)0x06) -#define RCC_MCO1SOURCE_LSE ((uint8_t)0x07) -#define RCC_MCO1SOURCE_HSI48 ((uint8_t)0x08) - -#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_NOCLOCK) || ((SOURCE) == RCC_MCO1SOURCE_SYSCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_MSI) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK) || \ - ((SOURCE) == RCC_MCO1SOURCE_LSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \ - ((SOURCE) == RCC_MCO1SOURCE_HSI48)) + +#define RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK +#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK +#define RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI +#define RCC_MCO1SOURCE_MSI RCC_CFGR_MCO_MSI +#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE +#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO_PLL +#define RCC_MCO1SOURCE_LSI RCC_CFGR_MCO_LSI +#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO_LSE +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO_HSI48 +#endif + +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)) +#else +#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || \ + ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || ((__SOURCE__) == RCC_MCO1SOURCE_LSE)) +#endif + /** * @} */ -/** @defgroup RCC_MCOPrescaler +/** @defgroup RCC_MCOPrescaler RCC MCO Prescaler * @{ */ @@ -460,27 +483,27 @@ typedef struct #define RCC_MCODIV_8 RCC_CFGR_MCO_PRE_8 #define RCC_MCODIV_16 RCC_CFGR_MCO_PRE_16 -#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || \ - ((DIV) == RCC_MCODIV_2) || \ - ((DIV) == RCC_MCODIV_4) || \ - ((DIV) == RCC_MCODIV_8) || \ - ((DIV) == RCC_MCODIV_16)) +#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || \ + ((__DIV__) == RCC_MCODIV_2) || \ + ((__DIV__) == RCC_MCODIV_4) || \ + ((__DIV__) == RCC_MCODIV_8) || \ + ((__DIV__) == RCC_MCODIV_16)) /** * @} */ -/** @defgroup RCC_MCO_Index +/** @defgroup RCC_MCO_Index RCC MCO Index * @{ */ #define RCC_MCO1 ((uint32_t)0x00000000) #define RCC_MCO2 ((uint32_t)0x00000001) -#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2)) +#define IS_RCC_MCO(__MCOx__) (((__MCOx__) == RCC_MCO1) || ((__MCOx__) == RCC_MCO2)) /** * @} */ -/** @defgroup RCC_Interrupt +/** @defgroup RCC_Interrupt RCC Interruptions * @{ */ #define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF @@ -489,31 +512,50 @@ typedef struct #define RCC_IT_HSERDY RCC_CIFR_HSERDYF #define RCC_IT_PLLRDY RCC_CIFR_PLLRDYF #define RCC_IT_MSIRDY RCC_CIFR_MSIRDYF -#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF + #define RCC_IT_LSECSS RCC_CIFR_LSECSSF #define RCC_IT_CSS RCC_CIFR_CSSF +#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF -#define IS_RCC_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \ - ((IT) == RCC_IT_HSI48RDY) || ((IT) == RCC_IT_LSECSS)) - -#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \ - ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY) || \ - ((IT) == RCC_IT_LSECSS)) - -#define IS_RCC_CLEAR_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ - ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ - ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \ - ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY) || \ - ((IT) == RCC_IT_LSECSS)) - +#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \ + ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \ + ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \ + ((__IT__) == RCC_IT_HSI48RDY) || ((__IT__) == RCC_IT_LSECSS)) + +#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \ + ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \ + ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \ + ((__IT__) == RCC_IT_CSS) || ((__IT__) == RCC_IT_HSI48RDY) || \ + ((__IT__) == RCC_IT_LSECSS)) + +#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \ + ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \ + ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \ + ((__IT__) == RCC_IT_CSS) || ((__IT__) == RCC_IT_HSI48RDY) || \ + ((__IT__) == RCC_IT_LSECSS)) +#else +#define IS_RCC_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \ + ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \ + ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \ + ((__IT__) == RCC_IT_LSECSS)) + +#define IS_RCC_GET_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \ + ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \ + ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \ + ((__IT__) == RCC_IT_CSS) || ((__IT__) == RCC_IT_LSECSS)) + + +#define IS_RCC_CLEAR_IT(__IT__) (((__IT__) == RCC_IT_LSIRDY) || ((__IT__) == RCC_IT_LSERDY) || \ + ((__IT__) == RCC_IT_HSIRDY) || ((__IT__) == RCC_IT_HSERDY) || \ + ((__IT__) == RCC_IT_PLLRDY) || ((__IT__) == RCC_IT_MSIRDY) || \ + ((__IT__) == RCC_IT_CSS) || ((__IT__) == RCC_IT_LSECSS)) + +#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ /** * @} */ - + /** @defgroup RCC_Flag * Elements values convention: 0XXYYYYYb * - YYYYY : Flag position in the register @@ -534,7 +576,7 @@ typedef struct #define RCC_FLAG_LSERDY ((uint8_t)0x49) #define RCC_FLAG_LSECSS ((uint8_t)0x4E) #define RCC_FLAG_LSIRDY ((uint8_t)0x41) -#define RCC_FLAG_FIREWALLRST ((uint8_t)0x58) +#define RCC_FLAG_FWRST ((uint8_t)0x58) #define RCC_FLAG_OBLRST ((uint8_t)0x59) #define RCC_FLAG_PINRST ((uint8_t)0x5A) #define RCC_FLAG_PORRST ((uint8_t)0x5B) @@ -543,13 +585,14 @@ typedef struct #define RCC_FLAG_WWDGRST ((uint8_t)0x5E) #define RCC_FLAG_LPWRRST ((uint8_t)0x5F) +#if !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /* Flags in the CRRCR register */ #define RCC_FLAG_HSI48RDY ((uint8_t)0x61) +#endif /* !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ +#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F) +#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0xFF) - -#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) -#define IS_RCC_MSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0xFF) /** * @} */ @@ -558,7 +601,7 @@ typedef struct * @} */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_Exported macro +/** @defgroup RCC_Exported_Macros RCC Exported Macros * @{ */ @@ -567,14 +610,34 @@ typedef struct * is disabled and the application software has to enable this clock before * using it. */ -#define __DMA1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA1EN)) -#define __MIF_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_MIFEN)) -#define __CRC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRCEN)) - - -#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN)) -#define __MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN)) -#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN)) +#define __HAL_RCC_DMA1_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_MIF_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_MIFEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_CRC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_DMA1EN)) +#define __HAL_RCC_MIF_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_MIFEN)) +#define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRCEN)) /** @brief Enable or disable the IOPORT peripheral clock. @@ -582,17 +645,52 @@ typedef struct * is disabled and the application software has to enable this clock before * using it. */ -#define __GPIOA_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIOAEN)) -#define __GPIOB_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIOBEN)) -#define __GPIOC_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIOCEN)) -#define __GPIOD_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIODEN)) -#define __GPIOH_CLK_ENABLE() (RCC->IOPENR |= (RCC_IOPENR_GPIOHEN)) - -#define __GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN)) -#define __GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN)) -#define __GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN)) -#define __GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN)) -#define __GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN)) +#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOBEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOCEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIODEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOHEN);\ + UNUSED(tmpreg); \ + } while(0) + + +#define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOAEN)) +#define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOBEN)) +#define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOCEN)) +#define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIODEN)) +#define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOHEN)) /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock. @@ -600,130 +698,130 @@ typedef struct * is disabled and the application software has to enable this clock before * using it. */ -#define __WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) -#define __PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) +#define __HAL_RCC_WWDG_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_PWR_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_PWREN)) -#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN)) -#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN)) +#define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_WWDGEN)) +#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_PWREN)) /** @brief Enable or disable the High Speed APB (APB2) peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ -#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) -#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN)) +#define __HAL_RCC_SYSCFG_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_DBGMCU_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_DBGMCUEN)) -#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN)) -#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN)) +#define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SYSCFGEN)) +#define __HAL_RCC_DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_DBGMCUEN)) /** @brief Force or release AHB peripheral reset. */ -#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) -#define __DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) -#define __MIF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_MIFRST)) -#define __CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) +#define __HAL_RCC_AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF) +#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST)) +#define __HAL_RCC_MIF_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_MIFRST)) +#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST)) -#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) -#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST)) -#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST)) -#define __MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST)) +#define __HAL_RCC_AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00) +#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRCRST)) +#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_DMA1RST)) +#define __HAL_RCC_MIF_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_MIFRST)) /** @brief Force or release IOPORT peripheral reset. */ -#define __IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF) -#define __GPIOA_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOARST)) -#define __GPIOB_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOBRST)) -#define __GPIOC_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOCRST)) -#define __GPIOD_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIODRST)) -#define __GPIOH_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOHRST)) +#define __HAL_RCC_IOP_FORCE_RESET() (RCC->IOPRSTR = 0xFFFFFFFF) +#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIODRST)) +#define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOHRST)) -#define __IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00) -#define __GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST)) -#define __GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST)) -#define __GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST)) -#define __GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST)) -#define __GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST)) +#define __HAL_RCC_IOP_RELEASE_RESET() (RCC->IOPRSTR = 0x00) +#define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOARST)) +#define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOBRST)) +#define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOCRST)) +#define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIODRST)) +#define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOHRST)) /** @brief Force or release APB1 peripheral reset. */ -#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) -#define __WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) -#define __PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF) +#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) -#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) -#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST)) -#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST)) +#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) +#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_WWDGRST)) +#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_PWRRST)) /** @brief Force or release APB2 peripheral reset. */ -#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) -#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) -#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF) +#define __HAL_RCC_DBGMCU_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_DBGMCURST)) +#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST)) -#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) -#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST)) -#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST)) +#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) +#define __HAL_RCC_DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_DBGMCURST)) +#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SYSCFGRST)) /** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. */ -#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_CRCSMEN)) -#define __MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_MIFSMEN)) -#define __SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_SRAMSMEN)) -#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_DMA1SMEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_CRCSMEN)) +#define __HAL_RCC_MIF_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_MIFSMEN)) +#define __HAL_RCC_SRAM_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_SRAMSMEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_DMA1SMEN)) -#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN)) -#define __MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN)) -#define __SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN)) -#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN)) +#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_CRCSMEN)) +#define __HAL_RCC_MIF_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_MIFSMEN)) +#define __HAL_RCC_SRAM_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_SRAMSMEN)) +#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_DMA1SMEN)) /** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. */ -#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOASMEN)) -#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOBSMEN)) -#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOCSMEN)) -#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIODSMEN)) -#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOHSMEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOASMEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOBSMEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOCSMEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIODSMEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOHSMEN)) -#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN)) -#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN)) -#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN)) -#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN)) -#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN)) +#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOASMEN)) +#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOBSMEN)) +#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOCSMEN)) +#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIODSMEN)) +#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOHSMEN)) /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @note By default, all peripheral activated clocks remain enabled during SLEEP mode. */ -#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_WWDGSMEN)) -#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_PWRSMEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_WWDGSMEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_PWRSMEN)) -#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN)) -#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN)) +#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_WWDGSMEN)) +#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_PWRSMEN)) /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode. + * @note By default, all peripheral actiated clocks remain enabled during SLEEP mode. */ -#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SYSCFGSMEN)) -#define __DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_DBGMCUSMEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SYSCFGSMEN)) +#define __HAL_RCC_DBGMCU_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_DBGMCUSMEN)) -#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN)) -#define __DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN)) +#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SYSCFGSMEN)) +#define __HAL_RCC_DBGMCU_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_DBGMCUSMEN)) /** @brief Macro to enable or disable the Internal High Speed oscillator (HSI). * @note After enabling the HSI, the application software should wait on @@ -742,7 +840,7 @@ typedef struct * clock cycles. */ #define __HAL_RCC_HSI_CONFIG(__STATE__) \ - MODIFY_REG(RCC->CR, RCC_CR_HSION|RCC_CR_HSIDIVEN, (uint32_t)(__STATE__)) + MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIVEN , (uint32_t)(__STATE__)) /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. @@ -780,21 +878,6 @@ typedef struct #define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSION) #define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSION) -/** - * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). - * @note After enabling the HSI48, the application software should wait on - * HSI48RDY flag to be set indicating that HSI48 clock is stable and can - * be used to clock the USB. - * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ - RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \ - SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); \ - } while (0) -#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ - SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); \ - } while (0) - /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. * @note The calibration is used to compensate for the variations in voltage * and temperature that influence the frequency of the internal HSI RC. @@ -865,8 +948,24 @@ typedef struct * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock. */ #define __HAL_RCC_HSE_CONFIG(__STATE__) \ - MODIFY_REG(RCC->CR, RCC_CR_HSEON|RCC_CR_HSEBYP, (uint32_t)(__STATE__)) - + do { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ + if((__STATE__) == RCC_HSE_ON) \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else if((__STATE__) == RCC_HSE_BYPASS) \ + { \ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ + SET_BIT(RCC->CR, RCC_CR_HSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ + } \ + } while(0) + /** * @brief Macro to configure the External Low Speed oscillator (LSE). * @note As the LSE is in the Backup domain and write access is denied to @@ -884,7 +983,27 @@ typedef struct * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock. */ #define __HAL_RCC_LSE_CONFIG(__STATE__) \ - MODIFY_REG(RCC->CSR, RCC_CSR_LSEON|RCC_CSR_LSEBYP, (uint32_t)(__STATE__)) + do { \ + if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_OFF) \ + { \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ + SET_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ + SET_BIT(RCC->CSR, RCC_CSR_LSEON); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEON); \ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSEBYP); \ + } \ + } while(0) /** @brief Macros to enable or disable the the RTC clock. * @note These macros must be used only after the RTC clock source was selected. @@ -898,7 +1017,7 @@ typedef struct * access is denied to this domain after reset, you have to enable write * access using PWR_RTCAccessCmd(ENABLE) function before to configure * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it can't be changed unless the RTC + * @note Once the RTC clock is configured it cannot be changed unless the RTC * is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR) * @note The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK). * @@ -1014,8 +1133,9 @@ typedef struct * @arg RCC_IT_PLLRDY: PLL ready interrupt * @arg RCC_IT_MSIRDY: MSI ready interrupt * @arg RCC_IT_LSECSS: LSE CSS interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIER_BYTE0_ADDRESS |= (__INTERRUPT__)) +#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (RCC->CIER |= (__INTERRUPT__)) /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIER[0:7] bits to disable * the selected interrupts). @@ -1033,9 +1153,11 @@ typedef struct * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: PLL ready interrupt * @arg RCC_IT_MSIRDY: MSI ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt * @arg RCC_IT_LSECSS: LSE CSS interrupt + */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIER_BYTE0_ADDRESS &= ~(__INTERRUPT__)) +#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (RCC->CIER &= ~(__INTERRUPT__)) /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] * bits to clear the selected interrupt pending bits. @@ -1046,7 +1168,8 @@ typedef struct * @arg RCC_IT_HSIRDY: HSI ready interrupt * @arg RCC_IT_HSERDY: HSE ready interrupt * @arg RCC_IT_PLLRDY: PLL ready interrupt - * @arg RCC_IT_MSIRDY: MSI ready interrupt + * @arg RCC_IT_MSIRDY: MSI ready interrupt + * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt * @arg RCC_IT_LSECSS: LSE CSS interrupt * @arg RCC_IT_CSS: Clock Security System interrupt */ @@ -1065,7 +1188,7 @@ typedef struct * @arg RCC_IT_CSS: Clock Security System interrupt * @retval The new state of __INTERRUPT__ (TRUE or FALSE). */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_RCC_GET_IT_SOURCE(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Set RMVF bit to clear the reset flags. * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, @@ -1083,6 +1206,7 @@ typedef struct * @arg RCC_FLAG_LSECSS: LSE oscillator clock CSS detected * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready + * @arg RCC_FLAG_FWRST: Firewall reset * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset * @arg RCC_FLAG_PINRST: Pin reset * @arg RCC_FLAG_PORRST: POR/PDR reset @@ -1100,21 +1224,30 @@ typedef struct * @} */ -#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC)) /** - * @} - */ + * @} + */ /* Include RCC HAL Extension module */ #include "stm32l0xx_hal_rcc_ex.h" -/* Exported functions --------------------------------------------------------*/ -/* Initialization and de-initialization methods ******************************/ +/** @defgroup RCC_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ void HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +/** + * @} + */ -/* Peripheral Control methods ************************************************/ +/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); void HAL_RCC_EnableCSS(void); uint32_t HAL_RCC_GetSysClockFreq(void); @@ -1123,13 +1256,19 @@ uint32_t HAL_RCC_GetPCLK1Freq(void); uint32_t HAL_RCC_GetPCLK2Freq(void); void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); - /* CSS NMI IRQ handler */ void HAL_RCC_NMI_IRQHandler(void); /* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CCSCallback(void); - +void HAL_RCC_CSSCallback(void); +/** + * @} + */ + +/** + * @} + */ + /** * @} */ @@ -1142,6 +1281,7 @@ void HAL_RCC_CCSCallback(void); } #endif -#endif /* __STM32L0xx_HAL_RCC_H */ +#endif /* __STM32l0xx_HAL_RCC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c index aa3898d8fd7..a07a5046c72 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rcc_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Extended RCC HAL module driver. * * This file provides firmware functions to manage the following @@ -60,7 +60,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -94,31 +94,31 @@ * @{ */ -/** @defgroup RCCEx +/** @addtogroup RCCEx * @brief RCC Extension HAL module driver * @{ */ #ifdef HAL_RCC_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ +/** @defgroup RCCEx_Private_Constants + * @{ + */ /* Bit position in register */ #define CRS_CFGR_FELIM_BITNUMBER 16 #define CRS_CR_TRIM_BITNUMBER 8 #define CRS_ISR_FECAP_BITNUMBER 16 -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/** + * @} + */ -/** @defgroup RCCEx_Private_Functions +/** @addtogroup RCCEx_Exported_Functions * @{ */ -/** @defgroup RCCEx_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions +/** @addtogroup RCCEx_Exported_Functions_Group1 + * @brief Extended Peripheral Initialization and Control functions * @verbatim =============================================================================== @@ -133,11 +133,53 @@ */ /** - * @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the + * @brief Resets the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - MSI ON and used as system clock source (MSI range is not modified + * - by this function, it keep the value configured by user application) + * - HSI, HSI_OUT, HSE and PLL OFF + * - AHB, APB1 and APB2 prescaler set to 1. + * - CSS and MCO OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * @note -Peripheral clocks + * @note -HSI48, LSI, LSE and RTC clocks + * @param None + * @retval None + */ +void HAL_RCC_DeInit(void) +{ + /* Set MSION bit */ + SET_BIT(RCC->CR, RCC_CR_MSION); + +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) + /* Reset HSE, HSI, CSS, PLL */ + CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | RCC_CR_HSIOUTEN | \ + RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); +#else + CLEAR_BIT(RCC->CR, RCC_CR_HSION| RCC_CR_HSIKERON| RCC_CR_HSIDIVEN | \ + RCC_CR_HSEON | RCC_CR_CSSHSEON | RCC_CR_PLLON); +#endif + + /* Reset HSEBYP bit */ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); + + /* Reset CFGR register */ + CLEAR_REG(RCC->CFGR); + + /* Disable all interrupts */ + CLEAR_REG(RCC->CIER); +} + +/** + * @brief Initializes the RCC extended peripherals clocks + * @note Initializes the RCC extended peripherals clocks according to the specified parameters in the * RCC_PeriphCLKInitTypeDef. * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that * contains the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1, - * I2C1, RTC, USB/RNG and LPTIM1 clocks). + * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks). * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) @@ -148,6 +190,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Check the parameters */ assert_param(IS_RCC_PERIPHCLK(PeriphClkInit->PeriphClockSelection)); +#if !defined (STM32L031xx) && !defined (STM32L041xx) /*------------------------------- USART1 Configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) { @@ -157,6 +200,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); } +#endif /*----------------------------- USART2 Configuration --------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) @@ -187,13 +231,29 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); } + +#if defined (STM32L071xx) || (STM32L072xx) || defined(STM32L073xx) || \ + defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + /*------------------------------ I2C3 Configuration ------------------------*/ + if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); - - /*---------------------------- RTC configuration -------------------------------*/ - if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC)) + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + } +#endif /* defined (STM32L071xx) (STM32L072xx)|| (STM32L073xx)|| (STM32L081xx)|| (STM32L082xx) || (STM32L083xx) */ + + /*---------------------------- RTC/LCD configuration -------------------------------*/ + if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) +#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) + || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) +#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ + ) { /* Enable Power Clock*/ - __PWR_CLK_ENABLE(); + __HAL_RCC_PWR_CLK_ENABLE(); /* Enable write access to Backup domain */ PWR->CR |= PWR_CR_DBP; @@ -203,14 +263,18 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk while((PWR->CR & PWR_CR_DBP) == RESET) { - if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE) { return HAL_TIMEOUT; } } /* Reset the Backup domain only if the RTC Clock source selection is modified */ - if((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) + if(((RCC->CSR & RCC_CSR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) +#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) + || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) +#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ + ) { /* Store the content of CSR register before the reset of Backup Domain */ tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); @@ -222,7 +286,11 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } /* If LSE is selected as RTC clock source, wait for LSE reactivation */ - if(PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) + if((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE) +#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) + || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE) +#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ + ) { /* Get timeout */ tickstart = HAL_GetTick(); @@ -230,7 +298,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk /* Wait till LSE is ready */ while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET) { - if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE) + if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) { return HAL_TIMEOUT; } @@ -238,14 +306,14 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk } __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); } -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /*---------------------------- USB and RNG configuration --------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); } -#endif /* !(STM32L051xx) && !(STM32L061xx) */ +#endif /*---------------------------- LPTIM1 configuration ------------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) @@ -256,46 +324,81 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk return HAL_OK; } + + /** - * @brief Get the RCC_ClkInitStruct according to the internal - * RCC configuration registers. + * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that * returns the configuration information for the Extended Peripherals clocks(USART1,USART2, LPUART1, - * I2C1, RTC, USB/RNG and LPTIM1 clocks). + * I2C1, I2C3, RTC, USB/RNG and LPTIM1 clocks). * @retval None */ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { /* Set all possible values for the extended clock type parameter -----------*/ /* Common part first */ - #if !defined(STM32L051xx) && !defined(STM32L061xx) +#if defined(STM32L031xx) || defined(STM32L041xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ + RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1; +#endif +#if defined(STM32L052xx) || defined(STM32L062xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1; + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_LPTIM1 ; +#endif +#if defined(STM32L053xx) || defined(STM32L063xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD; +#endif +#if defined(STM32L072xx) || defined(STM32L082xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 ; +#endif +#if defined(STM32L073xx) || defined(STM32L083xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD; - #else +#endif +#if defined(STM32L051xx) || defined(STM32L061xx) PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPTIM1; +#endif +#if defined(STM32L071xx) || defined(STM32L081xx) + PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_RTC | \ RCC_PERIPHCLK_LPTIM1; - #endif /* !(STM32L051xx) && !(STM32L061xx) */ - +#endif + +#if !defined (STM32L031xx) && !defined (STM32L041xx) /* Get the USART1 configuration --------------------------------------------*/ PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); +#endif /* Get the USART2 clock source ---------------------------------------------*/ PeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); - /* Get the LPUART1 clock source ---------------------------------------------*/ + /* Get the LPUART1 clock source ---------------------------------------------*/ PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); /* Get the I2C1 clock source -----------------------------------------------*/ PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || \ + defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) +/* Get the I2C3 clock source -----------------------------------------------*/ + PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); +#endif /* defined (STM32L071xx) || (STM32L073xx) || (STM32L082xx) || (STM32L082xx) || (STM32L083xx) */ /* Get the LPTIM1 clock source -----------------------------------------------*/ PeriphClkInit->LptimClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); /* Get the RTC clock source -----------------------------------------------*/ PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); +#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) + PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; +#endif /* defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /* Get the USB/RNG clock source -----------------------------------------------*/ PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); -#endif /* !(STM32L051xx) && !(STM32L061xx) */ +#endif } /** @@ -318,7 +421,7 @@ void HAL_RCCEx_DisableLSECSS(void) CLEAR_BIT(RCC->CSR, RCC_CSR_LSECSSON) ; } -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /** * @brief Start automatic synchronization using polling mode @@ -339,8 +442,8 @@ void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) /* CONFIGURATION */ /* Before configuration, reset CRS registers to their default values*/ - __CRS_FORCE_RESET(); - __CRS_RELEASE_RESET(); + __HAL_RCC_CRS_FORCE_RESET(); + __HAL_RCC_CRS_RELEASE_RESET(); /* Configure Synchronization input */ /* Clear SYNCDIV[2:0], SYNCSRC[1:0] & SYNCSPOL bits */ @@ -402,7 +505,7 @@ void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) { /* Check the parameter */ - assert_param(pSynchroInfo != HAL_NULL); + assert_param(pSynchroInfo != NULL); /* Get the reload value */ pSynchroInfo->ReloadValue = (uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD); @@ -434,9 +537,9 @@ void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo * @arg RCC_CRS_SYNCMISS * @arg RCC_CRS_TRIMOV */ -RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) { - RCC_CRSStatusTypeDef crsstatus = RCC_CRS_NONE; + uint32_t crsstatus = RCC_CRS_NONE; uint32_t tickstart = 0; /* Get timeout */ @@ -509,11 +612,36 @@ RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); } } - + return crsstatus; +} +/** + * @brief Enables Vrefint for the HSI48. + * @param None + * @note This is functional only if the LOCK is not set + * @retval None + */ +void HAL_RCCEx_EnableHSI48_VREFINT(void) +{ + /* Enable the Buffer for the ADC by setting EN_VREFINT bit */ + /* and the SYSCFG_CFGR3_ENREF_HSI48 in the CFGR3 register */ + SET_BIT (SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); +} + +/** + * @brief Disables the Vrefint for the HSI48. + * @param None. + * @note This is functional only if the LOCK is not set + * @retval None + */ +void HAL_RCCEx_DisableHSI48_VREFINT(void) +{ + /* Disable the Vrefint by resetting SYSCFG_CFGR3_ENREF_HSI48 bit */ + /* and the EN_VREFINT bit in the CFGR3 register */ + CLEAR_BIT(SYSCFG->CFGR3, (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); } - -#endif /* !(STM32L051xx) && !(STM32L061xx) */ +#endif /* !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) */ + /** * @} @@ -533,3 +661,4 @@ RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h index 2d3592a79c1..718ddf51a34 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rcc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_rcc_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of RCC HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup RCCEx +/** @defgroup RCCEx * @{ */ @@ -58,7 +58,7 @@ /** * @brief RCC extended clocks structure definition */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. @@ -74,9 +74,17 @@ typedef struct uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ +#if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx) + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ +#endif uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCCEx_RTC_Clock_Source */ + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) + uint32_t LCDClockSelection; /*!< specifies the LCD clock source. + This parameter can be a value of @ref RCC_RTC_Clock_Source */ +#endif uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection This parameter can be a value of @ref RCCEx_USB_Clock_Source */ @@ -85,16 +93,18 @@ typedef struct This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ }RCC_PeriphCLKInitTypeDef; -#endif /* !(STM32L051xx) && !(STM32L061xx) */ -#if defined(STM32L051xx) || defined(STM32L061xx) + +#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */ + typedef struct { uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ +#if !defined (STM32L031xx) && !defined (STM32L041xx) uint32_t Usart1ClockSelection; /*!< USART1 clock source This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - +#endif uint32_t Usart2ClockSelection; /*!< USART2 clock source This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ @@ -104,30 +114,41 @@ typedef struct uint32_t I2c1ClockSelection; /*!< I2C1 clock source This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ +#if defined (STM32L071xx) || defined(STM32L081xx) + uint32_t I2c3ClockSelection; /*!< I2C3 clock source + This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ +#endif + uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection - This parameter can be a value of @ref RCCEx_RTC_Clock_Source */ + This parameter can be a value of @ref RCC_RTC_Clock_Source */ uint32_t LptimClockSelection; /*!< LPTIM1 clock source This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ }RCC_PeriphCLKInitTypeDef; -#endif /* STM32L051xx || STM32L061xx */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#endif /* STM32L0x1xx */ + + +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +/** @defgroup RCCEx_Exported_Constants + * @{ + */ /** - * @brief RCC CRS Status structures definition + * @brief RCC CRS Status definition */ -typedef enum -{ - RCC_CRS_NONE = 0x00, - RCC_CRS_TIMEOUT = 0x01, - RCC_CRS_SYNCOK = 0x02, - RCC_CRS_SYNCWARM = 0x04, - RCC_CRS_SYNCERR = 0x08, - RCC_CRS_SYNCMISS = 0x10, - RCC_CRS_TRIMOV = 0x20 -} RCC_CRSStatusTypeDef; +#define RCC_CRS_NONE ((uint32_t) 0x00000000) +#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001) +#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002) +#define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004) +#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008) +#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010) +#define RCC_CRS_TRIMOV ((uint32_t) 0x00000020) + +/** + * @} + */ /** * @brief RCC_CRS Init structure definition */ @@ -175,17 +196,18 @@ typedef struct This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ }RCC_CRSSynchroInfoTypeDef; -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Constants +/** @addtogroup RCCEx_Exported_Constants * @{ */ /** @defgroup RCCEx_Periph_Clock_Selection * @{ */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) + #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004) @@ -194,31 +216,67 @@ typedef struct #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) #define RCC_PERIPHCLK_USB ((uint32_t)0x00000040) #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080) +#if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) +#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800) +#endif +#if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100) +#endif +#if defined (STM32L052xx) || defined(STM32L062xx) +#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1)) +#elif defined (STM32L053xx) || defined(STM32L063xx) +#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD)) +#elif defined (STM32L072xx) || defined(STM32L082xx) +#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 )) +#elif defined (STM32L073xx) || defined(STM32L083xx) +#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \ + RCC_PERIPHCLK_LCD)) +#endif -#define IS_RCC_PERIPHCLK(CLK) ((CLK) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1)) -#endif /* !(STM32L051xx) && !(STM32L061xx) */ +#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */ -#if defined(STM32L051xx) || defined(STM32L061xx) +#if !defined(STM32L031xx) && !defined(STM32L041xx) #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001) +#endif #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002) #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004) #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008) +#if !defined(STM32L031xx) && !defined(STM32L041xx) #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010) +#endif #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020) #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080) +#if defined(STM32L071xx) || defined(STM32L081xx) +#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100) +#endif +#if defined(STM32L031xx) || defined(STM32L041xx) +#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC )) +#elif defined(STM32L051xx) || defined(STM32L061xx) +#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_LPTIM1)) +#elif defined(STM32L071xx) || defined(STM32L081xx) +#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ + RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ + RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3)) +#endif -#define IS_RCC_PERIPHCLK(CLK) ((CLK) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_LPTIM1)) -#endif /* !(STM32L051xx) && !(STM32L061xx) */ +#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */ /** * @} */ - + /** @defgroup RCCEx_USART1_Clock_Source * @{ */ @@ -226,10 +284,10 @@ typedef struct #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1) -#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART1CLKSOURCE_HSI)) +#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) /** * @} */ @@ -241,10 +299,10 @@ typedef struct #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1) -#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_USART2CLKSOURCE_HSI)) +#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI)) /** * @} */ @@ -256,10 +314,10 @@ typedef struct #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1) -#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ - ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE) || \ - ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI)) +#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ + ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) /** * @} */ @@ -270,9 +328,26 @@ typedef struct #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000) #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1 -#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \ - ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ - ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)) +#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) +/** + * @} + */ + +#if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx)|| defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx) + +/** @defgroup RCCEx_I2C3_Clock_Source + * @{ + */ +#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000) +#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0 +#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1 +#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ + ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) +#endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */ + /** * @} */ @@ -286,15 +361,15 @@ typedef struct * @} */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /** @defgroup RCCEx_USB_Clock_Source * @{ */ #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL #define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000) -#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \ - ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK)) +#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ + ((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK)) /** * @} */ @@ -305,8 +380,8 @@ typedef struct #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL #define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000) -#define IS_RCC_RNGCLKSOURCE(SOURCE) (((SOURCE) == RCC_RNGCLKSOURCE_HSI48) || \ - ((SOURCE) == RCC_RNGCLKSOURCE_PLLCLK)) +#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \ + ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK)) /** * @} */ @@ -314,16 +389,39 @@ typedef struct /** @defgroup RCCEx_HSI48M_Clock_Source * @{ */ +#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF #define RCC_HSI48M_PLL ((uint32_t)0x00000000) -#define RCC_HSI48M_RC48 RCC_CCIPR_HSI48SEL +#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL -#define IS_RCC_HSI48MCLKSOURCE(HSI48MCLK) (((HSI48MCLK) == RCC_HSI48M_PLL) || ((HSI48MCLK) == RCC_HSI48M_RC48)) +#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48)) /** * @} */ -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ + +/** @defgroup RCC_HSI_Config + * @{ + */ +#define RCC_HSI_OFF ((uint8_t)0x00) +#define RCC_HSI_ON RCC_CR_HSION +#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION) +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN + +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \ + ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN )) +#else +#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \ + ((__HSI__) == RCC_HSI_DIV4)) +#endif + +/** + * @} + */ /** @defgroup RCCEx_LPTIM1_Clock_Source * @{ @@ -333,10 +431,10 @@ typedef struct #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL -#define IS_RCC_LPTIMCLK(LPTIMCLK) (((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_PCLK) || \ - ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((LPTIMCLK) == RCC_LPTIM1CLKSOURCE_LSE)) +#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \ + ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \ + ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \ + ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE)) /** * @} */ @@ -345,11 +443,11 @@ typedef struct * @{ */ -#define RCC_StopWakeUpClock_MSI ((uint32_t)0x00) -#define RCC_StopWakeUpClock_HSI RCC_CFGR_STOPWUCK +#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00) +#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK -#define IS_RCC_STOPWAKEUP_CLOCK(SOURCE) (((SOURCE) == RCC_StopWakeUpClock_MSI) || \ - ((SOURCE) == RCC_StopWakeUpClock_HSI)) +#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \ + ((__SOURCE__) == RCC_StopWakeUpClock_HSI)) /** * @} */ @@ -362,13 +460,13 @@ typedef struct #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1 #define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV -#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDRIVE_LOW) || ((DRIVE) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((DRIVE) == RCC_LSEDRIVE_MEDIUMHIGH) || ((DRIVE) == RCC_LSEDRIVE_HIGH)) +#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ + ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH)) /** * @} */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /** @defgroup RCCEx_CRS_SynchroSource * @{ */ @@ -376,9 +474,9 @@ typedef struct #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \ - ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) ||\ - ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB)) +#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\ + ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) /** * @} */ @@ -395,10 +493,10 @@ typedef struct #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) ||\ - ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \ - ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128)) +#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) ||\ + ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ + ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) /** * @} */ @@ -409,8 +507,8 @@ typedef struct #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */ #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \ - ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING)) +#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ + ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) /** * @} */ @@ -421,7 +519,7 @@ typedef struct #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */ -#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF)) +#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF)) /** * @} */ @@ -431,7 +529,7 @@ typedef struct */ #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */ -#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF)) +#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF)) /** * @} */ @@ -443,7 +541,7 @@ typedef struct The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency */ -#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F)) +#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F)) /** * @} */ @@ -454,8 +552,8 @@ typedef struct #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */ #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ -#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \ - ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN)) +#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ + ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) /** * @} */ @@ -490,13 +588,13 @@ typedef struct * @} */ -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ /** * @} */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Macros +/** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros * @{ */ @@ -506,18 +604,41 @@ typedef struct * using it. */ -#if defined(STM32L062xx) || defined(STM32L063xx) -#define __CRYP_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRYPEN)) -#define __CRYP_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN)) -#endif /* STM32L062xx || STM32L063xx */ +#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) +#define __HAL_RCC_AES_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRYPEN)) +#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN)) +#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) -#define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN)) -#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN)) +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define __HAL_RCC_TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN)) +#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN)) -#define __RNG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_RNGEN)) -#define __RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN)) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ +#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_RNGEN)) +#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN)) +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ + + +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +/** @brief Enable or disable the IOPORT peripheral clock. + * @note After reset, the peripheral clock (used for registers read/write access) + * is disabled and the application software has to enable this clock before + * using it. + */ +#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ + __IO uint32_t tmpreg; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\ + UNUSED(tmpreg); \ + } while(0) + +#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN)) + +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx */ /** @brief Enable or disable the APB1 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) @@ -525,150 +646,260 @@ typedef struct * using it. */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) -#define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) -#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN)) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define __HAL_RCC_USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN)) +#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN)) -#if !defined(STM32L051xx) && !defined(STM32L061xx) -#define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN)) -#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ +#define __HAL_RCC_CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN)) +#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN)) +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ -#if defined(STM32L053xx) || defined(STM32L063xx) -#define __LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN)) -#define __LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN)) -#endif /* STM32L053xx || STM32L063xx */ +#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) +#define __HAL_RCC_LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN)) +#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN)) +#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ #if defined(STM32L053xx) || defined(STM32L063xx) || \ defined(STM32L052xx) || defined(STM32L062xx) || \ defined(STM32L051xx) || defined(STM32L061xx) -#define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) -#define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) -#define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) -#define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) -#define __LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN)) -#define __I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) -#define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) -#define __DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) -#define __LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN)) - -#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN)) -#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN)) -#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN)) -#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN)) -#define __LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN)) -#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN)) -#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN)) -#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN)) -#define __LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN)) -#endif /* STM32L051xx || STM32L061xx || */ - /* STM32L052xx || STM32L062xx || */ - /* STM32L053xx || STM32L063xx || */ - +#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN)) +#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN)) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN)) +#endif /* STM32L051xx || STM32L061xx || */ + /* STM32L052xx || STM32L062xx || */ + /* STM32L053xx || STM32L063xx || */ + +#if defined(STM32L031xx) || defined(STM32L041xx) +#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN)) +#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN)) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN)) +#endif /* STM32L031xx || STM32L041xx || */ + + +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN)) +#define __HAL_RCC_USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN)) +#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN)) +#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN)) +#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN)) + +#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN)) +#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN)) +#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN)) +#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN)) +#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN)) +#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN)) +#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN)) +#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN)) +#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN)) +#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN)) +#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN)) +#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN)) +#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN)) +#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN)) +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx */ + +#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \ + defined(STM32L031xx) || defined(STM32L041xx) + /** @brief Enable or disable the APB2 peripheral clock. * @note After reset, the peripheral clock (used for registers read/write access) * is disabled and the application software has to enable this clock before * using it. */ - -#if defined(STM32L053xx) || defined(STM32L063xx) || \ - defined(STM32L052xx) || defined(STM32L062xx) || \ - defined(STM32L051xx) || defined(STM32L061xx) -#define __TIM21_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN)) -#define __TIM22_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN)) -#define __FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN)) -#define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) -#define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) -#define __USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) - -#define __TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN)) -#define __TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN)) -#define __FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN)) -#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN)) -#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN)) -#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN)) -#endif /* STM32L051xx || STM32L061xx || */ - /* STM32L052xx || STM32L062xx || */ - /* STM32L053xx || STM32L063xx || */ +#define __HAL_RCC_TIM21_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN)) +#define __HAL_RCC_TIM22_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN)) +#define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN)) +#define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN)) + +#define __HAL_RCC_TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN)) +#define __HAL_RCC_TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN)) +#define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN)) +#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN)) +#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN)) +#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN)) +#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */ + /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */ + /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ /** @brief Force or release AHB peripheral reset. */ -#if defined(STM32L062xx) || defined(STM32L063xx) -#define __CRYP_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST)) -#define __CRYP_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST)) -#endif /* STM32L062xx || STM32L063xx */ - -#if !defined(STM32L051xx) && !defined(STM32L061xx) -#define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) -#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST)) -#define __RNG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST)) -#define __RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST)) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ - +#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) +#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST)) +#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST)) +#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */ + +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST)) +#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST)) +#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST)) +#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST)) +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ + +/** @brief Force or release IOPORT peripheral reset. + */ +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOERST)) + +#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST)) + +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx */ + /** @brief Force or release APB1 peripheral reset. */ + #if defined(STM32L053xx) || defined(STM32L063xx) || \ defined(STM32L052xx) || defined(STM32L062xx) || \ - defined(STM32L051xx) || defined(STM32L061xx) -#define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) -#define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) -#define __LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) -#define __I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) -#define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) -#define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) -#define __LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST)) -#define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) -#define __DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) - -#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST)) -#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST)) -#define __LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST)) -#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST)) -#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST)) -#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST)) -#define __LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST)) -#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST)) -#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST)) + defined(STM32L051xx) || defined(STM32L061xx) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST)) #endif /* STM32L051xx || STM32L061xx || */ /* STM32L052xx || STM32L062xx || */ - /* STM32L053xx || STM32L063xx || */ - -#if !defined(STM32L051xx) && !defined(STM32L061xx) -#define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) -#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST)) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ - -#if !defined(STM32L051xx) && !defined(STM32L061xx) -#define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) -#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ - -#if defined(STM32L053xx) || defined(STM32L063xx) -#define __LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) -#define __LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST)) -#endif /* STM32L053xx || STM32L063xx */ - -/** @brief Force or release APB2 peripheral reset. + /* STM32L053xx || STM32L063xx */ +#if defined(STM32L031xx) || defined(STM32L041xx) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST)) +#endif /* STM32L031xx || STM32L041xx || */ + +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST)) +#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST)) +#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST)) +#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST)) + +#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST)) +#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST)) +#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST)) +#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST)) +#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST)) +#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST)) +#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST)) +#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST)) +#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST)) +#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST)) +#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST)) +#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST)) +#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST)) +#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST)) +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx || */ + +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST)) +#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST)) +#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST)) +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ + +#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) +#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST)) +#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST)) +#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ + +#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) + /** @brief Force or release APB2 peripheral reset. */ -#if defined(STM32L053xx) || defined(STM32L063xx) || \ - defined(STM32L052xx) || defined(STM32L062xx) || \ - defined(STM32L051xx) || defined(STM32L061xx) -#define __USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) -#define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) -#define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) -#define __TIM21_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST)) -#define __TIM22_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST)) - -#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST)) -#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST)) -#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST)) -#define __TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST)) -#define __TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST)) -#endif /* STM32L051xx || STM32L061xx || */ - /* STM32L052xx || STM32L062xx || */ - /* STM32L053xx || STM32L063xx || */ +#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_TIM21_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST)) +#define __HAL_RCC_TIM22_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST)) + +#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST)) +#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST)) +#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST)) +#define __HAL_RCC_TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST)) +#define __HAL_RCC_TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST)) +#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */ + /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */ + /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */ /** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -677,18 +908,34 @@ typedef struct * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) -#define __TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN)) -#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN)) -#define __TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN)) -#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN)) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN)) +#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN)) +#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN)) +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ -#if defined(STM32L062xx) || defined(STM32L063xx) -#define __CRYP_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN)) -#define __CRYP_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN)) -#endif /* STM32L062xx || STM32L063xx */ +#if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx) +#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN)) +#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN)) +#endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */ + +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode. + * @note Peripheral clock gating in SLEEP mode can be used to further reduce + * power consumption. + * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. + * @note By default, all peripheral clocks are enabled during SLEEP mode. + */ + +#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOESMEN)) +#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN)) +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx || */ /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce @@ -699,66 +946,101 @@ typedef struct #if defined(STM32L053xx) || defined(STM32L063xx) || \ defined(STM32L052xx) || defined(STM32L062xx) || \ - defined(STM32L051xx) || defined(STM32L061xx) -#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN)) -#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN)) -#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN)) -#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN)) -#define __LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN)) -#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN)) -#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN)) -#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN)) -#define __LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN)) - -#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN)) -#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN)) -#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN)) -#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN)) -#define __LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN)) -#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN)) -#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN)) -#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN)) -#define __LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN)) + defined(STM32L051xx) || defined(STM32L061xx) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN)) +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN)) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN)) #endif /* STM32L051xx || STM32L061xx || */ /* STM32L052xx || STM32L062xx || */ - /* STM32L053xx || STM32L063xx || */ + /* STM32L053xx || STM32L063xx */ -#if !defined(STM32L051xx) && !defined(STM32L061xx) -#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN)) -#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN)) - -#define __CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN)) -#define __CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN)) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ - -#if defined(STM32L053xx) || defined(STM32L063xx) -#define __LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN)) -#define __LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN)) -#endif /* STM32L053xx || STM32L063xx */ - +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM3SMEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM7SMEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN)) +#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART4SMEN)) +#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART5SMEN)) +#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C3SMEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN)) + +#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN)) +#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN)) +#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN)) +#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN)) +#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN)) +#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN)) +#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN)) +#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN)) +#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN)) +#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN)) +#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN)) +#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN)) +#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN)) +#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN)) +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx || */ + +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) +#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN)) +#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN)) +#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN)) +#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN)) +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ + +#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) +#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN)) +#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN)) +#endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */ + +#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode. * @note Peripheral clock gating in SLEEP mode can be used to further reduce * power consumption. * @note After wakeup from SLEEP mode, the peripheral clock is enabled again. * @note By default, all peripheral clocks are enabled during SLEEP mode. */ -#if defined(STM32L053xx) || defined(STM32L063xx) || \ - defined(STM32L052xx) || defined(STM32L062xx) || \ - defined(STM32L051xx) || defined(STM32L061xx) -#define __TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN)) -#define __TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN)) -#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN)) -#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN)) -#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN)) - -#define __TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN)) -#define __TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN)) -#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN)) -#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN)) -#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN)) -#endif /* STM32L051xx || STM32L061xx || */ - /* STM32L052xx || STM32L062xx || */ - /* STM32L053xx || STM32L063xx || */ +#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN)) +#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN)) + +#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN)) +#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN)) +#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN)) +#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN)) +#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN)) +#endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */ + /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */ + /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */ /** @brief macro to configure the I2C1 clock (I2C1CLK). * @@ -779,6 +1061,32 @@ typedef struct */ #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL))) +#if defined (STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +/** @brief macro to configure the I2C3 clock (I2C3CLK). + * + * @param __I2C3CLKSource__: specifies the I2C3 clock source. + * This parameter can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock + */ +#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__)) + +/** @brief macro to get the I2C3 clock source. + * @retval The clock source can be one of the following values: + * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock + * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock + */ +#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL))) + +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx || */ + /** @brief macro to configure the USART1 clock (USART1CLK). * * @param __USART1CLKSource__: specifies the USART1 clock source. @@ -863,7 +1171,7 @@ typedef struct */ #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL))) -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /** @brief Macro to configure the USB clock (USBCLK). * @param __USBCLKSource__: specifies the USB clock source. * This parameter can be one of the following values: @@ -904,7 +1212,7 @@ typedef struct * USB an RNG peripherals. * This parameter can be one of the following values: * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output. - * @arg RCC_HSI48M_RC48: 48MHZ issued from internal HSI48 oscillator. + * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator. */ #define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \ MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__)) @@ -914,10 +1222,10 @@ typedef struct * __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources. * @retval The clock source can be one of the following values: * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output. - * @arg RCC_HSI48M_RC48: 48MHZ issued from internal HSI48 oscillator. + * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator. */ #define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL))) -#endif /* !(STM32L051xx ) && !(STM32L061xx ) */ +#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */ /** * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) @@ -946,14 +1254,14 @@ typedef struct * @brief Macro to configures the wake up from stop clock. * @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop * This parameter can be one of the following values: - * @arg RCC_StopWakeUpClock_MSI: MSI selected as system clock source - * @arg RCC_StopWakeUpClock_HSI: HSI selected as system clock source + * @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source + * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source * @retval None */ #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\ RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) )) -#if !defined(STM32L051xx) && !defined(STM32L061xx) +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) /** * @brief Enables the specified CRS interrupts. * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled. @@ -978,7 +1286,7 @@ typedef struct */ #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__)) -/** @brief Check the CRS's interrupt has occurred or not. +/** @brief Check the CRS interrupt has occurred or not. * @param __INTERRUPT__: specifies the CRS interrupt source to check. * This parameter can be one of the following values: * @arg RCC_CRS_IT_SYNCOK @@ -989,7 +1297,7 @@ typedef struct */ #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET) -/** @brief Clear the CRS's interrupt pending bits +/** @brief Clear the CRS interrupt pending bits * bits to clear the selected interrupt pending bits. * @param __INTERRUPT__: specifies the interrupt pending bit to clear. * This parameter can be any combination of the following values: @@ -1002,7 +1310,7 @@ typedef struct * @arg RCC_CRS_IT_SYNCMISS */ /* CRS IT Error Mask */ -#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) +#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \ (CRS->ICR = (__INTERRUPT__))) @@ -1020,7 +1328,7 @@ typedef struct * @arg RCC_CRS_FLAG_SYNCMISS * @retval The new state of _FLAG_ (TRUE or FALSE). */ -#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_)) +#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__)) /** * @brief Clears the CRS specified FLAG. @@ -1037,7 +1345,7 @@ typedef struct */ /* CRS Flag Error Mask */ -#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) +#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \ (CRS->ICR = (__FLAG__))) @@ -1083,27 +1391,84 @@ typedef struct * @param _FSYNC_ Synchronization signal frequency (value in Hz) * @retval None */ -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1) +#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1) -#endif /* !(STM32L051xx) && !(STM32L061xx) */ +#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */ + +#if defined(STM32L073xx) || defined(STM32L083xx) || \ + defined(STM32L072xx) || defined(STM32L082xx) || \ + defined(STM32L071xx) || defined(STM32L081xx) +/** @brief Enable or disable the HSI OUT . + * @note After reset, the HSI output is not available + */ + +#define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN) +#define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN) + +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx */ + +#if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) ||\ + defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) +/** + * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48). + * @note After enabling the HSI48, the application software should wait on + * HSI48RDY flag to be set indicating that HSI48 clock is stable and can + * be used to clock the USB. + * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. + */ +#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \ + SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); \ + } while (0) +#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \ + SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); \ + } while (0) +/** @brief Enable or disable the HSI48M DIV6 OUT . + * @note After reset, the HSI48Mhz (divided by 6) output is not available + */ + +#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN) +#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN) + +#endif /* STM32L071xx || STM32L081xx || */ + /* STM32L072xx || STM32L082xx || */ + /* STM32L073xx || STM32L083xx */ + /** * @} */ - -/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions + * @{ + */ + +/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions + + * @{ + */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); -void HAL_RCCEx_EnableLSECSS(void); -void HAL_RCCEx_DisableLSECSS(void); -#if !defined(STM32L051xx) && !defined(STM32L061xx) +void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); +void HAL_RCCEx_EnableLSECSS(void); +void HAL_RCCEx_DisableLSECSS(void); +#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); -RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); -#endif /* !(STM32L051xx) && !(STM32L061xx) */ - +uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); +void HAL_RCCEx_EnableHSI48_VREFINT(void); +void HAL_RCCEx_DisableHSI48_VREFINT(void); +#endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */ + +/** + * @} + */ +/** + * @} + */ + /** * @} */ @@ -1119,3 +1484,4 @@ RCC_CRSStatusTypeDef HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); #endif /* __STM32L0xx_HAL_RCC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.c index 29803b81ce1..a50d9cbd8bf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rng.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief RNG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Random Number Generator (RNG) peripheral: @@ -15,20 +15,21 @@ ============================================================================== ##### How to use this driver ##### ============================================================================== - [..] + [..] The RNG HAL driver can be used as follows: - - (#) Enable the RNG controller clock using __RNG_CLK_ENABLE() macro. - (#) Activate the RNG peripheral using __HAL_RNG_ENABLE() macro. - (#) Wait until the 32 bit Random Number Generator contains a valid - random data using (polling/interrupt) mode. - (#) Get the 32 bit random number using HAL_RNG_GetRandomNumber() function. + + (#) Enable the RNG controller clock using __HAL_RCC_RNG_CLK_ENABLE() macro. + in HAL_RNG_MspInit(). + (#) Activate the RNG peripheral using HAL_RNG_Init() function. + (#) Wait until the 32 bit Random Number Generator contains a valid + random data using (polling/interrupt) mode. + (#) Get the 32 bit random number using HAL_RNG_GenerateRandomNumber() function. @endverbatim ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -62,28 +63,38 @@ * @{ */ -/** @defgroup RNG - * @brief RNG HAL module driver. +/** @addtogroup RNG * @{ */ #ifdef HAL_RNG_MODULE_ENABLED -#if !defined (STM32L051xx) && !defined (STM32L061xx) -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ + +#if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx) || \ + defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) +/* Private types -------------------------------------------------------------*/ +/* Private Defines -----------------------------------------------------------*/ +/** @addtogroup RNG_Private_Defines + * @{ + */ #define RNG_TIMEOUT_VALUE 1000 -/* Private macro -------------------------------------------------------------*/ +/** + * @} + */ + /* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private functions prototypes ----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Private_Functions +/** @addtogroup RNG_Exported_Functions * @{ */ -/** @defgroup RNG_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions. +/** @addtogroup RNG_Exported_Functions_Group1 + * @brief Initialization and de-initialization functions * @verbatim =============================================================================== @@ -95,106 +106,100 @@ (+) DeInitialize the RNG peripheral (+) Initialize the RNG MSP (+) DeInitialize RNG MSP - + @endverbatim * @{ */ - + /** - * @brief Initializes the RNG according to the specified - * parameters in the RNG_InitTypeDef and creates the associated handle. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. + * @brief Initializes the RNG peripheral and creates the associated handle. + * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) { /* Check the RNG handle allocation */ - if(hrng == HAL_NULL) + if(hrng == NULL) { return HAL_ERROR; } - + assert_param(IS_RNG_ALL_INSTANCE(hrng->Instance)); + + __HAL_LOCK(hrng); + if(hrng->State == HAL_RNG_STATE_RESET) - { + { /* Init the low level hardware */ HAL_RNG_MspInit(hrng); } - + /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_BUSY; - + /* Enable the RNG Peripheral */ __HAL_RNG_ENABLE(hrng); - + /* Initialize the RNG state */ hrng->State = HAL_RNG_STATE_READY; + __HAL_UNLOCK(hrng); + /* Return function status */ return HAL_OK; } /** * @brief DeInitializes the RNG peripheral. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. + * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval HAL status */ HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng) { - /* Check the RNG peripheral state */ - if(hrng->State == HAL_RNG_STATE_BUSY) + /* Check the RNG handle allocation */ + if(hrng == NULL) { - return HAL_BUSY; + return HAL_ERROR; } - - /* Update the RNG state */ - hrng->State = HAL_RNG_STATE_BUSY; - /* Disable the RNG Peripheral */ - __HAL_RNG_DISABLE(hrng); + CLEAR_BIT(hrng->Instance->CR, RNG_CR_IE | RNG_CR_RNGEN); - /* Set the RNG registers to their reset values */ - hrng->Instance->CR &= 0xFFFFFFF3; - hrng->Instance->SR &= 0xFFFFFF98; - hrng->Instance->DR &= 0x0; + /* Clear RNG interrupt status flags */ + CLEAR_BIT(hrng->Instance->SR, RNG_SR_CEIS | RNG_SR_SEIS); /* DeInit the low level hardware */ HAL_RNG_MspDeInit(hrng); - /* Update the RNG state */ + /* Update the RNG state */ hrng->State = HAL_RNG_STATE_RESET; - + /* Release Lock */ __HAL_UNLOCK(hrng); - - /* Return the function status */ + + /* Return the function status */ return HAL_OK; } /** * @brief Initializes the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. + * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval None */ __weak void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RNG_MspInit could be implemented in the user file + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_MspInit must be implemented in the user file. */ } /** * @brief DeInitializes the RNG MSP. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. + * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval None */ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RNG_MspDeInit could be implemented in the user file + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_MspDeInit must be implemented in the user file. */ } @@ -202,8 +207,8 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Group2 Peripheral Control functions - * @brief management functions. +/** @addtogroup RNG_Exported_Functions_Group2 + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -220,67 +225,95 @@ __weak void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng) */ /** - * @brief Returns a 32-bit random number. + * @brief Generates a 32-bit random number. * @note Each time the random number data is read the RNG_FLAG_DRDY flag * is automatically cleared. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval 32-bit random number + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @param random32bit: pointer to generated random number variable if successful. + * @retval HAL status */ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) + +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit) { - uint32_t random32bit = 0; uint32_t tickstart = 0; - + HAL_StatusTypeDef status = HAL_OK; + /* Process Locked */ __HAL_LOCK(hrng); - /* Get timeout */ - tickstart = HAL_GetTick(); + /* Check RNG peripheral state */ + if(hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Get tick */ + tickstart = HAL_GetTick(); + + /* Check if data register contains valid random data */ + while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + { + if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE) + { + hrng->State = HAL_RNG_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + return HAL_TIMEOUT; + } + } - /* Check if data register contains valid random data */ - while(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) == RESET) + /* Get a 32bit Random number */ + hrng->RandomNumber = hrng->Instance->DR; + *random32bit = hrng->RandomNumber; + + hrng->State = HAL_RNG_STATE_READY; + } + else { - if((HAL_GetTick() - tickstart ) > RNG_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } + status = HAL_ERROR; } - /* Get a 32bit Random number */ - random32bit = hrng->Instance->DR; - /* Process Unlocked */ __HAL_UNLOCK(hrng); - - /* Return the 32 bit random number */ - return random32bit; + + return status; } /** - * @brief Returns a 32-bit random number with interrupt enabled. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. - * @retval 32-bit random number + * @brief Generates a 32-bit random number in interrupt mode. + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval HAL status */ -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng) { - uint32_t random32bit = 0; + HAL_StatusTypeDef status = HAL_OK; /* Process Locked */ __HAL_LOCK(hrng); - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_BUSY; - - /* Get a 32bit Random number */ - random32bit = hrng->Instance->DR; + /* Check RNG peripheral state */ + if(hrng->State == HAL_RNG_STATE_READY) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; - /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ - __HAL_RNG_ENABLE_IT(hrng); + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ + __HAL_RNG_ENABLE_IT(hrng); + } + else + { + /* Process Unlocked */ + __HAL_UNLOCK(hrng); + + status = HAL_ERROR; + } - /* Return the 32 bit random number */ - return random32bit; + return status; } /** @@ -288,101 +321,144 @@ uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) * @note In the case of a clock error, the RNG is no more able to generate * random numbers because the PLL48CLK clock is not correct. User has * to check that the clock controller is correctly configured to provide - * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_FLAG(). + * the RNG clock and clear the CEIS bit using __HAL_RNG_CLEAR_IT(). * The clock error has no impact on the previously generated * random numbers, and the RNG_DR register contents can be used. * @note In the case of a seed error, the generation of random numbers is * interrupted as long as the SECS bit is '1'. If a number is * available in the RNG_DR register, it must not be used because it may * not have enough entropy. In this case, it is recommended to clear the - * SEIS bit using __HAL_RNG_CLEAR_FLAG(), then disable and enable + * SEIS bit using __HAL_RNG_CLEAR_IT(), then disable and enable * the RNG peripheral to reinitialize and restart the RNG. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. + * @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS + * or CEIS are set. + * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval None */ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng) { /* RNG clock error interrupt occurred */ - if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_CEI) != RESET) + if((__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) || (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)) { - HAL_RNG_ErrorCallback(hrng); - - /* Clear the clock error flag */ - __HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_CEI); - /* Change RNG peripheral state */ hrng->State = HAL_RNG_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); - } - /* RNG seed error interrupt occurred */ - if(__HAL_RNG_GET_FLAG(hrng, RNG_IT_SEI) != RESET) - { HAL_RNG_ErrorCallback(hrng); - /* Clear the seed error flag */ - __HAL_RNG_CLEAR_FLAG(hrng, RNG_IT_SEI); + /* Clear the clock error flag */ + __HAL_RNG_CLEAR_IT(hrng, RNG_IT_CEI|RNG_IT_SEI); - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrng); } - /* Check RNG data ready flag */ - if(__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != RESET) + /* Check RNG data ready interrupt occurred */ + if(__HAL_RNG_GET_IT(hrng, RNG_IT_DRDY) != RESET) { - /* Data Ready callback */ - HAL_RNG_ReadyCallback(hrng); + /* Generate random number once, so disable the IT */ + __HAL_RNG_DISABLE_IT(hrng); - /* Change RNG peripheral state */ - hrng->State = HAL_RNG_STATE_READY; - - /* Clear the RNG Data Ready flag */ - __HAL_RNG_CLEAR_FLAG(hrng, RNG_FLAG_DRDY); + /* Get the 32bit Random number (DRDY flag automatically cleared) */ + hrng->RandomNumber = hrng->Instance->DR; - /* Process Unlocked */ - __HAL_UNLOCK(hrng); + if(hrng->State != HAL_RNG_STATE_ERROR) + { + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_READY; + + /* Data Ready callback */ + HAL_RNG_ReadyDataCallback(hrng, hrng->RandomNumber); + } } } /** - * @brief Data Ready callback in non-blocking mode. + * @brief return generated random number in polling mode (Obsolete). + * Use HAL_RNG_GenerateRandomNumber() API instead. * @param hrng: pointer to a RNG_HandleTypeDef structure that contains * the configuration information for RNG. - * @retval None + * @retval random value + */ +uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng) +{ + if(HAL_RNG_GenerateRandomNumber(hrng, &(hrng->RandomNumber)) == HAL_OK) + { + return hrng->RandomNumber; + } + else + { + return 0; + } +} + + +/** + * @brief Returns a 32-bit random number with interrupt enabled (Obsolete), + * Use HAL_RNG_GenerateRandomNumber_IT() API instead. + * @param hrng: RNG handle + * @retval 32-bit random number */ +uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng) +{ + uint32_t random32bit = 0; + + /* Process locked */ + __HAL_LOCK(hrng); + + /* Change RNG peripheral state */ + hrng->State = HAL_RNG_STATE_BUSY; + + /* Get a 32bit Random number */ + random32bit = hrng->Instance->DR; + + /* Enable the RNG Interrupts: Data Ready, Clock error, Seed error */ + __HAL_RNG_ENABLE_IT(hrng); + + /* Return the 32 bit random number */ + return random32bit; +} -__weak void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng) + + +/** + * @brief Read latest generated random number. + * @param hrng: pointer to a RNG_HandleTypeDef structure. + * @retval random value + */ +uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng) +{ + return(hrng->RandomNumber); +} + +/** + * @brief Data Ready callback in non-blocking mode. + * @param hrng: pointer to a RNG_HandleTypeDef structure.. + * @param random32bit: generated random value + * @retval None + */ +__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RNG_ReadyCallback could be implemented in the user file + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_ReadyDataCallback must be implemented in the user file. */ } /** * @brief RNG error callbacks. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. + * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval None */ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RNG_ErrorCallback could be implemented in the user file - */ + /* NOTE : This function should not be modified. When the callback is needed, + function HAL_RNG_ErrorCallback must be implemented in the user file. + */ } /** * @} */ -/** @defgroup RNG_Group3 Peripheral State functions +/** @addtogroup RNG_Exported_Functions_Group3 * @brief Peripheral State functions. * @verbatim @@ -390,8 +466,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) ##### Peripheral State functions ##### =============================================================================== [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. + This subsection permits to get in run-time the status of the peripheral. @endverbatim * @{ @@ -399,8 +474,7 @@ __weak void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng) /** * @brief Returns the RNG state. - * @param hrng: pointer to a RNG_HandleTypeDef structure that contains - * the configuration information for RNG. + * @param hrng: pointer to a RNG_HandleTypeDef structure. * @retval HAL state */ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) @@ -415,8 +489,12 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) /** * @} */ -#endif /* STM32L051xx && STM32L061xx*/ + +#endif /* if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx) || \ + defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ + #endif /* HAL_RNG_MODULE_ENABLED */ + /** * @} */ @@ -426,4 +504,4 @@ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.h index b6056b3a16f..3879786f93a 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rng.h @@ -1,14 +1,15 @@ /** ****************************************************************************** * @file stm32l0xx_hal_rng.h + * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of RNG HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -43,7 +44,9 @@ extern "C" { #endif -#if !defined (STM32L051xx) && !defined (STM32L061xx) +#if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx) || \ + defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) + /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" @@ -51,15 +54,20 @@ * @{ */ -/** @addtogroup RNG +/** @defgroup RNG RNG + * @brief RNG HAL module driver * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ -/** - * @brief RNG HAL State Structure definition - */ +/** @defgroup RNG_Exported_Types RNG Exported Types + * @{ + */ + +/** @defgroup RNG_Exported_Types_Group1 RNG State Structure definition + * @{ + */ typedef enum { HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */ @@ -71,47 +79,57 @@ typedef enum }HAL_RNG_StateTypeDef; /** - * @brief RNG Handle Structure definition + * @} + */ + +/** @defgroup RNG_Exported_Types_Group2 RNG Handle Structure definition + * @{ */ typedef struct { - RNG_TypeDef *Instance; /*!< Register base address */ + RNG_TypeDef *Instance; /*!< Register base address */ - HAL_LockTypeDef Lock; /*!< RNG locking object */ + HAL_LockTypeDef Lock; /*!< RNG locking object */ - __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + __IO HAL_RNG_StateTypeDef State; /*!< RNG communication state */ + + uint32_t RandomNumber; /*!< Last Generated RNG Data */ }RNG_HandleTypeDef; +/** + * @} + */ + +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Exported_Constants +/** @defgroup RNG_Exported_Constants RNG Exported Constants * @{ */ -/** @defgroup RNG_Interrupt_definition +/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition * @{ */ -#define RNG_IT_CEI ((uint32_t)0x20) /*!< Clock error interrupt */ -#define RNG_IT_SEI ((uint32_t)0x40) /*!< Seed error interrupt */ +#define RNG_IT_DRDY ((uint32_t)RNG_SR_DRDY) /*!< Data ready interrupt */ +#define RNG_IT_CEI ((uint32_t)RNG_SR_CEIS) /*!< Clock error interrupt */ +#define RNG_IT_SEI ((uint32_t)RNG_SR_SEIS) /*!< Seed error interrupt */ + -#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \ - ((IT) == RNG_IT_SEI)) /** * @} */ - -/** @defgroup RNG_Flag_definition +/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition * @{ */ -#define RNG_FLAG_DRDY ((uint32_t)0x0001) /*!< Data ready */ -#define RNG_FLAG_CECS ((uint32_t)0x0002) /*!< Clock error current status */ -#define RNG_FLAG_SECS ((uint32_t)0x0004) /*!< Seed error current status */ +#define RNG_FLAG_DRDY ((uint32_t)RNG_SR_DRDY) /*!< Data ready */ +#define RNG_FLAG_CECS ((uint32_t)RNG_SR_CECS) /*!< Clock error current status */ +#define RNG_FLAG_SECS ((uint32_t)RNG_SR_SECS) /*!< Seed error current status */ -#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \ - ((FLAG) == RNG_FLAG_CECS) || \ - ((FLAG) == RNG_FLAG_SECS)) /** * @} */ @@ -120,7 +138,10 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RNG_Exported_Macros RNG Exported Macros + * @{ + */ /** @brief Reset RNG handle state * @param __HANDLE__: RNG Handle @@ -143,21 +164,30 @@ typedef struct #define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN) /** - * @brief Gets the selected RNG's flag status. + * @brief Check the selected RNG flag status. * @param __HANDLE__: RNG Handle * @param __FLAG__: RNG flag - * @retval The new state of RNG_FLAG (SET or RESET). + * This parameter can be one of the following values: + * @arg RNG_FLAG_DRDY: Data ready + * @arg RNG_FLAG_CECS: Clock error current status + * @arg RNG_FLAG_SECS: Seed error current status + * @retval The new state of __FLAG__ (SET or RESET). */ #define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + /** - * @brief Clears the RNG's pending flags. - * @param __HANDLE__: RNG Handle - * @param __FLAG__: RNG flag + * @brief Clears the selected RNG flag status. + * @param __HANDLE__: RNG handle + * @param __FLAG__: RNG flag to clear + * @note WARNING: This is a dummy macro for HAL code alignment, + * flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only. * @retval None */ -#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) - +#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__) /* dummy macro */ + + + /** * @brief Enables the RNG interrupts. * @param __HANDLE__: RNG Handle @@ -168,10 +198,6 @@ typedef struct /** * @brief Disables the RNG interrupts. * @param __HANDLE__: RNG Handle - * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data ready interrupt - * @arg RNG_FLAG_CECS: Clock error interrupt - * @arg RNG_FLAG_SECS: Seed error interrupt * @retval None */ #define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE) @@ -179,46 +205,158 @@ typedef struct /** * @brief Checks whether the specified RNG interrupt has occurred or not. * @param __HANDLE__: RNG Handle - * @param __INTERRUPT__: specifies the RNG interrupt source to check. + * @param __INTERRUPT__: specifies the RNG interrupt status flag to check. * This parameter can be one of the following values: - * @arg RNG_FLAG_DRDY: Data ready interrupt - * @arg RNG_FLAG_CECS: Clock error interrupt - * @arg RNG_FLAG_SECS: Seed error interrupt - * @retval The new state of RNG_FLAG (SET or RESET). + * @arg RNG_IT_DRDY: Data ready interrupt + * @arg RNG_IT_CEI: Clock error interrupt + * @arg RNG_IT_SEI: Seed error interrupt + * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) +/** + * @brief Clears the RNG interrupt status flags. + * @param __HANDLE__: RNG Handle + * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear. + * This parameter can be one of the following values: + * @arg RNG_IT_CEI: Clock error interrupt + * @arg RNG_IT_SEI: Seed error interrupt + * @note RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY. + * @retval None + */ +#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__)) + +/** + * @} + */ + /* Exported functions --------------------------------------------------------*/ +/** @defgroup RNG_Exported_Functions RNG Exported Functions + * @{ + */ -/* Initialization/de-initialization functions **********************************/ +/* Initialization and de-initialization functions ******************************/ +/** @defgroup RNG_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng); HAL_StatusTypeDef HAL_RNG_DeInit (RNG_HandleTypeDef *hrng); void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng); void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng); +/** + * @} + */ + /* Peripheral Control functions ************************************************/ -uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); +/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ +uint32_t HAL_RNG_GetRandomNumber(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber() instead */ +uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng); /* Obsolete, use HAL_RNG_GenerateRandomNumber_IT() instead */ + +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); +HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); + void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); -void HAL_RNG_ReadyCallback(RNG_HandleTypeDef* hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); +void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef* hrng, uint32_t random32bit); + +/** + * @} + */ /* Peripheral State functions **************************************************/ +/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions + * @{ + */ HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); +/** + * @} + */ + +/** + * @} + */ + +/* Private types -------------------------------------------------------------*/ +/** @defgroup RNG_Private_Types RNG Private Types + * @{ + */ + +/** + * @} + */ + +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RNG_Private_Defines RNG Private Defines + * @{ + */ + +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Variables RNG Private Variables + * @{ + */ + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Constants RNG Private Constants + * @{ + */ -#endif /* STM32L051xx && STM32L061xx*/ /** * @} */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup RNG_Private_Macros RNG Private Macros + * @{ + */ /** * @} */ +/* Private functions prototypes ----------------------------------------------*/ +/** @defgroup RNG_Private_Functions_Prototypes RNG Private Functions Prototypes + * @{ + */ + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ +/** @defgroup RNG_Private_Functions RNG Private Functions + * @{ + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* if defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L062xx) || defined (STM32L063xx) || \ + defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L082xx) || defined (STM32L083xx) */ #ifdef __cplusplus } #endif #endif /* __STM32L0xx_HAL_RNG_H */ + /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.c index a9a1a978f2e..0241b0ccad5 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_rtc.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief RTC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Real Time Clock (RTC) peripheral: @@ -35,14 +35,14 @@ is protected against possible unwanted write accesses. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() function. + __HAL_RCC_PWR_CLK_ENABLE() function. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. - ##### How to use this driver ##### - ================================================================== + ##### How to use RTC Driver ##### + =================================================================== [..] (+) Enable the RTC domain access (see description in the section above). (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour @@ -59,7 +59,8 @@ =========================== [..] (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. - You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function. + You can also configure the RTC Alarm with interrupt mode using the + HAL_RTC_SetAlarm_IT() function. (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function. *** RTC Wakeup configuration *** @@ -141,7 +142,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -175,7 +176,7 @@ * @{ */ -/** @defgroup RTC +/** @addtogroup RTC * @brief RTC HAL module driver * @{ */ @@ -184,29 +185,16 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_INITF | RTC_FLAG_RSF | \ - RTC_FLAG_INITS | RTC_FLAG_WUTWF | RTC_FLAG_ALRBWF | \ - RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | \ - RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) - -#define RTC_TIMEOUT_VALUE 1000 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup RTC_Private_Functions +/** @addtogroup RTC_Exported_Functions * @{ */ -/** @defgroup RTC_Group1 Initialization and de-initialization functions +/** @addtogroup RTC_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim @@ -219,7 +207,7 @@ RTC registers synchronization check and reference clock detection enable. (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is split into 2 programmable prescalers to minimize power consumption. - (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler. + (++) A 7-bit asynchronous prescaler and a 15-bit synchronous prescaler. (++) When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize power consumption. (#) All RTC registers are Write protected. Writing to the RTC registers @@ -242,19 +230,19 @@ /** * @brief Initializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) { /* Check the RTC peripheral state */ - if(hrtc == HAL_NULL) + if(hrtc == NULL) { return HAL_ERROR; } /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat)); assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv)); assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv)); @@ -298,9 +286,9 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); - hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_RTC_OUT_RMP); + hrtc->Instance->OR &= (uint32_t)~(RTC_OR_ALARMOUTTYPE | RTC_OR_OUT_RMP); hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); /* Enable the write protection for RTC registers */ @@ -315,14 +303,16 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) /** * @brief DeInitializes the RTC peripheral - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @note This function doesn't reset the RTC Backup Data registers. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart; + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance)); /* Set RTC state */ hrtc->State = HAL_RTC_STATE_BUSY; @@ -345,9 +335,9 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) { /* Reset TR, DR and CR registers */ hrtc->Instance->TR = (uint32_t)0x00000000; - hrtc->Instance->DR = (uint32_t)0x00002101; + hrtc->Instance->DR = ((uint32_t)(RTC_DR_WDU_0 | RTC_DR_MU_0 | RTC_DR_DU_0)); /* Reset All CR bits except CR[2:0] */ - hrtc->Instance->CR &= (uint32_t)0x00000007; + hrtc->Instance->CR &= RTC_CR_WUCKSEL; tickstart = HAL_GetTick(); @@ -368,8 +358,8 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /* Reset all RTC CR register bits */ hrtc->Instance->CR &= (uint32_t)0x00000000; - hrtc->Instance->WUTR = (uint32_t)0x0000FFFF; - hrtc->Instance->PRER = (uint32_t)0x007F00FF; + hrtc->Instance->WUTR = RTC_WUTR_WUT; + hrtc->Instance->PRER = ((uint32_t)(RTC_PRER_PREDIV_A | 0x000000FF)); hrtc->Instance->ALRMAR = (uint32_t)0x00000000; hrtc->Instance->ALRMBR = (uint32_t)0x00000000; hrtc->Instance->SHIFTR = (uint32_t)0x00000000; @@ -417,8 +407,7 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc) /** * @brief Initializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) @@ -430,8 +419,7 @@ __weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc) /** * @brief DeInitializes the RTC MSP. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) @@ -445,7 +433,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) * @} */ -/** @defgroup RTC_Group2 RTC Time and Date functions +/** @addtogroup RTC_Exported_Functions_Group2 * @brief RTC Time and Date functions * @verbatim @@ -453,8 +441,7 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) ##### RTC Time and Date functions ##### =============================================================================== - [..] This section provide functions allowing to control RTC features - (Time, Date, Alarm, Timestamp, Tamper, RefClock ...). + [..] This section provide functions allowing to configure Time and Date features @endverbatim * @{ @@ -462,13 +449,13 @@ __weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc) /** * @brief Sets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sTime: Pointer to Time structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD +: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -485,7 +472,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -525,7 +512,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim ((uint32_t)sTime->Seconds) | \ ((uint32_t)(sTime->TimeFormat) << 16)); } - + UNUSED(tmpreg); /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -549,13 +536,13 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK); /* Clear the bits to be configured */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK; + hrtc->Instance->CR &= ((uint32_t)~RTC_CR_BCK); /* Configure the RTC_CR register */ hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) @@ -587,15 +574,17 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Gets RTC current time. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sTime: Pointer to Time structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format - * @note Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values - * in the higher-order calendar shadow registers. + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD +: BCD data format + * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values in the + * higher-order calendar shadow registers. + * Reading RTC current time locks the values in calendar shadow registers until current + * date is read to ensure consistency between the time and date values. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) @@ -618,7 +607,7 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the time structure parameters to Binary format */ sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours); @@ -631,13 +620,13 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim /** * @brief Sets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sDate: Pointer to date structure * @param Format: specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD +: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -652,14 +641,14 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->State = HAL_RTC_STATE_BUSY; - if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) + if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10)) { - sDate->Month = (sDate->Month & (uint32_t)~(0x10)) + 0x0A; + sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A); } assert_param(IS_RTC_WEEKDAY(sDate->WeekDay)); - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { assert_param(IS_RTC_YEAR(sDate->Year)); assert_param(IS_RTC_MONTH(sDate->Month)); @@ -707,7 +696,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK); /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + hrtc->Instance->ISR &= ((uint32_t)~RTC_ISR_INIT); /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) @@ -740,13 +729,13 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat /** * @brief Gets RTC current date. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sDate: Pointer to Date structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD +: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) @@ -766,7 +755,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the date structure parameters to Binary format */ sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year); @@ -780,7 +769,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @} */ -/** @defgroup RTC_Group3 RTC Alarm functions +/** @addtogroup RTC_Exported_Functions_Group3 * @brief RTC Alarm functions * @verbatim @@ -795,24 +784,24 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat */ /** * @brief Sets the specified RTC Alarm. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sAlarm: Pointer to Alarm structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD +: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart; + uint32_t tickstart = 0; uint32_t tmpreg = 0, subsecondtmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(sAlarm->Alarm)); - assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); @@ -822,7 +811,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -977,24 +966,27 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief Sets the specified RTC Alarm with Interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sAlarm: Pointer to Alarm structure * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD +: BCD data format + * @note The Alarm register can only be written when the corresponding Alarm + * is disabled (Use the HAL_RTC_DeactivateAlarm()). + * @note The HAL_RTC_SetTime() must be called before enabling the Alarm feature. * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) { - uint32_t tickstart; + uint32_t tickstart = 0; uint32_t tmpreg = 0, subsecondtmpreg = 0; /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(sAlarm->Alarm)); - assert_param(IS_ALARM_MASK(sAlarm->AlarmMask)); + assert_param(IS_RTC_ALARM(sAlarm->Alarm)); + assert_param(IS_RTC_ALARM_MASK(sAlarm->AlarmMask)); assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel)); assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds)); assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask)); @@ -1004,7 +996,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef hrtc->State = HAL_RTC_STATE_BUSY; - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET) { @@ -1147,9 +1139,9 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef } /* RTC Alarm Interrupt Configuration: EXTI configuration */ - __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT); + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT; + __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1164,8 +1156,7 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef /** * @brief Deactive the specified RTC Alarm - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param Alarm: Specifies the Alarm. * This parameter can be one of the following values: * @arg RTC_ALARM_A: AlarmA @@ -1174,10 +1165,10 @@ HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef */ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) { - uint32_t tickstart; + uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_ALARM(Alarm)); + assert_param(IS_RTC_ALARM(Alarm)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -1254,8 +1245,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar /** * @brief Gets the RTC Alarm value and masks. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sAlarm: Pointer to Date structure * @param Alarm: Specifies the Alarm. * This parameter can be one of the following values: @@ -1263,8 +1253,9 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @arg RTC_ALARM_B: AlarmB * @param Format: Specifies the format of the entered parameters. * This parameter can be one of the following values: - * @arg FORMAT_BIN: Binary data format - * @arg FORMAT_BCD: BCD data format + * @arg RTC_FORMAT_BIN: Binary data format + * @arg RTC_FORMAT_BCD +: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) @@ -1273,7 +1264,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /* Check the parameters */ assert_param(IS_RTC_FORMAT(Format)); - assert_param(IS_ALARM(Alarm)); + assert_param(IS_RTC_ALARM(Alarm)); if(Alarm == RTC_ALARM_A) { @@ -1282,6 +1273,16 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA tmpreg = (uint32_t)(hrtc->Instance->ALRMAR); subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR ) & RTC_ALRMASSR_SS); + +/* Fill the structure with the read parameters */ + sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16); + sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8); + sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU)); + sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16); + sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg; + sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24); + sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL); + sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); } else { @@ -1289,8 +1290,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA tmpreg = (uint32_t)(hrtc->Instance->ALRMBR); subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS); - } - + /* Fill the structure with the read parameters */ sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMBR_HT | RTC_ALRMBR_HU)) >> 16); sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU)) >> 8); @@ -1300,8 +1300,9 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMBR_DT | RTC_ALRMBR_DU)) >> 24); sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMBR_WDSEL); sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL); - - if(Format == FORMAT_BIN) + } + + if(Format == RTC_FORMAT_BIN) { sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours); sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes); @@ -1314,8 +1315,7 @@ HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sA /** * @brief This function handles Alarm interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval None */ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) @@ -1347,7 +1347,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) } /* Clear the EXTI's line Flag for RTC Alarm */ - __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT); + __HAL_RTC_ALARM_EXTI_CLEAR_FLAG(); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1355,8 +1355,7 @@ void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc) /** * @brief Alarm A callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval None */ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) @@ -1368,24 +1367,20 @@ __weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc) /** * @brief This function handles AlarmA Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param Timeout: Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t tickstart; - - /* Get Timeout value */ - tickstart = HAL_GetTick(); + uint32_t tickstart = HAL_GetTick(); while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET) { if(Timeout != HAL_MAX_DELAY) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; return HAL_TIMEOUT; @@ -1406,7 +1401,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * @} */ -/** @defgroup RTC_Group4 Peripheral Control functions +/** @addtogroup RTC_Exported_Functions_Group4 * @brief Peripheral Control functions * @verbatim @@ -1415,9 +1410,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T =============================================================================== [..] This subsection provides functions allowing to - (+) get the RTC state - (+) poll for alarm, timestamp, tamper or wakeup timer events - (+) handle alarm, timestamp, tamper or wakeup timer interrupt request. + (+) Wait for RTC Time and Date Synchronization @endverbatim * @{ @@ -1434,13 +1427,12 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * The software must then wait until it is set again before reading * the calendar, which means that the calendar registers have been * correctly copied into the RTC_TR and RTC_DR shadow registers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart; + uint32_t tickstart = 0; /* Clear RSF flag */ hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK; @@ -1459,7 +1451,11 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) return HAL_OK; } -/** @defgroup RTC_Group5 Peripheral State functions +/** + * @} + */ + +/** @addtogroup RTC_Exported_Functions_Group5 * @brief Peripheral State functions * @verbatim @@ -1475,8 +1471,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc) */ /** * @brief Returns the RTC state. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval HAL state */ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) @@ -1484,21 +1479,26 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc) return hrtc->State; } +/** + * @} + */ /** * @} */ +/** @addtogroup RTC_Private_Functions + * @{ + */ /** * @brief Enters the RTC Initialization mode. * @note The RTC Initialization mode is write protected, use the * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart; + uint32_t tickstart = 0; /* Check if the Initialization mode is set */ if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET) @@ -1550,12 +1550,12 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10; return (tmp + (Value & (uint8_t)0x0F)); } - /** * @} */ #endif /* HAL_RTC_MODULE_ENABLED */ + /** * @} */ @@ -1565,3 +1565,4 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.h index 098bf49881f..466c3a801ff 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_rtc.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,11 +50,15 @@ * @{ */ -/** @addtogroup RTC +/** @defgroup RTC RTC + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup RTC_Exported_Types RTC Exported Types * @{ */ -/* Exported types ------------------------------------------------------------*/ /** * @brief HAL State structures definition */ @@ -116,7 +120,7 @@ typedef struct uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time. This parameter can be a value of @ref RTC_AM_PM_Definitions */ - uint32_t DayLightSaving; /*!< Specifies DayLight Save Operation. + uint32_t DayLightSaving; /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. This parameter can be a value of @ref RTC_DayLightSaving_Definitions */ uint32_t StoreOperation; /*!< Specifies RTC_StoreOperation value to be written in the BCK bit @@ -181,25 +185,48 @@ typedef struct __IO HAL_RTCStateTypeDef State; /*!< Time communication state */ }RTC_HandleTypeDef; +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_Exported_Constants +/** @defgroup RTC_Exported_Constants RTC Exported Constants * @{ */ -/** @defgroup RTC_Hour_Formats +/** @defgroup RTC_Mask_Definition RTC Mask Definition + * @{ + */ +/* Masks Definition */ +#define RTC_TR_RESERVED_MASK ((uint32_t) (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ + RTC_TR_SU)) +#define RTC_DR_RESERVED_MASK ((uint32_t) (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ + RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ + RTC_DR_DU)) + +#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) + +#define RTC_RSF_MASK ((uint32_t)~(RTC_ISR_INIT | RTC_ISR_RSF)) + +#define RTC_TIMEOUT_VALUE 1000 +/** + * @} + */ + +/** @defgroup RTC_Hour_Formats RTC Hour Formats * @{ */ #define RTC_HOURFORMAT_24 ((uint32_t)0x00000000) -#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040) +#define RTC_HOURFORMAT_12 ((uint32_t)RTC_CR_FMT) -#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ - ((FORMAT) == RTC_HOURFORMAT_24)) +#define IS_RTC_HOUR_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_HOURFORMAT_12) || \ + ((__FORMAT__) == RTC_HOURFORMAT_24)) /** * @} */ -/** @defgroup RTC_Output_selection_Definitions +/** @defgroup RTC_Output_selection_Definitions RTC Output selection Definitions * @{ */ #define RTC_OUTPUT_DISABLE ((uint32_t)0x00000000) @@ -207,136 +234,139 @@ typedef struct #define RTC_OUTPUT_ALARMB ((uint32_t)RTC_CR_OSEL_1) #define RTC_OUTPUT_WAKEUP ((uint32_t)RTC_CR_OSEL) -#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP)) +#define IS_RTC_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_OUTPUT_DISABLE) || \ + ((__OUTPUT__) == RTC_OUTPUT_ALARMA) || \ + ((__OUTPUT__) == RTC_OUTPUT_ALARMB) || \ + ((__OUTPUT__) == RTC_OUTPUT_WAKEUP)) /** * @} */ -/** @defgroup RTC_Output_Polarity_Definitions +/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions * @{ */ #define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000) -#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000) +#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)RTC_CR_POL) -#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \ - ((POL) == RTC_OUTPUT_POLARITY_LOW)) +#define IS_RTC_OUTPUT_POL(__POL__) (((__POL__) == RTC_OUTPUT_POLARITY_HIGH) || \ + ((__POL__) == RTC_OUTPUT_POLARITY_LOW)) /** * @} */ -/** @defgroup RTC_Output_Type_ALARM_OUT +/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT * @{ */ #define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000) #define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMOUTTYPE) -#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ - ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL)) +#define IS_RTC_OUTPUT_TYPE(__TYPE__) (((__TYPE__) == RTC_OUTPUT_TYPE_OPENDRAIN) || \ + ((__TYPE__) == RTC_OUTPUT_TYPE_PUSHPULL)) /** * @} */ -/** @defgroup RTC_Output_ALARM_OUT_Remap +/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap * @{ */ -#define RTC_OUTPUT_REMAP_PC13 ((uint32_t)0x00000000) -#define RTC_OUTPUT_REMAP_PB14 ((uint32_t)RTC_OR_RTC_OUT_RMP) -#define IS_RTC_OUTPUT_REMAP(REMAP) (((REMAP) == RTC_OUTPUT_REMAP_PC13) || \ - ((REMAP) == RTC_OUTPUT_REMAP_PB14)) +#define RTC_OUTPUT_REMAP_PC13 ((uint32_t)0x00000000) +#define RTC_OUTPUT_REMAP_PB14 ((uint32_t)RTC_OR_OUT_RMP) +#define IS_RTC_OUTPUT_REMAP(__REMAP__) (((__REMAP__) == RTC_OUTPUT_REMAP_PC13) || \ + ((__REMAP__) == RTC_OUTPUT_REMAP_PB14)) /** * @} */ -/** @defgroup RTC_Asynchronous_Predivider +/** @defgroup RTC_Asynchronous_Predivider RTC Asynchronous Predivider * @{ */ -#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7F) +#define IS_RTC_ASYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)0x7F) /** * @} */ -/** @defgroup RTC_Synchronous_Predivider +/** @defgroup RTC_Synchronous_Predivider RTC Synchronous Predivider * @{ */ -#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= (uint32_t)0x7FFF) +#define IS_RTC_SYNCH_PREDIV(__PREDIV__) ((__PREDIV__) <= (uint32_t)RTC_PRER_PREDIV_S) /** * @} */ -/** @defgroup RTC_Time_Definitions +/** @defgroup RTC_Time_Definitions RTC Time Definitions * @{ */ -#define IS_RTC_HOUR12(HOUR) (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12)) -#define IS_RTC_HOUR24(HOUR) ((HOUR) <= (uint32_t)23) -#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= (uint32_t)59) -#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= (uint32_t)59) +#define IS_RTC_HOUR12(__HOUR__) (((__HOUR__) > (uint32_t)0) && ((__HOUR__) <= (uint32_t)12)) +#define IS_RTC_HOUR24(__HOUR__) ((__HOUR__) <= (uint32_t)23) +#define IS_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= (uint32_t)59) +#define IS_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= (uint32_t)59) /** * @} */ -/** @defgroup RTC_AM_PM_Definitions +/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions * @{ */ #define RTC_HOURFORMAT12_AM ((uint8_t)0x00) #define RTC_HOURFORMAT12_PM ((uint8_t)0x40) -#define IS_RTC_HOURFORMAT12(PM) (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM)) +#define IS_RTC_HOURFORMAT12(__PM__) (((__PM__) == RTC_HOURFORMAT12_AM) || \ + ((__PM__) == RTC_HOURFORMAT12_PM)) /** * @} */ -/** @defgroup RTC_DayLightSaving_Definitions +/** @defgroup RTC_DayLightSaving_Definitions RTC DayLightSaving Definitions * @{ */ -#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000) -#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000) +#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)RTC_CR_SUB1H) +#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)RTC_CR_ADD1H) #define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000) -#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \ - ((SAVE) == RTC_DAYLIGHTSAVING_NONE)) +#define IS_RTC_DAYLIGHT_SAVING(__SAVE__) (((__SAVE__) == RTC_DAYLIGHTSAVING_SUB1H) || \ + ((__SAVE__) == RTC_DAYLIGHTSAVING_ADD1H) || \ + ((__SAVE__) == RTC_DAYLIGHTSAVING_NONE)) /** * @} */ -/** @defgroup RTC_StoreOperation_Definitions +/** @defgroup RTC_StoreOperation_Definitions RTC StoreOperation Definitions * @{ */ #define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000) -#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000) +#define RTC_STOREOPERATION_SET ((uint32_t)RTC_CR_BCK) -#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \ - ((OPERATION) == RTC_STOREOPERATION_SET)) +#define IS_RTC_STORE_OPERATION(__OPERATION__) (((__OPERATION__) == RTC_STOREOPERATION_RESET) || \ + ((__OPERATION__) == RTC_STOREOPERATION_SET)) /** * @} */ -/** @defgroup RTC_Input_parameter_format_definitions + +/** @defgroup RTC_Input_parameter_format_definitions RTC Input parameter format definitions * @{ */ -#define FORMAT_BIN ((uint32_t)0x000000000) -#define FORMAT_BCD ((uint32_t)0x000000001) +#define RTC_FORMAT_BIN ((uint32_t)0x000000000) +#define RTC_FORMAT_BCD ((uint32_t)0x000000001) + +#define IS_RTC_FORMAT(__FORMAT__) (((__FORMAT__) == RTC_FORMAT_BIN) || ((__FORMAT__) == RTC_FORMAT_BCD)) -#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD)) /** * @} */ -/** @defgroup RTC_Year_Date_Definitions +/** @defgroup RTC_Year_Date_Definitions RTC Year Date Definitions * @{ */ -#define IS_RTC_YEAR(YEAR) ((YEAR) <= (uint32_t)99) +#define IS_RTC_YEAR(__YEAR__) ((__YEAR__) <= (uint32_t)99) /** * @} */ -/** @defgroup RTC_Month_Date_Definitions +/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions * @{ */ @@ -354,13 +384,13 @@ typedef struct #define RTC_MONTH_NOVEMBER ((uint8_t)0x11) #define RTC_MONTH_DECEMBER ((uint8_t)0x12) -#define IS_RTC_MONTH(MONTH) (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12)) -#define IS_RTC_DATE(DATE) (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31)) +#define IS_RTC_MONTH(__MONTH__) (((__MONTH__) >= (uint32_t)1) && ((__MONTH__) <= (uint32_t)12)) +#define IS_RTC_DATE(__DATE__) (((__DATE__) >= (uint32_t)1) && ((__DATE__) <= (uint32_t)31)) /** * @} */ -/** @defgroup RTC_WeekDay_Definitions +/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions * @{ */ #define RTC_WEEKDAY_MONDAY ((uint8_t)0x01) @@ -371,144 +401,146 @@ typedef struct #define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06) #define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07) -#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +#define IS_RTC_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) /** * @} */ -/** @defgroup RTC_Alarm_Definitions +/** @defgroup RTC_Alarm_Definitions RTC Alarm Definitions * @{ */ -#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31)) -#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_TUESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_THURSDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_FRIDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SATURDAY) || \ - ((WEEKDAY) == RTC_WEEKDAY_SUNDAY)) +#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(__DATE__) (((__DATE__) >(uint32_t) 0) && ((__DATE__) <= (uint32_t)31)) +#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(__WEEKDAY__) (((__WEEKDAY__) == RTC_WEEKDAY_MONDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_TUESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_WEDNESDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_THURSDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_FRIDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SATURDAY) || \ + ((__WEEKDAY__) == RTC_WEEKDAY_SUNDAY)) /** * @} */ - -/** @defgroup RTC_AlarmDateWeekDay_Definitions +/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC AlarmDateWeekDay Definitions * @{ */ #define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000) -#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000) +#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL -#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ - ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) +#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(__SEL__) (((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \ + ((__SEL__) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY)) /** * @} */ - -/** @defgroup RTC_AlarmMask_Definitions +/** @defgroup RTC_AlarmMask_Definitions RTC AlarmMask Definitions * @{ */ -#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) -#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 -#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 -#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 -#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 -#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080) +#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000) +#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4 +#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3 +#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2 +#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1 +#define RTC_ALARMMASK_ALL ((uint32_t) (RTC_ALARMMASK_NONE | \ + RTC_ALARMMASK_DATEWEEKDAY | \ + RTC_ALARMMASK_HOURS | \ + RTC_ALARMMASK_MINUTES | \ + RTC_ALARMMASK_SECONDS)) -#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET) +#define IS_RTC_ALARM_MASK(__MASK__) (((__MASK__) & ~(RTC_ALARMMASK_ALL)) == (uint32_t)RESET) /** * @} */ -/** @defgroup RTC_Alarms_Definitions +/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions * @{ */ #define RTC_ALARM_A RTC_CR_ALRAE #define RTC_ALARM_B RTC_CR_ALRBE -#define IS_ALARM(ALARM) (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B)) +#define IS_RTC_ALARM(__ALARM__) (((__ALARM__) == RTC_ALARM_A) || ((__ALARM__) == RTC_ALARM_B)) /** * @} */ -/** @defgroup RTC_Alarm_Sub_Seconds_Value +/** @defgroup RTC_Alarm_Sub_Seconds_Value RTC Alarm Sub Seconds Value * @{ */ -#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF) +#define IS_RTC_ALARM_SUB_SECOND_VALUE(__VALUE__) ((__VALUE__) <= RTC_ALRMASSR_SS) /** * @} */ - /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions + /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions * @{ */ -#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. - There is no comparison on sub seconds - for Alarm */ -#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm - comparison. Only SS[0] is compared. */ -#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm - comparison. Only SS[1:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm - comparison. Only SS[2:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm - comparison. Only SS[3:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm - comparison. Only SS[4:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm - comparison. Only SS[5:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm - comparison. Only SS[6:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm - comparison. Only SS[7:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm - comparison. Only SS[8:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm - comparison. Only SS[9:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm - comparison. Only SS[10:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm - comparison.Only SS[11:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm - comparison. Only SS[12:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm - comparison.Only SS[13:0] are compared */ -#define RTC_ALARMSUBSECONDMASK_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match - to activate alarm. */ - -#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \ - ((MASK) == RTC_ALARMSUBSECONDMASK_None)) +#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. + There is no comparison on sub seconds + for Alarm */ +#define RTC_ALARMSUBSECONDMASK_SS14_1 RTC_ALRMASSR_MASKSS_0 /*!< SS[14:1] are don't care in Alarm + comparison. Only SS[0] is compared. */ +#define RTC_ALARMSUBSECONDMASK_SS14_2 RTC_ALRMASSR_MASKSS_1 /*!< SS[14:2] are don't care in Alarm + comparison. Only SS[1:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)) /*!< SS[14:3] are don't care in Alarm + comparison. Only SS[2:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_4 RTC_ALRMASSR_MASKSS_2 /*!< SS[14:4] are don't care in Alarm + comparison. Only SS[3:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:5] are don't care in Alarm + comparison. Only SS[4:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:6] are don't care in Alarm + comparison. Only SS[5:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)) /*!< SS[14:7] are don't care in Alarm + ` comparison. Only SS[6:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_8 RTC_ALRMASSR_MASKSS_3 /*!< SS[14:8] are don't care in Alarm + comparison. Only SS[7:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:9] are don't care in Alarm + comparison. Only SS[8:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:10] are don't care in Alarm + comparison. Only SS[9:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:11] are don't care in Alarm + comparison. Only SS[10:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t) (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:12] are don't care in Alarm + comparison.Only SS[11:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t) (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14:13] are don't care in Alarm + comparison. Only SS[12:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t) (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)) /*!< SS[14] is don't care in Alarm + comparison.Only SS[13:0] are compared */ +#define RTC_ALARMSUBSECONDMASK_NONE RTC_ALRMASSR_MASKSS /*!< SS[14:0] are compared and must match + to activate alarm. */ + +#define IS_RTC_ALARM_SUB_SECOND_MASK(__MASK__) (((__MASK__) == RTC_ALARMSUBSECONDMASK_ALL) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_1) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_2) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_3) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_4) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_5) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_6) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_7) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_8) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_9) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_10) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_11) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_12) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14_13) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_SS14) || \ + ((__MASK__) == RTC_ALARMSUBSECONDMASK_NONE)) /** * @} */ -/** @defgroup RTC_Interrupts_Definitions +/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions * @{ */ #define RTC_IT_TS ((uint32_t)RTC_CR_TSIE) #define RTC_IT_WUT ((uint32_t)RTC_CR_WUTIE) -#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) #define RTC_IT_ALRB ((uint32_t)RTC_CR_ALRBIE) +#define RTC_IT_ALRA ((uint32_t)RTC_CR_ALRAIE) #define RTC_IT_TAMP ((uint32_t)RTC_TAMPCR_TAMPIE) /* Used only to Enable the Tamper Interrupt */ #define RTC_IT_TAMP1 ((uint32_t)RTC_TAMPCR_TAMP1IE) #define RTC_IT_TAMP2 ((uint32_t)RTC_TAMPCR_TAMP2IE) @@ -516,7 +548,7 @@ typedef struct * @} */ -/** @defgroup RTC_Flags_Definitions +/** @defgroup RTC_Flags_Definitions RTC Flags Definitions * @{ */ #define RTC_FLAG_RECALPF ((uint32_t)RTC_ISR_RECALPF) @@ -527,6 +559,7 @@ typedef struct #define RTC_FLAG_WUTF ((uint32_t)RTC_ISR_WUTF) #define RTC_FLAG_ALRBF ((uint32_t)RTC_ISR_ALRBF) #define RTC_FLAG_ALRAF ((uint32_t)RTC_ISR_ALRAF) +#define RTC_FLAG_INIT ((uint32_t)RTC_ISR_INIT) #define RTC_FLAG_INITF ((uint32_t)RTC_ISR_INITF) #define RTC_FLAG_RSF ((uint32_t)RTC_ISR_RSF) #define RTC_FLAG_INITS ((uint32_t)RTC_ISR_INITS) @@ -542,10 +575,13 @@ typedef struct * @} */ -/* Exported macro ------------------------------------------------------------*/ +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup RTC_Exported_Macros RTC Exported Macros + * @{ + */ /** @brief Reset RTC handle state - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__: RTC handle. * @retval None */ #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) @@ -576,28 +612,28 @@ typedef struct * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) /** * @brief Disable the RTC ALARMA peripheral. * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) /** * @brief Enable the RTC ALARMB peripheral. * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) /** * @brief Disable the RTC ALARMB peripheral. * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) /** * @brief Enable the RTC Alarm interrupt. @@ -608,7 +644,7 @@ typedef struct * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** * @brief Disable the RTC Alarm interrupt. @@ -619,23 +655,23 @@ typedef struct * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__) ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((((__HANDLE__)->Instance->ISR)& ((__INTERRUPT__)>> 4)) & RTC_FLAGS_MASK) != RESET)? SET : RESET) /** * @brief Get the selected RTC Alarm's flag status. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __FLAG__: specifies the RTC Alarm Flag sources to check. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -643,110 +679,190 @@ typedef struct * @arg RTC_FLAG_ALRBWF * @retval None */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET) /** * @brief Clear the RTC Alarm's pending flags. * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& RTC_FLAGS_MASK) | ((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */ +#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)EXTI_IMR_IM19) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ +#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_IM20) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ -#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)0x00020000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ -#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */ -#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the RTC Wakeup event */ +/** + * @brief Enable interrupt on the RTC Alarm associated Exti line. + * @retval None + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Enable the RTC Exti line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT + * @brief Disable interrupt on the RTC Alarm associated Exti line. * @retval None */ -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__) (EXTI->IMR |= (__EXTILINE__)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) -/* alias define maintained for legacy */ -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT +/** + * @brief Enable event on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Disable the RTC Exti line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None + * @brief Disable event on the RTC Alarm associated Exti line. + * @retval None. */ -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__) (EXTI->IMR &= ~(__EXTILINE__)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) -/* alias define maintained for legacy */ -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT +/** + * @brief Enable falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_ALARM_EVENT) /** - * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None + * @brief Disable falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. */ -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) /** - * @brief Clear the RTC Exti flags. - * @param __FLAG__: specifies the RTC Exti sources to be enabled or disabled. - * This parameter can be: - * @arg RTC_EXTI_LINE_ALARM_EVENT - * @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT - * @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT - * @retval None + * @brief Enable rising edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_ALARM_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC Alarm associated Exti line. + * @retval None. */ -#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__) (EXTI->PR = (__FLAG__)) +#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); -/* alias define maintained for legacy */ -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG +/** + * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_ALARM_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_ALARM_EVENT) -/* Include RTC HAL Extension module */ +/** + * @brief Clear the RTC Alarm associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Generate a Software interrupt on RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) + +/** + * @brief Generate a Software interrupt on RTC Alarm associated Exti line. + * @retval None. + */ +#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_ALARM_EVENT) + + +/** + * @} + */ + +/* Include RTC HAL Extended module */ #include "stm32l0xx_hal_rtc_ex.h" /* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_Exported_Functions RTC Exported Functions + * @{ + */ +/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ /* Initialization and de-initialization functions ****************************/ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc); void HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc); void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); +/** + * @} + */ +/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions + * @{ + */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +/** + * @} + */ +/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions + * @{ + */ +/* RTC Alarm functions ********************************************************/ HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ -/* Peripheral State functions ***************************************************/ +/** @defgroup RTC_Exported_Functions_Group4 Peripheral Control functions + * @{ + */ +/* Peripheral Control functions ***********************************************/ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc); -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); -void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); +/** + * @} + */ +/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions + * @{ + */ /* Peripheral State functions *************************************************/ +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup RTC_Private_Functions RTC Private Functions + * @{ + */ HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc); uint8_t RTC_ByteToBcd2(uint8_t Value); uint8_t RTC_Bcd2ToByte(uint8_t Value); +/** + * @} + */ /** * @} @@ -763,3 +879,4 @@ uint8_t RTC_Bcd2ToByte(uint8_t Value); #endif /* __STM32L0xx_HAL_RTC_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.c index f776a79d780..4066be268cc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.c @@ -2,17 +2,17 @@ ****************************************************************************** * @file stm32l0xx_hal_rtc_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Extended RTC HAL module driver. * * This file provides firmware functions to manage the following - * functionalities of the Real Time Clock (RTC) Extension peripheral: + * functionalities of the Real Time Clock (RTC) Extended peripheral: * + RTC Time Stamp functions * + RTC Tamper functions * + RTC Wake-up functions - * + Extension Control functions - * + Extension RTC features functions + * + Extended Control functions + * + Extended RTC features functions * @verbatim ============================================================================== @@ -37,7 +37,7 @@ is protected against possible unwanted write accesses. [..] To enable access to the RTC Domain and RTC registers, proceed as follows: (+) Enable the Power Controller (PWR) APB1 interface clock using the - __PWR_CLK_ENABLE() function. + __HAL_RCC_PWR_CLK_ENABLE() function. (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function. (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function. @@ -67,10 +67,10 @@ *** RTC Wakeup configuration *** ================================ [..] - (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTC_SetWakeUpTimer() - function. You can also configure the RTC Wakeup timer in interrupt mode - using the HAL_RTC_SetWakeUpTimer_IT() function. - (+) To read the RTC WakeUp Counter register, use the HAL_RTC_GetWakeUpTimer() + (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer() + function. You can also configure the RTC Wakeup timer with interrupt mode + using the HAL_RTCEx_SetWakeUpTimer_IT() function. + (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer() function. *** Outputs configuration *** @@ -143,7 +143,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -177,8 +177,8 @@ * @{ */ -/** @defgroup RTCEx - * @brief RTC HAL module driver +/** @addtogroup RTCEx + * @brief RTC Extended HAL module driver * @{ */ @@ -186,34 +186,26 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -/* Masks Definition */ -#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F) -#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F) -#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF) -#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F) -#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ - RTC_FLAG_ALRBF | RTC_FLAG_INITF | RTC_FLAG_RSF | \ - RTC_FLAG_INITS | RTC_FLAG_WUTWF | RTC_FLAG_ALRBWF | \ - RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | \ - RTC_FLAG_RECALPF | RTC_FLAG_SHPF)) - -#define RTC_TIMEOUT_VALUE 1000 /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ -/** @defgroup RTCEx_Private_Functions +/** @addtogroup RTCEx_Exported_Functions * @{ */ -/** @defgroup RTCEx_Group1 RTC TimeStamp and Tamper functions + +/** @addtogroup RTCEx_Exported_Functions_Group1 * @brief RTC TimeStamp and Tamper functions * @verbatim =============================================================================== ##### RTC TimeStamp and Tamper functions ##### =============================================================================== + + [..] This section provide functions allowing to configure TimeStamp feature + @endverbatim * @{ */ @@ -221,8 +213,7 @@ /** * @brief Sets TimeStamp. * @note This API must be called before enabling the TimeStamp feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is * activated. * This parameter can be one of the following values: @@ -277,8 +268,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeS /** * @brief Sets TimeStamp with Interrupt. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @note This API must be called before enabling the TimeStamp feature. * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is * activated. @@ -324,9 +314,9 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS); /* RTC timestamp Interrupt Configuration: EXTI configuration */ - __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -341,8 +331,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti /** * @brief Deactivates TimeStamp. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) @@ -377,16 +366,18 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc) return HAL_OK; } + /** * @brief Gets the RTC TimeStamp value. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle + * @param sTimeStamp: Pointer to Time structure * @param sTimeStampDate: Pointer to Date structure * @param Format: specifies the format of the entered parameters. * This parameter can be one of the following values: - * FORMAT_BIN: Binary data format - * FORMAT_BCD: BCD data format + * RTC_FORMAT_BIN: Binary data format + * RTC_FORMAT_BCD +: BCD data format * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format) @@ -414,7 +405,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13); /* Check the input parameters format */ - if(Format == FORMAT_BIN) + if(Format == RTC_FORMAT_BIN) { /* Convert the TimeStamp structure parameters to Binary format */ sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours); @@ -436,8 +427,7 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe /** * @brief Sets Tamper * @note By calling this API we disable the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sTamper: Pointer to Tamper Structure. * @retval HAL status */ @@ -446,15 +436,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef uint32_t tmpreg = 0; /* Check the parameters */ - assert_param(IS_TAMPER(sTamper->Tamper)); - assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + assert_param( IS_RTC_TAMPER(sTamper->Tamper)); + assert_param( IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -467,35 +457,86 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); } - if(sTamper->NoErase == RTC_TAMPERERASEBACKUP_ENABLED) - { - /* Configure the RTC_TAMPCR register */ - sTamper->NoErase = RTC_TAMPERERASEBACKUP_ENABLED; - } - else + if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) { - sTamper->NoErase = (uint32_t)(sTamper->Tamper << 17); - } + sTamper->NoErase = 0; + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + } + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + } +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ +defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) - if(sTamper->MaskFlag == RTC_MASKTAMPERFLAG_DISABLED) - { - /* Configure the RTC_TAMPCR register */ - sTamper->MaskFlag = RTC_MASKTAMPERFLAG_DISABLED; + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + } + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || +* (STM32L073xx) || (STM32L072xx) || (STM32L071xx) +*/ } - else + + if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { - sTamper->MaskFlag = (uint32_t)(sTamper->Tamper << 18); + sTamper->MaskFlag = 0; + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + } + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + } +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + } +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || +* (STM32L073xx) || (STM32L072xx) || (STM32L071xx) +*/ } - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ + /* Configure the RTC_TAMPCR register */ + tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); - - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\ - (uint32_t)RTC_TAMPCR_TAMP2IE); - + (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection); + + +#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) + + hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ + RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\ + RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP2NOERASE|\ + RTC_TAMPCR_TAMP1MF | RTC_TAMPCR_TAMP2MF)); + +#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) + */ + +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + + hrtc->Instance->TAMPCR &= ((uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ + RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\ + RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1NOERASE |\ + RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE | RTC_TAMPCR_TAMP1MF |\ + RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF)); + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ + hrtc->Instance->TAMPCR |= tmpreg; hrtc->State = HAL_RTC_STATE_READY; @@ -509,8 +550,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef /** * @brief Sets Tamper with interrupt. * @note By calling this API we force the tamper interrupt for all tampers. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param sTamper: Pointer to RTC Tamper. * @retval HAL status */ @@ -519,16 +559,16 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType uint32_t tmpreg = 0; /* Check the parameters */ - assert_param(IS_TAMPER(sTamper->Tamper)); - assert_param(IS_TAMPER_INTERRUPT(sTamper->Interrupt)); - assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger)); - assert_param(IS_TAMPER_ERASE_MODE(sTamper->NoErase)); - assert_param(IS_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); - assert_param(IS_TAMPER_FILTER(sTamper->Filter)); - assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); - assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); - assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); - assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); + assert_param( IS_RTC_TAMPER(sTamper->Tamper)); + assert_param(IS_RTC_TAMPER_INTERRUPT(sTamper->Interrupt)); + assert_param( IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); + assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); + assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); + assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); + assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency)); + assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration)); + assert_param(IS_RTC_TAMPER_PULLUP_STATE(sTamper->TamperPullUp)); + assert_param(IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -541,41 +581,90 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1); } - if(sTamper->NoErase == RTC_TAMPERERASEBACKUP_ENABLED) - { - /* Configure the RTC_TAMPCR register */ - sTamper->NoErase = RTC_TAMPERERASEBACKUP_ENABLED; - } - else - { - sTamper->NoErase = (uint32_t)(sTamper->Tamper << 17); - } - - if(sTamper->MaskFlag == RTC_MASKTAMPERFLAG_DISABLED) - { - /* Configure the RTC_TAMPCR register */ - sTamper->MaskFlag = RTC_MASKTAMPERFLAG_DISABLED; + if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE) + { + sTamper->NoErase = 0; + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE; + } + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE; + } +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ +defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE; + } +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || +* (STM32L073xx) || (STM32L072xx) || (STM32L071xx) +*/ } - else + + if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE) { - sTamper->MaskFlag = (uint32_t)(sTamper->Tamper << 18); + sTamper->MaskFlag = 0; + if((sTamper->Tamper & RTC_TAMPER_1) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF; + } + if((sTamper->Tamper & RTC_TAMPER_2) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF; + } +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ +defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + + if((sTamper->Tamper & RTC_TAMPER_3) != 0) + { + sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF; + } +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || +* (STM32L073xx) || (STM32L072xx) || (STM32L071xx) +*/ } - tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ - (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ - (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection); + /* Configure the RTC_TAMPCR register */ + tmpreg = (uint32_t)((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Interrupt | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->NoErase |\ + (uint32_t)sTamper->MaskFlag | (uint32_t)sTamper->Filter | (uint32_t)sTamper->SamplingFrequency |\ + (uint32_t)sTamper->PrechargeDuration | (uint32_t)sTamper->TamperPullUp | (uint32_t)sTamper->TimeStampOnTamperDetection); - hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAMPCR_TAMPTS |\ - (uint32_t)RTC_TAMPCR_TAMPFREQ | (uint32_t)RTC_TAMPCR_TAMPFLT | (uint32_t)RTC_TAMPCR_TAMPPRCH |\ - (uint32_t)RTC_TAMPCR_TAMPPUDIS | (uint32_t)RTC_TAMPCR_TAMPIE | (uint32_t)RTC_TAMPCR_TAMP1IE |\ - (uint32_t)RTC_TAMPCR_TAMP2IE); + +#if defined (STM32L063xx) || defined (STM32L062xx) || defined (STM32L061xx) || \ + defined (STM32L053xx) || defined (STM32L052xx) || defined (STM32L051xx) + + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ + RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\ + RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP1NOERASE | RTC_TAMPCR_TAMP2NOERASE |\ + RTC_TAMPCR_TAMP1MF | RTC_TAMPCR_TAMP2MF); + +#endif /* (STM32L063xx) || (STM32L062xx) || (STM32L061xx) || + * (STM32L053xx) || (STM32L052xx) || (STM32L051xx) + */ +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + + hrtc->Instance->TAMPCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | RTC_TAMPCR_TAMPTS |\ + RTC_TAMPCR_TAMPFREQ | RTC_TAMPCR_TAMPFLT | RTC_TAMPCR_TAMPPRCH |\ + RTC_TAMPCR_TAMPPUDIS | RTC_TAMPCR_TAMPIE | RTC_TAMPCR_TAMP1IE |\ + RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP1NOERASE |\ + RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP3NOERASE | RTC_TAMPCR_TAMP1MF |\ + RTC_TAMPCR_TAMP2MF | RTC_TAMPCR_TAMP3MF); + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ hrtc->Instance->TAMPCR |= tmpreg; /* RTC Tamper Interrupt Configuration: EXTI configuration */ - __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT(); - EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT; + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE(); hrtc->State = HAL_RTC_STATE_READY; @@ -587,15 +676,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType /** * @brief Deactivates Tamper. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @param hrtc: RTC handle * @param Tamper: Selected tamper pin. - * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2. + * This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2 for NEMO. + * This parameter can be any combination of RTC_TAMPER_1, RTC_TAMPER_2 and RTC_TAMPER_3 for BIG NEMO. * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) { - assert_param(IS_TAMPER(Tamper)); + assert_param( IS_RTC_TAMPER(Tamper)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -603,19 +692,32 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the selected Tamper pin */ - hrtc->Instance->TAMPCR &= (uint32_t)~Tamper; + hrtc->Instance->TAMPCR &= ((uint32_t)~Tamper); - if (Tamper == RTC_TAMPER_1) + if ((Tamper & RTC_TAMPER_1) != 0) { /* Disable the Tamper1 interrupt */ - hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1); + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP1)); } - else + if ((Tamper & RTC_TAMPER_2) != 0) { /* Disable the Tamper2 interrupt */ - hrtc->Instance->TAMPCR &= (uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2); + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP2)); } +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + + if ((Tamper & RTC_TAMPER_3) != 0) + { + /* Disable the Tamper2 interrupt */ + hrtc->Instance->TAMPCR &= ((uint32_t)~(RTC_IT_TAMP | RTC_IT_TAMP3)); + } + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -625,289 +727,315 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T } /** - * @brief Sets wake up timer. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status + * @brief This function handles TimeStamp interrupt request. + * @param hrtc: RTC handle + * @retval None */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - tickstart = HAL_GetTick(); - - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS)) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* TIMESTAMP callback */ + HAL_RTCEx_TimeStampEventCallback(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Clear the TIMESTAMP interrupt pending bit */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); + } + } - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== SET) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ + (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP1IE)) != (uint32_t)RESET)) + { + /* Tamper callback */ + HAL_RTCEx_Tamper1EventCallback(hrtc); - return HAL_TIMEOUT; + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); } } - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F)== SET) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ + (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP2IE)) != (uint32_t)RESET)) + { + /* Tamper callback */ + HAL_RTCEx_Tamper2EventCallback(hrtc); - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); + } + } - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + + /* Get the status of the Interrupt */ + if(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP3F)== SET) + { + /* Get the TAMPER Interrupt enable bit and pending bit */ + if((((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) || \ + (((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMP3IE)) != (uint32_t)RESET)) + { + /* Tamper callback */ + HAL_RTCEx_Tamper3EventCallback(hrtc); - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); + /* Clear the Tamper interrupt pending bit */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F); + } + } + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ + __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG(); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; +} - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - - return HAL_OK; +/** + * @brief TimeStamp callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file + */ } /** - * @brief Sets wake up timer with interrupt - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param WakeUpCounter: Wake up counter - * @param WakeUpClock: Wake up clock - * @retval HAL status + * @brief Tamper 1 callback. + * @param hrtc: RTC handle + * @retval None */ -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) +__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart; + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file + */ +} - /* Check the parameters */ - assert_param(IS_WAKEUP_CLOCK(WakeUpClock)); - assert_param(IS_WAKEUP_COUNTER(WakeUpCounter)); +/** + * @brief Tamper 2 callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file + */ +} - /* Process Locked */ - __HAL_LOCK(hrtc); - hrtc->State = HAL_RTC_STATE_BUSY; +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +/** + * @brief Tamper 3 callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file + */ +} - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - tickstart = HAL_GetTick(); +/** + * @brief This function handles TimeStamp polling request. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Clear the TIMESTAMP OverRun Flag */ + __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Change TIMESTAMP state */ + hrtc->State = HAL_RTC_STATE_ERROR; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + return HAL_ERROR; + } - return HAL_TIMEOUT; + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } } } - /* Configure the Wakeup Timer counter */ - hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - - /* Clear the Wakeup Timer clock source bits in CR register */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - - /* Configure the clock source */ - hrtc->Instance->CR |= (uint32_t)WakeUpClock; - - /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ - __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); - - EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; - - /* Configure the Interrupt in the RTC_CR register */ - __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; - /* Enable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); - - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - hrtc->State = HAL_RTC_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - return HAL_OK; } /** - * @brief Deactivates wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief This function handles Tamper1 Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration * @retval HAL status */ -uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) { - uint32_t tickstart; - - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Disable the Wakeup Timer */ - __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - - /* In case of interrupt mode is used, the interrupt source must disabled */ - __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); + uint32_t tickstart = HAL_GetTick(); - tickstart = HAL_GetTick(); - /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + if(Timeout != HAL_MAX_DELAY) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } - hrtc->State = HAL_RTC_STATE_TIMEOUT; + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; +} - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); +/** + * @brief This function handles Tamper2 Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); - return HAL_TIMEOUT; + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } } } - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - return HAL_OK; } -/** - * @brief Gets wake up timer counter. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval Counter value - */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) -{ - /* Get the counter value */ - return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); -} +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + /** - * @brief Writes a data in a specified RTC Backup data register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @param Data: Data to be written in the specified RTC Backup data register. - * @retval None + * @brief This function handles Tamper3 Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) -{ - uint32_t tmp = 0; +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); + /* Get the status of the Interrupt */ + while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + return HAL_TIMEOUT; + } + } + } - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); + /* Clear the Tamper Flag */ + __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F); - /* Write the specified register */ - *(__IO uint32_t *)tmp = (uint32_t)Data; + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + return HAL_OK; } +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ /** - * @brief Reads data from the specified RTC Backup data Register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param BackupRegister: RTC Backup data Register number. - * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to - * specify the register. - * @retval Read value + * @} */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) -{ - uint32_t tmp = 0; + +/** @addtogroup RTCEx_Exported_Functions_Group2 + * @brief RTC Wake-up functions + * +@verbatim + =============================================================================== + ##### RTC Wake-up functions ##### + =============================================================================== - /* Check the parameters */ - assert_param(IS_RTC_BKP(BackupRegister)); + [..] This section provide functions allowing to configure Wake-up feature - tmp = (uint32_t)&(hrtc->Instance->BKP0R); - tmp += (BackupRegister * 4); - - /* Read the specified register */ - return (*(__IO uint32_t *)tmp); -} +@endverbatim + * @{ + */ /** - * @brief Sets the Smooth calibration parameters. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param SmoothCalibPeriod: Select the Smooth Calibration Period. - * This parameter can be can be one of the following values : - * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s. - * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s. - * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s. - * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. - * This parameter can be one of the following values: - * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses. - * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. - * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits. - * This parameter can be one any value from 0 to 0x000001FF. - * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses - * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field - * SmouthCalibMinusPulsesValue mut be equal to 0. + * @brief Sets wake up timer. + * @param hrtc: RTC handle + * @param WakeUpCounter: Wake up counter + * @param WakeUpClock: Wake up clock * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue) +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t tickstart; + uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); - assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); - assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue)); + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -917,38 +1045,43 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* check if a calibration is pending*/ - if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) - { - tickstart = HAL_GetTick(); + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* check if a calibration is pending*/ - while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; } } - /* Configure the Smooth calibration settings */ - hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue); + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; + + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; + + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -957,25 +1090,19 @@ HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t Smo } /** - * @brief Configures the Synchronization Shift Control Settings. - * @note When REFCKON is set, firmware must not write to Shift control register. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. - * This parameter can be one of the following values : - * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. - * @arg RTC_SHIFTADD1S_RESET: No effect. - * @param ShiftSubFS: Select the number of Second Fractions to substitute. - * This parameter can be one any value from 0 to 0x7FFF. + * @brief Sets wake up timer with interrupt + * @param hrtc: RTC handle + * @param WakeUpCounter: Wake up counter + * @param WakeUpClock: Wake up clock * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { - uint32_t tickstart; + uint32_t tickstart = 0; /* Check the parameters */ - assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); - assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); @@ -985,67 +1112,51 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - tickstart = HAL_GetTick(); + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Wait until the shift is completed*/ - while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + tickstart = HAL_GetTick(); + + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { - if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - hrtc->State = HAL_RTC_STATE_TIMEOUT; + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_TIMEOUT; - } + return HAL_TIMEOUT; } + } - /* Check if the reference clock detection is disabled */ - if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) - { - /* Configure the Shift settings */ - hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); + /* Configure the Wakeup Timer counter */ + hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; - /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ - if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) - { - if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Clear the Wakeup Timer clock source bits in CR register */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; - hrtc->State = HAL_RTC_STATE_ERROR; + /* Configure the clock source */ + hrtc->Instance->CR |= (uint32_t)WakeUpClock; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); - return HAL_ERROR; - } - } - } - else - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE(); - return HAL_ERROR; - } + /* Configure the Interrupt in the RTC_CR register */ + __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); + + /* Enable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1054,21 +1165,15 @@ HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t Sh } /** - * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param CalibOutput : Select the Calibration output Selection . - * This parameter can be one of the following values: - * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. - * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @brief Deactivates wake up timer counter. + * @param hrtc: RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) { - /* Check the parameters */ - assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); + uint32_t tickstart = 0; - /* Process Locked */ + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1076,18 +1181,33 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Clear flags before config */ - hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; + /* Disable the Wakeup Timer */ + __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); - /* Configure the RTC_CR register */ - hrtc->Instance->CR |= (uint32_t)CalibOutput; + /* In case of interrupt mode is used, the interrupt source must disabled */ + __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT); - __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); + tickstart = HAL_GetTick(); + /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_TIMEOUT; + } + } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ @@ -1097,128 +1217,232 @@ HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32 } /** - * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status + * @brief Gets wake up timer counter. + * @param hrtc: RTC handle + * @retval Counter value */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) { - /* Process Locked */ - __HAL_LOCK(hrtc); + /* Get the counter value */ + return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT)); +} - hrtc->State = HAL_RTC_STATE_BUSY; +/** + * @brief This function handles Wake Up Timer interrupt request. + * @param hrtc: RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT)) + { + /* Get the status of the Interrupt */ + if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) + { + /* WAKEUPTIMER callback */ + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); + + /* Clear the WAKEUPTIMER interrupt pending bit */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + } + } - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + /* Clear the EXTI's line Flag for RTC WakeUpTimer */ + __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG(); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; +} - __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); +/** + * @brief Wake Up Timer callback. + * @param hrtc: RTC handle + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +/** + * @brief This function handles Wake Up Timer Polling. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + return HAL_TIMEOUT; + } + } + } + + /* Clear the WAKEUPTIMER Flag */ + __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); - return HAL_OK; } /** - * @brief Enables the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval HAL status + * @} */ -HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); - - hrtc->State = HAL_RTC_STATE_BUSY; - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) - { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); +/** @addtogroup RTCEx_Exported_Functions_Group3 + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Extended Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides functions allowing to + (+) Writes a data in a specified RTC Backup data register + (+) Read a data in a specified RTC Backup data register + (+) Sets the Coarse calibration parameters. + (+) Deactivates the Coarse calibration parameters + (+) Sets the Smooth calibration parameters. + (+) Configures the Synchronization Shift Control Settings. + (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + (+) Enables the RTC reference clock detection. + (+) Disable the RTC reference clock detection. + (+) Enables the Bypass Shadow feature. + (+) Disables the Bypass Shadow feature. - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; +@endverbatim + * @{ + */ - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); +/** + * @brief Writes a data in a specified RTC Backup data register. + * @param hrtc: RTC handle + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @param Data: Data to be written in the specified RTC Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + uint32_t tmp = 0; - return HAL_ERROR; - } - else - { - __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } + tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp += (BackupRegister * 4); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; +} - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; +/** + * @brief Reads data from the specified RTC Backup data Register. + * @param hrtc: RTC handle + * @param BackupRegister: RTC Backup data Register number. + * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to + * specify the register. + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + uint32_t tmp = 0; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); - return HAL_OK; + tmp = (uint32_t)&(hrtc->Instance->BKP0R); + tmp += (BackupRegister * 4); + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); } /** - * @brief Disable the RTC reference clock detection. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. + * @brief Sets the Smooth calibration parameters. + * @param hrtc: RTC handle + * @param SmoothCalibPeriod: Select the Smooth Calibration Period. + * This parameter can be can be one of the following values : + * @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s. + * @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s. + * @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s. + * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit. + * This parameter can be one of the following values: + * @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses. + * @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added. + * @param SmoothCalibMinusPulsesValue: Select the value of CALM[8:0] bits. + * This parameter can be one any value from 0 to 0x000001FF. + * @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses + * must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field + * SmoothCalibMinusPulsesValue mut be equal to 0. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue) { - /* Process Locked */ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod)); + assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses)); + assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmoothCalibMinusPulsesValue)); + + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - - /* Set Initialization mode */ - if(RTC_EnterInitMode(hrtc) != HAL_OK) + + /* check if a calibration is pending*/ + if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) { - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + tickstart = HAL_GetTick(); - /* Set RTC state*/ - hrtc->State = HAL_RTC_STATE_ERROR; + /* check if a calibration is pending*/ + while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_TIMEOUT; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_ERROR; + return HAL_TIMEOUT; + } + } } - else - { - __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); - /* Exit Initialization mode */ - hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; - } + /* Configure the Smooth calibration settings */ + hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmoothCalibMinusPulsesValue); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); @@ -1227,16 +1451,26 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) } /** - * @brief Enables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. + * @brief Configures the Synchronization Shift Control Settings. + * @note When REFCKON is set, firmware must not write to Shift control register. + * @param hrtc: RTC handle + * @param ShiftAdd1S: Select to add or not 1 second to the time calendar. + * This parameter can be one of the following values : + * @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. + * @arg RTC_SHIFTADD1S_RESET: No effect. + * @param ShiftSubFS: Select the number of Second Fractions to substitute. + * This parameter can be one any value from 0 to 0x7FFF. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) +HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS) { - /* Process Locked */ + uint32_t tickstart = 0; + + /* Check the parameters */ + assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S)); + assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS)); + + /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; @@ -1244,41 +1478,61 @@ HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Set the BYPSHAD bit */ - hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + tickstart = HAL_GetTick(); - /* Enable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Wait until the shift is completed*/ + while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET) + { + if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; + hrtc->State = HAL_RTC_STATE_TIMEOUT; - /* Process Unlocked */ - __HAL_UNLOCK(hrtc); + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - return HAL_OK; -} + return HAL_TIMEOUT; + } + } -/** - * @brief Disables the Bypass Shadow feature. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @note When the Bypass Shadow is enabled the calendar value are taken - * directly from the Calendar counter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) -{ - /* Process Locked */ - __HAL_LOCK(hrtc); + /* Check if the reference clock detection is disabled */ + if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET) + { + /* Configure the Shift settings */ + hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S); - hrtc->State = HAL_RTC_STATE_BUSY; + /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */ + if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET) + { + if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Disable the write protection for RTC registers */ - __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + hrtc->State = HAL_RTC_STATE_ERROR; - /* Reset the BYPSHAD bit */ - hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD; + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } + } + } + else + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; + } /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); @@ -1293,325 +1547,295 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) } /** - * @brief This function handles TimeStamp interrupt request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None + * @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). + * @param hrtc: RTC handle + * @param CalibOutput : Select the Calibration output Selection . + * This parameter can be one of the following values: + * @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. + * @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz. + * @retval HAL status */ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET) - { - /* TIMESTAMP callback */ - HAL_RTCEx_TimeStampEventCallback(hrtc); +HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput) +{ + /* Check the parameters */ + assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput)); - /* Clear the TIMESTAMP interrupt pending bit */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF); - } - } + /* Process Locked */ + __HAL_LOCK(hrtc); - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1)) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if(((hrtc->Instance->TAMPCR & (RTC_TAMPCR_TAMPIE))) != (uint32_t)RESET) - { - /* Tamper callback */ - HAL_RTCEx_Tamper1EventCallback(hrtc); + hrtc->State = HAL_RTC_STATE_BUSY; - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); - } - } + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Get the status of the Interrupt */ - if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2)) - { - /* Get the TAMPER Interrupt enable bit and pending bit */ - if(((hrtc->Instance->TAMPCR & RTC_TAMPCR_TAMPIE)) != (uint32_t)RESET) - { - /* Tamper callback */ - HAL_RTCEx_Tamper2EventCallback(hrtc); + /* Clear flags before config */ + hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL; - /* Clear the Tamper interrupt pending bit */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F); - } - } - /* Clear the EXTI's Flag for RTC TimeStamp and Tamper */ - __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT); + /* Configure the RTC_CR register */ + hrtc->Instance->CR |= (uint32_t)CalibOutput; - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} + __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc); -/** - * @brief This function handles Wake Up Timer interrupt request. - * @param hrtc: RTC handle - * @retval None - */ -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) -{ - if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT)) - { - /* Get the status of the Interrupt */ - if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET) - { - /* WAKEUPTIMER callback */ - HAL_RTCEx_WakeUpTimerEventCallback(hrtc); - - /* Clear the WAKEUPTIMER interrupt pending bit */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - } - } + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Clear the EXTI's line Flag for RTC WakeUpTimer */ - __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT); - /* Change RTC state */ - hrtc->State = HAL_RTC_STATE_READY; -} - -/** - * @brief Alarm B callback. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @retval None - */ -__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_AlarmBEventCallback could be implemented in the user file - */ -} - -/** - * @brief TimeStamp callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_TimeStampEventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 1 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_Tamper1EventCallback could be implemented in the user file - */ -} - -/** - * @brief Tamper 2 callback. - * @param hrtc: RTC handle - * @retval None - */ -__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_Tamper2EventCallback could be implemented in the user file - */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; } /** - * @brief Wake Up Timer callback. + * @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz). * @param hrtc: RTC handle - * @retval None + * @retval HAL status */ -__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_RTC_WakeUpTimerEventCallback could be implemented in the user file - */ + /* Process Locked */ + __HAL_LOCK(hrtc); + + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; } /** - * @brief This function handles AlarmB Polling request. - * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains - * the configuration information for RTC. - * @param Timeout: Timeout duration + * @brief Enables the RTC reference clock detection. + * @param hrtc: RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart; +HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); - /* Get Timeout value */ - tickstart = HAL_GetTick(); - - while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) + hrtc->State = HAL_RTC_STATE_BUSY; + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_ERROR; } + else + { + __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc); - /* Clear the Alarm Flag */ - __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; + } - /* Change RTC state */ + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_OK; } /** - * @brief This function handles TimeStamp polling request. + * @brief Disable the RTC reference clock detection. * @param hrtc: RTC handle - * @param Timeout: Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) -{ - uint32_t tickstart; +HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc) +{ + /* Process Locked */ + __HAL_LOCK(hrtc); - /* Get Timeout value */ - tickstart = HAL_GetTick(); + hrtc->State = HAL_RTC_STATE_BUSY; - while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET) + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set Initialization mode */ + if(RTC_EnterInitMode(hrtc) != HAL_OK) { - if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET) - { - /* Clear the TIMESTAMP OverRun Flag */ - __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF); + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Change TIMESTAMP state */ - hrtc->State = HAL_RTC_STATE_ERROR; + /* Set RTC state*/ + hrtc->State = HAL_RTC_STATE_ERROR; - return HAL_ERROR; - } + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } + return HAL_ERROR; + } + else + { + __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc); + + /* Exit Initialization mode */ + hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; } + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_OK; } /** - * @brief This function handles Tamper1 Polling. + * @brief Enables the Bypass Shadow feature. * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart; + /* Process Locked */ + __HAL_LOCK(hrtc); - /* Get Timeout value */ - tickstart = HAL_GetTick(); + hrtc->State = HAL_RTC_STATE_BUSY; - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP1F)== RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + + /* Set the BYPSHAD bit */ + hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD; + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F); - /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; - - return HAL_OK; + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + + return HAL_OK; } /** - * @brief This function handles Tamper2 Polling. + * @brief Disables the Bypass Shadow feature. * @param hrtc: RTC handle - * @param Timeout: Timeout duration + * @note When the Bypass Shadow is enabled the calendar value are taken + * directly from the Calendar counter. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc) { - uint32_t tickstart; + /* Process Locked */ + __HAL_LOCK(hrtc); - /* Get Timeout value */ - tickstart = HAL_GetTick(); + hrtc->State = HAL_RTC_STATE_BUSY; - /* Get the status of the Interrupt */ - while(__HAL_RTC_TAMPER_GET_FLAG(hrtc, RTC_FLAG_TAMP2F) == RESET) - { - if(Timeout != HAL_MAX_DELAY) - { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) - { - hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; - } - } - } + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); - /* Clear the Tamper Flag */ - __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F); + /* Reset the BYPSHAD bit */ + hrtc->Instance->CR &= ((uint8_t)~RTC_CR_BYPSHAD); + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + return HAL_OK; } +/** + * @} + */ + +/** @addtogroup RTCEx_Exported_Functions_Group4 + * @brief Extended features functions + * +@verbatim + =============================================================================== + ##### Extended features functions ##### + =============================================================================== + [..] This section provides functions allowing to: + (+) RTC Alram B callback + (+) RTC Poll for Alarm B request + +@endverbatim + * @{ + */ /** - * @brief This function handles Wake Up Timer Polling. + * @brief Alarm B callback. * @param hrtc: RTC handle - * @param Timeout: Timeout duration - * @retval HAL status + * @retval None */ -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc) { - uint32_t tickstart; + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_RTC_AlarmBEventCallback could be implemented in the user file + */ +} - /* Get Timeout value */ - tickstart = HAL_GetTick(); - while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET) +/** + * @brief This function handles AlarmB Polling request. + * @param hrtc: RTC handle + * @param Timeout: Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout) +{ + uint32_t tickstart = HAL_GetTick(); + + while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET) { if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { hrtc->State = HAL_RTC_STATE_TIMEOUT; - return HAL_TIMEOUT; } } } - /* Clear the WAKEUPTIMER Flag */ - __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF); - + /* Clear the Alarm Flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF); + /* Change RTC state */ hrtc->State = HAL_RTC_STATE_READY; @@ -1636,3 +1860,4 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.h index 1951477179b..daaada07c1f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_rtc_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 - * @brief Header file of PWR HAL Extension module. + * @version V1.2.0 + * @date 06-February-2015 + * @brief Header file of RTC HAL Extended module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,12 +50,16 @@ * @{ */ -/** @addtogroup RTCEx +/** @defgroup RTCEx RTCEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ + +/** @defgroup RTCEx_Exported_Types RTC Extended Exported Types * @{ */ -/* Exported types ------------------------------------------------------------*/ - /** * @brief RTC Tamper structure definition */ @@ -86,18 +90,54 @@ typedef struct This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ uint32_t TamperPullUp; /*!< Specifies the Tamper PullUp . - This parameter can be a value of @ref RTCEx_Tamper_PullUP_Definitions */ + This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */ uint32_t TimeStampOnTamperDetection; /*!< Specifies the TimeStampOnTamperDetection. This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */ }RTC_TamperTypeDef; +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RTCEx_Exported_Constants +/** @defgroup RTCEx_Exported_Constants RTC Extended Exported Constants * @{ */ -/** @defgroup RTCEx_Backup_Registers_Definitions + +/** @defgroup RTCEx_Interrupts_Definitions RTC Extended Interrupts Definitions + * @{ + */ +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +#define RTC_IT_TAMP3 RTC_TAMPCR_TAMP3IE + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ +/** + * @} + */ + + +/** @defgroup RTCEx_Flags_Definitions RTC Extended Flags Definitions + * @{ + */ +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ + +/** + * @} + */ + +/** @defgroup RTCEx_Backup_Registers_Definitions RTC Extended Backup Registers Definition * @{ */ #define RTC_BKP_DR0 ((uint32_t)0x00000000) @@ -106,303 +146,355 @@ typedef struct #define RTC_BKP_DR3 ((uint32_t)0x00000003) #define RTC_BKP_DR4 ((uint32_t)0x00000004) -#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \ - ((BKP) == RTC_BKP_DR1) || \ - ((BKP) == RTC_BKP_DR2) || \ - ((BKP) == RTC_BKP_DR3) || \ - ((BKP) == RTC_BKP_DR4)) +#define IS_RTC_BKP(__BKP__) (((__BKP__) == RTC_BKP_DR0) || \ + ((__BKP__) == RTC_BKP_DR1) || \ + ((__BKP__) == RTC_BKP_DR2) || \ + ((__BKP__) == RTC_BKP_DR3) || \ + ((__BKP__) == RTC_BKP_DR4)) /** * @} */ + +/** @defgroup RTC_Mask_Definition RTC Mask Definition + * @{ + */ + +/* Masks Definition */ + +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \ + RTC_FLAG_TAMP1F| RTC_FLAG_TSOVF | RTC_FLAG_TSF | \ + RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \ + RTC_FLAG_INIT | RTC_FLAG_INITF | RTC_FLAG_RSF | \ + RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \ + RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF)) + +#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E)) + +#else + +#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP1F| \ + RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ + RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INIT | \ + RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS | \ + RTC_FLAG_SHPF | RTC_FLAG_WUTWF |RTC_FLAG_ALRBWF | \ + RTC_FLAG_ALRAWF)) + +#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E)) -/** @defgroup RTCEx_Time_Stamp_Edges_definitions +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ +/** + * @} + */ + +/** @defgroup RTCEx_Time_Stamp_Edges_definitions RTC Extended Time Stamp Edges definition * @{ */ -#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) -#define RTC_TIMESTAMPEDGE_FALLING ((uint32_t)0x00000008) +#define RTC_TIMESTAMPEDGE_RISING ((uint32_t)0x00000000) +#define RTC_TIMESTAMPEDGE_FALLING RTC_CR_TSEDGE -#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \ - ((EDGE) == RTC_TIMESTAMPEDGE_FALLING)) +#define IS_TIMESTAMP_EDGE(__EDGE__) (((__EDGE__) == RTC_TIMESTAMPEDGE_RISING) || \ + ((__EDGE__) == RTC_TIMESTAMPEDGE_FALLING)) /** * @} */ -/** @defgroup RTCEx_Tamper_Pins_Definitions +/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Extended Tamper Pins Definition * @{ */ + #define RTC_TAMPER_1 RTC_TAMPCR_TAMP1E #define RTC_TAMPER_2 RTC_TAMPCR_TAMP2E -#define IS_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFF6) == 0x00) && ((TAMPER) != (uint32_t)RESET)) +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +#define RTC_TAMPER_3 RTC_TAMPCR_TAMP3E + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ + +#define IS_RTC_TAMPER(__TAMPER__) ((((__TAMPER__) & ((uint32_t)(0xFFFFFFFF ^ RTC_TAMPCR_TAMPXE))) == 0x00) && ((__TAMPER__) != (uint32_t)RESET)) + /** * @} */ -/** @defgroup RTCEx_Tamper_Interrupt_Definitions + +/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Extended Tamper Interrupt Definitions * @{ */ + #define RTC_TAMPER1_INTERRUPT RTC_TAMPCR_TAMP1IE #define RTC_TAMPER2_INTERRUPT RTC_TAMPCR_TAMP2IE -#define RTC_TAMPER1_2_INTERRUPT RTC_TAMPCR_TAMPIE +#define RTC_ALL_TAMPER_INTERRUPT RTC_TAMPCR_TAMPIE + +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +#define RTC_TAMPER3_INTERRUPT RTC_TAMPCR_TAMP3IE +#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) (((__INTERRUPT__) == RTC_TAMPER1_INTERRUPT) || \ + ((__INTERRUPT__) == RTC_TAMPER2_INTERRUPT) || \ + ((__INTERRUPT__) == RTC_TAMPER3_INTERRUPT) || \ + ((__INTERRUPT__) == RTC_ALL_TAMPER_INTERRUPT )) + +#else + +#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__) (((__INTERRUPT__) == RTC_TAMPER1_INTERRUPT) || \ + ((__INTERRUPT__) == RTC_TAMPER2_INTERRUPT) || \ + ((__INTERRUPT__) == RTC_ALL_TAMPER_INTERRUPT )) + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ -#define IS_TAMPER_INTERRUPT(INTERRUPT) (((INTERRUPT) == RTC_TAMPER1_INTERRUPT) || \ - ((INTERRUPT) == RTC_TAMPER2_INTERRUPT) || \ - ((INTERRUPT) == RTC_TAMPER1_2_INTERRUPT)) /** * @} */ -/** @defgroup RTCEx_TimeStamp_Pin_Selection +/** @defgroup RTCEx_TimeStamp_Pin_Selections RTC Extended TimeStamp Pin Selection * @{ */ #define RTC_TIMESTAMPPIN_PC13 ((uint32_t)0x00000000) -#define IS_RTC_TIMESTAMP_PIN(PIN) ((PIN) == RTC_TIMESTAMPPIN_PC13) +#define IS_RTC_TIMESTAMP_PIN(__PIN__) (((__PIN__) == RTC_TIMESTAMPPIN_PC13)) /** * @} */ -/** @defgroup RTCEx_Tamper_Trigger_Definitions +/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Extended Tamper Trigger Definition * @{ */ #define RTC_TAMPERTRIGGER_RISINGEDGE ((uint32_t)0x00000000) -#define RTC_TAMPERTRIGGER_FALLINGEDGE ((uint32_t)0x00000002) +#define RTC_TAMPERTRIGGER_FALLINGEDGE RTC_TAMPCR_TAMP1TRG #define RTC_TAMPERTRIGGER_LOWLEVEL RTC_TAMPERTRIGGER_RISINGEDGE #define RTC_TAMPERTRIGGER_HIGHLEVEL RTC_TAMPERTRIGGER_FALLINGEDGE -#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ - ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) +#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL) || \ + ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL)) /** * @} */ -/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions +/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Extended Tamper EraseBackUp Definitions * @{ */ -#define RTC_TAMPERERASEBACKUP_ENABLED ((uint32_t)0x00000000) -#define RTC_TAMPERERASEBACKUP_DISABLED ((uint32_t)0x00020000) +#define RTC_TAMPER_ERASE_BACKUP_ENABLE ((uint32_t)0x00000000) +#define RTC_TAMPER_ERASE_BACKUP_DISABLE RTC_TAMPCR_TAMP1NOERASE -#define IS_TAMPER_ERASE_MODE(MODE) (((MODE) == RTC_TAMPERERASEBACKUP_ENABLED) || \ - ((MODE) == RTC_TAMPERERASEBACKUP_DISABLED)) +#define IS_RTC_TAMPER_ERASE_MODE(__MODE__) (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \ + ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE)) /** * @} */ -/** @defgroup RTCEx_Tamper_MaskFlag_Definitions +/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Extended Tamper MaskFlag Definitions * @{ */ -#define RTC_MASKTAMPERFLAG_DISABLED ((uint32_t)0x00000000) -#define RTC_MASKTAMPERFLAG_ENABLED ((uint32_t)0x00040000) +#define RTC_TAMPERMASK_FLAG_DISABLE ((uint32_t)0x00000000) +#define RTC_TAMPERMASK_FLAG_ENABLE RTC_TAMPCR_TAMP1MF -#define IS_TAMPER_MASKFLAG_STATE(STATE) (((STATE) == RTC_MASKTAMPERFLAG_ENABLED) || \ - ((STATE) == RTC_MASKTAMPERFLAG_DISABLED)) +#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__) (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE ) || \ + ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE)) /** * @} */ -/** @defgroup RTCEx_Tamper_Filter_Definitions +/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Extended Tamper Filter Definitions * @{ */ #define RTC_TAMPERFILTER_DISABLE ((uint32_t)0x00000000) /*!< Tamper filter is disabled */ -#define RTC_TAMPERFILTER_2SAMPLE ((uint32_t)0x00000800) /*!< Tamper is activated after 2 +#define RTC_TAMPERFILTER_2SAMPLE RTC_TAMPCR_TAMPFLT_0 /*!< Tamper is activated after 2 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_4SAMPLE ((uint32_t)0x00001000) /*!< Tamper is activated after 4 +#define RTC_TAMPERFILTER_4SAMPLE RTC_TAMPCR_TAMPFLT_1 /*!< Tamper is activated after 4 consecutive samples at the active level */ -#define RTC_TAMPERFILTER_8SAMPLE ((uint32_t)0x00001800) /*!< Tamper is activated after 8 +#define RTC_TAMPERFILTER_8SAMPLE RTC_TAMPCR_TAMPFLT /*!< Tamper is activated after 8 consecutive samples at the active leve. */ -#define IS_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \ - ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \ - ((FILTER) == RTC_TAMPERFILTER_8SAMPLE)) +#define IS_RTC_TAMPER_FILTER(__FILTER__) (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \ + ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE)) /** * @} */ -/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions - * @{ - */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 32768 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 16384 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 8192 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 4096 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 2048 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 1024 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 512 */ -#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled - with a frequency = RTCCLK / 256 */ - -#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ - ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) -/** - * @} - */ - -/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions +/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Extended Tamper Sampling Frequencies Definitions * @{ */ -#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before - sampling during 1 RTCCLK cycle */ -#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before - sampling during 2 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before - sampling during 4 RTCCLK cycles */ -#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before - sampling during 8 RTCCLK cycles */ - -#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ - ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 32768 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384 RTC_TAMPCR_TAMPFREQ_0 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 16384 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192 RTC_TAMPCR_TAMPFREQ_1 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 8192 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1)) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 4096 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048 RTC_TAMPCR_TAMPFREQ_2 /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 2048 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2)) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 1024 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2)) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 512 */ +#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 ((uint32_t) (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1 | \ + RTC_TAMPCR_TAMPFREQ_2)) /*!< Each of the tamper inputs are sampled + with a frequency = RTCCLK / 256 */ + +#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512) || \ + ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256)) /** * @} */ -/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions +/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Extended Tamper Pin Precharge Duration Definitions * @{ */ -#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE ((uint32_t)RTC_TAMPCR_TAMPTS) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before + sampling during 1 RTCCLK cycle */ +#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK RTC_TAMPCR_TAMPPRCH_0 /*!< Tamper pins are pre-charged before + sampling during 2 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK RTC_TAMPCR_TAMPPRCH_1 /*!< Tamper pins are pre-charged before + sampling during 4 RTCCLK cycles */ +#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)(RTC_TAMPCR_TAMPPRCH_0 | RTC_TAMPCR_TAMPPRCH_1)) /*!< Tamper pins are pre-charged before + sampling during 8 RTCCLK cycles */ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ - ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) +#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION_) (((__DURATION_) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \ + ((__DURATION_) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \ + ((__DURATION_) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \ + ((__DURATION_) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK)) /** * @} */ -/** @defgroup RTCEx_Tamper_PullUP_Definitions +/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Extended Tamper TimeStampOnTamperDetection Definitions * @{ */ -#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event saved */ -#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAMPCR_TAMPPUDIS) /*!< TimeStamp on Tamper Detection event is not saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE RTC_TAMPCR_TAMPTS /*!< TimeStamp on Tamper Detection event saved */ +#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000) /*!< TimeStamp on Tamper Detection event is not saved */ -#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \ - ((STATE) == RTC_TAMPER_PULLUP_DISABLE)) +#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \ + ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE)) /** * @} */ -/** @defgroup RTCEx_Wakeup_Timer_Definitions +/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Extended Tamper Pull UP Definitions * @{ */ -#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 ((uint32_t)0x00000001) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 ((uint32_t)0x00000002) -#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t)0x00000003) -#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS ((uint32_t)0x00000004) -#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t)0x00000006) +#define RTC_TAMPER_PULLUP_ENABLE ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before sampling */ +#define RTC_TAMPER_PULLUP_DISABLE RTC_TAMPCR_TAMPPUDIS /*!< Tamper pins pre-charge is disabled */ -#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ - ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) - -#define IS_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF) +#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \ + ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE)) /** * @} */ -/** @defgroup RTCEx_Digital_Calibration_Definitions +/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Extended Wakeup Timer Definitions * @{ */ -#define RTC_CALIBSIGN_POSITIVE ((uint32_t)0x00000000) -#define RTC_CALIBSIGN_NEGATIVE ((uint32_t)0x00000080) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV16 ((uint32_t)0x00000000) +#define RTC_WAKEUPCLOCK_RTCCLK_DIV8 RTC_CR_WUCKSEL_0 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV4 RTC_CR_WUCKSEL_1 +#define RTC_WAKEUPCLOCK_RTCCLK_DIV2 ((uint32_t) (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)) +#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS RTC_CR_WUCKSEL_2 +#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS ((uint32_t) (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)) -#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \ - ((SIGN) == RTC_CALIBSIGN_NEGATIVE)) +#define IS_RTC_WAKEUP_CLOCK(__CLOCK__) (((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV16) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV8) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV4) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_RTCCLK_DIV2) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \ + ((__CLOCK__) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS)) -#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20) +#define IS_RTC_WAKEUP_COUNTER(__COUNTER__) ((__COUNTER__) <= RTC_WUTR_WUT) /** * @} */ -/** @defgroup RTCEx_Smooth_calib_period_Definitions +/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Extended Smooth calib period Definitions * @{ */ #define RTC_SMOOTHCALIB_PERIOD_32SEC ((uint32_t)0x00000000) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 32s, else 2exp20 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_16SEC ((uint32_t)0x00002000) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 16s, else 2exp19 RTCCLK seconds */ -#define RTC_SMOOTHCALIB_PERIOD_8SEC ((uint32_t)0x00004000) /*!< If RTCCLK = 32768 Hz, Smooth calibation - period is 8s, else 2exp18 RTCCLK seconds */ + period is 32s, else 2exp20 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_16SEC RTC_CAL_CALW16 /*!< If RTCCLK = 32768 Hz, Smooth calibation + period is 16s, else 2exp19 RTCCLK pulses */ +#define RTC_SMOOTHCALIB_PERIOD_8SEC RTC_CAL_CALW8 /*!< If RTCCLK = 32768 Hz, Smooth calibation + period is 8s, else 2exp18 RTCCLK pulses */ -#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ - ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC)) +#define IS_RTC_SMOOTH_CALIB_PERIOD(__PERIOD__) (((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \ + ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \ + ((__PERIOD__) == RTC_SMOOTHCALIB_PERIOD_8SEC)) /** * @} */ -/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions +/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Extended Smooth calib Plus pulses Definitions * @{ */ -#define RTC_SMOOTHCALIB_PLUSPULSES_SET ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added +#define RTC_SMOOTHCALIB_PLUSPULSES_SET RTC_CAL_CALP /*!< The number of RTCCLK pulses added during a X -second window = Y - CALM[8:0] with Y = 512, 256, 128 when X = 32, 16, 8 */ #define RTC_SMOOTHCALIB_PLUSPULSES_RESET ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited during a 32-second window = CALM[8:0] */ -#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ - ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) +#define IS_RTC_SMOOTH_CALIB_PLUS(__PLUS__) (((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \ + ((__PLUS__) == RTC_SMOOTHCALIB_PLUSPULSES_RESET)) /** * @} */ -/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions +/** @defgroup RTCEx_Smooth_calib_Minus_pulses_Definitions RTC Extended Smooth calib Minus pulses Definitions * @{ */ -#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF) +#define IS_RTC_SMOOTH_CALIB_MINUS(__VALUE__) ((__VALUE__) <= RTC_CAL_CALM) /** * @} */ -/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions +/** @defgroup RTCEx_Add_1_Second_Parameter_Definition RTC Extended Add 1 Second Parameter Definitions * @{ */ #define RTC_SHIFTADD1S_RESET ((uint32_t)0x00000000) -#define RTC_SHIFTADD1S_SET ((uint32_t)0x80000000) +#define RTC_SHIFTADD1S_SET RTC_SHIFTR_ADD1S -#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \ - ((SEL) == RTC_SHIFTADD1S_SET)) +#define IS_RTC_SHIFT_ADD1S(__SEL__) (((__SEL__) == RTC_SHIFTADD1S_RESET) || \ + ((__SEL__) == RTC_SHIFTADD1S_SET)) /** * @} */ -/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value +/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value RTC Extended Substract Fraction Of Second Value * @{ */ -#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF) +#define IS_RTC_SHIFT_SUBFS(__FS__) ((__FS__) <= RTC_SHIFTR_SUBFS) /** * @} */ - /** @defgroup RTCEx_Calib_Output_selection_Definitions + /** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Extended Calib Output selection Definitions * @{ */ #define RTC_CALIBOUTPUT_512HZ ((uint32_t)0x00000000) -#define RTC_CALIBOUTPUT_1HZ ((uint32_t)0x00080000) +#define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL -#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \ - ((OUTPUT) == RTC_CALIBOUTPUT_1HZ)) +#define IS_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == RTC_CALIBOUTPUT_512HZ) || \ + ((__OUTPUT__) == RTC_CALIBOUTPUT_1HZ)) /** * @} */ @@ -412,9 +504,9 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup RTCEx_Exported macro - * @{ - */ +/** @defgroup RTCEx_Exported_Macros RTC Extended Exported Macros + * @{ + */ /** * @brief Enable the RTC WakeUp Timer peripheral. @@ -424,18 +516,18 @@ typedef struct #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** - * @brief Disable the RTC WakeUp Timer peripheral. + * @brief Enable the RTC TimeStamp peripheral. * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** - * @brief Enable the RTC TimeStamp peripheral. + * @brief Disable the RTC WakeUp Timer peripheral. * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** * @brief Disable the RTC TimeStamp peripheral. @@ -449,28 +541,28 @@ typedef struct * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) /** * @brief Disable the calibration output. * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) /** * @brief Enable the clock reference detection. * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) /** * @brief Disable the clock reference detection. * @param __HANDLE__: specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) /** * @brief Enable the RTC TimeStamp interrupt. @@ -483,24 +575,24 @@ typedef struct #define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** - * @brief Disable the RTC TimeStamp interrupt. + * @brief Enable the RTC WakeUpTimer interrupt. * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. * This parameter can be: - * @arg RTC_IT_TS: TimeStamp interrupt + * @arg RTC_IT_WUT: WakeUpTimer A interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) /** - * @brief Enable the RTC WakeUpTimer interrupt. + * @brief Disable the RTC TimeStamp interrupt. * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. * This parameter can be: - * @arg RTC_IT_WUT: WakeUpTimer A interrupt + * @arg RTC_IT_TS: TimeStamp interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** * @brief Disable the RTC WakeUpTimer interrupt. @@ -592,7 +684,7 @@ typedef struct * @arg RTC_FLAG_TSF * @retval None */ -#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& RTC_FLAGS_MASK)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) /** * @brief Clear the RTC Tamper's pending flags. @@ -602,7 +694,7 @@ typedef struct * @arg RTC_FLAG_TAMP1F * @retval None */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& RTC_FLAGS_MASK)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) /** * @brief Clear the RTC Wake Up timer's pending flags. @@ -612,13 +704,184 @@ typedef struct * @arg RTC_FLAG_WUTF * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) +#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& RTC_FLAGS_MASK)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) + +/* WAKE-UP TIMER EXTI */ +/* ------------------ */ +/** + * @brief Enable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable event on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable event on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the RTC WakeUp Timer associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line. + * @retval None. + */ +#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + + +/* TAMPER TIMESTAMP EXTI */ +/* --------------------- */ +/** + * @brief Enable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT() (EXTI->IMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable interrupt on the RTC Tamper and Timestamp associated Exti line. + * @retval None + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable event on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable event on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)) + +/** + * @brief Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); + +/** + * @brief Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line. + * This parameter can be: + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();__HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); + +/** + * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not. + * @retval Line Status. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() (EXTI->PR & RTC_EXTI_LINE_WAKEUPTIMER_EVENT) + +/** + * @brief Clear the RTC Tamper and Timestamp associated Exti line flag. + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG() (EXTI->PR = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + +/** + * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line + * @retval None. + */ +#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT) + /** * @} */ /* Exported functions --------------------------------------------------------*/ +/** @defgroup RTCEx_Exported_Functions RTC Extended Exported Functions + * @{ + */ + +/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp and Tamper functions + * @{ + */ /* RTC TimeStamp and Tamper functions *****************************************/ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin); @@ -629,12 +892,59 @@ HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDe HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper); HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); +void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); + +void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); + +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc); + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ + +void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); + +#if defined (STM32L083xx) || defined (STM32L082xx) || defined (STM32L081xx) || \ + defined (STM32L073xx) || defined (STM32L072xx) || defined (STM32L071xx) + +HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); + +#endif /* (STM32L083xx) || (STM32L082xx) || (STM32L081xx) || + * (STM32L073xx) || (STM32L072xx) || (STM32L071xx) + */ + +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions + * @{ + */ +/* RTC Wake-up functions ******************************************************/ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions + * @{ + */ +/* Extended Control functions ************************************************/ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); @@ -646,23 +956,24 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); +/** + * @} + */ -/* Peripheral State functions ***************************************************/ -void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); - -void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); - +/* Extended RTC features functions *******************************************/ +/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions + * @{ + */ +void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); +/** + * @} + */ + +/** + * @} + */ /** * @} @@ -676,6 +987,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin } #endif -#endif /* __STM32L0xx_HAL_PWR_EX_H */ +#endif /* __STM32L0xx_HAL_RTC_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.c index dd1005334d6..9fa50cad7cc 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smartcard.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief SMARTCARD HAL module driver. * * This file provides firmware functions to manage the following @@ -60,7 +60,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -94,7 +94,7 @@ * @{ */ -/** @defgroup SMARTCARD +/** @addtogroup SMARTCARD * @brief HAL SMARTCARD module driver * @{ */ @@ -123,11 +123,11 @@ static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc); static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc); /* Private functions ---------------------------------------------------------*/ -/** @defgroup SMARTCARD_Private_Functions +/** @addtogroup SMARTCARD_Exported_Functions * @{ */ -/** @defgroup SMARTCARD_Group1 Initialization/de-initialization functions +/** @addtogroup SMARTCARD_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim @@ -181,7 +181,7 @@ static void SMARTCARD_AdvFeatureConfig(SMARTCARD_HandleTypeDef *hsc); HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) { /* Check the SMARTCARD handle allocation */ - if(hsc == HAL_NULL) + if(hsc == NULL) { return HAL_ERROR; } @@ -232,7 +232,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc) HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) { /* Check the SMARTCARD handle allocation */ - if(hsc == HAL_NULL) + if(hsc == NULL) { return HAL_ERROR; } @@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc) * @} */ -/** @defgroup SMARTCARD_Group2 IO operation functions +/** @addtogroup SMARTCARD_Exported_Functions_Group2 * @brief SMARTCARD Transmit/Receive functions * @verbatim @@ -340,7 +340,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t * { if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -406,7 +406,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *p { if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -470,7 +470,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_ { if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -521,7 +521,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t { if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -577,7 +577,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_RX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -610,6 +610,9 @@ HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8 tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->TDR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_SMARTCARD_CLEAR_FLAG(hsc, SMARTCARD_FLAG_TC); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the SMARTCARD associated USART CR3 register */ hsc->Instance->CR3 |= USART_CR3_DMAT; @@ -640,7 +643,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_ if((hsc->State == HAL_SMARTCARD_STATE_READY) || (hsc->State == HAL_SMARTCARD_STATE_BUSY_TX)) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -697,7 +700,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /* SMARTCARD parity error interrupt occurred -------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_PE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE) != RESET)) { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_PEF); + __HAL_SMARTCARD_CLEAR_PEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE; /* Set the SMARTCARD state ready to be able to start again the process */ hsc->State = HAL_SMARTCARD_STATE_READY; @@ -706,7 +709,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /* SMARTCARD frame error interrupt occured ---------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_FE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_FEF); + __HAL_SMARTCARD_CLEAR_FEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE; /* Set the SMARTCARD state ready to be able to start again the process */ hsc->State = HAL_SMARTCARD_STATE_READY; @@ -715,7 +718,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /* SMARTCARD noise error interrupt occured ---------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_NE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_NEF); + __HAL_SMARTCARD_CLEAR_NEFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE; /* Set the SMARTCARD state ready to be able to start again the process */ hsc->State = HAL_SMARTCARD_STATE_READY; @@ -724,7 +727,7 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc) /* SMARTCARD Over-Run interrupt occured ------------------------------------*/ if((__HAL_SMARTCARD_GET_IT(hsc, SMARTCARD_IT_ORE) != RESET) && (__HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR) != RESET)) { - __HAL_SMARTCARD_CLEAR_IT(hsc, SMARTCARD_CLEAR_OREF); + __HAL_SMARTCARD_CLEAR_OREFLAG(hsc); hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE; /* Set the SMARTCARD state ready to be able to start again the process */ hsc->State = HAL_SMARTCARD_STATE_READY; @@ -810,7 +813,7 @@ __weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc) * @} */ -/** @defgroup SMARTCARD_Group3 Peripheral State functions +/** @addtogroup SMARTCARD_Exported_Functions_Group3 * @brief SMARTCARD State functions * @verbatim @@ -968,7 +971,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity)); assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase)); assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit)); - assert_param(IS_SMARTCARD_ONEBIT_SAMPLING(hsc->Init.OneBitSampling)); + assert_param(IS_SMARTCARD_ONE_BIT_SAMPLE(hsc->Init.OneBitSampling)); assert_param(IS_SMARTCARD_NACK(hsc->Init.NACKState)); assert_param(IS_SMARTCARD_TIMEOUT(hsc->Init.TimeOutEnable)); assert_param(IS_SMARTCARD_AUTORETRY_COUNT(hsc->Init.AutoRetryCount)); @@ -983,7 +986,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) /* in case of TX-only mode, if NACK is enabled, the USART must be able to monitor the bidirectional line to detect a NACK signal in case of parity error. Therefore, the receiver block must be enabled as well (RE bit must be set). */ - if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLED)) + if((hsc->Init.Mode == SMARTCARD_MODE_TX) && (hsc->Init.NACKState == SMARTCARD_NACK_ENABLE)) { tmpreg |= USART_CR1_RE; } @@ -1016,7 +1019,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) /*-------------------------- USART RTOR Configuration ----------------------*/ tmpreg = (uint32_t) (hsc->Init.BlockLength << SMARTCARD_RTOR_BLEN_LSB_POS); - if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLED) + if(hsc->Init.TimeOutEnable == SMARTCARD_TIMEOUT_ENABLE) { assert_param(IS_SMARTCARD_TIMEOUT_VALUE(hsc->Init.TimeOutValue)); tmpreg |= (uint32_t) hsc->Init.TimeOutValue; @@ -1024,7 +1027,7 @@ static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc) MODIFY_REG(hsc->Instance->RTOR, (USART_RTOR_RTO|USART_RTOR_BLEN), tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ - __HAL_SMARTCARD_GETCLOCKSOURCE(hsc, clocksource); + SMARTCARD_GETCLOCKSOURCE(hsc, clocksource); switch (clocksource) { case SMARTCARD_CLOCKSOURCE_PCLK1: @@ -1220,34 +1223,15 @@ static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDe */ static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - hsc->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit + SMARTCARD_HandleTypeDef* hsmartcard = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + hsmartcard->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the SMARTCARD associated USART CR3 register */ - hsc->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); - - /* Wait for SMARTCARD TC Flag */ - if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, HAL_SMARTCARD_TXDMA_TIMEOUTVALUE) != HAL_OK) - { - /* Timeout Occured */ - hsc->State = HAL_SMARTCARD_STATE_TIMEOUT; - HAL_SMARTCARD_ErrorCallback(hsc); - } - else - { - /* No Timeout */ - /* Check if a receive Process is ongoing or not */ - if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) - { - hsc->State = HAL_SMARTCARD_STATE_BUSY_RX; - } - else - { - hsc->State = HAL_SMARTCARD_STATE_READY; - } - HAL_SMARTCARD_TxCpltCallback(hsc); - } + hsmartcard->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_DMAT); + + /* Enable the SMARTCARD Transmit Complete Interrupt */ + __HAL_SMARTCARD_ENABLE_IT(hsmartcard, SMARTCARD_IT_TC); } /** @@ -1305,3 +1289,4 @@ static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.h index d83c327a645..16ac921af49 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_smartcard.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup SMARTCARD +/** @defgroup SMARTCARD SMARTCARD * @{ */ @@ -166,18 +166,17 @@ typedef enum }HAL_SMARTCARD_StateTypeDef; /** - * @brief HAL SMARTCARD Error Code structure definition + * @brief HAL SMARTCARD Error Code definition */ -typedef enum -{ - HAL_SMARTCARD_ERROR_NONE = 0x00, /*!< No error */ - HAL_SMARTCARD_ERROR_PE = 0x01, /*!< Parity error */ - HAL_SMARTCARD_ERROR_NE = 0x02, /*!< Noise error */ - HAL_SMARTCARD_ERROR_FE = 0x04, /*!< frame error */ - HAL_SMARTCARD_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_SMARTCARD_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_SMARTCARD_ERROR_RTO = 0x20 /*!< Receiver TimeOut error */ -}HAL_SMARTCARD_ErrorTypeDef; + +#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x04) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x20) /*!< Receiver TimeOut error */ + /** * @brief SMARTCARD clock sources definition @@ -220,18 +219,18 @@ typedef struct HAL_LockTypeDef Lock; /* Locking object */ - __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */ + __IO HAL_SMARTCARD_StateTypeDef State; /* SmartCard communication state */ - __IO HAL_SMARTCARD_ErrorTypeDef ErrorCode; /* SmartCard Error code */ + __IO uint32_t ErrorCode; /* SmartCard Error code */ }SMARTCARD_HandleTypeDef; /* Exported constants --------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Constants +/** @defgroup SMARTCARD_Exported_Constants SMARTCARD Exported Constants * @{ */ -/** @defgroup SMARTCARD_Word_Length +/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length * @{ */ #define SMARTCARD_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0) @@ -240,7 +239,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Stop_Bits +/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Stop Bits * @{ */ #define SMARTCARD_STOPBITS_1_5 ((uint32_t)(USART_CR2_STOP)) @@ -249,7 +248,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Parity +/** @defgroup SMARTCARD_Parity SMARTCARD Parity * @{ */ #define SMARTCARD_PARITY_EVEN ((uint32_t)USART_CR1_PCE) @@ -260,7 +259,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Mode +/** @defgroup SMARTCARD_Mode SMARTCARD Mode * @{ */ #define SMARTCARD_MODE_RX ((uint32_t)USART_CR1_RE) @@ -271,7 +270,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Clock_Polarity +/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity * @{ */ #define SMARTCARD_POLARITY_LOW ((uint32_t)0x0000) @@ -281,7 +280,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Clock_Phase +/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase * @{ */ #define SMARTCARD_PHASE_1EDGE ((uint32_t)0x0000) @@ -291,7 +290,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Last_Bit +/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit * @{ */ #define SMARTCARD_LASTBIT_DISABLE ((uint32_t)0x0000) @@ -302,41 +301,41 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_OneBit_Sampling +/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD OneBit Sampling * @{ */ -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED ((uint32_t)0x0000) -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED ((uint32_t)USART_CR3_ONEBIT) -#define IS_SMARTCARD_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_DISABLED) || \ - ((ONEBIT) == SMARTCARD_ONEBIT_SAMPLING_ENABLED)) +#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x0000) +#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) +#define IS_SMARTCARD_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \ + ((ONEBIT) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE)) /** * @} */ -/** @defgroup SMARTCARD_NACK_Enable +/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable * @{ */ -#define SMARTCARD_NACK_ENABLED ((uint32_t)USART_CR3_NACK) -#define SMARTCARD_NACK_DISABLED ((uint32_t)0x0000) -#define IS_SMARTCARD_NACK(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \ - ((NACK) == SMARTCARD_NACK_DISABLED)) +#define SMARTCARD_NACK_ENABLE ((uint32_t)USART_CR3_NACK) +#define SMARTCARD_NACK_DISABLE ((uint32_t)0x0000) +#define IS_SMARTCARD_NACK(NACK) (((NACK) == SMARTCARD_NACK_ENABLE) || \ + ((NACK) == SMARTCARD_NACK_DISABLE)) /** * @} */ -/** @defgroup SMARTCARD_Timeout_Enable +/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable * @{ */ -#define SMARTCARD_TIMEOUT_DISABLED ((uint32_t)0x00000000) -#define SMARTCARD_TIMEOUT_ENABLED ((uint32_t)USART_CR2_RTOEN) -#define IS_SMARTCARD_TIMEOUT(TIMEOUT) (((TIMEOUT) == SMARTCARD_TIMEOUT_DISABLED) || \ - ((TIMEOUT) == SMARTCARD_TIMEOUT_ENABLED)) +#define SMARTCARD_TIMEOUT_DISABLE ((uint32_t)0x00000000) +#define SMARTCARD_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) +#define IS_SMARTCARD_TIMEOUT(TIMEOUT) (((TIMEOUT) == SMARTCARD_TIMEOUT_DISABLE) || \ + ((TIMEOUT) == SMARTCARD_TIMEOUT_ENABLE)) /** * @} */ -/** @defgroup SmartCard_DMA_Requests +/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA Requests * @{ */ @@ -347,7 +346,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type +/** @defgroup SMARTCARD_Advanced_Features_Initialization_Type SMARTCARD Advanced Features Initialization * @{ */ #define SMARTCARD_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) @@ -370,7 +369,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Tx_Inv +/** @defgroup SMARTCARD_Tx_Inv SMARTCARD Tx Inv * @{ */ #define SMARTCARD_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) @@ -381,7 +380,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Rx_Inv +/** @defgroup SMARTCARD_Rx_Inv SMARTCARD Rx Inv * @{ */ #define SMARTCARD_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) @@ -392,7 +391,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Data_Inv +/** @defgroup SMARTCARD_Data_Inv SMARTCARD Data Inv * @{ */ #define SMARTCARD_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) @@ -403,7 +402,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Rx_Tx_Swap +/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD Rx Tx Swap * @{ */ #define SMARTCARD_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) @@ -414,7 +413,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Overrun_Disable +/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD Overrun Enabling * @{ */ #define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) @@ -425,7 +424,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error +/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD DMA on Rx Error * @{ */ #define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) @@ -436,7 +435,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_MSB_First +/** @defgroup SMARTCARD_MSB_First SMARTCARD MSB First * @{ */ #define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) @@ -447,7 +446,7 @@ typedef struct * @} */ -/** @defgroup SmartCard_Flags +/** @defgroup SMARTCARD_Flags SMARTCARD Flags * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ @@ -468,7 +467,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Interrupt_definition +/** @defgroup SMARTCARD_Interrupt_definition SMARTCARD Interrupt definition * Elements values convention: 0000ZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) @@ -496,13 +495,14 @@ typedef struct */ -/** @defgroup SMARTCARD_IT_CLEAR_Flags +/** @defgroup SMARTCARD_IT_CLEAR_Flags SMARTCARD IT CLEAR Flags * @{ */ #define SMARTCARD_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ #define SMARTCARD_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ #define SMARTCARD_CLEAR_NEF USART_ICR_NCF /*!< Noise detected Clear Flag */ #define SMARTCARD_CLEAR_OREF USART_ICR_ORECF /*!< OverRun Error Clear Flag */ +#define SMARTCARD_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ #define SMARTCARD_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define SMARTCARD_CLEAR_RTOF USART_ICR_RTOCF /*!< Receiver Time Out Clear Flag */ #define SMARTCARD_CLEAR_EOBF USART_ICR_EOBCF /*!< End Of Block Clear Flag */ @@ -510,7 +510,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Request_Parameters +/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters * @{ */ #define SMARTCARD_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ @@ -522,7 +522,7 @@ typedef struct */ -/** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS +/** @defgroup SMARTCARD_CR3_SCAR_CNT_LSB_POS SMARTCARD CR3 LSB Position * @{ */ #define SMARTCARD_CR3_SCARCNT_LSB_POS ((uint32_t) 17) @@ -530,7 +530,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_GTPR_GT_LSBPOS +/** @defgroup SMARTCARD_GTPR_GT_LSBPOS SMARTCARD GTPR GT LSB Position * @{ */ #define SMARTCARD_GTPR_GT_LSB_POS ((uint32_t) 8) @@ -538,7 +538,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS +/** @defgroup SMARTCARD_RTOR_BLEN_LSBPOS SMARTCARD RTOR BLEN LSB Position * @{ */ #define SMARTCARD_RTOR_BLEN_LSB_POS ((uint32_t) 24) @@ -546,7 +546,7 @@ typedef struct * @} */ -/** @defgroup SMARTCARD_Interruption_Mask +/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD Interruption Mask * @{ */ #define SMARTCARD_IT_MASK ((uint16_t)0x001F) @@ -559,7 +559,7 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup SMARTCARD_Exported_Macros +/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros * @{ */ @@ -572,10 +572,60 @@ typedef struct /** @brief Flushs the Smartcard DR register * @param __HANDLE__: specifies the SMARTCARD Handle. - * The Handle Instance which can be USART1 or USART2. * @retval None */ -#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST)) +#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \ + } while(0) + +/** @brief Clears the specified SMARTCARD pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg SMARTCARD_CLEAR_PEF + * @arg SMARTCARD_CLEAR_FEF + * @arg SMARTCARD_CLEAR_NEF + * @arg SMARTCARD_CLEAR_OREF + * @arg SMARTCARD_CLEAR_IDLEF + * @arg SMARTCARD_CLEAR_TCF + * @arg SMARTCARD_CLEAR_RTOF + * @arg SMARTCARD_CLEAR_EOBF + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__)) + +/** @brief Clear the SMARTCARD PE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__,SMARTCARD_CLEAR_PEF) + + +/** @brief Clear the SMARTCARD FE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__,SMARTCARD_CLEAR_FEF) + +/** @brief Clear the SMARTCARD NE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__,SMARTCARD_CLEAR_NEF) + +/** @brief Clear the SMARTCARD ORE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__,SMARTCARD_CLEAR_OREF) + +/** @brief Clear the SMARTCARD IDLE pending flag. + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__,SMARTCARD_CLEAR_IDLEF) /** @brief Checks whether the specified Smartcard flag is set or not. * @param __HANDLE__: specifies the SMARTCARD Handle. @@ -701,11 +751,24 @@ typedef struct */ #define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) +/** @brief Enables the SMARTCARD one bit sample method + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disables the SMARTCARD one bit sample method + * @param __HANDLE__: specifies the SMARTCARD Handle. + * @retval None + */ +#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) + /** @brief Enable the USART associated to the SMARTCARD Handle * @param __HANDLE__: specifies the SMARTCARD Handle. * The Handle Instance which can be USART1 or USART2. * @retval None */ + #define __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE) /** @brief Disable the USART associated to the SMARTCARD Handle @@ -761,13 +824,25 @@ typedef struct /* Include SMARTCARD HAL Extension module */ #include "stm32l0xx_hal_smartcard_ex.h" /* Exported functions --------------------------------------------------------*/ +/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions + * @{ + */ /* Initialization/de-initialization functions **********************************/ +/** @defgroup SMARTCARD_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc); HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc); +/** + * @} + */ /* IO operation functions *******************************************************/ +/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions + * @{ + */ HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size); @@ -778,10 +853,24 @@ void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc); void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc); - +/** + * @} + */ +/* IO operation functions *******************************************************/ +/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State functions + * @{ + */ /* Peripheral State functions **************************************************/ HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc); uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); +/** + * @} + */ + +/** + * @} + */ + /** * @} */ @@ -797,3 +886,4 @@ uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc); #endif /* __STM32L0xx_HAL_SMARTCARD_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.c index 3c94e394a86..cb76ebadd04 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following @@ -25,7 +25,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -59,7 +59,7 @@ * @{ */ -/** @defgroup SMARTCARDEx +/** @addtogroup SMARTCARDEx * @brief SMARTCARD Extended HAL module driver * @{ */ @@ -72,11 +72,11 @@ /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ -/** @defgroup SMARTCARDEx_Private_Functions +/** @addtogroup SMARTCARDEx_Exported_Functions * @{ */ -/** @defgroup SMARTCARDEx_Group1 Extended Peripheral Control functions +/** @addtogroup SMARTCARDEx_Exported_Functions_Group1 * @brief Extended control functions * @verbatim @@ -182,3 +182,4 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.h index 2942e11361b..b5cc09da2a2 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smartcard_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_smartcard_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of SMARTCARD HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup SMARTCARDEx +/** @defgroup SMARTCARDEx SMARTCARDEx * @{ */ @@ -63,7 +63,34 @@ * @param __CLOCKSOURCE__ : output variable * @retval the USART clocking source, written in __CLOCKSOURCE__. */ -#define __HAL_SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#if defined (STM32L031xx) || defined (STM32L041xx) +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE; \ + break; \ + default: \ + break; \ + } \ + } \ + } while(0) + +#else /* (STM32L031xx) || defined (STM32L041xx) */ + +#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -106,8 +133,17 @@ } \ } \ } while(0) +#endif /* (STM32L031xx) || (STM32L041xx) */ /* Exported functions --------------------------------------------------------*/ +/** @defgroup SMARTCARDEx_Exported_Functions SMARTCARD Extended Exported functions + * @{ + */ +/* Initialization/de-initialization functions ********************************/ +/** @defgroup SMARTCARDEx_Exported_Functions_Group1 Extended Peripheral Control functions + * @{ + */ + /* Initialization and de-initialization functions ****************************/ /* IO operation functions *****************************************************/ /* Peripheral Control functions ***********************************************/ @@ -125,7 +161,14 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef /** * @} */ - + +/** + * @} + */ + +/** + * @} + */ #ifdef __cplusplus } #endif @@ -133,3 +176,4 @@ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef #endif /* __STM32L0xx_HAL_SMARTCARD_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c index 8cfa28c182f..d7b24af7c5e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_smbus.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief SMBUS HAL module driver. * * This file provides firmware functions to manage the following @@ -58,11 +58,11 @@ (++) The associated previous transfer callback is called at the end of abort process (++) mean HAL_SMBUS_MasterTxCpltCallback in case of previous state was master transmit (++) mean HAL_SMBUS_MasterRxCpltCallback in case of previous state was master receive - (+) Enable the Address listen mode in slave/device SMBUS mode using HAL_SMBUS_Slave_Listen_IT() - (++) When address slave/device SMBUS match, HAL_SMBUS_SlaveAddrCallback is executed and user can + (+) Enable the Address listen mode in slave/device SMBUS mode using HAL_SMBUS_EnableListen_IT() + (++) When address slave/device SMBUS match, HAL_SMBUS_AddrCallback is executed and user can add his own code to check the Address Match Code and the transmission direction request by master/host (Write/Read). - (++) At Listen mode end HAL_SMBUS_SlaveListenCpltCallback is executed and user can - add his own code by customization of function pointer HAL_SMBUS_SlaveListenCpltCallback + (++) At Listen mode end HAL_SMBUS_ListenCpltCallback is executed and user can + add his own code by customization of function pointer HAL_SMBUS_ListenCpltCallback (+) Transmit in slave/device SMBUS mode an amount of data in non blocking mode using HAL_SMBUS_Slave_Transmit_IT() (++) At transmission end of transfer HAL_SMBUS_SlaveTxCpltCallback is executed and user can add his own code by customization of function pointer HAL_SMBUS_SlaveTxCpltCallback @@ -98,7 +98,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -218,7 +218,7 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) { /* Check the SMBUS handle allocation */ - if(hsmbus == HAL_NULL) + if(hsmbus == NULL) { return HAL_ERROR; } @@ -289,7 +289,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter); /* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */ - if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLED) + if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE) && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) ) { hsmbus->Instance->CR1 |= I2C_CR1_SBC; @@ -314,7 +314,7 @@ HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus) HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) { /* Check the SMBUS handle allocation */ - if(hsmbus == HAL_NULL) + if(hsmbus == NULL) { return HAL_ERROR; } @@ -395,7 +395,7 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) (++) HAL_SMBUS_Master_Receive_IT() (++) HAL_SMBUS_Slave_Transmit_IT() (++) HAL_SMBUS_Slave_Receive_IT() - (++) HAL_SMBUS_Slave_Listen_IT() + (++) HAL_SMBUS_EnableListen_IT() (++) HAL_SMBUS_EnableAlert_IT() (++) HAL_SMBUS_DisableAlert_IT() @@ -404,8 +404,8 @@ HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus) (++) HAL_SMBUS_MasterRxCpltCallback() (++) HAL_SMBUS_SlaveTxCpltCallback() (++) HAL_SMBUS_SlaveRxCpltCallback() - (++) HAL_SMBUS_SlaveAddrCallback() - (++) HAL_SMBUS_SlaveListenCpltCallback() + (++) HAL_SMBUS_AddrCallback() + (++) HAL_SMBUS_ListenCpltCallback() (++) HAL_SMBUS_ErrorCallback() @endverbatim @@ -441,7 +441,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == HAL_NULL) + if(hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } @@ -477,7 +477,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint /* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -530,7 +530,7 @@ HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint1 /* In case of Quick command, remove autoend mode */ /* Manage the stop generation by software */ - if(hsmbus->pBuffPtr == HAL_NULL) + if(hsmbus->pBuffPtr == NULL) { hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE; } @@ -657,7 +657,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -685,7 +685,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8 /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -728,7 +728,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ if(hsmbus->State == HAL_SMBUS_STATE_LISTEN) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -756,7 +756,7 @@ HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_ /* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */ /* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */ /* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */ - if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET))) + if((hsmbus->XferSize == 1) || ((hsmbus->XferSize == 2) && (__SMBUS_GET_PEC_MODE(hsmbus) != RESET))) { SMBUS_TransferConfig(hsmbus,0,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP); } @@ -891,7 +891,7 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t do { /* Generate Start */ - hsmbus->Instance->CR2 = __HAL_SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); + hsmbus->Instance->CR2 = __SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress); /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ /* Wait until STOPF flag is set or a NACK flag is set*/ @@ -1094,7 +1094,7 @@ void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus) if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT) { /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX and HAL_SMBUS_STATE_MASTER_BUSY_XX */ - /* keep HAL_SMBUS_STATE_SLAVE_LISTEN if set */ + /* keep HAL_SMBUS_STATE_LISTEN if set */ hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_MASTER_BUSY_RX | HAL_SMBUS_STATE_MASTER_BUSY_TX | HAL_SMBUS_STATE_SLAVE_BUSY_RX | HAL_SMBUS_STATE_SLAVE_BUSY_TX); } @@ -1165,7 +1165,7 @@ __weak void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus) __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_SlaveAddrCallback could be implemented in the user file + the HAL_SMBUS_AddrCallback could be implemented in the user file */ } @@ -1178,7 +1178,7 @@ __weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t Transfer __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SMBUS_SlaveListenCpltCallback could be implemented in the user file + the HAL_SMBUS_ListenCpltCallback could be implemented in the user file */ } @@ -1219,7 +1219,7 @@ __weak void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus) * @param hsmbus : SMBUS handle * @retval HAL state */ -HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) +uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus) { return hsmbus->State; } @@ -1280,7 +1280,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_SMBUS_RESET_CR2(hsmbus); + __SMBUS_RESET_CR2(hsmbus); /* Flush remaining data in Fifo register in case of error occurs before TXEmpty */ @@ -1307,7 +1307,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); /* Clear Configuration Register 2 */ - __HAL_SMBUS_RESET_CR2(hsmbus); + __SMBUS_RESET_CR2(hsmbus); hsmbus->PreviousState = HAL_SMBUS_STATE_READY; hsmbus->State = HAL_SMBUS_STATE_READY; @@ -1348,7 +1348,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_AUTOEND_MODE, SMBUS_GENERATE_START_WRITE); /* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */ /* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */ - if(__HAL_SMBUS_GET_PEC_MODE(hsmbus) != RESET) + if(__SMBUS_GET_PEC_MODE(hsmbus) != RESET) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -1359,7 +1359,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) else if((hsmbus->XferSize == 0)&&(hsmbus->XferCount==0)) { /* Call TxCpltCallback if no stop mode is set */ - if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + if(__SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* Call the corresponding callback to inform upper layer of End of Transfer */ if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX) @@ -1393,13 +1393,13 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus) if(hsmbus->XferCount == 0) { /* Specific use case for Quick command */ - if(hsmbus->pBuffPtr == HAL_NULL) + if(hsmbus->pBuffPtr == NULL) { /* Generate a Stop command */ hsmbus->Instance->CR2 |= I2C_CR2_STOP; } /* Call TxCpltCallback if no stop mode is set */ - else if(__HAL_SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) + else if(__SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE) { /* No Generate Stop, to permit restart mode */ /* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */ @@ -1493,8 +1493,8 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) } else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET) { - TransferDirection = __HAL_SMBUS_GET_DIR(hsmbus); - SlaveAddrCode = __HAL_SMBUS_GET_ADDR_MATCH(hsmbus); + TransferDirection = __SMBUS_GET_DIR(hsmbus); + SlaveAddrCode = __SMBUS_GET_ADDR_MATCH(hsmbus); /* Disable ADDR interrupt to prevent multiple ADDRInterrupt*/ /* Other ADDRInterrupt will be treat in next Listen usecase */ @@ -1526,7 +1526,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) /* Last Byte is received, disable Interrupt */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX); - /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_SLAVE_LISTEN */ + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_RX, keep only HAL_SMBUS_STATE_LISTEN */ hsmbus->PreviousState = hsmbus->State; hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_RX); @@ -1563,7 +1563,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) if(hsmbus->XferSize == 0) { /* Last Byte is Transmitted */ - /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_SLAVE_LISTEN */ + /* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */ SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX); hsmbus->PreviousState = hsmbus->State; hsmbus->State &= (uint32_t)~((uint32_t)HAL_SMBUS_STATE_SLAVE_BUSY_TX); @@ -1591,7 +1591,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus) hsmbus->Instance->CR2 |= I2C_CR2_NACK; /* Clear Configuration Register 2 */ - __HAL_SMBUS_RESET_CR2(hsmbus); + __SMBUS_RESET_CR2(hsmbus); /* Clear STOP Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); @@ -1681,7 +1681,7 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Disable TC, STOP, NACK, TXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI; - if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if((__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET) && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ @@ -1700,7 +1700,7 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Disable TC, STOP, NACK, RXI interrupt */ tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI; - if((__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if((__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET) && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)) { /* Disable ERR interrupt */ @@ -1719,7 +1719,7 @@ static HAL_StatusTypeDef SMBUS_Disable_IRQ(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Enable ADDR, STOP interrupt */ tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI; - if(__HAL_SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET) + if(__SMBUS_GET_ALERT_ENABLE(hsmbus) == RESET) { /* Disable ERR interrupt */ tmpisr |= SMBUS_IT_ERRI; @@ -1848,3 +1848,4 @@ static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddre */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h index 98a7d09bedf..17632463c8b 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_smbus.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_smbus.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of SMBUS HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -101,66 +101,66 @@ typedef struct section in Reference manual */ } SMBUS_InitTypeDef; -/** - * @brief HAL State structures definition +/** @defgroup SMBUS_State SMBUS State + * @brief HAL States definition + * @{ + */ + +#define HAL_SMBUS_STATE_RESET 0x00 /*!< SMBUS not yet initialized or disabled */ +#define HAL_SMBUS_STATE_READY 0x01 /*!< SMBUS initialized and ready for use */ +#define HAL_SMBUS_STATE_BUSY 0x02 /*!< SMBUS internal process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_TX 0x12 /*!< Master Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_MASTER_BUSY_RX 0x22 /*!< Master Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_TX 0x32 /*!< Slave Data Transmission process is ongoing */ +#define HAL_SMBUS_STATE_SLAVE_BUSY_RX 0x42 /*!< Slave Data Reception process is ongoing */ +#define HAL_SMBUS_STATE_TIMEOUT 0x03 /*!< Timeout state */ +#define HAL_SMBUS_STATE_ERROR 0x04 /*!< Reception process is ongoing */ +#define HAL_SMBUS_STATE_LISTEN 0x08 /*!< Address Listen Mode is ongoing */ +/** + * @} + */ + +/** @defgroup SMBUS_Error_Code SMBUS Error Code + * @brief SMBUS Error Code + * @{ */ -typedef enum -{ - HAL_SMBUS_STATE_RESET = 0x00, /*!< SMBUS not yet initialized or disabled */ - HAL_SMBUS_STATE_READY = 0x01, /*!< SMBUS initialized and ready for use */ - HAL_SMBUS_STATE_BUSY = 0x02, /*!< SMBUS internal process is ongoing */ - HAL_SMBUS_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */ - HAL_SMBUS_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */ - HAL_SMBUS_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */ - HAL_SMBUS_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */ - HAL_SMBUS_STATE_TIMEOUT = 0x03, /*!< Timeout state */ - HAL_SMBUS_STATE_ERROR = 0x04, /*!< Reception process is ongoing */ - HAL_SMBUS_STATE_LISTEN = 0x08, /*!< Address Listen Mode is ongoing */ -/* Aliases for inter STM32 series compatibility */ - HAL_SMBUS_STATE_SLAVE_LISTEN = HAL_SMBUS_STATE_LISTEN -}HAL_SMBUS_StateTypeDef; - +#define HAL_SMBUS_ERROR_NONE 0x00 /*!< No error */ +#define HAL_SMBUS_ERROR_BERR 0x01 /*!< BERR error */ +#define HAL_SMBUS_ERROR_ARLO 0x02 /*!< ARLO error */ +#define HAL_SMBUS_ERROR_ACKF 0x04 /*!< ACKF error */ +#define HAL_SMBUS_ERROR_OVR 0x08 /*!< OVR error */ +#define HAL_SMBUS_ERROR_HALTIMEOUT 0x10 /*!< Timeout error */ +#define HAL_SMBUS_ERROR_BUSTIMEOUT 0x20 /*!< Bus Timeout error */ +#define HAL_SMBUS_ERROR_ALERT 0x40 /*!< Alert error */ +#define HAL_SMBUS_ERROR_PECERR 0x80 /*!< PEC error */ /** - * @brief HAL SMBUS Error Code structure definition - */ -typedef enum -{ - HAL_SMBUS_ERROR_NONE = 0x00, /*!< No error */ - HAL_SMBUS_ERROR_BERR = 0x01, /*!< BERR error */ - HAL_SMBUS_ERROR_ARLO = 0x02, /*!< ARLO error */ - HAL_SMBUS_ERROR_ACKF = 0x04, /*!< ACKF error */ - HAL_SMBUS_ERROR_OVR = 0x08, /*!< OVR error */ - HAL_SMBUS_ERROR_HALTIMEOUT = 0x10, /*!< Timeout error */ - HAL_SMBUS_ERROR_BUSTIMEOUT = 0x20, /*!< Bus Timeout error */ - HAL_SMBUS_ERROR_ALERT = 0x40, /*!< Alert error */ - HAL_SMBUS_ERROR_PECERR = 0x80 /*!< PEC error */ - -}HAL_SMBUS_ErrorTypeDef; + * @} + */ /** * @brief SMBUS handle Structure definition */ typedef struct { - I2C_TypeDef *Instance; /*!< SMBUS registers base address */ - - SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ - - uint16_t XferSize; /*!< SMBUS transfer size */ - - __IO uint16_t XferCount; /*!< SMBUS transfer counter */ - - __IO uint32_t XferOptions; /*!< SMBUS transfer options */ - - __IO HAL_SMBUS_StateTypeDef PreviousState; /*!< SMBUS communication Previous tate */ - - HAL_LockTypeDef Lock; /*!< SMBUS locking object */ - - __IO HAL_SMBUS_StateTypeDef State; /*!< SMBUS communication state */ - - __IO HAL_SMBUS_ErrorTypeDef ErrorCode; /*!< SMBUS Error code */ + I2C_TypeDef *Instance; /*!< SMBUS registers base address */ + + SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ + + uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ + + uint16_t XferSize; /*!< SMBUS transfer size */ + + __IO uint16_t XferCount; /*!< SMBUS transfer counter */ + + __IO uint32_t XferOptions; /*!< SMBUS transfer options */ + + __IO uint32_t PreviousState; /*!< SMBUS communication Previous tate */ + + HAL_LockTypeDef Lock; /*!< SMBUS locking object */ + + __IO uint32_t State; /*!< SMBUS communication state */ + + __IO uint32_t ErrorCode; /*!< SMBUS Error code , see SMBUS_Error_Code */ }SMBUS_HandleTypeDef; @@ -173,11 +173,11 @@ typedef struct /** @defgroup SMBUS_Analog_Filter * @{ */ -#define SMBUS_ANALOGFILTER_ENABLED ((uint32_t)0x00000000) -#define SMBUS_ANALOGFILTER_DISABLED I2C_CR1_ANFOFF +#define SMBUS_ANALOGFILTER_ENABLE ((uint32_t)0x00000000) +#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLED) || \ - ((FILTER) == SMBUS_ANALOGFILTER_DISABLED)) +#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ + ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) /** * @} */ @@ -198,11 +198,11 @@ typedef struct * @{ */ -#define SMBUS_DUALADDRESS_DISABLED ((uint32_t)0x00000000) -#define SMBUS_DUALADDRESS_ENABLED I2C_OAR2_OA2EN +#define SMBUS_DUALADDRESS_DISABLE ((uint32_t)0x00000000) +#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLED) || \ - ((ADDRESS) == SMBUS_DUALADDRESS_ENABLED)) +#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ + ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) /** * @} */ @@ -236,11 +236,11 @@ typedef struct /** @defgroup SMBUS_general_call_addressing_mode * @{ */ -#define SMBUS_GENERALCALL_DISABLED ((uint32_t)0x00000000) -#define SMBUS_GENERALCALL_ENABLED I2C_CR1_GCEN +#define SMBUS_GENERALCALL_DISABLE ((uint32_t)0x00000000) +#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN -#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLED) || \ - ((CALL) == SMBUS_GENERALCALL_ENABLED)) +#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ + ((CALL) == SMBUS_GENERALCALL_ENABLE)) /** * @} */ @@ -248,11 +248,11 @@ typedef struct /** @defgroup SMBUS_nostretch_mode * @{ */ -#define SMBUS_NOSTRETCH_DISABLED ((uint32_t)0x00000000) -#define SMBUS_NOSTRETCH_ENABLED I2C_CR1_NOSTRETCH +#define SMBUS_NOSTRETCH_DISABLE ((uint32_t)0x00000000) +#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLED) || \ - ((STRETCH) == SMBUS_NOSTRETCH_ENABLED)) +#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ + ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) /** * @} */ @@ -260,11 +260,11 @@ typedef struct /** @defgroup SMBUS_packet_error_check_mode * @{ */ -#define SMBUS_PEC_DISABLED ((uint32_t)0x00000000) -#define SMBUS_PEC_ENABLED I2C_CR1_PECEN +#define SMBUS_PEC_DISABLE ((uint32_t)0x00000000) +#define SMBUS_PEC_ENABLE I2C_CR1_PECEN -#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLED) || \ - ((PEC) == SMBUS_PEC_ENABLED)) +#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ + ((PEC) == SMBUS_PEC_ENABLE)) /** * @} */ @@ -487,17 +487,17 @@ typedef struct #define __HAL_SMBUS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE) #define __HAL_SMBUS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~I2C_CR1_PE) -#define __HAL_SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) -#define __HAL_SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) +#define __SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) +#define __SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) -#define __HAL_SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ +#define __SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) -#define __HAL_SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) -#define __HAL_SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) -#define __HAL_SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define __HAL_SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) -#define __HAL_SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) +#define __SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17) +#define __SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16) +#define __SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) +#define __SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) +#define __SMBUS_GET_ALERT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= I2C_CR2_NACK) #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF) @@ -516,7 +516,7 @@ HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); /* Aliases for inter STM32 series compatibility */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT +#define HAL_SMBUS_EnableListen_IT HAL_SMBUS_EnableListen_IT /******* Blocking mode: Polling */ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); @@ -538,14 +538,14 @@ void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); /* Aliases for inter STM32 series compatibility */ -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback +#define HAL_SMBUS_AddrCallback HAL_SMBUS_AddrCallback +#define HAL_SMBUS_ListenCpltCallback HAL_SMBUS_ListenCpltCallback void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); /* Peripheral State and Errors functions *************************************/ -HAL_SMBUS_StateTypeDef HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); -uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); +uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); /** * @} @@ -563,3 +563,5 @@ uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); #endif /* __STM32L0xx_HAL_SMBUS_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c index f3a0681b44a..474e76470c1 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.c @@ -2,10 +2,10 @@ ****************************************************************************** * @file stm32l0xx_hal_spi.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief SPI HAL module driver. - * + * * This file provides firmware functions to manage the following * functionalities of the Serial Peripheral Interface (SPI) peripheral: * + Initialization and de-initialization functions @@ -22,7 +22,7 @@ (#) Declare a SPI_HandleTypeDef handle structure, for example: SPI_HandleTypeDef hspi; - (#)Initialize the SPI low level resources by implement the HAL_SPI_MspInit ()API: + (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API: (##) Enable the SPIx interface clock (##) SPI pins configuration (+++) Enable the clock for the SPI GPIOs @@ -31,20 +31,20 @@ (+++) Configure the SPIx interrupt priority (+++) Enable the NVIC SPI IRQ handle (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream - (+++) Enable the DMAx interface clock using + (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel + (+++) Enable the DMAx clock (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Stream - (+++) Associate the initilalized hdma_tx handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream + (+++) Configure the DMA Tx or Rx Channel + (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customed HAL_SPI_MspInit(&hspi) API. - [..] + by calling the customed HAL_SPI_MspInit() API. + [..] Circular mode restriction: (#) The DMA circular mode cannot be used when the SPI is configured in these modes: (##) Master 2Lines RxOnly @@ -55,31 +55,59 @@ [..] Using the HAL it is not possible to reach all supported SPI frequency with the differents SPI Modes, - the following table resume the max SPI frequency reached with data size 8bits/16bits: - +-----------------------------------------------------------------------------------------+ - | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | - | Process | Tranfert mode |--------------------|--------------------|--------------------| - | | | Master | Slave | Master | Slave | Master | Slave | - |=========================================================================================| - | T | Polling | Fcpu/2 | Fcpu/2 | NA | NA | NA | NA | - | X |----------------|----------|---------|----------|---------|----------|---------| - | / | Interrupt | Fcpu/4 | Fcpu/16 | NA | NA | NA | NA | - | R |----------------|----------|---------|----------|---------|----------|---------| - | X | DMA | Fcpu/2 | Fcpu/2 | NA | NA | NA | NA | - |=========|================|==========|=========|==========|=========|==========|=========| - | | Polling | Fcpu/2 | Fcpu/4 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | - | |----------------|----------|---------|----------|---------|----------|---------| - | R | Interrupt | Fcpu/8 | Fcpu/16 | Fcpu/8 | Fcpu/8 | Fcpu/8 | Fcpu/4 | - | X |----------------|----------|---------|----------|---------|----------|---------| - | | DMA | Fcpu/4 | Fcpu/2 | Fcpu/4 | Fcpu/16 | Fcpu/2 | Fcpu/16 | - |=========|================|==========|=========|==========|=========|==========|=========| - | | Polling | Fcpu/2 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/8 | - | |----------------|----------|---------|----------|---------|----------|---------| - | T | Interrupt | Fcpu/2 | Fcpu/4 | NA | NA | Fcpu/16 | Fcpu/8 | - | X |----------------|----------|---------|----------|---------|----------|---------| - | | DMA | Fcpu/2 | Fcpu/2 | NA | NA | Fcpu/8 | Fcpu/16 | - +-----------------------------------------------------------------------------------------+ - @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), + the following table resume the max SPI frequency reached with data size 8bits/16bits, + according to frequency used on APBx Peripheral Clock (fPCLK) used by the SPI instance : + + DataSize = SPI_DATASIZE_8BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/64 | Fpclk/64 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/64 | Fpclk/32 | Fpclk/32 | Fpclk/16 | Fpclk/32 | Fpclk/32 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/16 | Fpclk/2 | Fpclk/16 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/8 | Fpclk/8 | NA | NA | Fpclk/4 | Fpclk/16 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/8 | Fpclk/32 | NA | NA | Fpclk/8 | Fpclk/16 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 | + +----------------------------------------------------------------------------------------------+ + + DataSize = SPI_DATASIZE_16BIT: + +----------------------------------------------------------------------------------------------+ + | | | 2Lines Fullduplex | 2Lines RxOnly | 1Line | + | Process | Tranfert mode |---------------------|----------------------|----------------------| + | | | Master | Slave | Master | Slave | Master | Slave | + |==============================================================================================| + | T | Polling | Fpclk/4 | Fpclk/8 | NA | NA | NA | NA | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | / | Interrupt | Fpclk/32 | Fpclk/16 | NA | NA | NA | NA | + | R |----------------|----------|----------|-----------|----------|-----------|----------| + | X | DMA | Fpclk/2 | Fpclk/4 | NA | NA | NA | NA | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/2 | Fpclk/4 | Fpclk/8 | Fpclk/4 | Fpclk/2 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | R | Interrupt | Fpclk/32 | Fpclk/8 | Fpclk/16 | Fpclk/16 | Fpclk/16 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/2 | Fpclk/8 | Fpclk/2 | Fpclk/8 | Fpclk/2 | + |=========|================|==========|==========|===========|==========|===========|==========| + | | Polling | Fpclk/4 | Fpclk/4 | NA | NA | Fpclk/4 | Fpclk/8 | + | |----------------|----------|----------|-----------|----------|-----------|----------| + | T | Interrupt | Fpclk/4 | Fpclk/16 | NA | NA | Fpclk/8 | Fpclk/8 | + | X |----------------|----------|----------|-----------|----------|-----------|----------| + | | DMA | Fpclk/2 | Fpclk/4 | NA | NA | Fpclk/2 | Fpclk/2 | + +----------------------------------------------------------------------------------------------+ + @note The max SPI frequency depend on SPI data size (8bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() @@ -90,7 +118,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -124,7 +152,7 @@ * @{ */ -/** @defgroup SPI +/** @defgroup SPI SPI * @brief SPI HAL module driver * @{ */ @@ -133,10 +161,20 @@ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ -#define SPI_TIMEOUT_VALUE 100 +/** @defgroup SPI_Private_Constants SPI Private Constants + * @{ + */ +#define SPI_TIMEOUT_VALUE 10 +/** + * @} + */ + /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ +/** @defgroup SPI_Private_Functions SPI Private Functions + * @{ + */ static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); static void SPI_TxISR(SPI_HandleTypeDef *hspi); static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); @@ -150,14 +188,17 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout); +/** + * @} + */ -/* Private functions ---------------------------------------------------------*/ +/* Exported functions ---------------------------------------------------------*/ -/** @defgroup SPI_Private_Functions +/** @defgroup SPI_Exported_Functions SPI Exported Functions * @{ */ -/** @defgroup SPI_Group1 Initialization and de-initialization functions +/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions * @brief Initialization and Configuration functions * @verbatim @@ -167,7 +208,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin [..] This subsection provides a set of functions allowing to initialize and de-initialiaze the SPIx peripheral: - (+) User must Implement HAL_SPI_MspInit() function in which he configures + (+) User must implement HAL_SPI_MspInit() function in which he configures all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). (+) Call the function HAL_SPI_Init() to configure the selected device with @@ -200,12 +241,13 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) { /* Check the SPI handle allocation */ - if(hspi == HAL_NULL) + if(hspi == NULL) { return HAL_ERROR; } /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); assert_param(IS_SPI_MODE(hspi->Init.Mode)); assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction)); assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); @@ -232,19 +274,19 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management, Communication speed, First bit and CRC calculation state */ - hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | - hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation); + WRITE_REG(hspi->Instance->CR1, (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize | + hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) | + hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit | hspi->Init.CRCCalculation) ); /* Configure : NSS management */ - hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode); + WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode)); /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ /* Configure : CRC Polynomial */ - hspi->Instance->CRCPR = hspi->Init.CRCPolynomial; - + WRITE_REG(hspi->Instance->CRCPR, hspi->Init.CRCPolynomial); + /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ - hspi->Instance->I2SCFGR &= (uint32_t)~((uint32_t)SPI_I2SCFGR_I2SMOD); + CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); hspi->ErrorCode = HAL_SPI_ERROR_NONE; hspi->State = HAL_SPI_STATE_READY; @@ -261,7 +303,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) { /* Check the SPI handle allocation */ - if(hspi == HAL_NULL) + if(hspi == NULL) { return HAL_ERROR; } @@ -286,20 +328,20 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) /** * @brief SPI MSP Init * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_SPI_MspInit could be implenetd in the user file + the HAL_SPI_MspInit could be implenetd in the user file */ } /** * @brief SPI MSP DeInit * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. + * the configuration information for SPI module. * @retval None */ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) @@ -313,7 +355,7 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) * @} */ -/** @defgroup SPI_Group2 IO operation functions +/** @defgroup SPI_Exported_Functions_Group2 IO operation functions * @brief Data transfers functions * @verbatim @@ -325,12 +367,12 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) [..] The SPI supports master and slave mode : - (#) There are two mode of transfer: + (#) There are two modes of transfer: (++) Blocking mode: The communication is performed in polling mode. The HAL status of all data processing is returned by the same function after finishing transfer. (++) No-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. + or DMA, These APIs return the HAL status. The end of the data processing will be indicated through the dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -338,27 +380,30 @@ HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) will be executed respectivelly at the end of the transmit or Receive process The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected - (#) Blocking mode API's are : + (#) Blocking mode APIs are : (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_TransmitReceive() in full duplex mode - (#) Non-Blocking mode API's with Interrupt are : + (#) Non Blocking mode API's with Interrupt are : (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_TransmitReceive_IT()in full duplex mode (++) HAL_SPI_IRQHandler() - (#) No-Blocking mode functions with DMA are : + (#) Non Blocking mode functions with DMA are : (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode - (++) HAL_SPI_TransmitReceie_DMA() in full duplex mode + (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode - (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode: + (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: (++) HAL_SPI_TxCpltCallback() (++) HAL_SPI_RxCpltCallback() - (++) HAL_SPI_ErrorCallback() (++) HAL_SPI_TxRxCpltCallback() + (++) HAL_SPI_TxHalfCpltCallback() + (++) HAL_SPI_RxHalfCpltCallback() + (++) HAL_SPI_TxRxHalfCpltCallback() + (++) HAL_SPI_ErrorCallback() @endverbatim * @{ @@ -378,7 +423,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -393,26 +438,27 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; - hspi->TxXferSize = Size; + hspi->pTxBuffPtr = pData; + hspi->TxXferSize = Size; hspi->TxXferCount = Size; /*Init field not used in handle to zero */ hspi->TxISR = 0; hspi->RxISR = 0; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { /* Configure communication direction : 1Line */ - __HAL_SPI_1LINE_TX(hspi); + SPI_1LINE_TX(hspi); } /* Check if the SPI is already enabled */ @@ -425,7 +471,6 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Transmit data in 8 Bit mode */ if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) { - if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01)) { hspi->Instance->DR = (*hspi->pTxBuffPtr++); @@ -443,9 +488,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint hspi->TxXferCount--; } /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } } /* Transmit data in 16 Bit mode */ @@ -470,23 +515,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint hspi->TxXferCount--; } /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } } /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } /* Wait until Busy flag is reset before disabling SPI */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } @@ -520,12 +565,11 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg; - uint32_t tmp = 0; + __IO uint16_t tmpreg = 0; if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -544,19 +588,20 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /*Init field not used in handle to zero */ hspi->RxISR = 0; hspi->TxISR = 0; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_RX(hspi); + SPI_1LINE_RX(hspi); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -589,10 +634,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 (*hspi->pRxBuffPtr++) = hspi->Instance->DR; hspi->RxXferCount--; } - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } } /* Receive data in 16 Bit mode */ @@ -610,10 +655,10 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->pRxBuffPtr+=2; hspi->RxXferCount--; } - /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + /* Enable CRC Reception */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } } @@ -636,17 +681,19 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } hspi->RxXferCount--; - /* Wait until RXNE flag is set: CRC Received */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + /* If CRC computation is enabled */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { + /* Wait until RXNE flag is set: CRC Received */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); return HAL_TIMEOUT; } - /* Read CRC to Flush RXNE flag */ + /* Read CRC to clear RXNE flag */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ } if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) @@ -657,14 +704,13 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 hspi->State = HAL_SPI_STATE_READY; - tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR); /* Check if CRC error occurred */ - if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET)) + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Reset CRC Calculation */ - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -695,13 +741,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 */ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout) { - __IO uint16_t tmpreg; - uint32_t tmpstate = 0, tmp = 0; - - tmpstate = hspi->State; - if((tmpstate == HAL_SPI_STATE_READY) || (tmpstate == HAL_SPI_STATE_BUSY_RX)) + __IO uint16_t tmpreg = 0; + + if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX)) { - if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -734,9 +778,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxISR = 0; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } /* Check if the SPI is already enabled */ @@ -758,9 +802,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if(hspi->TxXferCount == 0) { /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } /* Wait until RXNE flag is set */ @@ -788,9 +832,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxXferCount--; /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } /* Wait until RXNE flag is set */ @@ -798,7 +842,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { return HAL_TIMEOUT; } - + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; hspi->pRxBuffPtr+=2; hspi->RxXferCount--; @@ -829,9 +873,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD if(hspi->TxXferCount == 0) { /* Enable CRC Transmission */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } /* Wait until RXNE flag is set */ @@ -857,19 +901,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->TxXferCount--; /* Enable CRC Transmission */ - if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } - /* Wait until RXNE flag is set */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) - { - return HAL_TIMEOUT; - } - - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - hspi->RxXferCount--; + /* Wait until RXNE flag is set */ + if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) + { + return HAL_TIMEOUT; + } + + (*hspi->pRxBuffPtr++) = hspi->Instance->DR; + hspi->RxXferCount--; } if(hspi->Init.Mode == SPI_MODE_SLAVE) { @@ -886,38 +930,34 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } /* Read CRC from DR to close CRC calculation process */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Wait until RXNE flag is set */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); return HAL_TIMEOUT; } /* Read CRC */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* avoid warning on tmpreg affectation with stupid compiler */ } /* Wait until Busy flag is reset before disabling SPI */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); return HAL_TIMEOUT; } hspi->State = HAL_SPI_STATE_READY; - tmp = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR); /* Check if CRC error occurred */ - if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (tmp != RESET)) + if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)) { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) - { - __HAL_SPI_RESET_CRC(hspi); - } + SPI_RESET_CRC(hspi); /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -948,7 +988,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -963,32 +1003,34 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->TxISR = &SPI_TxISR; + hspi->TxISR = &SPI_TxISR; hspi->pTxBuffPtr = pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; /*Init field not used in handle to zero */ - hspi->RxISR = 0; + hspi->RxISR = 0; + hspi->pRxBuffPtr = NULL; hspi->RxXferSize = 0; hspi->RxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_TX(hspi); + SPI_1LINE_TX(hspi); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } if (hspi->Init.Direction == SPI_DIRECTION_2LINES) { __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE)); - }else + } + else { /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); @@ -1023,7 +1065,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -1035,34 +1077,35 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->RxISR = &SPI_RxISR; + hspi->RxISR = &SPI_RxISR; hspi->pRxBuffPtr = pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size ; /*Init field not used in handle to zero */ - hspi->TxISR = 0; + hspi->TxISR = 0; + hspi->pTxBuffPtr = NULL; hspi->TxXferSize = 0; hspi->TxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_RX(hspi); + SPI_1LINE_RX(hspi); } else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } /* Enable TXE and ERR interrupt */ @@ -1075,7 +1118,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui to avoid the risk of SPI interrupt handle execution before current process unlock */ - /* Check if the SPI is already enabled */ + /* Check if the SPI is already enabled */ if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ @@ -1101,13 +1144,11 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t tmpstate = 0; - tmpstate = hspi->State; - if((tmpstate == HAL_SPI_STATE_READY) || \ - ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX))) + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) { - if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -1138,9 +1179,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p hspi->RxXferCount = Size; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } /* Enable TXE, RXNE and ERR interrupt */ @@ -1176,8 +1217,10 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); return HAL_ERROR; } @@ -1191,42 +1234,49 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = pData; + hspi->pTxBuffPtr = (uint8_t*)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; /*Init field not used in handle to zero */ - hspi->TxISR = 0; - hspi->RxISR = 0; - hspi->RxXferSize = 0; - hspi->RxXferCount = 0; + hspi->TxISR = 0; + hspi->RxISR = 0; + + hspi->pRxBuffPtr = NULL; + hspi->RxXferSize = 0; + hspi->RxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_TX(hspi); + SPI_1LINE_TX(hspi); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* Set the SPI TxDMA Half transfer complete callback */ hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; - + /* Set the SPI TxDMA transfer complete callback */ hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; /* Set the DMA error callback */ hspi->hdmatx->XferErrorCallback = SPI_DMAError; - /* Enable the Tx DMA Stream */ + /* Reset content of SPI RxDMA descriptor */ + hspi->hdmarx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; + hspi->hdmarx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; + hspi->hdmarx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL; + + /* Enable the Tx DMA Channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); /* Enable Tx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1242,6 +1292,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, } else { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); return HAL_BUSY; } } @@ -1259,8 +1311,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { if(hspi->State == HAL_SPI_STATE_READY) { - if((pData == HAL_NULL) || (Size == 0)) + if((pData == NULL) || (Size == 0)) { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); return HAL_ERROR; } @@ -1271,50 +1325,57 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = pData; + hspi->pRxBuffPtr = (uint8_t*)pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; /*Init field not used in handle to zero */ - hspi->RxISR = 0; - hspi->TxISR = 0; - hspi->TxXferSize = 0; - hspi->TxXferCount = 0; + hspi->RxISR = 0; + hspi->TxISR = 0; + + hspi->pTxBuffPtr = NULL; + hspi->TxXferSize = 0; + hspi->TxXferCount = 0; /* Configure communication direction : 1Line */ if(hspi->Init.Direction == SPI_DIRECTION_1LINE) { - __HAL_SPI_1LINE_RX(hspi); + SPI_1LINE_RX(hspi); } else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER)) { - /* Process Unlocked */ - __HAL_UNLOCK(hspi); + /* Process Unlocked */ + __HAL_UNLOCK(hspi); - /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ - return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); + /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */ + return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size); } /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } - + /* Set the SPI RxDMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - + /* Set the SPI Rx DMA transfer complete callback */ hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; - /* Enable the Rx DMA Stream */ + /* Reset content of SPI TxDMA descriptor */ + hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; + hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; + hspi->hdmatx->XferErrorCallback = (void (*)(DMA_HandleTypeDef *))NULL; + + /* Enable the Rx DMA Channel */ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); /* Enable Rx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1329,7 +1390,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u return HAL_OK; } else - { + { + /* Process Unlocked */ + __HAL_UNLOCK(hspi); return HAL_BUSY; } } @@ -1346,12 +1409,10 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u */ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { - uint32_t tmpstate = 0; - tmpstate = hspi->State; - if((tmpstate == HAL_SPI_STATE_READY) || ((hspi->Init.Mode == SPI_MODE_MASTER) && \ - (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmpstate == HAL_SPI_STATE_BUSY_RX))) + if((hspi->State == HAL_SPI_STATE_READY) || \ + ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX))) { - if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0)) + if((pTxData == NULL ) || (pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -1384,9 +1445,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * hspi->TxISR = 0; /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */ @@ -1401,38 +1462,39 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Set the SPI Tx/Rx DMA Half transfer complete callback */ hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - + hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; } /* Set the DMA error callback */ hspi->hdmarx->XferErrorCallback = SPI_DMAError; - /* Enable the Rx DMA Stream */ + /* Enable the Rx DMA Channel */ HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount); /* Enable Rx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - /* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing + /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing is performed in DMA reception complete callback */ - hspi->hdmatx->XferCpltCallback = HAL_NULL; + hspi->hdmatx->XferHalfCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; + hspi->hdmatx->XferCpltCallback = (void (*)(DMA_HandleTypeDef *))NULL; /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - - /* Enable the Tx DMA Stream */ + hspi->hdmatx->XferErrorCallback = SPI_DMAError; + + /* Enable the Tx DMA Channel */ HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount); /* Check if the SPI is already enabled */ - if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE) + if((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } /* Enable Tx DMA Request */ - hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1445,6 +1507,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * } } + /** * @brief Pauses the DMA Transfer. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains @@ -1457,8 +1520,8 @@ HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) __HAL_LOCK(hspi); /* Disable the SPI DMA Tx & Rx requests */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1478,8 +1541,8 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) __HAL_LOCK(hspi); /* Enable the SPI DMA Tx & Rx requests */ - hspi->Instance->CR2 |= SPI_CR2_TXDMAEN; - hspi->Instance->CR2 |= SPI_CR2_RXDMAEN; + SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1489,8 +1552,8 @@ HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) /** * @brief Stops the DMA Transfer. - * @param huart: pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for the specified SPI module. * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) @@ -1501,20 +1564,20 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() */ - /* Abort the SPI DMA tx Stream */ - if(hspi->hdmatx != HAL_NULL) + /* Abort the SPI DMA tx Channel */ + if(hspi->hdmatx != NULL) { HAL_DMA_Abort(hspi->hdmatx); } - /* Abort the SPI DMA rx Stream */ - if(hspi->hdmarx != HAL_NULL) + /* Abort the SPI DMA rx Channel */ + if(hspi->hdmarx != NULL) { HAL_DMA_Abort(hspi->hdmarx); } /* Disable the SPI DMA Tx & Rx requests */ - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN); - hspi->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); hspi->State = HAL_SPI_STATE_READY; @@ -1529,22 +1592,15 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) */ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) { - uint32_t tmp1 = 0, tmp2 = 0, tmp3 = 0; - - tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE); - tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE); - tmp3 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR); /* SPI in mode Receiver and Overrun not occurred ---------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET) && (tmp3 == RESET)) + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) { hspi->RxISR(hspi); return; - } + } - tmp1 = __HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE); - tmp2 = __HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE); /* SPI in mode Tramitter ---------------------------------------------------*/ - if((tmp1 != RESET) && (tmp2 != RESET)) + if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET)) { hspi->TxISR(hspi); return; @@ -1552,39 +1608,40 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET) { - /* SPI CRC error interrupt occured ---------------------------------------*/ + /* SPI CRC error interrupt occurred ---------------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } - /* SPI Mode Fault error interrupt occured --------------------------------*/ + /* SPI Mode Fault error interrupt occurred --------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_MODF; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); __HAL_SPI_CLEAR_MODFFLAG(hspi); } - /* SPI Overrun error interrupt occured -----------------------------------*/ + /* SPI Overrun error interrupt occurred -----------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET) { if(hspi->State != HAL_SPI_STATE_BUSY_TX) { - hspi->ErrorCode |= HAL_SPI_ERROR_OVR; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); __HAL_SPI_CLEAR_OVRFLAG(hspi); } } - /* SPI Frame error interrupt occured -------------------------------------*/ + /* SPI Frame error interrupt occurred -------------------------------------*/ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_FRE; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); __HAL_SPI_CLEAR_FREFLAG(hspi); } /* Call the Error call Back in case of Errors */ if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE) { + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR); hspi->State = HAL_SPI_STATE_READY; HAL_SPI_ErrorCallback(hspi); } @@ -1680,7 +1737,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* NOTE : - This function Should not be modified, when the callback is needed, the HAL_SPI_ErrorCallback() could be implenetd in the user file. - The ErrorCode parameter in the hspi handle is updated by the SPI processes - and user can use HAL_SPI_GetError() API to check the latest error occured. + and user can use HAL_SPI_GetError() API to check the latest error occurred. */ } @@ -1688,7 +1745,7 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) * @} */ -/** @defgroup SPI_Group3 Peripheral State and Errors functions +/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions * @brief SPI control functions * @verbatim @@ -1705,7 +1762,8 @@ __weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI state - * @param hspi : SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval SPI state */ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) @@ -1715,10 +1773,11 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) /** * @brief Return the SPI error code - * @param hspi : SPI handle + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. * @retval SPI Error Code */ -HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) { return hspi->ErrorCode; } @@ -1726,6 +1785,17 @@ HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi) /** * @} */ + +/** + * @} + */ + + + +/** @addtogroup SPI_Private_Functions + * @{ + */ + /** * @brief Interrupt Handler to close Tx transfer @@ -1738,21 +1808,21 @@ static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (uint32_t)SPI_IT_TXE); + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); /* Disable ERR interrupt if Receive process is finished */ if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) { - __HAL_SPI_DISABLE_IT(hspi, (uint32_t)SPI_IT_ERR); + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); /* Wait until Busy flag is reset before disabling SPI */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ @@ -1811,10 +1881,10 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi) if(hspi->TxXferCount == 0) { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* calculate and transfer CRC on Tx line */ - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } SPI_TxCloseIRQHandler(hspi); } @@ -1828,43 +1898,44 @@ static void SPI_TxISR(SPI_HandleTypeDef *hspi) */ static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) { - __IO uint16_t tmpreg; + __IO uint16_t tmpreg = 0; - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* Wait until RXNE flag is set to send data */ + /* Wait until RXNE flag is set to read CRC data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Read CRC to reset RXNE flag */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ - /* Wait until RXNE flag is set to send data */ + /* Wait until RXNE flag is reset */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Reset CRC Calculation */ - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } } - /* Disable RXNE and ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_RXNE)); + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); /* if Transmit process is finished */ if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) { /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (uint32_t)(SPI_IT_ERR)); + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) { @@ -1948,10 +2019,10 @@ static void SPI_RxISR(SPI_HandleTypeDef *hspi) hspi->RxXferCount--; /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)) + if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) { /* Set CRC Next to calculate CRC on Rx side */ - hspi->Instance->CR1 |= SPI_CR1_CRCNEXT; + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); } if(hspi->RxXferCount == 0) @@ -1977,27 +2048,26 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } - + /* Disable Tx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); /* Wait until Busy flag is reset before disabling SPI */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } hspi->TxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; } /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ if(hspi->Init.Direction == SPI_DIRECTION_2LINES) { - __HAL_SPI_CLEAR_OVRFLAG(hspi); + __HAL_SPI_CLEAR_OVRFLAG(hspi); } /* Check if Errors has been detected during transfer */ @@ -2019,52 +2089,55 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - __IO uint16_t tmpreg; + __IO uint16_t tmpreg = 0; SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; + /* DMA Normal mode */ if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) { - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - /* Disable Rx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_RXDMAEN); - /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ - hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); - hspi->RxXferCount = 0; - hspi->State = HAL_SPI_STATE_READY; + /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */ + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - /* Wait until RXNE flag is set to send data */ + /* Wait until RXNE flag is set (CRC ready) */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Read CRC */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ - /* Wait until RXNE flag is set */ + /* Wait until RXNE flag is reset */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } } + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + hspi->RxXferCount = 0; + hspi->State = HAL_SPI_STATE_READY; + /* Check if Errors has been detected during transfer */ if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) { @@ -2078,7 +2151,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) else { HAL_SPI_RxCpltCallback(hspi); - } + } } /** @@ -2089,13 +2162,13 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - __IO uint16_t tmpreg; + __IO uint16_t tmpreg = 0; SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) { - /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + /* CRC Calculation handling */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { /* Check if CRC is done on going (RXNE flag set) */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK) @@ -2103,36 +2176,38 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Wait until RXNE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } } /* Read CRC */ tmpreg = hspi->Instance->DR; + UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ /* Check if CRC error occurred */ if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) { - hspi->ErrorCode |= HAL_SPI_ERROR_CRC; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); __HAL_SPI_CLEAR_CRCERRFLAG(hspi); } } + /* Wait until TXE flag is set to send data */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Disable Tx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_TXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); /* Wait until Busy flag is reset before disabling SPI */ if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) { - hspi->ErrorCode |= HAL_SPI_ERROR_FLAG; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); } /* Disable Rx DMA Request */ - hspi->Instance->CR2 &= (uint32_t)~((uint32_t)SPI_CR2_RXDMAEN); + CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); hspi->TxXferCount = 0; hspi->RxXferCount = 0; @@ -2194,7 +2269,6 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) HAL_SPI_TxRxHalfCpltCallback(hspi); } - /** * @brief DMA SPI communication error callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains @@ -2207,19 +2281,24 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) hspi->TxXferCount = 0; hspi->RxXferCount = 0; hspi->State= HAL_SPI_STATE_READY; - hspi->ErrorCode |= HAL_SPI_ERROR_DMA; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); HAL_SPI_ErrorCallback(hspi); } /** - * @brief This function handles SPI Communication Timeout. + * @brief This function handles SPI Communication Timeout. * @param hspi: pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param Status: Flag status to check: RESET or set + * @param Timeout: Timeout duration * @retval HAL status */ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout) { - uint32_t tickstart = 0x00; + uint32_t tickstart = 0; + + /* Get tick */ tickstart = HAL_GetTick(); /* Wait until flag is set */ @@ -2227,10 +2306,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin { while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET) { - /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -2243,9 +2321,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin __HAL_SPI_DISABLE(hspi); /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } hspi->State= HAL_SPI_STATE_READY; @@ -2264,7 +2342,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin { if(Timeout != HAL_MAX_DELAY) { - if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) + if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable the SPI and reset the CRC: the CRC value should be cleared on both master and slave sides in order to resynchronize the master @@ -2277,9 +2355,9 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin __HAL_SPI_DISABLE(hspi); /* Reset CRC Calculation */ - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { - __HAL_SPI_RESET_CRC(hspi); + SPI_RESET_CRC(hspi); } hspi->State= HAL_SPI_STATE_READY; @@ -2294,8 +2372,6 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin } return HAL_OK; } - - /** * @} */ @@ -2310,3 +2386,4 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.h index f622193a709..9eb2ecdf9bf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_spi.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_spi.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -55,6 +55,9 @@ */ /* Exported types ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Types SPI Exported Types + * @{ + */ /** * @brief SPI Configuration Structure definition @@ -115,207 +118,177 @@ typedef enum }HAL_SPI_StateTypeDef; -/** - * @brief HAL SPI Error Code structure definition - */ -typedef enum -{ - HAL_SPI_ERROR_NONE = 0x00, /*!< No error */ - HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */ - HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */ - HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */ - HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */ - HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */ - HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */ - -}HAL_SPI_ErrorTypeDef; - /** * @brief SPI handle Structure definition */ typedef struct __SPI_HandleTypeDef { - SPI_TypeDef *Instance; /* SPI registers base address */ + SPI_TypeDef *Instance; /*!< SPI registers base address */ - SPI_InitTypeDef Init; /* SPI communication parameters */ + SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */ + uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ - uint16_t TxXferSize; /* SPI Tx transfer size */ + uint16_t TxXferSize; /*!< SPI Tx transfer size */ - uint16_t TxXferCount; /* SPI Tx Transfer Counter */ + uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ - uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */ + uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - uint16_t RxXferSize; /* SPI Rx transfer size */ + uint16_t RxXferSize; /*!< SPI Rx transfer size */ - uint16_t RxXferCount; /* SPI Rx Transfer Counter */ + uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ - DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */ + DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA handle parameters */ - DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */ + DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA handle parameters */ - void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */ + void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Rx ISR */ - void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */ + void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /*!< function pointer on Tx ISR */ - HAL_LockTypeDef Lock; /* SPI locking object */ + HAL_LockTypeDef Lock; /*!< SPI locking object */ - __IO HAL_SPI_StateTypeDef State; /* SPI communication state */ + __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ - __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */ + __IO uint32_t ErrorCode; /*!< SPI Error code */ }SPI_HandleTypeDef; +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ -/** @defgroup SPI_Exported_Constants +/** @defgroup SPI_Exported_Constants SPI Exported Constants + * @{ + */ + +/** + * @defgroup SPI_ErrorCode SPI Error Code * @{ */ +#define HAL_SPI_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_SPI_ERROR_MODF ((uint32_t)0x01) /*!< MODF error */ +#define HAL_SPI_ERROR_CRC ((uint32_t)0x02) /*!< CRC error */ +#define HAL_SPI_ERROR_OVR ((uint32_t)0x04) /*!< OVR error */ +#define HAL_SPI_ERROR_FRE ((uint32_t)0x08) /*!< FRE error */ +#define HAL_SPI_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ +#define HAL_SPI_ERROR_FLAG ((uint32_t)0x20) /*!< Flag: RXNE,TXE, BSY */ +/** + * @} + */ -/** @defgroup SPI_mode +/** @defgroup SPI_mode SPI mode * @{ */ #define SPI_MODE_SLAVE ((uint32_t)0x00000000) #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) -#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ - ((MODE) == SPI_MODE_MASTER)) /** * @} */ -/** @defgroup SPI_Direction_mode +/** @defgroup SPI_Direction_mode SPI Direction mode * @{ */ -#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) -#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY -#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE - -#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((MODE) == SPI_DIRECTION_1LINE)) - -#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_1LINE)) - -#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) +#define SPI_DIRECTION_2LINES ((uint32_t)0x00000000) +#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY +#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE /** * @} */ -/** @defgroup SPI_data_size +/** @defgroup SPI_data_size SPI data size * @{ */ #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000) #define SPI_DATASIZE_16BIT SPI_CR1_DFF -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ - ((DATASIZE) == SPI_DATASIZE_8BIT)) /** * @} */ -/** @defgroup SPI_Clock_Polarity +/** @defgroup SPI_Clock_Polarity SPI Clock Polarity * @{ */ #define SPI_POLARITY_LOW ((uint32_t)0x00000000) #define SPI_POLARITY_HIGH SPI_CR1_CPOL -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ - ((CPOL) == SPI_POLARITY_HIGH)) /** * @} */ -/** @defgroup SPI_Clock_Phase +/** @defgroup SPI_Clock_Phase SPI Clock Phase * @{ */ #define SPI_PHASE_1EDGE ((uint32_t)0x00000000) #define SPI_PHASE_2EDGE SPI_CR1_CPHA -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ - ((CPHA) == SPI_PHASE_2EDGE)) /** * @} */ -/** @defgroup SPI_Slave_Select_management +/** @defgroup SPI_Slave_Select_management SPI Slave Select management * @{ */ #define SPI_NSS_SOFT SPI_CR1_SSM #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000) -#define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000) +#define SPI_NSS_HARD_OUTPUT ((uint32_t)(SPI_CR2_SSOE << 16)) -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ - ((NSS) == SPI_NSS_HARD_INPUT) || \ - ((NSS) == SPI_NSS_HARD_OUTPUT)) /** * @} */ -/** @defgroup SPI_BaudRate_Prescaler +/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler * @{ */ #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000) -#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008) -#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010) -#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018) -#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020) -#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028) -#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030) -#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038) - -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) +#define SPI_BAUDRATEPRESCALER_4 ((uint32_t)SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_8 ((uint32_t)SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_16 ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_32 ((uint32_t)SPI_CR1_BR_2) +#define SPI_BAUDRATEPRESCALER_64 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0) +#define SPI_BAUDRATEPRESCALER_128 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1) +#define SPI_BAUDRATEPRESCALER_256 ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) + /** * @} */ -/** @defgroup SPI_MSB_LSB_transmission +/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission * @{ */ #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000) #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ - ((BIT) == SPI_FIRSTBIT_LSB)) /** * @} */ -/** @defgroup SPI_TI_mode +/** @defgroup SPI_TI_mode SPI TI mode * @{ */ -#define SPI_TIMODE_DISABLED ((uint32_t)0x00000000) -#define SPI_TIMODE_ENABLED SPI_CR2_FRF +#define SPI_TIMODE_DISABLE ((uint32_t)0x00000000) +#define SPI_TIMODE_ENABLE SPI_CR2_FRF -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \ - ((MODE) == SPI_TIMODE_ENABLED)) /** * @} */ -/** @defgroup SPI_CRC_Calculation +/** @defgroup SPI_CRC_Calculation SPI CRC Calculation * @{ */ -#define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000) -#define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN +#define SPI_CRCCALCULATION_DISABLE ((uint32_t)0x00000000) +#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLED)) /** * @} */ -/** @defgroup SPI_Interrupt_configuration_definition +/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition * @{ */ #define SPI_IT_TXE SPI_CR2_TXEIE @@ -325,7 +298,7 @@ typedef struct __SPI_HandleTypeDef * @} */ -/** @defgroup SPI_Flag_definition +/** @defgroup SPI_Flag_definition SPI Flag definition * @{ */ #define SPI_FLAG_RXNE SPI_SR_RXNE @@ -344,31 +317,46 @@ typedef struct __SPI_HandleTypeDef * @} */ + /* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_Exported_Macros SPI Exported Macros + * @{ + */ /** @brief Reset SPI handle state * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -/** @brief Enable or disable the specified SPI interrupts. +/** @brief Enable the specified SPI interrupts. + * @param __HANDLE__: specifies the SPI handle. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to enable. + * This parameter can be one of the following values: + * @arg SPI_IT_TXE: Tx buffer empty interrupt enable + * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable + * @arg SPI_IT_ERR: Error interrupt enable + * @retval None + */ +#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) + +/** @brief Disable the specified SPI interrupts. * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. + * @param __INTERRUPT__: specifies the interrupt source to disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable * @arg SPI_IT_ERR: Error interrupt enable * @retval None */ -#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__)) -#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) +#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) /** @brief Check if the specified SPI interrupt source is enabled or disabled. * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. * @param __INTERRUPT__: specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable @@ -380,7 +368,7 @@ typedef struct __SPI_HandleTypeDef /** @brief Check whether the specified SPI flag is set or not. * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. * @param __FLAG__: specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag @@ -396,55 +384,223 @@ typedef struct __SPI_HandleTypeDef /** @brief Clear the SPI CRCERR pending flag. * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR &= (uint32_t)~((uint32_t)SPI_FLAG_CRCERR)) +#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. * @retval None - */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\ - (__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_SPE);}while(0) + */ +#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \ + UNUSED(tmpreg); \ + } while(0) /** @brief Clear the SPI OVR pending flag. * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. * @retval None */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\ - (__HANDLE__)->Instance->SR;}while(0) +#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->DR; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ + } while(0) /** @brief Clear the SPI FRE pending flag. * @param __HANDLE__: specifies the SPI handle. - * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ + do{ \ + __IO uint32_t tmpreg; \ + tmpreg = (__HANDLE__)->Instance->SR; \ + UNUSED(tmpreg); \ + } while(0) + +/** @brief Enables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) + +/** @brief Disables the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. + * @retval None + */ +#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) +/** + * @} + */ + + +/* Private macros -----------------------------------------------------------*/ +/** @defgroup SPI_Private_Macros SPI Private Macros + * @{ + */ + +/** @brief Checks if SPI Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Mode. + * This parameter can be a value of @ref SPI_mode + * @retval None + */ +#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || ((__MODE__) == SPI_MODE_MASTER)) + +/** @brief Checks if SPI Direction Mode parameter is in allowed range. + * @param __MODE__: specifies the SPI Direction Mode. + * This parameter can be a value of @ref SPI_Direction_mode + * @retval None + */ +#define IS_SPI_DIRECTION_MODE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ + ((__MODE__) == SPI_DIRECTION_1LINE)) + +/** @brief Checks if SPI Direction Mode parameter is 2 lines. + * @param __MODE__: specifies the SPI Direction Mode. + * @retval None + */ +#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) + +/** @brief Checks if SPI Data Size parameter is in allowed range. + * @param __DATASIZE__: specifies the SPI Data Size. + * This parameter can be a value of @ref SPI_data_size + * @retval None + */ +#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ + ((__DATASIZE__) == SPI_DATASIZE_8BIT)) + +/** @brief Checks if SPI Serial clock steady state parameter is in allowed range. + * @param __CPOL__: specifies the SPI serial clock steady state. + * This parameter can be a value of @ref SPI_Clock_Polarity * @retval None */ -#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR) +#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ + ((__CPOL__) == SPI_POLARITY_HIGH)) -#define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) -#define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_SPE)) +/** @brief Checks if SPI Clock Phase parameter is in allowed range. + * @param __CPHA__: specifies the SPI Clock Phase. + * This parameter can be a value of @ref SPI_Clock_Phase + * @retval None + */ +#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ + ((__CPHA__) == SPI_PHASE_2EDGE)) + +/** @brief Checks if SPI Slave select parameter is in allowed range. + * @param __NSS__: specifies the SPI Slave Slelect management parameter. + * This parameter can be a value of @ref SPI_Slave_Select_management + * @retval None + */ +#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ + ((__NSS__) == SPI_NSS_HARD_INPUT) || \ + ((__NSS__) == SPI_NSS_HARD_OUTPUT)) + +/** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. + * @param __PRESCALER__: specifies the SPI Baudrate prescaler. + * This parameter can be a value of @ref SPI_BaudRate_Prescaler + * @retval None + */ +#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ + ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) + +/** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. + * @param __BIT__: specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). + * This parameter can be a value of @ref SPI_MSB_LSB_transmission + * @retval None + */ +#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ + ((__BIT__) == SPI_FIRSTBIT_LSB)) -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF)) +/** @brief Checks if SPI TI mode parameter is in allowed range. + * @param __MODE__: specifies the SPI TI mode. + * This parameter can be a value of @ref SPI_TI_mode + * @retval None + */ +#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ + ((__MODE__) == SPI_TIMODE_ENABLE)) +/** @brief Checks if SPI CRC calculation enabled state is in allowed range. + * @param __CALCULATION__: specifies the SPI CRC calculation enable state. + * This parameter can be a value of @ref SPI_CRC_Calculation + * @retval None + */ +#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ + ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) -#define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) +/** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. + * @param __POLYNOMIAL__: specifies the SPI polynomial value to be used for the CRC calculation. + * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 + * @retval None + */ +#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1) && ((__POLYNOMIAL__) <= 0xFFFF)) +/** @brief Sets the SPI transmit-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) -#define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_BIDIOE)) +/** @brief Sets the SPI receive-only mode. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. + * @retval None + */ +#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) -#define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)SPI_CR1_CRCEN);\ - (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0) +/** @brief Resets the CRC calculation of the SPI. + * @param __HANDLE__: specifies the SPI Handle. + * This parameter can be SPIx where x: 1 or 2 to select the SPI peripheral. + * @retval None + */ +#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0) +/** + * @} + */ /* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_Exported_Functions + * @{ + */ /* Initialization/de-initialization functions **********************************/ +/** @addtogroup SPI_Exported_Functions_Group1 + * @{ + */ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi); void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); +/** + * @} + */ /* I/O operation functions *****************************************************/ +/** @addtogroup SPI_Exported_Functions_Group2 + * @{ + */ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); @@ -466,10 +622,26 @@ void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); +/** + * @} + */ + /* Peripheral State and Control functions **************************************/ +/** @addtogroup SPI_Exported_Functions_Group3 + * @{ + */ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); + +/** + * @} + */ + +/** + * @} + */ + /** * @} @@ -486,3 +658,4 @@ HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi); #endif /* __STM32L0xx_HAL_SPI_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c index 0079450af17..a1b3cd6d0a7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.c @@ -2,36 +2,36 @@ ****************************************************************************** * @file stm32l0xx_hal_tim.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief TIM HAL module driver. * @brief This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: - * + Time Base Initialization - * + Time Base Start - * + Time Base Start Interruption - * + Time Base Start DMA - * + Time Output Compare/PWM Initialization - * + Time Output Compare/PWM Channel Configuration - * + Time Output Compare/PWM Start - * + Time Output Compare/PWM Start Interruption - * + Time Output Compare/PWM Start DMA - * + Time Input Capture Initialization - * + Time Input Capture Channel Configuration - * + Time Input Capture Start - * + Time Input Capture Start Interruption - * + Time Input Capture Start DMA - * + Time One Pulse Initialization - * + Time One Pulse Channel Configuration - * + Time One Pulse Start - * + Time Encoder Interface Initialization - * + Time Encoder Interface Start - * + Time Encoder Interface Start Interruption - * + Time Encoder Interface Start DMA - * + Time OCRef clear configuration - * + Time External Clock configuration - * + Time Complementary signal bread and dead time configuration - * + Time Master and Slave synchronization configuration + * + Timer Base Initialization + * + Timer Base Start + * + Timer Base Start Interruption + * + Timer Base Start DMA + * + Timer Output Compare/PWM Initialization + * + Timer Output Compare/PWM Channel Configuration + * + Timer Output Compare/PWM Start + * + Timer Output Compare/PWM Start Interruption + * + Timer Output Compare/PWM Start DMA + * + Timer Input Capture Initialization + * + Timer Input Capture Channel Configuration + * + Timer Input Capture Start + * + Timer Input Capture Start Interruption + * + Timer Input Capture Start DMA + * + Timer One Pulse Initialization + * + Timer One Pulse Channel Configuration + * + Timer One Pulse Start + * + Timer Encoder Interface Initialization + * + Timer Encoder Interface Start + * + Timer Encoder Interface Start Interruption + * + Timer Encoder Interface Start DMA + * + Timer OCRef clear configuration + * + Timer External Clock configuration + * + Timer Complementary signal bread and dead time configuration + * + Timer Master and Slave synchronization configuration @verbatim ============================================================================== ##### TIMER Generic features ##### @@ -53,13 +53,21 @@ ##### How to use this driver ##### ================================================================================ [..] - (#) Enable the TIM interface clock using - __TIMx_CLK_ENABLE(); - - (#) TIM pins configuration - (++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); - (++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); + (#) Initialize the TIM low level resources by implementing the following functions + depending from feature used : + (++) Time Base : HAL_TIM_Base_MspInit() + (++) Input Capture : HAL_TIM_IC_MspInit() + (++) Output Compare : HAL_TIM_OC_MspInit() + (++) PWM generation : HAL_TIM_PWM_MspInit() + (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() + (++) Encoder mode output : HAL_TIM_Encoder_MspInit() + + (#) Initialize the TIM low level resources : + (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); + (##) TIM pins configuration + (+++) Enable the clock for the TIM GPIOs using the following function: + __HAL_RCC_GPIOx_CLK_ENABLE(); + (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), using the following function: @@ -93,7 +101,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -127,7 +135,7 @@ * @{ */ -/** @defgroup TIM +/** @addtogroup TIM * @brief TIM HAL module driver * @{ */ @@ -151,26 +159,37 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t TIM_ITRx); +static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource); static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState); static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -/* Private functions ---------------------------------------------------------*/ +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,TIM_SlaveConfigTypeDef * sSlaveConfig); -/** @defgroup TIM_Private_Functions +/*******************************************************************************/ +/* Exported functions ---------------------------------------------------------*/ +/*******************************************************************************/ + +/** @addtogroup TIM_Exported_Functions * @{ */ -/** @defgroup TIM_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions +/** @addtogroup TIM_Exported_Functions_Group1 + * @brief Time Base functions * @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the TIM. - (+) De-initialize the TIM. + ============================================================================== + ##### Timer Base functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM base. + (+) De-initialize the TIM base. + (+) Start the Timer Base. + (+) Stop the Timer Base. + (+) Start the Timer Base and enable interrupt. + (+) Stop the Timer Base and disable interrupt. + (+) Start the Timer Base and enable DMA transfer. + (+) Stop the Timer Base and disable DMA transfer. @endverbatim * @{ @@ -178,14 +197,13 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { /* Check the TIM handle allocation */ - if(htim == HAL_NULL) + if(htim == NULL) { return HAL_ERROR; } @@ -194,6 +212,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); if(htim->State == HAL_TIM_STATE_RESET) { @@ -214,429 +234,304 @@ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) } /** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM Output Compare handle + * @brief DeInitializes the TIM Base peripheral + * @param htim : TIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) +HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) { - /* Check the TIM handle allocation */ - if(htim == HAL_NULL) - { - return HAL_ERROR; - } - /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_OC_MspInit(htim); - } - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Base_MspDeInit(htim); - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + /* Release Lock */ + __HAL_UNLOCK(htim); + return HAL_OK; } /** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM handle - * @retval HAL status + * @brief Initializes the TIM Base MSP. + * @param htim : TIM handle + * @retval None */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) { - /* Check the TIM handle allocation */ - if(htim == HAL_NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspInit could be implemented in the user file + */ +} - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - return HAL_OK; +/** + * @brief DeInitializes TIM Base MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Base_MspDeInit could be implemented in the user file + */ } /** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM Input Capture handle + * @brief Starts the TIM Base generation. + * @param htim : TIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) { - /* Check the TIM handle allocation */ - if(htim == HAL_NULL) - { - return HAL_ERROR; - } - /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); - } /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the TIM state*/ + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Change the TIM state*/ htim->State= HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: TIM OnePulse handle - * @param OnePulseMode: Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated. + * @brief Stops the TIM Base generation. + * @param htim : TIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { - /* Check the TIM handle allocation */ - if(htim == HAL_NULL) - { - return HAL_ERROR; - } - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); - } + assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Set the TIM state */ htim->State= HAL_TIM_STATE_BUSY; - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the TIM state*/ + /* Change the TIM state*/ htim->State= HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim: TIM Encoder Interface handle - * @param sConfig: TIM Encoder Interface configuration structure + * @brief Starts the TIM Base generation in interrupt mode. + * @param htim : TIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the TIM handle allocation */ - if(htim == HAL_NULL) - { - return HAL_ERROR; - } - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - - if(htim->State == HAL_TIM_STATE_RESET) - { - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); - } - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Reset the SMS bits */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); - - /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); - tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; + /* Enable the TIM Update interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } /** - * @brief DeInitializes the TIM Base peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @brief Stops the TIM Base generation in interrupt mode. + * @param htim : TIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ +HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) +{ /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + /* Disable the TIM Update interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - + + /* Return function status */ return HAL_OK; } /** - * @brief DeInitializes the TIM peripheral - * @param htim: TIM Output Compare handle + * @brief Starts the TIM Base generation in DMA mode. + * @param htim : TIM handle + * @param pData: The source Buffer address. + * @param Length: The length of data to be transferred from memory to peripheral. * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) +HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) { /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); + if((htim->State == HAL_TIM_STATE_BUSY)) + { + return HAL_BUSY; + } + else if((htim->State == HAL_TIM_STATE_READY)) + { + if((pData == 0 ) && (Length > 0)) + { + return HAL_ERROR; + } + else + { + htim->State = HAL_TIM_STATE_BUSY; + } + } + /* Set the DMA Period elapsed callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; + + /* Set the DMA error callback */ + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; + /* Enable the DMA Stream */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - /* Release Lock */ - __HAL_UNLOCK(htim); + /* Enable the TIM Update DMA request */ + __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } /** - * @brief DeInitializes the TIM peripheral - * @param htim: TIM handle + * @brief Stops the TIM Base generation in DMA mode. + * @param htim : TIM handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) { /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ + assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); + + /* Disable the TIM Update DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); + + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ return HAL_OK; } /** - * @brief DeInitializes the TIM peripheral - * @param htim: TIM Input Capture handle - * @retval HAL status + * @} */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} +/** @addtogroup TIM_Exported_Functions_Group2 + * @brief Time Output Compare functions + * +@verbatim + ============================================================================== + ##### Timer Output Compare functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Output Compare. + (+) De-initialize the TIM Output Compare. + (+) Start the Timer Output Compare. + (+) Stop the Timer Output Compare. + (+) Start the Timer Output Compare and enable interrupt. + (+) Stop the Timer Output Compare and disable interrupt. + (+) Start the Timer Output Compare and enable DMA transfer. + (+) Stop the Timer Output Compare and disable DMA transfer. + +@endverbatim + * @{ + */ /** - * @brief DeInitializes the TIM One Pulse - * @param htim: TIM One Pulse handle + * @brief Initializes the TIM Output Compare according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim: TIM Output Compare handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim) { + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA*/ + HAL_TIM_OC_MspInit(htim); + } + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the Output Compare */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; return HAL_OK; } /** - * @brief DeInitializes the TIM Encoder interface - * @param htim: TIM Encoder handle + * @brief DeInitializes the TIM peripheral + * @param htim: TIM Output Compare handle * @retval HAL status */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - + + htim->State = HAL_TIM_STATE_BUSY; + /* Disable the TIM Peripheral Clock */ __HAL_TIM_DISABLE(htim); - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); - - /* Change TIM state */ + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OC_MspDeInit(htim); + + /* Change TIM state */ htim->State = HAL_TIM_STATE_RESET; - + /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} + __HAL_UNLOCK(htim); -/** - * @brief Initializes the TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ + return HAL_OK; } /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: TIM handle + * @param htim : TIM handle * @retval None */ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) @@ -647,441 +542,118 @@ __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) } /** - * @brief Initializes the TIM PWM MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief Initializes the TIM INput Capture MSP. - * @param htim: TIM handle + * @brief DeInitializes TIM Output Compare MSP. + * @param htim : TIM handle * @retval None */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) { /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file + the HAL_TIM_OC_MspDeInit could be implemented in the user file */ } /** - * @brief Initializes the TIM One Pulse MSP. - * @param htim: TIM handle - * @retval None + * @brief Starts the TIM Output Compare signal generation. + * @param htim : TIM handle + * @param Channel: TIM Channel to be enabled. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ + /* Enable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + + /* Enable the Peripheral */ + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; } /** - * @brief DeInitializes TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None + * @brief Stops the TIM Output Compare signal generation. + * @param htim : TIM handle + * @param Channel: TIM Channel to be disabled. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) +HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + + /* Disable the Output compare channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; } /** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim: TIM handle - * @retval None + * @brief Starts the TIM Output Compare signal generation in interrupt mode. + * @param htim : TIM handle + * @param Channel: TIM Channel to be enabled. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) +HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIM_Group2 I/O operation functions - * @brief I/O operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - (+) Start the Output Compare/PWM. - (+) Stop the Output Compare/PWM. - (+) Start the Output Compare/PWM and enable interrupts. - (+) Stop the Output Compare/PWM and disable interrupts. - (+) Start the Output Compare/PWM and enable DMA transfers. - (+) Stop the Output Compare/PWM and disable DMA transfers. - (+) Start the Input Capture measurement. - (+) Stop the Input Capture. - (+) Start the Input Capture and enable interrupts. - (+) Stop the Input Capture and disable interrupts. - (+) Start the Input Capture and enable DMA transfers. - (+) Stop the Input Capture and disable DMA transfers. - (+) Start the One Pulse generation. - (+) Stop the One Pulse. - (+) Start the One Pulse and enable interrupts. - (+) Stop the One Pulse and disable interrupts. - (+) Start the Encoder Interface. - (+) Stop the Encoder Interface. - (+) Start the Encoder Interface and enable interrupts. - (+) Stop the Encoder Interface and disable interrupts. - (+) Start the Encoder Interface and enable DMA transfers. - (+) Stop the Encoder Interface and disable DMA transfers. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - (+) Handle TIM interrupt request. - -@endverbatim - * @{ - */ -/** - * @brief Starts the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - htim->State= HAL_TIM_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the TIM state*/ - htim->State= HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - if((htim->State == HAL_TIM_STATE_BUSY)) - { - return HAL_BUSY; - } - else if((htim->State == HAL_TIM_STATE_READY)) - { - if((pData == 0 ) && (Length > 0)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; - - /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length); - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim : pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - switch (Channel) { case TIM_CHANNEL_1: - { + { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); } break; - + default: break; - } + } /* Enable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); @@ -1095,8 +667,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1109,55 +680,54 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); } break; - + default: - break; - } - + break; + } + /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1172,106 +742,105 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } switch (Channel) { case TIM_CHANNEL_1: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1284,58 +853,174 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; - } - + } + /* Disable the Output compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group3 + * @brief Time PWM functions + * +@verbatim + ============================================================================== + ##### Timer PWM functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM OPWM. + (+) De-initialize the TIM PWM. + (+) Start the Timer PWM. + (+) Stop the Timer PWM. + (+) Start the Timer PWM and enable interrupt. + (+) Stop the Timer PWM and disable interrupt. + (+) Start the Timer PWM and enable DMA transfer. + (+) Stop the Timer PWM and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM PWM Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim : TIM handle + * @retval HAL status + */ + + +HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the PWM */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim : TIM handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_PWM_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + return HAL_OK; } +/** + * @brief Initializes the TIM PWM MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM PWM MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_PWM_MspDeInit could be implemented in the user file + */ +} + /** * @brief Starts the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1351,18 +1036,17 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Stops the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1372,27 +1056,26 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ +{ /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1405,55 +1088,54 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); } break; - + default: break; - } - + } + /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1466,62 +1148,62 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); } break; - + default: - break; + break; } - + /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Return function status */ return HAL_OK; -} +} /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. + * @param pData: The source Buffer address. This buffer contains the values + * which will be loaded inside the capture/compare registers. * @param Length: The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ @@ -1529,106 +1211,105 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if(((uint32_t)pData == 0 ) && (Length > 0)) + if(((uint32_t)pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } switch (Channel) { case TIM_CHANNEL_1: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length); - + /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length); - + /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length); - + /* Enable the TIM Output Capture/Compare 3 request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length); - + /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1641,58 +1322,171 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; - } - + } + /* Disable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); - + /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; - + /* Return function status */ return HAL_OK; } - + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group4 + * @brief Time Input Capture functions + * +@verbatim + ============================================================================== + ##### Timer Input Capture functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Input Capture. + (+) De-initialize the TIM Input Capture. + (+) Start the Timer Input Capture. + (+) Stop the Timer Input Capture. + (+) Start the Timer Input Capture and enable interrupt. + (+) Stop the Timer Input Capture and disable interrupt. + (+) Start the Timer Input Capture and enable DMA transfer. + (+) Stop the Timer Input Capture and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Input Capture Time base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim: TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Init the base time for the input capture */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM peripheral + * @param htim: TIM Input Capture handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_IC_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM INput Capture MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM Input Capture MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_IC_MspDeInit could be implemented in the user file + */ +} /** * @brief Starts the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1705,21 +1499,20 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); /* Return function status */ - return HAL_OK; -} + return HAL_OK; +} /** * @brief Stops the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1729,24 +1522,23 @@ HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel) * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ +{ /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + /* Disable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1759,54 +1551,53 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Enable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Enable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); } break; - + default: break; - } + } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); + __HAL_TIM_ENABLE(htim); /* Return function status */ - return HAL_OK; -} + return HAL_OK; +} /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel : TIM Channels to be disabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1819,55 +1610,54 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) { /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - + switch (Channel) { case TIM_CHANNEL_1: - { + { /* Disable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); } break; - + case TIM_CHANNEL_2: { /* Disable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); } break; - + case TIM_CHANNEL_3: { /* Disable the TIM Capture/Compare 3 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); } break; - + case TIM_CHANNEL_4: { /* Disable the TIM Capture/Compare 4 interrupt */ __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); } break; - + default: - break; - } - + break; + } + /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel : TIM Channels to be enabled * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1883,200 +1673,322 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - + if((htim->State == HAL_TIM_STATE_BUSY)) { return HAL_BUSY; } else if((htim->State == HAL_TIM_STATE_READY)) { - if((pData == 0 ) && (Length > 0)) + if((pData == 0 ) && (Length > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } - + } + switch (Channel) { case TIM_CHANNEL_1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); - - /* Enable the TIM Capture/Compare 1 DMA request */ + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length); + + /* Enable the TIM Capture/Compare 1 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); } break; - + case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length); - + /* Enable the TIM Capture/Compare 2 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); } break; - + case TIM_CHANNEL_3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length); - + /* Enable the TIM Capture/Compare 3 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); } break; - + case TIM_CHANNEL_4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length); - + /* Enable the TIM Capture/Compare 4 DMA request */ __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); } break; - + default: break; } /* Enable the Input Capture channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - + /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - + __HAL_TIM_ENABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @brief Stops the TIM Input Capture measurement on in DMA mode. + * @param htim : TIM handle + * @param Channel : TIM Channels to be disabled + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +{ + /* Check the parameters */ + assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); + assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); + + switch (Channel) + { + case TIM_CHANNEL_1: + { + /* Disable the TIM Capture/Compare 1 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); + } + break; + + case TIM_CHANNEL_2: + { + /* Disable the TIM Capture/Compare 2 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); + } + break; + + case TIM_CHANNEL_3: + { + /* Disable the TIM Capture/Compare 3 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); + } + break; + + case TIM_CHANNEL_4: + { + /* Disable the TIM Capture/Compare 4 DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); + } + break; + + default: + break; + } + + /* Disable the Input Capture channel */ + TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Change the htim state */ + htim->State = HAL_TIM_STATE_READY; + /* Return function status */ return HAL_OK; } /** - * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param Channel : TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group5 + * @brief Time One Pulse functions + * +@verbatim + ============================================================================== + ##### Timer One Pulse functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM One Pulse. + (+) De-initialize the TIM One Pulse. + (+) Start the Timer One Pulse. + (+) Stop the Timer One Pulse. + (+) Start the Timer One Pulse and enable interrupt. + (+) Stop the Timer One Pulse and disable interrupt. + (+) Start the Timer One Pulse and enable DMA transfer. + (+) Stop the Timer One Pulse and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM One Pulse Time Base according to the specified + * parameters in the TIM_HandleTypeDef and create the associated handle. + * @param htim: TIM OnePulse handle + * @param OnePulseMode: Select the One pulse mode. + * This parameter can be one of the following values: + * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. + * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) +{ + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); + assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); + assert_param(IS_TIM_OPM_MODE(OnePulseMode)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_OnePulse_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Configure the Time base in the One Pulse Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Reset the OPM Bit */ + htim->Instance->CR1 &= ~TIM_CR1_OPM; + + /* Configure the OPM Mode */ + htim->Instance->CR1 |= OnePulseMode; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM One Pulse + * @param htim: TIM One Pulse handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_OnePulse_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + +/** + * @brief Initializes the TIM One Pulse MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspInit could be implemented in the user file + */ +} + +/** + * @brief DeInitializes TIM One Pulse MSP. + * @param htim : TIM handle + * @retval None */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) +__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) { - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - } - break; - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - } - break; - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - } - break; - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - } - break; - - default: - break; - } - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file + */ } /** * @brief Starts the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param OutputChannel : TIM Channels to be enabled. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * This parameter is not used since both channels TIM_CHANNEL_1 and + * TIM_CHANNEL_2 are automatically selected. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { - /* Enable the Capture compare and the Input Capture channels + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - + /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param OutputChannel : TIM Channels to be disable. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -2085,26 +1997,25 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t Outpu */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { - /* Disable the Capture compare and the Input Capture channels + /* Disable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - + /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - + __HAL_TIM_DISABLE(htim); + /* Return function status */ return HAL_OK; } /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param OutputChannel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -2113,32 +2024,31 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output */ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { - /* Enable the Capture compare and the Input Capture channels + /* Enable the Capture compare and the Input Capture channels (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together + + No need to enable the counter, it's enabled automatically by hardware (the counter starts in response to a stimulus and generate a pulse */ - + /* Enable the TIM Capture/Compare 1 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - + /* Enable the TIM Capture/Compare 2 interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - + + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); + /* Return function status */ return HAL_OK; } /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param OutputChannel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -2147,35 +2057,202 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t Ou */ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Return function status */ - return HAL_OK; + /* Disable the TIM Capture/Compare 1 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); + + /* Disable the TIM Capture/Compare 2 interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); + + /* Disable the Capture compare and the Input Capture channels + (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) + if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and + if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output + in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); + TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); + + /* Disable the Peripheral */ + __HAL_TIM_DISABLE(htim); + + /* Return function status */ + return HAL_OK; +} + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group6 + * @brief Time Encoder functions + * +@verbatim + ============================================================================== + ##### Timer Encoder functions ##### + ============================================================================== + [..] + This section provides functions allowing to: + (+) Initialize and configure the TIM Encoder. + (+) De-initialize the TIM Encoder. + (+) Start the Timer Encoder. + (+) Stop the Timer Encoder. + (+) Start the Timer Encoder and enable interrupt. + (+) Stop the Timer Encoder and disable interrupt. + (+) Start the Timer Encoder and enable DMA transfer. + (+) Stop the Timer Encoder and disable DMA transfer. + +@endverbatim + * @{ + */ +/** + * @brief Initializes the TIM Encoder Interface and create the associated handle. + * @param htim: TIM Encoder Interface handle + * @param sConfig: TIM Encoder Interface configuration structure + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) +{ + uint32_t tmpsmcr = 0; + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Check the TIM handle allocation */ + if(htim == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); + assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); + assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); + assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); + assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); + assert_param(IS_TIM_PERIOD(htim->Init.Period)); + assert_param(IS_TIM_PRESCALER(htim->Init.Prescaler)); + + if(htim->State == HAL_TIM_STATE_RESET) + { + /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ + HAL_TIM_Encoder_MspInit(htim); + } + + /* Set the TIM state */ + htim->State= HAL_TIM_STATE_BUSY; + + /* Reset the SMS bits */ + htim->Instance->SMCR &= ~TIM_SMCR_SMS; + + /* Configure the Time base in the Encoder Mode */ + TIM_Base_SetConfig(htim->Instance, &htim->Init); + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = htim->Instance->CCMR1; + + /* Get the TIMx CCER register value */ + tmpccer = htim->Instance->CCER; + + /* Set the encoder Mode */ + tmpsmcr |= sConfig->EncoderMode; + + /* Select the Capture Compare 1 and the Capture Compare 2 as input */ + tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); + tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8)); + + /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ + tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); + tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); + tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8); + tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12); + + /* Set the TI1 and the TI2 Polarities */ + tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); + tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); + tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4); + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Write to TIMx CCMR1 */ + htim->Instance->CCMR1 = tmpccmr1; + + /* Write to TIMx CCER */ + htim->Instance->CCER = tmpccer; + + /* Initialize the TIM state*/ + htim->State= HAL_TIM_STATE_READY; + + return HAL_OK; +} + +/** + * @brief DeInitializes the TIM Encoder interface + * @param htim: TIM Encoder handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) +{ + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(htim->Instance)); + + htim->State = HAL_TIM_STATE_BUSY; + + /* Disable the TIM Peripheral Clock */ + __HAL_TIM_DISABLE(htim); + + /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ + HAL_TIM_Encoder_MspDeInit(htim); + + /* Change TIM state */ + htim->State = HAL_TIM_STATE_RESET; + + /* Release Lock */ + __HAL_UNLOCK(htim); + + return HAL_OK; +} + + +/** + * @brief Initializes the TIM Encoder Interface MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspInit could be implemented in the user file + */ +} + + +/** + * @brief DeInitializes TIM Encoder Interface MSP. + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_Encoder_MspDeInit could be implemented in the user file + */ } /** * @brief Starts the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2212,12 +2289,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channe /** * @brief Stops the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2255,12 +2332,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2303,12 +2380,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Cha /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2354,12 +2431,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL : TIM Channel 1 and 2 selected * @param pData1: The destination Buffer address for IC1. * @param pData2: The destination Buffer address for IC2. * @param Length: The length of data to be transferred from TIM peripheral to memory. @@ -2391,10 +2468,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch case TIM_CHANNEL_1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length); @@ -2413,10 +2490,10 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch case TIM_CHANNEL_2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); @@ -2434,19 +2511,19 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch case TIM_CHANNEL_ALL: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length); /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length); @@ -2474,12 +2551,12 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -2527,8 +2604,139 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha * @} */ -/** @defgroup TIM_Group3 Peripheral Control functions - * @brief Peripheral Control functions +/** @addtogroup TIM_Exported_Functions_Group7 + * @brief IRQ handler management + * +@verbatim + ============================================================================== + ##### IRQ handler management ##### + ============================================================================== + [..] + This section provides Timer IRQ handler function. + +@endverbatim + * @{ + */ +/** + * @brief This function handles TIM interrupts requests. + * @param htim: TIM handle + * @retval None + */ +void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) +{ + /* Capture compare 1 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) !=RESET) + { + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + } + /* Capture compare 2 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + /* Input capture event */ + if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 3 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* Capture compare 4 event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + /* Input capture event */ + if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) + { + HAL_TIM_IC_CaptureCallback(htim); + } + /* Output compare event */ + else + { + HAL_TIM_OC_DelayElapsedCallback(htim); + HAL_TIM_PWM_PulseFinishedCallback(htim); + } + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; + } + } + /* TIM Update event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); + HAL_TIM_PeriodElapsedCallback(htim); + } + } + /* TIM Trigger detection event */ + if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) + { + if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET) + { + __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); + HAL_TIM_TriggerCallback(htim); + } + } +} + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group8 + * @brief Peripheral Control functions * @verbatim ============================================================================== @@ -2536,26 +2744,25 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha ============================================================================== [..] This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. + (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. (+) Configure External Clock source. (+) Configure Master and the Slave synchronization. (+) Configure the DMA Burst Mode. - + @endverbatim * @{ */ /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param sConfig: TIM Output Compare configuration structure * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) @@ -2564,13 +2771,12 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_OC_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Check input state */ - __HAL_LOCK(htim); - + __HAL_LOCK(htim); + htim->State = HAL_TIM_STATE_BUSY; - + switch (Channel) { case TIM_CHANNEL_1: @@ -2610,7 +2816,7 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT } htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); + __HAL_UNLOCK(htim); return HAL_OK; } @@ -2618,15 +2824,14 @@ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitT /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param sConfig: TIM Input Capture configuration structure * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel) @@ -2637,11 +2842,11 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - + __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; - + if (Channel == TIM_CHANNEL_1) { /* TI1 Configuration */ @@ -2649,7 +2854,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; @@ -2661,7 +2866,7 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT /* TI2 Configuration */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - TIM_TI2_SetConfig(htim->Instance, + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); @@ -2676,8 +2881,8 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT { /* TI3 Configuration */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, + + TIM_TI3_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); @@ -2692,31 +2897,30 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT { /* TI4 Configuration */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, + + TIM_TI4_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC4PSC Bits */ htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; /* Set the IC4PSC value */ htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8); } - + htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - - return HAL_OK; + + return HAL_OK; } /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param sConfig: TIM PWM configuration structure * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: @@ -2729,14 +2933,15 @@ HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitT HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel) { __HAL_LOCK(htim); - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); + + /* Check the parameters */ + assert_param(IS_TIM_CHANNELS(Channel)); assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); + assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); htim->State = HAL_TIM_STATE_BUSY; - + switch (Channel) { case TIM_CHANNEL_1: @@ -2744,77 +2949,76 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); - + /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - + /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; htim->Instance->CCMR1 |= sConfig->OCFastMode; } break; - + case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); - + /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - + /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; htim->Instance->CCMR1 |= sConfig->OCFastMode << 8; } break; - + case TIM_CHANNEL_3: { assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); - + /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - + /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; + htim->Instance->CCMR2 |= sConfig->OCFastMode; } break; - + case TIM_CHANNEL_4: { assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); - + /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - + /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; + htim->Instance->CCMR2 |= sConfig->OCFastMode << 8; } break; - + default: - break; + break; } htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - + return HAL_OK; } /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param sConfig: TIM One Pulse configuration structure * @param OutputChannel: TIM Channels to be enabled. * This parameter can be one of the following values: @@ -2829,41 +3033,41 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_Init HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel) { TIM_OC_InitTypeDef temp1; - + /* Check the parameters */ assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - if(OutputChannel != InputChannel) + if(OutputChannel != InputChannel) { __HAL_LOCK(htim); htim->State = HAL_TIM_STATE_BUSY; - /* Extract the Ouput compare configuration from sConfig structure */ + /* Extract the Ouput compare configuration from sConfig structure */ temp1.OCMode = sConfig->OCMode; temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - + temp1.OCPolarity = sConfig->OCPolarity; + switch (OutputChannel) { case TIM_CHANNEL_1: { assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); + + TIM_OC1_SetConfig(htim->Instance, &temp1); } break; case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + TIM_OC2_SetConfig(htim->Instance, &temp1); } break; default: - break; - } + break; + } switch (InputChannel) { case TIM_CHANNEL_1: @@ -2872,15 +3076,15 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC1PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ + + /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; } @@ -2888,31 +3092,31 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O case TIM_CHANNEL_2: { assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - + TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, sConfig->ICSelection, sConfig->ICFilter); - + /* Reset the IC2PSC Bits */ htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; /* Select the Trigger source */ htim->Instance->SMCR &= ~TIM_SMCR_TS; htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ + + /* Select the Slave Mode */ htim->Instance->SMCR &= ~TIM_SMCR_SMS; htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; } break; - + default: - break; + break; } - + htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); - + return HAL_OK; } else @@ -2922,28 +3126,27 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O } /** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral + * @param htim : TIM handle * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. * This parameters can be on of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_DCR + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_DCR * @param BurstRequestSrc: TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -2954,7 +3157,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer: The Buffer address. * @param BurstLength: DMA Burst length. This parameter can be one value - * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS . * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -2989,58 +3192,58 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC1: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC2: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC3: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC4: { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMADelayPulseCplt; + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_TRIGGER: @@ -3049,21 +3252,21 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1); } break; default: break; } /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - + htim->Instance->DCR = BurstBaseAddress | BurstLength; + /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - + __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); + htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -3071,9 +3274,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t } /** - * @brief Stops the TIM DMA Burst mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @brief Stops the TIM DMA Burst mode + * @param htim : TIM handle * @param BurstRequestSrc: TIM DMA Request sources to disable * @retval HAL status */ @@ -3082,6 +3284,42 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); @@ -3090,28 +3328,27 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B } /** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory + * @param htim : TIM handle * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. * This parameters can be on of the following values: - * @arg TIM_DMABase_CR1 - * @arg TIM_DMABase_CR2 - * @arg TIM_DMABase_SMCR - * @arg TIM_DMABase_DIER - * @arg TIM_DMABase_SR - * @arg TIM_DMABase_EGR - * @arg TIM_DMABase_CCMR1 - * @arg TIM_DMABase_CCMR2 - * @arg TIM_DMABase_CCER - * @arg TIM_DMABase_CNT - * @arg TIM_DMABase_PSC - * @arg TIM_DMABase_ARR - * @arg TIM_DMABase_CCR1 - * @arg TIM_DMABase_CCR2 - * @arg TIM_DMABase_CCR3 - * @arg TIM_DMABase_CCR4 - * @arg TIM_DMABase_DCR + * @arg TIM_DMABASE_CR1 + * @arg TIM_DMABASE_CR2 + * @arg TIM_DMABASE_SMCR + * @arg TIM_DMABASE_DIER + * @arg TIM_DMABASE_SR + * @arg TIM_DMABASE_EGR + * @arg TIM_DMABASE_CCMR1 + * @arg TIM_DMABASE_CCMR2 + * @arg TIM_DMABASE_CCER + * @arg TIM_DMABASE_CNT + * @arg TIM_DMABASE_PSC + * @arg TIM_DMABASE_ARR + * @arg TIM_DMABASE_CCR1 + * @arg TIM_DMABASE_CCR2 + * @arg TIM_DMABASE_CCR3 + * @arg TIM_DMABASE_CCR4 + * @arg TIM_DMABASE_DCR * @param BurstRequestSrc: TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source @@ -3122,7 +3359,7 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source * @param BurstBuffer: The Buffer address. * @param BurstLength: DMA Burst length. This parameter can be one value - * between TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. + * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS . * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, @@ -3140,99 +3377,99 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } else if((htim->State == HAL_TIM_STATE_READY)) { - if((BurstBuffer == 0 ) && (BurstLength > 0)) + if((BurstBuffer == 0 ) && (BurstLength > 0)) { - return HAL_ERROR; + return HAL_ERROR; } else { htim->State = HAL_TIM_STATE_BUSY; } - } + } switch(BurstRequestSrc) { case TIM_DMA_UPDATE: - { + { /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC1: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC2: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC3: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = HAL_TIM_DMAError ; + htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_CC4: - { + { /* Set the DMA Period elapsed callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = HAL_TIM_DMACaptureCplt; - + htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; case TIM_DMA_TRIGGER: - { + { /* Set the DMA Period elapsed callback */ htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - + /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = HAL_TIM_DMAError ; - + htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; + /* Enable the DMA Stream */ - HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); + HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1); } break; default: - break; + break; } /* configure the DMA Burst Mode */ - htim->Instance->DCR = BurstBaseAddress | BurstLength; - + htim->Instance->DCR = BurstBaseAddress | BurstLength; + /* Enable the TIM DMA Request */ __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - + htim->State = HAL_TIM_STATE_READY; /* Return function status */ @@ -3240,9 +3477,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B } /** - * @brief Stop the DMA burst reading - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @brief Stop the DMA burst reading + * @param htim : TIM handle * @param BurstRequestSrc: TIM DMA Request sources to disable. * @retval HAL status */ @@ -3251,59 +3487,94 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu /* Check the parameters */ assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); + /* Abort the DMA transfer (at least disable the DMA channel) */ + switch(BurstRequestSrc) + { + case TIM_DMA_UPDATE: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]); + } + break; + case TIM_DMA_CC1: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]); + } + break; + case TIM_DMA_CC2: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]); + } + break; + case TIM_DMA_CC3: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]); + } + break; + case TIM_DMA_CC4: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]); + } + break; + case TIM_DMA_TRIGGER: + { + HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]); + } + break; + default: + break; + } + /* Disable the TIM Update DMA request */ __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - + /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @brief Generate a software event - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param EventSource: specifies the event source. * This parameter can be one of the following values: * @arg TIM_EventSource_Update: Timer update Event source - * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source + * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EventSource_Trigger: Timer Trigger Event source - * @note TIM6 can only generate an update event. + * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source + * @arg TIM_EVENTSOURCE_TRIGGER : Timer Trigger Event source + * @note TIM6 can only generate an update event. * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) { /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - + /* Process Locked */ __HAL_LOCK(htim); - + /* Change the TIM state */ htim->State = HAL_TIM_STATE_BUSY; /* Set the event sources */ htim->Instance->EGR = EventSource; - + /* Change the TIM state */ htim->State = HAL_TIM_STATE_READY; - + __HAL_UNLOCK(htim); /* Return function status */ - return HAL_OK; + return HAL_OK; } /** * @brief Configures the OCRef clear feature - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. + * contains the OCREF clear feature and parameters for the TIM peripheral. * @param Channel: specifies the TIM Channel. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -3311,9 +3582,9 @@ HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventS * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status - */ + */ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel) -{ +{ /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); assert_param(IS_TIM_CHANNELS(Channel)); @@ -3321,25 +3592,25 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - + /* Process Locked */ __HAL_LOCK(htim); - + htim->State = HAL_TIM_STATE_BUSY; - + if(sClearInputConfig->ClearInputSource == TIM_CLEARINPUTSOURCE_ETR) { - TIM_ETR_SetConfig(htim->Instance, + TIM_ETR_SetConfig(htim->Instance, sClearInputConfig->ClearInputPrescaler, sClearInputConfig->ClearInputPolarity, sClearInputConfig->ClearInputFilter); } - + switch (Channel) { case TIM_CHANNEL_1: - { - if(sClearInputConfig->ClearInputState != RESET) + { + if(sClearInputConfig->ClearInputState != RESET) { /* Enable the Ocref clear feature for Channel 1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE; @@ -3347,7 +3618,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp else { /* Disable the Ocref clear feature for Channel 1 */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; + htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE; } } break; @@ -3409,8 +3680,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp /** * @brief Configures the clock source to be used - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status @@ -3543,8 +3813,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockCo /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module.. + * @param htim : TIM handle * @param TI1_Selection: Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: @@ -3568,155 +3837,44 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S tmpcr2 &= ~TIM_CR2_TI1S; /* Set the the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module.. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the ) and the Slave - * mode (Disable, Reset, Gated, Trigger, External clock mode 1). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) -{ - uint32_t tmpsmcr = 0; - uint32_t tmpccmr1 = 0; - uint32_t tmpccer = 0; - - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - - } - break; - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - } - break; - - case TIM_TS_ITR0: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR1: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR2: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - case TIM_TS_ITR3: - { - /* Check the parameter */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - } - break; - - default: - break; - } + tmpcr2 |= TI1_Selection; + + /* Write to TIMxCR2 */ + htim->Instance->CR2 = tmpcr2; + + return HAL_OK; +} + +/** + * @brief Configures the TIM in Slave mode + * @param htim : TIM handle + * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + htim->State = HAL_TIM_STATE_BUSY; + + /* Configuration in slave mode */ + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Disable Trigger Interrupt */ + __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + /* Set the new state */ htim->State = HAL_TIM_STATE_READY; __HAL_UNLOCK(htim); @@ -3724,10 +3882,45 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TI return HAL_OK; } +/** + * @brief Configures the TIM in Slave mode in interrupt mode + * @param htim : TIM handle. + * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + /* Check the parameters */ + assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); + assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); + assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger)); + + __HAL_LOCK(htim); + + htim->State = HAL_TIM_STATE_BUSY; + + TIM_SlaveTimer_SetConfig(htim, sSlaveConfig); + + /* Enable Trigger Interrupt */ + __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); + + /* Disable Trigger DMA request */ + __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); + + htim->State = HAL_TIM_STATE_READY; + + __HAL_UNLOCK(htim); + + return HAL_OK; +} + /** * @brief Read the captured value from Capture Compare unit - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module.. + * @param htim : TIM handle * @param Channel: TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -3799,7 +3992,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) * @} */ -/** @defgroup TIM_Group4 TIM Callbacks functions +/** @addtogroup TIM_Exported_Functions_Group9 * @brief TIM Callbacks functions * @verbatim @@ -3820,8 +4013,7 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel) /** * @brief Period elapsed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @retval None */ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) @@ -3833,8 +4025,7 @@ __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) } /** * @brief Output Compare callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) @@ -3857,8 +4048,7 @@ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) /** * @brief PWM Pulse finished callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) @@ -3870,8 +4060,7 @@ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) /** * @brief Hall Trigger detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. + * @param htim : TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) @@ -3880,241 +4069,107 @@ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) the HAL_TIM_TriggerCallback could be implemented in the user file */ } - -/** - * @brief Timer error callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIM_Group5 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC state - * @param htim: TIM Ouput Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode state - * @param htim: TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @} - */ - -/** @defgroup TIM_Group6 TIM IRQ handler management - * @brief IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim: TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - /* Capture compare 1 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET) - { - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00) - { - HAL_TIM_IC_CaptureCallback(htim); - } - /* Output compare event */ - else - { - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE); - HAL_TIM_PeriodElapsedCallback(htim); - } - } - /* TIM Trigger detection event */ - if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET) - { - if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET) - { - __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER); - HAL_TIM_TriggerCallback(htim); - } - } + +/** + * @brief Timer error callback in non blocking mode + * @param htim : TIM handle + * @retval None + */ +__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) +{ + /* NOTE : This function Should not be modified, when the callback is needed, + the HAL_TIM_ErrorCallback could be implemented in the user file + */ +} + +/** + * @} + */ + +/** @addtogroup TIM_Exported_Functions_Group10 + * @brief Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State functions ##### + ============================================================================== + [..] + This subsection permits to get in run-time the status of the peripheral + and the data flow. + +@endverbatim + * @{ + */ + +/** + * @brief Return the TIM Base state + * @param htim : TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM OC state + * @param htim: TIM Ouput Compare handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM PWM state + * @param htim : TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Input Capture state + * @param htim : TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM One Pulse Mode state + * @param htim: TIM OPM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; +} + +/** + * @brief Return the TIM Encoder Mode state + * @param htim : TIM handle + * @retval HAL state + */ +HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim) +{ + return htim->State; } + + /** * @brief TIM DMA error callback * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) +void TIM_DMAError(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; @@ -4125,42 +4180,88 @@ void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; htim->State= HAL_TIM_STATE_READY; + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } HAL_TIM_PWM_PulseFinishedCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } /** * @brief TIM DMA Capture complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma : pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ -void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) { TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - htim->State= HAL_TIM_STATE_READY; - - HAL_TIM_IC_CaptureCallback(htim); - + + htim->State= HAL_TIM_STATE_READY; + + if (hdma == htim->hdma[TIM_DMA_ID_CC1]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; + } + else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) + { + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; + } + + HAL_TIM_IC_CaptureCallback(htim); + + htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; } + /** * @} */ - +/** + * @} + */ +/*************************************************************/ +/* Private functions */ +/*************************************************************/ + +/** @defgroup TIM_Private_Functions TIM Private Functions + * @{ + */ /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma: pointer to DMA handle. + * @param hdma : pointer to DMA handle. * @retval None */ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) @@ -4175,7 +4276,7 @@ static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) /** * @brief TIM DMA Trigger callback. - * @param hdma: pointer to DMA handle. + * @param hdma : pointer to DMA handle. * @retval None */ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) @@ -4189,7 +4290,8 @@ static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) /** * @brief Time Base configuration - * @param TIMx: TIM periheral + * @param TIMx : TIM peripheral + * @param Structure : TIM Base configuration structure * @retval None */ static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4198,7 +4300,7 @@ static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structur tmpcr1 = TIMx->CR1; /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if(IS_TIM_CC3_INSTANCE(TIMx) != RESET) + if(IS_TIM_CC1_INSTANCE(TIMx) != RESET) { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); @@ -4456,11 +4558,11 @@ static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4); + tmpccmr1 |= ((TIM_ICFilter << 4) & TIM_CCMR1_IC1F); /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; + tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; @@ -4536,11 +4638,11 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12); + tmpccmr1 |= ((TIM_ICFilter << 12) & TIM_CCMR1_IC2F); /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4); + tmpccer |= ((TIM_ICPolarity << 4) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; @@ -4616,11 +4718,11 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= (TIM_ICFilter << 4); + tmpccmr2 |= ((TIM_ICFilter << 4) & TIM_CCMR2_IC3F); /* Select the Polarity and set the CC3E Bit */ tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= (TIM_ICPolarity << 8); + tmpccer |= ((TIM_ICPolarity << 8) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -4661,11 +4763,11 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 /* Set the filter */ tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= (TIM_ICFilter << 12); + tmpccmr2 |= ((TIM_ICFilter << 12) & TIM_CCMR2_IC4F); /* Select the Polarity and set the CC4E Bit */ tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= (TIM_ICPolarity << 12); + tmpccer |= ((TIM_ICPolarity << 12) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); /* Write to TIMx CCMR2 and CCER registers */ TIMx->CCMR2 = tmpccmr2; @@ -4687,7 +4789,7 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) +static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource) { uint32_t tmpsmcr = 0; @@ -4696,7 +4798,7 @@ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t TIM_ITRx) /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= TIM_ITRx | TIM_SLAVEMODE_EXTERNAL1; + tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1; /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; } @@ -4752,8 +4854,7 @@ static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Chan uint32_t tmp = 0; /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); + assert_param(IS_TIM_CCX_INSTANCE(TIMx,Channel)); tmp = TIM_CCER_CC1E << Channel; @@ -4763,6 +4864,146 @@ static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Chan /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << Channel); } +/** + * @brief Set the slave timer configuration. + * @param htim : TIM handle + * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * contains the selected trigger (internal trigger input, filtered + * timer input or external trigger input) and the ) and the Slave + * mode (Disable, Reset, Gated, Trigger, External clock mode 1). + * @retval None + */ +static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, + TIM_SlaveConfigTypeDef * sSlaveConfig) +{ + uint32_t tmpsmcr = 0; + uint32_t tmpccmr1 = 0; + uint32_t tmpccer = 0; + + /* Get the TIMx SMCR register value */ + tmpsmcr = htim->Instance->SMCR; + + /* Reset the Trigger Selection Bits */ + tmpsmcr &= ~TIM_SMCR_TS; + /* Set the Input Trigger source */ + tmpsmcr |= sSlaveConfig->InputTrigger; + + /* Reset the slave mode Bits */ + tmpsmcr &= ~TIM_SMCR_SMS; + /* Set the slave mode */ + tmpsmcr |= sSlaveConfig->SlaveMode; + + /* Write to TIMx SMCR */ + htim->Instance->SMCR = tmpsmcr; + + /* Configure the trigger prescaler, filter, and polarity */ + switch (sSlaveConfig->InputTrigger) + { + case TIM_TS_ETRF: + { + /* Check the parameters */ + assert_param(IS_TIM_ETR_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + /* Configure the ETR Trigger source */ + TIM_ETR_SetConfig(htim->Instance, + sSlaveConfig->TriggerPrescaler, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI1F_ED: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + tmpccer = htim->Instance->CCER; + htim->Instance->CCER &= ~TIM_CCER_CC1E; + tmpccmr1 = htim->Instance->CCMR1; + + /* Set the filter */ + tmpccmr1 &= ~TIM_CCMR1_IC1F; + tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4); + + /* Write to TIMx CCMR1 and CCER registers */ + htim->Instance->CCMR1 = tmpccmr1; + htim->Instance->CCER = tmpccer; + + } + break; + + case TIM_TS_TI1FP1: + { + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI1 Filter and Polarity */ + TIM_TI1_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_TI2FP2: + { + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); + assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); + + /* Configure TI2 Filter and Polarity */ + TIM_TI2_ConfigInputStage(htim->Instance, + sSlaveConfig->TriggerPolarity, + sSlaveConfig->TriggerFilter); + } + break; + + case TIM_TS_ITR0: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR1: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR2: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + case TIM_TS_ITR3: + { + /* Check the parameter */ + assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); + } + break; + + default: + break; + } +} + +/** + * @} + */ + +/** + * @} + */ /** * @} @@ -4777,3 +5018,4 @@ static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t Chan * @} */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h index 1e4109465d5..0fbe0c86e92 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_tim.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,12 +50,19 @@ * @{ */ -/** @addtogroup TIM +/** @defgroup TIM TIM (Timer) * @{ */ /* Exported types ------------------------------------------------------------*/ + /** @defgroup TIM_Exported_Types TIM Exported Types + * @{ + */ + +/** @defgroup TIM_Base_Configuration TIM base configuration structure + * @{ + */ /** * @brief TIM Time base Configuration Structure definition */ @@ -74,8 +81,15 @@ typedef struct uint32_t ClockDivision; /*!< Specifies the clock division. This parameter can be a value of @ref TIM_ClockDivision */ } TIM_Base_InitTypeDef; +/** + * @} + */ -/** +/** @defgroup TIM_Output_Configuration TIM output compare configuration structure + * @{ + */ + +/** * @brief TIM Output Compare Configuration Structure definition */ @@ -95,7 +109,13 @@ typedef struct @note This parameter is valid only in PWM1 and PWM2 mode. */ } TIM_OC_InitTypeDef; +/** + * @} + */ +/** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure + * @{ + */ /** * @brief TIM One Pulse Mode Configuration Structure definition */ @@ -120,8 +140,13 @@ typedef struct uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_OnePulse_InitTypeDef; +/** + * @} + */ - +/** @defgroup TIM_Input_Capture TIM input capture configuration structure + * @{ + */ /** * @brief TIM Input Capture Configuration Structure definition */ @@ -140,7 +165,13 @@ typedef struct uint32_t ICFilter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_IC_InitTypeDef; +/** + * @} + */ +/** @defgroup TIM_Encoder TIM encoder configuration structure + * @{ + */ /** * @brief TIM Encoder Configuration Structure definition */ @@ -174,7 +205,13 @@ typedef struct uint32_t IC2Filter; /*!< Specifies the input capture filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ } TIM_Encoder_InitTypeDef; +/** + * @} + */ +/** @defgroup TIM_Clock_Configuration TIM clock configuration structure + * @{ + */ /** * @brief Clock Configuration Handle Structure definition */ @@ -189,7 +226,13 @@ typedef struct uint32_t ClockFilter; /*!< TIM clock filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_ClockConfigTypeDef; +/** + * @} + */ +/** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure + * @{ + */ /** * @brief Clear Input Configuration Handle Structure definition */ @@ -206,7 +249,13 @@ typedef struct uint32_t ClearInputFilter; /*!< TIM Clear Input filter. This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_ClearInputConfigTypeDef; +/** + * @} + */ +/** @defgroup TIM_Slave_Configuratio TIM slave configuration structure + * @{ + */ /** * @brief TIM Slave configuration Structure definition */ @@ -223,7 +272,13 @@ typedef struct { This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ }TIM_SlaveConfigTypeDef; +/** + * @} + */ +/** @defgroup TIM_State_Definition TIM state definition + * @{ + */ /** * @brief HAL State structures definition */ @@ -235,7 +290,13 @@ typedef enum HAL_TIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */ HAL_TIM_STATE_ERROR = 0x04 /*!< Reception process is ongoing */ }HAL_TIM_StateTypeDef; +/** + * @} + */ +/** @defgroup TIM_Active_Channel TIM active channel definition + * @{ + */ /** * @brief HAL Active channel structures definition */ @@ -247,7 +308,13 @@ typedef enum HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /*!< The active channel is 4 */ HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /*!< All active channels cleared */ }HAL_TIM_ActiveChannel; +/** + * @} + */ +/** @defgroup TIM_Handle TIM handler + * @{ + */ /** * @brief TIM Time Base Handle Structure definition */ @@ -261,13 +328,25 @@ typedef struct HAL_LockTypeDef Lock; /*!< Locking object */ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ }TIM_HandleTypeDef; +/** + * @} + */ +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants +/** @defgroup TIM_Exported_Constants TIM Exported Constants * @{ */ -/** @defgroup TIM_Input_Channel_Polarity + +#define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFF) + +#define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFF) + + +/** @defgroup TIM_Input_Channel_Polarity Input channel polarity * @{ */ #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /*!< Polarity for TIx source */ @@ -277,7 +356,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @} */ -/** @defgroup TIM_ETR_Polarity +/** @defgroup TIM_ETR_Polarity ETR polarity * @{ */ #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ @@ -286,7 +365,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @} */ -/** @defgroup TIM_ETR_Prescaler +/** @defgroup TIM_ETR_Prescaler ETR prescaler * @{ */ #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /*!< No prescaler is used */ @@ -297,7 +376,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @} */ -/** @defgroup TIM_Counter_Mode +/** @defgroup TIM_Counter_Mode Counter mode * @{ */ #define TIM_COUNTERMODE_UP ((uint32_t)0x0000) @@ -305,31 +384,33 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS - -#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) || \ - ((MODE) == TIM_COUNTERMODE_DOWN) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3)) /** * @} - */ + */ +#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ + ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ + ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) + + + -/** @defgroup TIM_ClockDivision +/** @defgroup TIM_ClockDivision Clock division * @{ */ #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000) #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) - -#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV2) || \ - ((DIV) == TIM_CLOCKDIVISION_DIV4)) /** * @} */ +#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ + ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) -/** @defgroup TIM_Output_Compare_and_PWM_modes + +/** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes * @{ */ #define TIM_OCMODE_TIMING ((uint32_t)0x0000) @@ -340,106 +421,98 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) - -#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \ - ((MODE) == TIM_OCMODE_PWM2)) - -#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) || \ - ((MODE) == TIM_OCMODE_ACTIVE) || \ - ((MODE) == TIM_OCMODE_INACTIVE) || \ - ((MODE) == TIM_OCMODE_TOGGLE) || \ - ((MODE) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((MODE) == TIM_OCMODE_FORCED_INACTIVE)) /** * @} */ -/** @defgroup TIM_Output_Compare_State +#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ + ((__MODE__) == TIM_OCMODE_PWM2)) + +#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ + ((__MODE__) == TIM_OCMODE_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_INACTIVE) || \ + ((__MODE__) == TIM_OCMODE_TOGGLE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ + ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) + + +/** @defgroup TIM_Output_Compare_State Output compare state * @{ */ #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000) #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) - -#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTSTATE_ENABLE)) /** * @} - */ -/** @defgroup TIM_Output_Fast_State + */ + +/** @defgroup TIM_Output_Fast_State Output fast state * @{ */ #define TIM_OCFAST_DISABLE ((uint32_t)0x0000) #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) - -#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \ - ((STATE) == TIM_OCFAST_ENABLE)) /** * @} */ -/** @defgroup TIM_Output_Compare_N_State +#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ + ((__STATE__) == TIM_OCFAST_ENABLE)) + +/** @defgroup TIM_Output_Compare_N_State Output compare N state * @{ */ #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000) #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) - -#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \ - ((STATE) == TIM_OUTPUTNSTATE_ENABLE)) /** * @} - */ + */ -/** @defgroup TIM_Output_Compare_Polarity +/** @defgroup TIM_Output_Compare_Polarity Output compare polarity * @{ */ #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000) #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) - -#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \ - ((POLARITY) == TIM_OCPOLARITY_LOW)) /** * @} */ +#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ + ((__POLARITY__) == TIM_OCPOLARITY_LOW)) -/** @defgroup TIM_Channel +/** @defgroup TIM_Channel TIM channels * @{ */ - #define TIM_CHANNEL_1 ((uint32_t)0x0000) #define TIM_CHANNEL_2 ((uint32_t)0x0004) #define TIM_CHANNEL_3 ((uint32_t)0x0008) #define TIM_CHANNEL_4 ((uint32_t)0x000C) #define TIM_CHANNEL_ALL ((uint32_t)0x0018) - -#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_ALL)) - -#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) - -#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2)) /** * @} - */ + */ + +#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4) || \ + ((__CHANNEL__) == TIM_CHANNEL_ALL)) -/** @defgroup TIM_Input_Capture_Polarity +#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)) + + +/** @defgroup TIM_Input_Capture_Polarity Input capture polarity * @{ */ #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE - -#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) || \ - ((POLARITY) == TIM_ICPOLARITY_FALLING) || \ - ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE)) /** * @} - */ + */ +#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) + -/** @defgroup TIM_Input_Capture_Selection +/** @defgroup TIM_Input_Capture_Selection Input capture selection * @{ */ #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be @@ -448,52 +521,53 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state connected to IC2, IC1, IC4 or IC3, respectively */ #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \ - ((SELECTION) == TIM_ICSELECTION_TRC)) +#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ + ((__SELECTION__) == TIM_ICSELECTION_TRC)) /** * @} */ -/** @defgroup TIM_Input_Capture_Prescaler +/** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler * @{ */ #define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input */ #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ - -#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \ - ((PRESCALER) == TIM_ICPSC_DIV2) || \ - ((PRESCALER) == TIM_ICPSC_DIV4) || \ - ((PRESCALER) == TIM_ICPSC_DIV8)) /** * @} - */ + */ +#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ + ((__PRESCALER__) == TIM_ICPSC_DIV8)) -/** @defgroup TIM_One_Pulse_Mode +/** @defgroup TIM_One_Pulse_Mode One pulse mode * @{ */ #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000) -#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \ - ((MODE) == TIM_OPMODE_REPETITIVE)) /** * @} */ -/** @defgroup TIM_Encoder_Mode +#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ + ((__MODE__) == TIM_OPMODE_REPETITIVE)) + +/** @defgroup TIM_Encoder_Mode Encoder_Mode * @{ */ #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) -#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \ - ((MODE) == TIM_ENCODERMODE_TI2) || \ - ((MODE) == TIM_ENCODERMODE_TI12)) /** * @} - */ -/** @defgroup TIM_Interrupt_definition + */ +#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ + ((__MODE__) == TIM_ENCODERMODE_TI2) || \ + ((__MODE__) == TIM_ENCODERMODE_TI12)) + +/** @defgroup TIM_Interrupt_definition Interrupt definition * @{ */ #define TIM_IT_UPDATE (TIM_DIER_UIE) @@ -502,20 +576,20 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_IT_CC3 (TIM_DIER_CC3IE) #define TIM_IT_CC4 (TIM_DIER_CC4IE) #define TIM_IT_TRIGGER (TIM_DIER_TIE) - -#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFFA0) == 0x00000000) && ((IT) != 0x00000000)) - -#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) || \ - ((IT) == TIM_IT_CC1) || \ - ((IT) == TIM_IT_CC2) || \ - ((IT) == TIM_IT_CC3) || \ - ((IT) == TIM_IT_CC4) || \ - ((IT) == TIM_IT_TRIGGER)) /** * @} */ +#define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFFA0) == 0x00000000) && ((__IT__) != 0x00000000)) + +#define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \ + ((__IT__) == TIM_IT_CC1) || \ + ((__IT__) == TIM_IT_CC2) || \ + ((__IT__) == TIM_IT_CC3) || \ + ((__IT__) == TIM_IT_CC4) || \ + ((__IT__) == TIM_IT_TRIGGER)) -/** @defgroup TIM_DMA_sources + +/** @defgroup TIM_DMA_sources DMA sources * @{ */ #define TIM_DMA_UPDATE (TIM_DIER_UDE) @@ -524,28 +598,29 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_DMA_CC3 (TIM_DIER_CC3DE) #define TIM_DMA_CC4 (TIM_DIER_CC4DE) #define TIM_DMA_TRIGGER (TIM_DIER_TDE) -#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFA0FF) == 0x00000000) && ((SOURCE) != 0x00000000)) - /** * @} */ +#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FF) == 0x00000000) && ((__SOURCE__) != 0x00000000)) + + -/** @defgroup TIM_Event_Source +/** @defgroup TIM_Event_Source Event sources * @{ */ -#define TIM_EventSource_Update TIM_EGR_UG -#define TIM_EventSource_CC1 TIM_EGR_CC1G -#define TIM_EventSource_CC2 TIM_EGR_CC2G -#define TIM_EventSource_CC3 TIM_EGR_CC3G -#define TIM_EventSource_CC4 TIM_EGR_CC4G -#define TIM_EventSource_Trigger TIM_EGR_TG -#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFFA0) == 0x00000000) && ((SOURCE) != 0x00000000)) - +#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG +#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G +#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G +#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G +#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G +#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /** * @} - */ + */ +#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0) == 0x00000000) && ((__SOURCE__) != 0x00000000)) + -/** @defgroup TIM_Flag_definition +/** @defgroup TIM_Flag_definition Flag definition * @{ */ #define TIM_FLAG_UPDATE (TIM_SR_UIF) @@ -558,50 +633,51 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) - -#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) || \ - ((FLAG) == TIM_FLAG_CC1) || \ - ((FLAG) == TIM_FLAG_CC2) || \ - ((FLAG) == TIM_FLAG_CC3) || \ - ((FLAG) == TIM_FLAG_CC4) || \ - ((FLAG) == TIM_FLAG_TRIGGER) || \ - ((FLAG) == TIM_FLAG_CC1OF) || \ - ((FLAG) == TIM_FLAG_CC2OF) || \ - ((FLAG) == TIM_FLAG_CC3OF) || \ - ((FLAG) == TIM_FLAG_CC4OF)) /** * @} */ +#define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \ + ((__FLAG__) == TIM_FLAG_CC1) || \ + ((__FLAG__) == TIM_FLAG_CC2) || \ + ((__FLAG__) == TIM_FLAG_CC3) || \ + ((__FLAG__) == TIM_FLAG_CC4) || \ + ((__FLAG__) == TIM_FLAG_TRIGGER) || \ + ((__FLAG__) == TIM_FLAG_CC1OF) || \ + ((__FLAG__) == TIM_FLAG_CC2OF) || \ + ((__FLAG__) == TIM_FLAG_CC3OF) || \ + ((__FLAG__) == TIM_FLAG_CC4OF)) -/** @defgroup TIM_Clock_Source + +/** @defgroup TIM_Clock_Source Clock source * @{ */ -#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) -#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) -#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) -#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) -#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) -#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) -#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) - -#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR0) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ITR3) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1ED) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI1) || \ - ((CLOCK) == TIM_CLOCKSOURCE_TI2) || \ - ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1)) +#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) +#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) +#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000) +#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) +#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) +#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) +#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) /** * @} - */ + */ + +#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ + ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) -/** @defgroup TIM_Clock_Polarity + +/** @defgroup TIM_Clock_Polarity Clock polarity * @{ */ #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ @@ -609,112 +685,105 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ - -#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_RISING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_FALLING) || \ - ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE)) /** * @} */ -/** @defgroup TIM_Clock_Prescaler +#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ + ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) + +/** @defgroup TIM_Clock_Prescaler Clock prescaler * @{ */ #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ - -#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8)) -/** - * @} - */ - -/** @defgroup TIM_Clock_Filter - * @{ - */ -#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF) /** * @} */ +#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) + + +/* Check clock filter */ +#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) -/** @defgroup TIM_ClearInput_Source +/** @defgroup TIM_ClearInput_Source Clear input source * @{ */ #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001) #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000) - -#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) || \ - ((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)) /** * @} */ -/** @defgroup TIM_ClearInput_Polarity +#define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) || \ + ((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR)) + + +/** @defgroup TIM_ClearInput_Polarity Clear input polarity * @{ */ #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) /** * @} */ +#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ + ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) + -/** @defgroup TIM_ClearInput_Prescaler +/** @defgroup TIM_ClearInput_Prescaler Clear input prescaler * @{ */ #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8)) /** * @} */ +#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) + -/** @defgroup TIM_ClearInput_Filter - * @{ - */ +/* Check IC filter */ #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ -/** @defgroup TIM_Master_Mode_Selection +/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) - -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ - ((SOURCE) == TIM_TRGO_ENABLE) || \ - ((SOURCE) == TIM_TRGO_UPDATE) || \ - ((SOURCE) == TIM_TRGO_OC1) || \ - ((SOURCE) == TIM_TRGO_OC1REF) || \ - ((SOURCE) == TIM_TRGO_OC2REF) || \ - ((SOURCE) == TIM_TRGO_OC3REF) || \ - ((SOURCE) == TIM_TRGO_OC4REF)) - - +#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) /** * @} - */ -/** @defgroup TIM_Slave_Mode + */ +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) + + + +/** @defgroup TIM_Slave_Mode Slave mode * @{ */ #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000) @@ -722,28 +791,28 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005) #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006) #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007) - -#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \ - ((MODE) == TIM_SLAVEMODE_GATED) || \ - ((MODE) == TIM_SLAVEMODE_RESET) || \ - ((MODE) == TIM_SLAVEMODE_TRIGGER) || \ - ((MODE) == TIM_SLAVEMODE_EXTERNAL1)) /** * @} - */ + */ +#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ + ((__MODE__) == TIM_SLAVEMODE_GATED) || \ + ((__MODE__) == TIM_SLAVEMODE_RESET) || \ + ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ + ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) -/** @defgroup TIM_Master_Slave_Mode +/** @defgroup TIM_Master_Slave_Mode Master slave mode * @{ */ #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080) #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000) -#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((STATE) == TIM_MASTERSLAVEMODE_DISABLE)) /** * @} - */ -/** @defgroup TIM_Trigger_Selection + */ +#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ + ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) + +/** @defgroup TIM_Trigger_Selection Trigger selection * @{ */ #define TIM_TS_ITR0 ((uint32_t)0x0000) @@ -755,28 +824,25 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_TS_TI2FP2 ((uint32_t)0x0060) #define TIM_TS_ETRF ((uint32_t)0x0070) #define TIM_TS_NONE ((uint32_t)0xFFFF) -#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_TI1F_ED) || \ - ((SELECTION) == TIM_TS_TI1FP1) || \ - ((SELECTION) == TIM_TS_TI2FP2) || \ - ((SELECTION) == TIM_TS_ETRF)) -#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3)) -#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \ - ((SELECTION) == TIM_TS_ITR1) || \ - ((SELECTION) == TIM_TS_ITR2) || \ - ((SELECTION) == TIM_TS_ITR3) || \ - ((SELECTION) == TIM_TS_NONE)) /** * @} - */ - -/** @defgroup TIM_Trigger_Polarity + */ +#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_TI1F_ED) || \ + ((__SELECTION__) == TIM_TS_TI1FP1) || \ + ((__SELECTION__) == TIM_TS_TI2FP2) || \ + ((__SELECTION__) == TIM_TS_ETRF)) +#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ + ((__SELECTION__) == TIM_TS_ITR1) || \ + ((__SELECTION__) == TIM_TS_ITR2) || \ + ((__SELECTION__) == TIM_TS_ITR3) || \ + ((__SELECTION__) == TIM_TS_NONE)) + + +/** @defgroup TIM_Trigger_Polarity Trigger polarity * @{ */ #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ @@ -784,147 +850,140 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ - -#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE )) /** * @} */ +#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ + ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) -/** @defgroup TIM_Trigger_Prescaler + +/** @defgroup TIM_Trigger_Prescaler Trigger prescaler * @{ */ #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ - -#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8)) /** * @} */ +#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ + ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) + + +/* Check trigger filter */ +#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) -/** @defgroup TIM_Trigger_Filter - * @{ - */ -#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF) -/** - * @} - */ - /** @defgroup TIM_TI1_Selection + /** @defgroup TIM_TI1_Selection TI1 selection * @{ */ #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000) #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) - -#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \ - ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION)) /** * @} - */ - -/** @defgroup TIM_DMA_Base_address - * @{ */ -#define TIM_DMABase_CR1 (0x00000000) -#define TIM_DMABase_CR2 (0x00000001) -#define TIM_DMABase_SMCR (0x00000002) -#define TIM_DMABase_DIER (0x00000003) -#define TIM_DMABase_SR (0x00000004) -#define TIM_DMABase_EGR (0x00000005) -#define TIM_DMABase_CCMR1 (0x00000006) -#define TIM_DMABase_CCMR2 (0x00000007) -#define TIM_DMABase_CCER (0x00000008) -#define TIM_DMABase_CNT (0x00000009) -#define TIM_DMABase_PSC (0x0000000A) -#define TIM_DMABase_ARR (0x0000000B) -#define TIM_DMABase_CCR1 (0x0000000D) -#define TIM_DMABase_CCR2 (0x0000000E) -#define TIM_DMABase_CCR3 (0x0000000F) -#define TIM_DMABase_CCR4 (0x00000010) -#define TIM_DMABase_DCR (0x00000012) -#define TIM_DMABase_OR (0x00000013) -#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \ - ((BASE) == TIM_DMABase_CR2) || \ - ((BASE) == TIM_DMABase_SMCR) || \ - ((BASE) == TIM_DMABase_DIER) || \ - ((BASE) == TIM_DMABase_SR) || \ - ((BASE) == TIM_DMABase_EGR) || \ - ((BASE) == TIM_DMABase_CCMR1) || \ - ((BASE) == TIM_DMABase_CCMR2) || \ - ((BASE) == TIM_DMABase_CCER) || \ - ((BASE) == TIM_DMABase_CNT) || \ - ((BASE) == TIM_DMABase_PSC) || \ - ((BASE) == TIM_DMABase_ARR) || \ - ((BASE) == TIM_DMABase_CCR1) || \ - ((BASE) == TIM_DMABase_CCR2) || \ - ((BASE) == TIM_DMABase_CCR3) || \ - ((BASE) == TIM_DMABase_CCR4) || \ - ((BASE) == TIM_DMABase_DCR) || \ - ((BASE) == TIM_DMABase_OR)) -/** - * @} - */ +#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ + ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) -/** @defgroup TIM_DMA_Burst_Length + +/** @defgroup TIM_DMA_Base_address DMA base address * @{ */ -#define TIM_DMABurstLength_1Transfer (0x00000000) -#define TIM_DMABurstLength_2Transfers (0x00000100) -#define TIM_DMABurstLength_3Transfers (0x00000200) -#define TIM_DMABurstLength_4Transfers (0x00000300) -#define TIM_DMABurstLength_5Transfers (0x00000400) -#define TIM_DMABurstLength_6Transfers (0x00000500) -#define TIM_DMABurstLength_7Transfers (0x00000600) -#define TIM_DMABurstLength_8Transfers (0x00000700) -#define TIM_DMABurstLength_9Transfers (0x00000800) -#define TIM_DMABurstLength_10Transfers (0x00000900) -#define TIM_DMABurstLength_11Transfers (0x00000A00) -#define TIM_DMABurstLength_12Transfers (0x00000B00) -#define TIM_DMABurstLength_13Transfers (0x00000C00) -#define TIM_DMABurstLength_14Transfers (0x00000D00) -#define TIM_DMABurstLength_15Transfers (0x00000E00) -#define TIM_DMABurstLength_16Transfers (0x00000F00) -#define TIM_DMABurstLength_17Transfers (0x00001000) -#define TIM_DMABurstLength_18Transfers (0x00001100) -#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \ - ((LENGTH) == TIM_DMABurstLength_2Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_3Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_4Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_5Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_6Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_7Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_8Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_9Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_10Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_11Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_12Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_13Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_14Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_15Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_16Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_17Transfers) || \ - ((LENGTH) == TIM_DMABurstLength_18Transfers)) +#define TIM_DMABASE_CR1 (0x00000000) +#define TIM_DMABASE_CR2 (0x00000001) +#define TIM_DMABASE_SMCR (0x00000002) +#define TIM_DMABASE_DIER (0x00000003) +#define TIM_DMABASE_SR (0x00000004) +#define TIM_DMABASE_EGR (0x00000005) +#define TIM_DMABASE_CCMR1 (0x00000006) +#define TIM_DMABASE_CCMR2 (0x00000007) +#define TIM_DMABASE_CCER (0x00000008) +#define TIM_DMABASE_CNT (0x00000009) +#define TIM_DMABASE_PSC (0x0000000A) +#define TIM_DMABASE_ARR (0x0000000B) +#define TIM_DMABASE_CCR1 (0x0000000D) +#define TIM_DMABASE_CCR2 (0x0000000E) +#define TIM_DMABASE_CCR3 (0x0000000F) +#define TIM_DMABASE_CCR4 (0x00000010) +#define TIM_DMABASE_DCR (0x00000012) +#define TIM_DMABASE_OR (0x00000013) /** * @} - */ - -/** @defgroup TIM_Input_Capture_Filer_Value + */ +#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ + ((__BASE__) == TIM_DMABASE_CR2) || \ + ((__BASE__) == TIM_DMABASE_SMCR) || \ + ((__BASE__) == TIM_DMABASE_DIER) || \ + ((__BASE__) == TIM_DMABASE_SR) || \ + ((__BASE__) == TIM_DMABASE_EGR) || \ + ((__BASE__) == TIM_DMABASE_CCMR1) || \ + ((__BASE__) == TIM_DMABASE_CCMR2 ) || \ + ((__BASE__) == TIM_DMABASE_CCER) || \ + ((__BASE__) == TIM_DMABASE_CNT) || \ + ((__BASE__) == TIM_DMABASE_PSC) || \ + ((__BASE__) == TIM_DMABASE_ARR) || \ + ((__BASE__) == TIM_DMABASE_CCR1) || \ + ((__BASE__) == TIM_DMABASE_CCR2) || \ + ((__BASE__) == TIM_DMABASE_CCR3) || \ + ((__BASE__) == TIM_DMABASE_CCR4) || \ + ((__BASE__) == TIM_DMABASE_DCR) || \ + ((__BASE__) == TIM_DMABASE_OR)) + + +/** @defgroup TIM_DMA_Burst_Length DMA burst length * @{ */ -#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) +#define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000) +#define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100) +#define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200) +#define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300) +#define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400) +#define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500) +#define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600) +#define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700) +#define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800) +#define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900) +#define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00) +#define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00) +#define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00) +#define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00) +#define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00) +#define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00) +#define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000) +#define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100) /** * @} - */ - -/** @defgroup DMA_Handle_index + */ +#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ + ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS )) + + +/* Check IC filter */ +#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF) + +/** @defgroup DMA_Handle_index DMA handle index * @{ */ #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /*!< Index of the DMA handle used for Update DMA requests */ @@ -937,7 +996,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @} */ -/** @defgroup Channel_CC_State +/** @defgroup Channel_CC_State Channel state * @{ */ #define TIM_CCx_ENABLE ((uint32_t)0x0001) @@ -951,35 +1010,35 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macro +/** @defgroup TIM_Exported_Macro TIM Exported Macro * @{ */ /** @brief Reset UART handle state - * @param __HANDLE__: TIM handle + * @param __HANDLE__ : TIM handle * @retval None */ #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) /** * @brief Enable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ : TIM handle * @retval None */ #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) /* The counter of a timer instance is disabled only if all the CCx channels have been disabled */ -#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) /** * @brief Disable the TIM peripheral. - * @param __HANDLE__: TIM handle + * @param __HANDLE__ : TIM handle * @retval None */ #define __HAL_TIM_DISABLE(__HANDLE__) \ do { \ - if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \ + if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \ { \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ } \ @@ -992,28 +1051,40 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) -#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) +#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) -#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) -#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) +#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) +#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) -#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \ +#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) -#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \ +#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) +#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\ + ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P))) + +#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ +(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ + ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ + ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) + /** * @brief Sets the TIM Capture Compare Register value on runtime without * calling another time ConfigChannel function. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @param __CHANNEL__ : TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1023,12 +1094,12 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @param __COMPARE__: specifies the Capture Compare register new value. * @retval None */ -#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \ +#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__)) /** * @brief Gets the TIM Capture Compare Register value on runtime - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @param __CHANNEL__ : TIM Channel associated with the capture compare register * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get capture/compare 1 register value @@ -1037,47 +1108,47 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @arg TIM_CHANNEL_4: get capture/compare 4 register value * @retval None */ -#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \ +#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2))) /** * @brief Sets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @param __COUNTER__: specifies the Counter register new value. * @retval None */ -#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) +#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) /** * @brief Gets the TIM Counter Register value on runtime. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @retval None */ -#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT) +#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) /** * @brief Sets the TIM Autoreload Register value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @param __AUTORELOAD__: specifies the Counter register new value. * @retval None */ -#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \ +#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ do{ \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ } while(0) /** * @brief Gets the TIM Autoreload Register value on runtime - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @retval None */ -#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR) +#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) /** * @brief Sets the TIM Clock Division value on runtime without calling * another time any Init function. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @param __CKD__: specifies the clock division value. * This parameter can be one of the following value: * @arg TIM_CLOCKDIVISION_DIV1 @@ -1085,7 +1156,7 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @arg TIM_CLOCKDIVISION_DIV4 * @retval None */ -#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \ +#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ do{ \ (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \ @@ -1093,15 +1164,15 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state } while(0) /** * @brief Gets the TIM Clock Division value on runtime - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @retval None */ -#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) +#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) /** * @brief Sets the TIM Input Capture prescaler on runtime without calling * another time HAL_TIM_IC_ConfigChannel() function. - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @param __CHANNEL__ : TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected @@ -1116,15 +1187,15 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @arg TIM_ICPSC_DIV8: capture is done once every 8 events * @retval None */ -#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \ +#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ do{ \ - __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \ - __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ + TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ } while(0) /** * @brief Gets the TIM Input Capture prescaler on runtime - * @param __HANDLE__: TIM handle. + * @param __HANDLE__ : TIM handle. * @param __CHANNEL__ : TIM Channels to be configured. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: get input capture 1 prescaler value @@ -1133,13 +1204,60 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state * @arg TIM_CHANNEL_4: get input capture 4 prescaler value * @retval None */ -#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \ +#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8) +/** + * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__: TIM handle. + * @note When the URS bit of the TIMx_CR1 register is set, only counter + * overflow/underflow generates an update interrupt or DMA request (if + * enabled) + * @retval None + */ +#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) + +/** + * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register + * @param __HANDLE__: TIM handle. + * @note When the URS bit of the TIMx_CR1 register is reset, any of the + * following events generate an update interrupt or DMA request (if + * enabled): + * Counter overflow/underflow + * Setting the UG bit + * Update generation through the slave mode controller + * @retval None + */ +#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ + ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) + +/** + * @brief Sets the TIM Capture x input polarity on runtime. + * @param __HANDLE__: TIM handle. + * @param __CHANNEL__: TIM Channels to be configured. + * This parameter can be one of the following values: + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected + * @param __POLARITY__: Polarity for TIx source + * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge + * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge + * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge + * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. + * @retval None + */ +#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ + do{ \ + TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ + TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ + }while(0) + /** * @} */ @@ -1147,8 +1265,18 @@ __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state /* Include TIM HAL Extension module */ #include "stm32l0xx_hal_tim_ex.h" +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_Exported_Functions TIM Exported Functions + * @{ + */ + /* Exported functions --------------------------------------------------------*/ /* Time Base functions ********************************************************/ + +/** @defgroup TIM_Exported_Functions_Group1 Timer Base functions + * @brief Time Base functions + * @{ + */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); @@ -1163,7 +1291,18 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); +/** + * @} + */ + + /* Timer Output Compare functions **********************************************/ + +/** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions + * @brief Timer Output Compare functions + * @{ + */ + HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); @@ -1177,8 +1316,17 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + /* Timer PWM functions *********************************************************/ + +/** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions + * @brief Timer PWM functions + * @{ + */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); @@ -1192,8 +1340,16 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ /* Timer Input Capture functions ***********************************************/ + +/** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions + * @brief Timer Input Capture functions + * @{ + */ HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); @@ -1207,8 +1363,16 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); /* Non-Blocking mode: DMA */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ /* Timer One Pulse functions ***************************************************/ + +/** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions + * @brief Timer One Pulse functions + * @{ + */ HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); @@ -1221,7 +1385,16 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t Output HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); +/** + * @} + */ + /* Timer Encoder functions *****************************************************/ + +/** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions + * @brief Timer Encoder functions + * @{ + */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); @@ -1236,10 +1409,27 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + /* Interrupt Handler functions **********************************************/ + +/** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management + * @brief Interrupt Handler functions + * @{ + */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); +/** + * @} + */ /* Control functions *********************************************************/ + +/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions + * @brief Control functions + * @{ + */ HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); @@ -1248,6 +1438,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInp HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); +HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ uint32_t *BurstBuffer, uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); @@ -1257,24 +1448,42 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t Bu HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); +/** + * @} + */ + /* Callback in non blocking modes (Interrupt and DMA) *************************/ + +/** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions + * @brief Callback functions + * @{ + */ void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); +/** + * @} + */ + /* Peripheral State functions **************************************************/ + +/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions + * @brief Peripheral State functions + * @{ + */ HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); -void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma); -void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); +void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); +void TIM_DMAError(DMA_HandleTypeDef *hdma); +void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); /** * @} @@ -1282,8 +1491,16 @@ void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); /** * @} - */ - + */ + +/** + * @} + */ + +/** + * @} + */ + #ifdef __cplusplus } #endif @@ -1291,3 +1508,4 @@ void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); #endif /* __STM32L0xx_HAL_TIM_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.c index 88ecf1ec7dd..118663073f8 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief TIM HAL module driver. * @brief This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -33,11 +33,11 @@ ================================================================================ [..] (#) Enable the TIM interface clock using - __TIMx_CLK_ENABLE(); + __HAL_RCC_TIMx_CLK_ENABLE(); (#) TIM pins configuration (++) Enable the clock for the TIM GPIOs using the following function: - __GPIOx_CLK_ENABLE(); + __HAL_RCC_GPIOx_CLK_ENABLE(); (++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); (#) The external Clock can be configured, if needed (the default clock is the internal clock from the APBx), @@ -55,7 +55,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -89,27 +89,21 @@ * @{ */ -/** @defgroup TIMEx +/** @addtogroup TIMEx * @brief TIMEx HAL module driver * @{ */ #ifdef HAL_TIM_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions +/** @addtogroup TIMEx_Exported_Functions * @{ */ -/** @defgroup TIMEx_Group1 Peripheral Control functions - * @brief Peripheral Control functions +/** @addtogroup TIMEx_Exported_Functions_Group1 + * @brief Peripheral Control functions * @verbatim =============================================================================== @@ -159,65 +153,188 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, return HAL_OK; } + +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ + || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) + +/** + * @brief Configures the remapping of the TIM2, TIM3, TIM21 and TIM22 inputs. + * The channel inputs (T1..T4) and the Trigger input (ETR) of the + * timers can be remaped thanks to this function. When an input is + * mapped, on a GPIO, refer yourself to the GPIO alternate functions + * for more details. + * @note It is not possible to connect TIM2 and TIM21 on + * GPIOB5_AF4 at the same time. + * When selecting TIM3_TI2_GPIOB5_AF4, Channel2 of TIM3 will be + * connected to GPIOB5_AF4 and Channel2 of TIM22 will be connected to + * some other GPIOs. (refer to alternate functions for more details) + * When selecting TIM3_TI2_GPIO_DEF, Channel2 of Timer 3 will be + * connected an GPIO (other than GPIOB5_AF4) and Channel2 of TIM22 + * will be connected to GPIOB5_AF4. + * + * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * the configuration information for TIM module. + * @param Remap: specifies the TIM input remapping source. + * This parameter is a combination of the following values + * depending on TIM instance: + * + * For TIM2, the parameter can have the following values: + * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): + * GPIOA(0)_AF5 or GPIOA(5)_AF2 or + * GPIOA(15)_AF2 or GPIOE(9)_AF2 + * @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48 + * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE + * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output + * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output + * @arg TIM2_TI4_GPIO : TIM2 TI4 connected to GPIO1(default): + * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + * GPIOE(12)_AF0 + * @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1 + * @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2 + * + * For TIM3, the parameter can have the following values: + * @arg TIM3_ETR_GPIO: TIM3 ETR connected to GPIO (default): + * GPIOE(2)_AF2 or GPIOD(2)_AF2 or + * GPIOE(2)AF2 + * @arg TIM3_ETR_HSI: TIM3 ETR connected to HSI + * @arg TIM3_TI1_USB_SOF: TIM3 TI1 connected to USB_SOF (default) + * @arg TIM3_TI1_GPIO: TIM3 TI1 connected to GPIO : + * GPIOE(3)_AF2 or GPIOA(6)_AF2 or + * GPIOC(6)_AF2 or GPIOB(4)_AF2 + * @arg TIM3_TI2_GPIOB5_AF4:TIM3 TI3 connected to GPIOB(5)_AF4 + * (refer to note) + * @arg TIM3_TI2_GPIO_DEF: TIM3 TI3 connected to GPIO (default): + * GPIO_A(7)_AF2 or GPIO_B(5)_AF4 or + * GPIOC(7)_AF2 or GPIOE(7)_AF2 + * @arg TIM3_TI4_GPIO_DEF: TIM3 TI4 connected to GPIO: + * GPIO_B(1)_AF2 or GPIO_E(6)_AF2 + * @arg TIM3_TI4_GPIOC9_AF2:TIM3 TI4 connected to GPIOC(9)_AF2 + * + * For TIM21, the parameter can have the following values: + * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : + * APB2_PC(9)_AF0 or APB2_PA(1)_AF5 + * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output + * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output + * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE + * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO + * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt + * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC + * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock + * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE + * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI + * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT + * @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default): + * GPIOA(2)_AF0 or GPIOB(13)_AF6 or + * GPIOE(5)_AF0 or GPIOD(0)_AF0 + * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): + * GPIOA(3)_AF0 or GPIOB(14)_AF6 or + * GPIOE(6)_AF0 or GPIOD(7)_AF1 + * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output + * + * For TIM22, the parameter can have the following values: + * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE + * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output + * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output + * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): + * GPIOC(8)_AF0 or GPIOA(4)_AF5 + * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): + * GPIOC(6)_AF0 or GPIOA(6)_AF5 or + * GPIOB(4)_AF4 or GPIOE(0)_AF3 + * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output + * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output + * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: + * GPIOC(6)_AF0 or GPIOA(6)_AF5 or + * GPIOB(4)_AF4 or GPIOE(3)_AF0 + * + * @retval HAL status + */ +#else /** - * @brief Configures the TIM2, TIM21 and TIM22 Remapping input capabilities. + * @brief Configures the remapping of the TIM2, TIM21 and TIM22 inputs. + * The channel inputs (T1..T4) and the Trigger input (ETR) of the + * timers can be remaped thanks to this function. When an input is + * mapped, on a GPIO, refer yourself to the GPIO alternate functions + * for more details. + * * @param htim: pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @param TIM_Remap: specifies the TIM input remapping source. - * This parameter can be one of the following values: - * @arg TIM2_ETR_GPIO: TIM2 ETR is connected to GPIO (default) - * @arg TIM2_ETR_HSI48: TIM2 ETR is connected to HSI48 - * @arg TIM2_ETR_LSE: TIM2 ETR is connected to LSE - * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR is connected to COMP2 output - * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR is connected to COMP1 output - * @arg TIM2_TI4_GPIO1: TIM2 TI4 is connected to GPIO1(default) - * @arg TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 - * @arg TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 - * @arg TIM2_TI4_GPIO2: TIM2 TI4 is connected to GPIO2 - * @arg TIM21_ETR_GPIO: TIM21 ETR is connected to GPIO(default) - * @arg TIM21_ETR_COMP2_OUT: TIM21 ETR is connected to COMP2 output - * @arg TIM21_ETR_COMP1_OUT: TIM21 ETR is connected to COMP1 output - * @arg TIM21_ETR_LSE: TIM21 ETR is connected to LSE - * @arg TIM21_TI1_MCO: TIM21 TI1 is connected to MCO - * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 is connected to RTC WAKEUP interrupt - * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 is connected to HSE_RTC - * @arg TIM21_TI1_MSI: TIM21 TI1 is connected to MSI clock - * @arg TIM21_TI1_LSE: TIM21 TI1 is connected to LSE - * @arg TIM21_TI1_LSI: TIM21 TI1 is connected to LSI - * @arg TIM21_TI1_COMP1_OUT: TIM21 TI1 is connected to COMP1_OUT - * @arg TIM21_TI1_GPIO: TIM21 TI1 is connected to GPIO(default) - * @arg TIM21_TI2_GPIO: TIM21 TI2 is connected to GPIO(default) - * @arg TIM21_TI2_COMP2_OUT: TIM21 TI2 is connected to COMP2 output - * @arg TIM22_ETR_LSE: TIM22 ETR is connected to LSE - * @arg TIM22_ETR_COMP2_OUT: TIM22 ETR is connected to COMP2 output - * @arg TIM22_ETR_COMP1_OUT: TIM22 ETR is connected to COMP1 output - * @arg TIM22_ETR_GPIO: TIM22 ETR is connected to GPIO(default) - * @arg TIM22_TI1_GPIO1: TIM22 TI1 is connected to GPIO(default) - * @arg TIM22_TI1_COMP2_OUT: TIM22 TI1 is connected to COMP2 output - * @arg TIM22_TI1_COMP1_OUT: TIM22 TI1 is connected to COMP1 output - * @arg TIM22_TI1_GPIO2: TIM22 TI1 is connected to GPIO + * the configuration information for TIM module. + * @param Remap: specifies the TIM input remapping source. + * This parameter is a combination of the following values + * depending on TIM instance: + * + * For TIM2, the parameter can have the following values: + * @arg TIM2_ETR_GPIO: TIM2 ETR connected to GPIO (default): + * GPIOA(0)_AF5 or GPIOA(5)_AF2 or + * GPIOA(15)_AF2 or GPIOE(9)_AF2 + * @arg TIM2_ETR_HSI48: TIM2 ETR connected to HSI48 + * @arg TIM2_ETR_LSE: TIM2 ETR connected to LSE + * @arg TIM2_ETR_COMP2_OUT: TIM2 ETR connected to COMP2 output + * @arg TIM2_ETR_COMP1_OUT: TIM2 ETR connected to COMP1 output + * @arg TIM2_TI4_GPIO: TIM2 TI4 connected to GPIO1(default): + * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + * GPIOE(12)_AF0 + * @arg TIM2_TI4_COMP1: TIM2 TI4 connected to COMP1 + * @arg TIM2_TI4_COMP2: TIM2 TI4 connected to COMP2 + * @arg TIM2_TI4_GPIO2: TIM2 TI4 connected to GPIO2 : + * GPIOA(3)_AF2 or GPIOB(11)_AF2 or + * GPIOE(12)_AF0 + * + * For TIM21, the parameter can have the following values: + * @arg TIM21_ETR_GPIO: TIM21 ETR connected to GPIO(default) : + * APB2_PC(9)_AF0 or APB2_PA(1)_AF5 + * @arg TIM21_ETR_COMP2_OUT:TIM21 ETR connected to COMP2 output + * @arg TIM21_ETR_COMP1_OUT:TIM21 ETR connected to COMP1 output + * @arg TIM21_ETR_LSE: TIM21 ETR connected to LSE + * @arg TIM21_TI1_MCO: TIM21 TI1 connected to MCO + * @arg TIM21_TI1_RTC_WKUT_IT: TIM21 TI1 connected to RTC WAKEUP interrupt + * @arg TIM21_TI1_HSE_RTC: TIM21 TI1 connected to HSE_RTC + * @arg TIM21_TI1_MSI: TIM21 TI1 connected to MSI clock + * @arg TIM21_TI1_LSE: TIM21 TI1 connected to LSE + * @arg TIM21_TI1_LSI: TIM21 TI1 connected to LSI + * @arg TIM21_TI1_COMP1_OUT:TIM21 TI1 connected to COMP1_OUT + * @arg TIM21_TI1_GPIO: TIM21 TI1 connected to GPIO(default): + * GPIOA(2)_AF0 or GPIOB(13)_AF6 or + * GPIOE(5)_AF0 or GPIOD(0)_AF0 + * @arg TIM21_TI2_GPIO: TIM21 TI2 connected to GPIO(default): + * GPIOA(3)_AF0 or GPIOB(14)_AF6 or + * GPIOE(6)_AF0 or GPIOD(7)_AF1 + * @arg TIM21_TI2_COMP2_OUT:TIM21 TI2 connected to COMP2 output + * + * For TIM22, the parameter can have the following values: + * @arg TIM22_ETR_LSE: TIM22 ETR connected to LSE + * @arg TIM22_ETR_COMP2_OUT:TIM22 ETR connected to COMP2 output + * @arg TIM22_ETR_COMP1_OUT:TIM22 ETR connected to COMP1 output + * @arg TIM22_ETR_GPIO: TIM22 ETR connected to GPIO(default): + * GPIOC(8)_AF0 or GPIOA(4)_AF5 + * @arg TIM22_TI1_GPIO1: TIM22 TI1 connected to GPIO(default): + * GPIOC(6)_AF0 or GPIOA(6)_AF5 or + * GPIOB(4)_AF4 or GPIOE(0)_AF3 + * @arg TIM22_TI1_COMP2_OUT:TIM22 TI1 connected to COMP2 output + * @arg TIM22_TI1_COMP1_OUT:TIM22 TI1 connected to COMP1 output + * @arg TIM22_TI1_GPIO2: TIM22 TI1 connected to GPIO: + * GPIOC(6)_AF0 or GPIOA(6)_AF5 or + * GPIOB(4)_AF4 or GPIOE(3)_AF0 + * * @retval HAL status */ + +#endif /* STM32L07xxx or STM32L08xxx */ + HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) { - __HAL_LOCK(htim); - + + __HAL_LOCK(htim); + /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - /* Change the handler state */ - htim->State = HAL_TIM_STATE_BUSY; - + assert_param(IS_TIM_REMAP(htim->Instance,Remap)); + /* Set the Timer remapping configuration */ - htim->Instance->OR &= (uint32_t)(Remap >> 16); - htim->Instance->OR |= Remap; - - /* Change the handler state */ + htim->Instance->OR = Remap; + htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - + + __HAL_UNLOCK(htim); + return HAL_OK; } diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.h index 6e0e6e73ccb..91983b0ddbf 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tim_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of TIM HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -46,11 +46,11 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" -/** @addtogroup STM32L0xx_HAL +/** @addtogroup STM32L0xx_HAL_Driver * @{ */ -/** @addtogroup TIMEx +/** @defgroup TIMEx TIMEx (Timer extended) * @{ */ @@ -61,133 +61,183 @@ */ typedef struct { uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIMEx_Master_Mode_Selection */ + This parameter can be a value of @ref TIM_Master_Mode_Selection */ uint32_t MasterSlaveMode; /*!< Master/slave mode selection This parameter can be a value of @ref TIM_Master_Slave_Mode */ }TIM_MasterConfigTypeDef; + /* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants +/** @defgroup TIMEx_Exported_Constants TIMEx Exported Constants * @{ */ -/** @defgroup TIMEx_Master_Mode_Selection +/** @defgroup TIMEx_Trigger_Selection Trigger selection * @{ */ -#define TIM_TRGO_RESET ((uint32_t)0x0000) -#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) -#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) -#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) -#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) -#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) -#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) - -#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \ - ((SOURCE) == TIM_TRGO_ENABLE) || \ - ((SOURCE) == TIM_TRGO_UPDATE) || \ - ((SOURCE) == TIM_TRGO_OC1) || \ - ((SOURCE) == TIM_TRGO_OC1REF) || \ - ((SOURCE) == TIM_TRGO_OC2REF) || \ - ((SOURCE) == TIM_TRGO_OC3REF) || \ - ((SOURCE) == TIM_TRGO_OC4REF)) +#define TIM_TRGO_RESET ((uint32_t)0x0000) +#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) +#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) +#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) +#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) +#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) +#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) + +#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ + ((__SOURCE__) == TIM_TRGO_ENABLE) || \ + ((__SOURCE__) == TIM_TRGO_UPDATE) || \ + ((__SOURCE__) == TIM_TRGO_OC1) || \ + ((__SOURCE__) == TIM_TRGO_OC1REF) || \ + ((__SOURCE__) == TIM_TRGO_OC2REF) || \ + ((__SOURCE__) == TIM_TRGO_OC3REF) || \ + ((__SOURCE__) == TIM_TRGO_OC4REF)) /** * @} */ -/** @defgroup TIMEx_Remap +/** @defgroup TIMEx_Remap Remaping * @{ */ -#define TIM2_ETR_GPIO ((uint32_t)0xFFF80000) -#define TIM2_ETR_HSI48 ((uint32_t)0xFFF80004) -#define TIM2_ETR_LSE ((uint32_t)0xFFF80005) -#define TIM2_ETR_COMP2_OUT ((uint32_t)0xFFF80006) -#define TIM2_ETR_COMP1_OUT ((uint32_t)0xFFF80007) -#define TIM2_TI4_GPIO1 ((uint32_t)0xFFE70000) -#define TIM2_TI4_COMP2 ((uint32_t)0xFFE70008) -#define TIM2_TI4_COMP1 ((uint32_t)0xFFE70010) -#define TIM2_TI4_GPIO2 ((uint32_t)0xFFE70018) -#define TIM21_ETR_GPIO ((uint32_t)0xFFF40000) -#define TIM21_ETR_COMP2_OUT ((uint32_t)0xFFF40001) -#define TIM21_ETR_COMP1_OUT ((uint32_t)0xFFF40002) -#define TIM21_ETR_LSE ((uint32_t)0xFFF40003) -#define TIM21_TI1_MCO ((uint32_t)0xFFE3001C) -#define TIM21_TI1_RTC_WKUT_IT ((uint32_t)0xFFE30004) -#define TIM21_TI1_HSE_RTC ((uint32_t)0xFFE30008) -#define TIM21_TI1_MSI ((uint32_t)0xFFE3000C) -#define TIM21_TI1_LSE ((uint32_t)0xFFE30010) -#define TIM21_TI1_LSI ((uint32_t)0xFFE30014) -#define TIM21_TI1_COMP1_OUT ((uint32_t)0xFFE30018) -#define TIM21_TI1_GPIO ((uint32_t)0xFFE30000) -#define TIM21_TI2_GPIO ((uint32_t)0xFFDF0000) -#define TIM21_TI2_COMP2_OUT ((uint32_t)0xFFDF0020) -#define TIM22_ETR_LSE ((uint32_t)0xFFFC0000) -#define TIM22_ETR_COMP2_OUT ((uint32_t)0xFFFC0001) -#define TIM22_ETR_COMP1_OUT ((uint32_t)0xFFFC0002) -#define TIM22_ETR_GPIO ((uint32_t)0xFFFC0003) -#define TIM22_TI1_GPIO1 ((uint32_t)0xFFF70000) -#define TIM22_TI1_COMP2_OUT ((uint32_t)0xFFF70004) -#define TIM22_TI1_COMP1_OUT ((uint32_t)0xFFF70008) -#define TIM22_TI1_GPIO2 ((uint32_t)0xFFF7000C) - - -#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_ETR_GPIO )|| \ - ((TIM_REMAP) == TIM2_ETR_HSI48 )|| \ - ((TIM_REMAP) == TIM2_ETR_LSE )|| \ - ((TIM_REMAP) == TIM2_ETR_COMP2_OUT )|| \ - ((TIM_REMAP) == TIM2_ETR_COMP1_OUT )|| \ - ((TIM_REMAP) == TIM2_TI4_GPIO1 )|| \ - ((TIM_REMAP) == TIM2_TI4_COMP1 )|| \ - ((TIM_REMAP) == TIM2_TI4_COMP2 )|| \ - ((TIM_REMAP) == TIM2_TI4_GPIO2 )|| \ - ((TIM_REMAP) == TIM21_ETR_GPIO )|| \ - ((TIM_REMAP) == TIM21_ETR_COMP2_OUT )|| \ - ((TIM_REMAP) == TIM21_ETR_COMP1_OUT )|| \ - ((TIM_REMAP) == TIM21_ETR_LSE )|| \ - ((TIM_REMAP) == TIM21_TI1_MCO )|| \ - ((TIM_REMAP) == TIM21_TI1_RTC_WKUT_IT )|| \ - ((TIM_REMAP) == TIM21_TI1_HSE_RTC )|| \ - ((TIM_REMAP) == TIM21_TI1_MSI )|| \ - ((TIM_REMAP) == TIM21_TI1_LSE )|| \ - ((TIM_REMAP) == TIM21_TI1_LSI )|| \ - ((TIM_REMAP) == TIM21_TI1_COMP1_OUT )|| \ - ((TIM_REMAP) == TIM21_TI1_GPIO )|| \ - ((TIM_REMAP) == TIM21_TI2_GPIO )|| \ - ((TIM_REMAP) == TIM21_TI2_COMP2_OUT )|| \ - ((TIM_REMAP) == TIM22_ETR_LSE )|| \ - ((TIM_REMAP) == TIM22_ETR_COMP2_OUT )|| \ - ((TIM_REMAP) == TIM22_ETR_COMP1_OUT )|| \ - ((TIM_REMAP) == TIM22_ETR_GPIO )|| \ - ((TIM_REMAP) == TIM22_TI1_GPIO1 )|| \ - ((TIM_REMAP) == TIM22_TI1_COMP2_OUT )|| \ - ((TIM_REMAP) == TIM22_TI1_COMP1_OUT )|| \ - ((TIM_REMAP) == TIM22_TI1_GPIO2 )) +#define TIM2_ETR_GPIO ((uint32_t)0x0) +#define TIM2_ETR_HSI48 TIM2_OR_ETR_RMP_2 +#define TIM2_ETR_LSE (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_0) +#define TIM2_ETR_COMP2_OUT (TIM2_OR_ETR_RMP_2 | TIM2_OR_ETR_RMP_1) +#define TIM2_ETR_COMP1_OUT TIM2_OR_ETR_RMP +#define TIM2_TI4_GPIO ((uint32_t)0x0) +#define TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_0 +#define TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_1 + +#define TIM21_ETR_GPIO ((uint32_t)0x0) +#define TIM21_ETR_COMP2_OUT TIM21_OR_ETR_RMP_0 +#define TIM21_ETR_COMP1_OUT TIM21_OR_ETR_RMP_1 +#define TIM21_ETR_LSE TIM21_OR_ETR_RMP +#define TIM21_TI1_GPIO ((uint32_t)0x0) +#define TIM21_TI1_MCO TIM21_OR_TI1_RMP +#define TIM21_TI1_RTC_WKUT_IT TIM21_OR_TI1_RMP_0 +#define TIM21_TI1_HSE_RTC TIM21_OR_TI1_RMP_1 +#define TIM21_TI1_MSI (TIM21_OR_TI1_RMP_0 | TIM21_OR_TI1_RMP_1) +#define TIM21_TI1_LSE TIM21_OR_TI1_RMP_2 +#define TIM21_TI1_LSI (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_0) +#define TIM21_TI1_COMP1_OUT (TIM21_OR_TI1_RMP_2 | TIM21_OR_TI1_RMP_1) +#define TIM21_TI2_GPIO ((uint32_t)0x0) +#define TIM21_TI2_COMP2_OUT TIM21_OR_TI2_RMP + +#define TIM22_ETR_LSE ((uint32_t)0x0) +#define TIM22_ETR_COMP2_OUT TIM22_OR_ETR_RMP_0 +#define TIM22_ETR_COMP1_OUT TIM22_OR_ETR_RMP_1 +#define TIM22_ETR_GPIO TIM22_OR_ETR_RMP +#define TIM22_TI1_GPIO1 ((uint32_t)0x0) +#define TIM22_TI1_COMP2_OUT TIM22_OR_TI1_RMP_0 +#define TIM22_TI1_COMP1_OUT TIM22_OR_TI1_RMP_1 +#define TIM22_TI1_GPIO2 TIM22_OR_TI1_RMP + +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ + || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) + +#define TIM3_TI4_GPIO_DEF ((uint32_t)0x0) +#define TIM3_TI4_GPIOC9_AF2 TIM3_OR_TI4_RMP +#define TIM3_TI2_GPIO_DEF ((uint32_t)0x0) +#define TIM3_TI2_GPIOB5_AF4 TIM3_OR_TI2_RMP +#define TIM3_TI1_USB_SOF ((uint32_t)0x0) +#define TIM3_TI1_GPIO TIM3_OR_TI1_RMP +#define TIM3_ETR_GPIO ((uint32_t)0x0) +#define TIM3_ETR_HSI TIM3_OR_ETR_RMP_1 + +#endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ + + + +#if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \ + || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) + + +#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ + (((__INSTANCE__ == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \ + ((__INSTANCE__ == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \ + ((__INSTANCE__ == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP))) || \ + ((__INSTANCE__ == TIM3) && ((__TIM_REMAP__) <= (TIM3_OR_ETR_RMP | TIM3_OR_TI1_RMP | TIM3_OR_TI2_RMP | TIM3_OR_TI4_RMP)))) + +#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ + (((__INSTANCE__ == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4))) || \ + ((__INSTANCE__ == TIM3) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4))) || \ + ((__INSTANCE__ == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2))) || \ + ((__INSTANCE__ == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)))) + +#else + +#define IS_TIM_REMAP(__INSTANCE__, __TIM_REMAP__) \ + (((__INSTANCE__ == TIM2) && ((__TIM_REMAP__) <= (TIM2_OR_TI4_RMP | TIM2_OR_ETR_RMP))) || \ + ((__INSTANCE__ == TIM22) && ((__TIM_REMAP__) <= (TIM22_OR_TI1_RMP | TIM22_OR_ETR_RMP))) || \ + ((__INSTANCE__ == TIM21) && ((__TIM_REMAP__) <= (TIM21_OR_ETR_RMP | TIM21_OR_TI1_RMP | TIM21_OR_TI2_RMP)))) + +#define IS_CHANNEL_AVAILABLE(__INSTANCE__, __CHANNEL__) \ + (((__INSTANCE__ == TIM2) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2) || \ + ((__CHANNEL__) == TIM_CHANNEL_3) || \ + ((__CHANNEL__) == TIM_CHANNEL_4))) || \ + ((__INSTANCE__ == TIM21) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2))) || \ + ((__INSTANCE__ == TIM22) && (((__CHANNEL__) == TIM_CHANNEL_1) || \ + ((__CHANNEL__) == TIM_CHANNEL_2)))) + +#endif /*defined (STM32L07Xxx) or defined (STM32L08Xxx) */ /** * @} - */ + */ /** * @} - */ - + */ + + /* Exported macro ------------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ /* Control functions ***********************************************************/ + +/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions + * @{ + */ + +/** @defgroup TIMEx_Exported_Functions_Group1 TIMEx Peripheral Control functions + * @{ + */ + HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig); + /** * @} - */ + */ + +/** + * @} + */ /** * @} */ - + +/** + * @} + */ + +/** + * @} + */ #ifdef __cplusplus } #endif @@ -195,3 +245,4 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, #endif /* __STM32L0xx_HAL_TIM_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.c index 60b09f064c2..0f8179b23ca 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_tsc.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief This file provides firmware functions to manage the following * functionalities of the Touch Sensing Controller (TSC) peripheral: * + Initialization and DeInitialization @@ -47,10 +47,10 @@ ##### How to use this driver ##### ================================================================================ [..] - (#) Enable the TSC interface clock using __TSC_CLK_ENABLE() macro. + (#) Enable the TSC interface clock using __HAL_RCC_TSC_CLK_ENABLE() macro. (#) GPIO pins configuration - (++) Enable the clock for the TSC GPIOs using __GPIOx_CLK_ENABLE() macro. + (++) Enable the clock for the TSC GPIOs using __HAL_RCC_GPIOx_CLK_ENABLE() macro. (++) Configure the TSC pins used as sampling IOs in alternate function output Open-Drain mode, and TSC pins used as channel/shield IOs in alternate function output Push-Pull mode using HAL_GPIO_Init() function. @@ -81,7 +81,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -109,8 +109,10 @@ */ /* Includes ------------------------------------------------------------------*/ +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) #include "stm32l0xx_hal.h" +#ifdef HAL_TSC_MODULE_ENABLED /** @addtogroup STM32L0xx_HAL_Driver * @{ */ @@ -120,7 +122,6 @@ * @{ */ -#ifdef HAL_TSC_MODULE_ENABLED /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -157,7 +158,7 @@ static uint32_t TSC_extract_groups(uint32_t iomask); HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) { /* Check TSC handle allocation */ - if (htsc == HAL_NULL) + if (htsc == NULL) { return HAL_ERROR; } @@ -240,7 +241,7 @@ HAL_StatusTypeDef HAL_TSC_Init(TSC_HandleTypeDef* htsc) HAL_StatusTypeDef HAL_TSC_DeInit(TSC_HandleTypeDef* htsc) { /* Check TSC handle allocation */ - if (htsc == HAL_NULL) + if (htsc == NULL) { return HAL_ERROR; } @@ -753,7 +754,6 @@ static uint32_t TSC_extract_groups(uint32_t iomask) * @} */ -#endif /* HAL_TSC_MODULE_ENABLED */ /** * @} @@ -762,5 +762,8 @@ static uint32_t TSC_extract_groups(uint32_t iomask) /** * @} */ +#endif /* HAL_TSC_MODULE_ENABLED */ +#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.h index e0570bc27bb..a742c7a1e2f 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_tsc.h @@ -2,14 +2,14 @@ ****************************************************************************** * @file stm32l0xx_hal_tsc.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief This file contains all the functions prototypes for the TSC firmware * library. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -36,6 +36,7 @@ ****************************************************************************** */ +#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) /* Define to prevent recursive inclusion -------------------------------------*/ #ifndef __STM32L0xx_TSC_H #define __STM32L0xx_TSC_H @@ -237,8 +238,8 @@ typedef struct #define TSC_IODEF_IN_FLOAT (TSC_CR_IODEF) #define IS_TSC_IODEF(VAL) (((VAL) == TSC_IODEF_OUT_PP_LOW) || ((VAL) == TSC_IODEF_IN_FLOAT)) -#define TSC_SYNC_POL_FALL ((uint32_t)0) -#define TSC_SYNC_POL_RISE_HIGH (TSC_CR_SYNCPOL) +#define TSC_SYNC_POLARITY_FALLING ((uint32_t)0) +#define TSC_SYNC_POLARITY_RISING (TSC_CR_SYNCPOL) #define IS_TSC_SYNC_POL(VAL) (((VAL) == TSC_SYNC_POL_FALL) || ((VAL) == TSC_SYNC_POL_RISE_HIGH)) #define TSC_ACQ_MODE_NORMAL ((uint32_t)0) @@ -582,5 +583,7 @@ void HAL_TSC_ErrorCallback(TSC_HandleTypeDef* htsc); #endif #endif /*__STM32L0xx_TSC_H */ +#endif /* #if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.c index f3632e7e647..92aa380f1e4 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_uart.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief UART HAL module driver. * * This file provides firmware functions to manage the following @@ -76,17 +76,14 @@ (+) Send an amount of data in blocking mode using HAL_UART_Transmit() (+) Receive an amount of data in blocking mode using HAL_UART_Receive() - *** Interrupt mode IO operation *** + +*** Interrupt mode IO operation *** =================================== [..] (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() - (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_TxCpltCallback (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() - (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can - add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can add his own code by customization of function pointer HAL_UART_RxCpltCallback (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can @@ -129,7 +126,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -163,7 +160,7 @@ * @{ */ -/** @defgroup UART +/** @addtogroup UART * @brief UART module driver * @{ */ @@ -183,15 +180,18 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); static void UART_DMAError(DMA_HandleTypeDef *hdma); static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart); +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart); static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); + + /* Private functions ---------------------------------------------------------*/ -/** @defgroup UART_Private_Functions +/** @addtogroup UART_Exported_Functions UART Exported Functions * @{ */ -/** @defgroup UART_Group1 Initialization/de-initialization methods +/** @addtogroup UART_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim @@ -255,7 +255,7 @@ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } @@ -312,11 +312,15 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if(huart->State == HAL_UART_STATE_RESET) { /* Init the low level hardware : GPIO, CLOCK, CORTEX */ @@ -363,10 +367,13 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); @@ -376,6 +383,12 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe return HAL_ERROR; } + /* in LIN mode limited, data length limited to 8-bit only */ + if(huart->Init.WordLength!= UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + if(huart->State == HAL_UART_STATE_RESET) { /* Init the low level hardware : GPIO, CLOCK, CORTEX */ @@ -433,7 +446,7 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } @@ -490,7 +503,7 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } @@ -547,7 +560,7 @@ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) * @} */ -/** @defgroup UART_Group2 IO operation functions +/** @addtogroup UART_Exported_Functions_Group2 * @brief UART Transmit/Receive functions * @verbatim @@ -616,7 +629,7 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, u if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -695,7 +708,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -718,7 +731,7 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui huart->RxXferCount = Size; /* Computation of UART mask to apply to RDR register */ - __HAL_UART_MASK_COMPUTATION(huart); + UART_MASK_COMPUTATION(huart); uhMask = huart->Mask; /* as long as data have to be received */ @@ -772,7 +785,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData { if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -826,7 +839,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, { if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -839,7 +852,7 @@ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, huart->RxXferCount = Size; /* Computation of UART mask to apply to RDR register */ - __HAL_UART_MASK_COMPUTATION(huart); + UART_MASK_COMPUTATION(huart); huart->ErrorCode = HAL_UART_ERROR_NONE; /* Check if a transmit process is ongoing or not */ @@ -885,7 +898,7 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_RX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -921,6 +934,9 @@ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pDat tmp = (uint32_t*)&pData; HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->TDR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_UART_CLEAR_FLAG(huart, UART_FLAG_TC); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the UART CR3 register */ huart->Instance->CR3 |= USART_CR3_DMAT; @@ -950,7 +966,7 @@ HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData if((huart->State == HAL_UART_STATE_READY) || (huart->State == HAL_UART_STATE_BUSY_TX)) { - if((pData == HAL_NULL ) || (Size == 0)) + if((pData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -1092,12 +1108,12 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) huart->Instance->CR3 &= ~USART_CR3_DMAR; /* Abort the UART DMA tx channel */ - if(huart->hdmatx != HAL_NULL) + if(huart->hdmatx != NULL) { HAL_DMA_Abort(huart->hdmatx); } /* Abort the UART DMA rx channel */ - if(huart->hdmarx != HAL_NULL) + if(huart->hdmarx != NULL) { HAL_DMA_Abort(huart->hdmarx); } @@ -1115,9 +1131,10 @@ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) { /* UART parity error interrupt occurred ------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_PE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_PEF); + __HAL_UART_CLEAR_PEFLAG(huart); huart->ErrorCode |= HAL_UART_ERROR_PE; /* Set the UART state ready to be able to start again the process */ @@ -1127,7 +1144,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* UART frame error interrupt occured --------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_FE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_FEF); + __HAL_UART_CLEAR_FEFLAG(huart); huart->ErrorCode |= HAL_UART_ERROR_FE; /* Set the UART state ready to be able to start again the process */ @@ -1137,7 +1154,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* UART noise error interrupt occured --------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_NE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_NEF); + __HAL_UART_CLEAR_NEFLAG(huart); huart->ErrorCode |= HAL_UART_ERROR_NE; /* Set the UART state ready to be able to start again the process */ @@ -1147,7 +1164,7 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) /* UART Over-Run interrupt occured -----------------------------------------*/ if((__HAL_UART_GET_IT(huart, UART_IT_ORE) != RESET) && (__HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR) != RESET)) { - __HAL_UART_CLEAR_IT(huart, UART_CLEAR_OREF); + __HAL_UART_CLEAR_OREFLAG(huart); huart->ErrorCode |= HAL_UART_ERROR_ORE; /* Set the UART state ready to be able to start again the process */ @@ -1181,6 +1198,12 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) UART_Transmit_IT(huart); } + /* UART in mode Transmitter -- TC ------------------------------------------*/ + if((__HAL_UART_GET_IT(huart, UART_IT_TC) != RESET) &&(__HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC) != RESET)) + { + UART_EndTransmit_IT(huart); + } + if(huart->ErrorCode != HAL_UART_ERROR_NONE) { HAL_UART_ErrorCallback(huart); @@ -1252,7 +1275,7 @@ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) * @} */ -/** @defgroup UART_Group3 Peripheral Control funtions +/** @addtogroup UART_Exported_Functions_Group3 * @brief UART control functions * @verbatim @@ -1424,6 +1447,10 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) * @} */ +/*************************************************************** + * Private functions... + * + ***************************************************************/ /** * @brief DMA UART transmit process complete callback * @param hdma: DMA handle @@ -1432,43 +1459,15 @@ uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart) static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - - /* DMA Normal mode*/ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) - { - huart->TxXferCount = 0; - - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); - - /* Wait for UART TC Flag */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Timeout Occured */ - huart->State = HAL_UART_STATE_TIMEOUT; - HAL_UART_ErrorCallback(huart); - } - else - { - /* No Timeout */ - /* Check if a receive process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - huart->State = HAL_UART_STATE_READY; - } - HAL_UART_TxCpltCallback(huart); - } - } - /* DMA Circular mode */ - else - { - HAL_UART_TxCpltCallback(huart); - } + huart->TxXferCount = 0; + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT); + + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); + } /** @@ -1559,31 +1558,11 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) /* Disable the UART TXE Interrupt */ __HAL_UART_DISABLE_IT(huart, UART_IT_TXE); - /* Check if a receive Process is ongoing or not */ - if(huart->State == HAL_UART_STATE_BUSY_TX_RX) - { - huart->State = HAL_UART_STATE_BUSY_RX; - } - else - { - /* Disable the UART Parity Error Interrupt */ - __HAL_UART_DISABLE_IT(huart, UART_IT_PE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - - huart->State = HAL_UART_STATE_READY; - } + /* Enable the UART Transmit Complete Interrupt */ + __HAL_UART_ENABLE_IT(huart, UART_IT_TC); - /* Wait on TC flag to be able to start a second transfer */ - if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK) - { - return HAL_TIMEOUT; - } - - HAL_UART_TxCpltCallback(huart); - return HAL_OK; + } else { @@ -1609,6 +1588,36 @@ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) } } +/** + * @brief Wraps up transmission in non blocking mode. + * @param huart: pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + __HAL_UART_DISABLE_IT(huart, UART_IT_TC); + + /* Check if a receive process is ongoing or not */ + if(huart->State == HAL_UART_STATE_BUSY_TX_RX) + { + huart->State = HAL_UART_STATE_BUSY_RX; + } + else + { + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); + + huart->State = HAL_UART_STATE_READY; + } + + HAL_UART_TxCpltCallback(huart); + + return HAL_OK; +} + + /** * @brief Receive an amount of data in interrupt mode * Function called under interruption only, once @@ -1686,7 +1695,8 @@ void UART_SetConfig(UART_HandleTypeDef *huart) assert_param(IS_UART_PARITY(huart->Init.Parity)); assert_param(IS_UART_MODE(huart->Init.Mode)); assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_ONEBIT_SAMPLING(huart->Init.OneBitSampling)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); /*-------------------------- USART CR1 Configuration -----------------------*/ /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure @@ -1713,7 +1723,7 @@ void UART_SetConfig(UART_HandleTypeDef *huart) MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT), tmpreg); /*-------------------------- USART BRR Configuration -----------------------*/ - __HAL_UART_GETCLOCKSOURCE(huart, clocksource); + UART_GETCLOCKSOURCE(huart, clocksource); /* Check LPUART instace */ if(huart->Instance == LPUART1) @@ -1742,19 +1752,19 @@ void UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - usartdiv = (uint32_t)(__DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_PCLK2: - usartdiv = (uint32_t)(__DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: - usartdiv = (uint32_t)(__DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(HSI_VALUE, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_SYSCLK: - huart->Instance->BRR = (uint32_t)(__DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING8(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_LSE: - usartdiv = (uint32_t)(__DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(LSE_VALUE, huart->Init.BaudRate)); break; default: break; @@ -1769,19 +1779,19 @@ void UART_SetConfig(UART_HandleTypeDef *huart) switch (clocksource) { case UART_CLOCKSOURCE_PCLK1: - huart->Instance->BRR = (uint32_t)(__DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); + huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_PCLK2: - huart->Instance->BRR = (uint32_t)(__DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); + huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_HSI: - huart->Instance->BRR = (uint32_t)(__DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); + huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HSI_VALUE, huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_SYSCLK: - huart->Instance->BRR = (uint32_t)(__DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); + huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), huart->Init.BaudRate)); break; case UART_CLOCKSOURCE_LSE: - huart->Instance->BRR = (uint32_t)(__DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); + huart->Instance->BRR = (uint32_t)(UART_DIV_SAMPLING16(LSE_VALUE, huart->Init.BaudRate)); break; default: break; @@ -1880,6 +1890,7 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) /* if required, configure auto Baud rate detection scheme */ if(HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); /* set auto Baudrate detection parameters if detection is enabled */ @@ -1913,7 +1924,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ /* Wait until flag is set */ if(Status == RESET) - { + { while(__HAL_UART_GET_FLAG(huart, Flag) == RESET) { /* Check for the Timeout */ @@ -1927,7 +1938,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State= HAL_UART_STATE_TIMEOUT; + huart->State= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1952,7 +1963,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ __HAL_UART_DISABLE_IT(huart, UART_IT_PE); __HAL_UART_DISABLE_IT(huart, UART_IT_ERR); - huart->State= HAL_UART_STATE_TIMEOUT; + huart->State= HAL_UART_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(huart); @@ -1979,3 +1990,4 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_ */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.h index 661de03679d..cad428e5031 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_uart.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of UART HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,12 +50,21 @@ * @{ */ -/** @addtogroup UART +/** @defgroup UART UART * @{ */ -/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ + /** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** @defgroup UART_Init_Configuration UART initialization configuration structure + * @{ + */ /** * @brief UART Init Structure definition */ @@ -95,9 +104,14 @@ typedef struct uint32_t OneBitSampling; /*!< Specifies wether a single sample or three samples' majority vote is selected. Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling */ + deviations. This parameter can be a value of @ref UART_One_Bit */ }UART_InitTypeDef; - +/** + * @} + */ +/** @defgroup UART_Advanced_Feature UART advanced feature structure + * @{ + */ /** * @brief UART Advanced Features initalization structure definition */ @@ -136,7 +150,13 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref UART_MSB_First */ } UART_AdvFeatureInitTypeDef; +/** + * @} + */ +/** @defgroup UART_State_Definition UART state definition + * @{ + */ /** * @brief HAL UART State structures definition */ @@ -151,20 +171,29 @@ typedef enum HAL_UART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ HAL_UART_STATE_ERROR = 0x04 /*!< Error */ }HAL_UART_StateTypeDef; - +/** + * @} + */ +/** @defgroup UART_Error_Definition UART error definition + * @{ + */ /** - * @brief HAL UART Error Code structure definition + * @brief HAL UART Error Code definition */ -typedef enum -{ - HAL_UART_ERROR_NONE = 0x00, /*!< No error */ - HAL_UART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_UART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_UART_ERROR_FE = 0x04, /*!< frame error */ - HAL_UART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_UART_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_UART_ErrorTypeDef; +#define HAL_UART_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_UART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ +#define HAL_UART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ +#define HAL_UART_ERROR_FE ((uint32_t)0x04) /*!< frame error */ +#define HAL_UART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ + +/** + * @} + */ +/** @defgroup UART_Clock_SourceDefinition UART clock source definition + * @{ + */ /** * @brief UART clock sources definition */ @@ -176,10 +205,16 @@ typedef enum UART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ UART_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */ }UART_ClockSourceTypeDef; - +/** + * @} + */ +/** @defgroup UART_handle_Definition Handle structure definition + * @{ + */ /** * @brief UART handle Structure definition - */ + */ + typedef struct { USART_TypeDef *Instance; /* UART registers base address */ @@ -210,17 +245,22 @@ typedef struct __IO HAL_UART_StateTypeDef State; /* UART communication state */ - __IO HAL_UART_ErrorTypeDef ErrorCode; /* UART Error code */ + __IO uint32_t ErrorCode; /* UART Error code */ }UART_HandleTypeDef; +/** + * @} + */ +/** + * @} + */ - /* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants +/** @defgroup UART_Exported_Constants UART Exported Constants * @{ */ -/** @defgroup UART_Stop_Bits +/** @defgroup UART_Stop_Bits UART stop bit definition * @{ */ #define UART_STOPBITS_1 ((uint32_t)0x0000) @@ -231,7 +271,7 @@ typedef struct * @} */ -/** @defgroup UART_Parity +/** @defgroup UART_Parity UART parity definition * @{ */ #define UART_PARITY_NONE ((uint32_t)0x0000) @@ -244,7 +284,7 @@ typedef struct * @} */ -/** @defgroup UART_Hardware_Flow_Control +/** @defgroup UART_Hardware_Flow_Control UART hardware flow control definition * @{ */ #define UART_HWCONTROL_NONE ((uint32_t)0x0000) @@ -260,7 +300,7 @@ typedef struct * @} */ -/** @defgroup UART_Mode +/** @defgroup UART_Mode UART mode definition * @{ */ #define UART_MODE_RX ((uint32_t)USART_CR1_RE) @@ -271,7 +311,7 @@ typedef struct * @} */ - /** @defgroup UART_State + /** @defgroup UART_State UART state enable and disable definition * @{ */ #define UART_STATE_DISABLE ((uint32_t)0x0000) @@ -282,7 +322,7 @@ typedef struct * @} */ -/** @defgroup UART_Over_Sampling +/** @defgroup UART_Over_Sampling UART over sampling definition * @{ */ #define UART_OVERSAMPLING_16 ((uint32_t)0x0000) @@ -292,20 +332,9 @@ typedef struct /** * @} */ - -/** @defgroup UART_OneBit_Sampling - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED ((uint32_t)0x0000) -#define UART_ONEBIT_SAMPLING_ENABLED ((uint32_t)USART_CR3_ONEBIT) -#define IS_UART_ONEBIT_SAMPLING(ONEBIT) (((ONEBIT) == UART_ONEBIT_SAMPLING_DISABLED) || \ - ((ONEBIT) == UART_ONEBIT_SAMPLING_ENABLED)) -/** - * @} - */ -/** @defgroup UART_Receiver_TimeOut +/** @defgroup UART_Receiver_TimeOut UART receiver timeOut definition * @{ */ #define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) @@ -316,7 +345,7 @@ typedef struct * @} */ -/** @defgroup UART_LIN +/** @defgroup UART_LIN UART LIN enable and disable definition * @{ */ #define UART_LIN_DISABLE ((uint32_t)0x00000000) @@ -327,7 +356,7 @@ typedef struct * @} */ -/** @defgroup UART_LIN_Break_Detection +/** @defgroup UART_LIN_Break_Detection UART LIN break detection definition * @{ */ #define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) @@ -340,18 +369,18 @@ typedef struct -/** @defgroup UART_One_Bit +/** @defgroup UART_One_Bit UART one bit definition * @{ */ -#define UART_ONE_BIT_SAMPLE_DISABLED ((uint32_t)0x00000000) -#define UART_ONE_BIT_SAMPLE_ENABLED ((uint32_t)USART_CR3_ONEBIT) -#define IS_UART_ONEBIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLED) || \ - ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLED)) +#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) +#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) +#define IS_UART_ONE_BIT_SAMPLE(ONEBIT) (((ONEBIT) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((ONEBIT) == UART_ONE_BIT_SAMPLE_ENABLE)) /** * @} */ -/** @defgroup UART_DMA_Tx +/** @defgroup UART_DMA_Tx UART DMA Tx definition * @{ */ #define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) @@ -362,7 +391,7 @@ typedef struct * @} */ -/** @defgroup UART_DMA_Rx +/** @defgroup UART_DMA_Rx UART DMA Rx definition * @{ */ #define UART_DMA_RX_DISABLE ((uint32_t)0x0000) @@ -373,7 +402,7 @@ typedef struct * @} */ -/** @defgroup UART_Half_Duplex_Selection +/** @defgroup UART_Half_Duplex_Selection UART half duplex selection definition * @{ */ #define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x0000) @@ -384,7 +413,7 @@ typedef struct * @} */ -/** @defgroup UART_Flags +/** @defgroup UART_Flags UART flags definition * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ @@ -415,14 +444,14 @@ typedef struct * @} */ -/** @defgroup UART_Interrupt_definition - * Elements values convention: 0000ZZZZ0XXYYYYYb +/** @defgroup UART_Interrupt_definition UART interrupt definition + * Elements values convention: 000ZZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) * - 01: CR1 register * - 10: CR2 register * - 11: CR3 register - * - ZZZZ : Flag position in the ISR register(4bits) + * - ZZZZZ : Flag position in the ISR register(5bits) * @{ */ #define UART_IT_PE ((uint32_t)0x0028) @@ -432,7 +461,7 @@ typedef struct #define UART_IT_IDLE ((uint32_t)0x0424) #define UART_IT_LBD ((uint32_t)0x0846) #define UART_IT_CTS ((uint32_t)0x096A) -#define UART_IT_CM ((uint32_t)0x142E) +#define UART_IT_CM ((uint32_t)0x112E) #define UART_IT_WUF ((uint32_t)0x1476) /** Elements values convention: 000000000XXYYYYYb @@ -454,7 +483,7 @@ typedef struct * @} */ -/** @defgroup UART_IT_CLEAR_Flags +/** @defgroup UART_IT_CLEAR_Flags UART interrupt clear flags definition * @{ */ #define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ @@ -473,7 +502,7 @@ typedef struct * @} */ -/** @defgroup UART_Request_Parameters +/** @defgroup UART_Request_Parameters UART request parameter definition * @{ */ #define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /*!< Auto-Baud Rate Request */ @@ -490,7 +519,7 @@ typedef struct * @} */ -/** @defgroup UART_Advanced_Features_Initialization_Type +/** @defgroup UART_Advanced_Features_Initialization_Type UART advanced features initialization type definition * @{ */ #define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) @@ -515,7 +544,7 @@ typedef struct * @} */ -/** @defgroup UART_Tx_Inv +/** @defgroup UART_Tx_Inv UART advanced Tx inv activation definition * @{ */ #define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) @@ -526,7 +555,7 @@ typedef struct * @} */ -/** @defgroup UART_Rx_Inv +/** @defgroup UART_Rx_Inv UART advanced Rx inv activation definition * @{ */ #define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) @@ -537,7 +566,7 @@ typedef struct * @} */ -/** @defgroup UART_Data_Inv +/** @defgroup UART_Data_Inv UART advanced data inv activation definition * @{ */ #define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) @@ -548,7 +577,7 @@ typedef struct * @} */ -/** @defgroup UART_Rx_Tx_Swap +/** @defgroup UART_Rx_Tx_Swap UART advanced swap activation definition * @{ */ #define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) @@ -559,7 +588,7 @@ typedef struct * @} */ -/** @defgroup UART_Overrun_Disable +/** @defgroup UART_Overrun_Disable UART advanced overrun activation definition * @{ */ #define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) @@ -570,7 +599,7 @@ typedef struct * @} */ -/** @defgroup UART_AutoBaudRate_Enable +/** @defgroup UART_AutoBaudRate_Enable UART advanced auto baud rate activation definition * @{ */ #define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) @@ -581,7 +610,7 @@ typedef struct * @} */ -/** @defgroup UART_DMA_Disable_on_Rx_Error +/** @defgroup UART_DMA_Disable_on_Rx_Error UART advanced DMA on Rx error activation definition * @{ */ #define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) @@ -592,7 +621,7 @@ typedef struct * @} */ -/** @defgroup UART_MSB_First +/** @defgroup UART_MSB_First UART advanced MSB first activation definition * @{ */ #define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) @@ -603,7 +632,7 @@ typedef struct * @} */ -/** @defgroup UART_Stop_Mode_Enable +/** @defgroup UART_Stop_Mode_Enable UART advanced stop mode activation definition * @{ */ #define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) @@ -614,7 +643,7 @@ typedef struct * @} */ -/** @defgroup UART_Mute_Mode +/** @defgroup UART_Mute_Mode UART advanced mute mode activation definition * @{ */ #define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) @@ -625,7 +654,7 @@ typedef struct * @} */ -/** @defgroup UART_CR2_ADDRESS_LSBPOS +/** @defgroup UART_CR2_ADDRESS_LSBPOS UART CR2 address lsb position definition * @{ */ #define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) @@ -633,7 +662,7 @@ typedef struct * @} */ -/** @defgroup UART_WakeUp_from_Stop_Selection +/** @defgroup UART_WakeUp_from_Stop_Selection UART wake up mode selection definition * @{ */ #define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x0000) @@ -646,7 +675,7 @@ typedef struct * @} */ -/** @defgroup UART_DriverEnable_Polarity +/** @defgroup UART_DriverEnable_Polarity UART driver polarity level definition * @{ */ #define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) @@ -657,7 +686,7 @@ typedef struct * @} */ -/** @defgroup UART_CR1_DEAT_ADDRESS_LSBPOS +/** @defgroup UART_CR1_DEAT_ADDRESS_LSBPOS UART CR1 DEAT address lsb position definition * @{ */ #define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) @@ -665,7 +694,7 @@ typedef struct * @} */ -/** @defgroup UART_CR1_DEDT_ADDRESS_LSBPOS +/** @defgroup UART_CR1_DEDT_ADDRESS_LSBPOS UART CR1 DEDT address lsb position definition * @{ */ #define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) @@ -673,7 +702,7 @@ typedef struct * @} */ -/** @defgroup UART_Interruption_Mask +/** @defgroup UART_Interruption_Mask UART interruption mask definition * @{ */ #define UART_IT_MASK ((uint32_t)0x001F) @@ -686,7 +715,7 @@ typedef struct */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros +/** @defgroup UART_Exported_Macros UART Exported Macros * @{ */ @@ -697,6 +726,66 @@ typedef struct */ #define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET) +/** @brief Flush the UART Data registers + * @param __HANDLE__: specifies the UART Handle. + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0) + + +/** @brief Clears the specified UART pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg UART_CLEAR_PEF + * @arg UART_CLEAR_FEF + * @arg UART_CLEAR_NEF + * @arg UART_CLEAR_OREF + * @arg UART_CLEAR_IDLEF + * @arg UART_CLEAR_TCF + * @arg UART_CLEAR_LBDF + * @arg UART_CLEAR_CTSF + * @arg UART_CLEAR_RTOF + * @arg UART_CLEAR_EOBF + * @arg UART_CLEAR_CMF + * @arg UART_CLEAR_WUF + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG(__HANDLE__,UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG(__HANDLE__,UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG(__HANDLE__,UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG(__HANDLE__,UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG(__HANDLE__,UART_CLEAR_IDLEF) + /** @brief Checks whether the specified UART flag is set or not. * @param __HANDLE__: specifies the UART Handle. * This parameter can be USART1, USART2 or LPUART. @@ -844,7 +933,19 @@ typedef struct * @arg UART_TXDATA_FLUSH_REQUEST: Transmit data flush Request * @retval None */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) + +/** @brief Enables the UART one bit sample method + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disables the UART one bit sample method + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable UART * @param __HANDLE__: specifies the UART Handle. @@ -936,6 +1037,13 @@ typedef struct (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ } while(0) +/** @brief macros to enables or disables the UART's one bit sampling method + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) +#define __HAL_UART_ONE_BIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT)) + /** @brief BRR division operation to set BRR register with LPUART * @param _PCLK_: LPUART clock @@ -949,14 +1057,14 @@ typedef struct * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define __DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_))) +#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) (((_PCLK_)*2)/((_BAUD_))) /** @brief BRR division operation to set BRR register in 16-bit oversampling mode * @param _PCLK_: UART clock * @param _BAUD_: Baud rate set by the user * @retval Division result */ -#define __DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_))) +#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) (((_PCLK_))/((_BAUD_))) /** @brief Check UART Baud rate * @param BAUDRATE: Baudrate specified by the user @@ -995,8 +1103,19 @@ typedef struct */ /* Include UART HAL Extension module */ #include "stm32l0xx_hal_uart_ex.h" + +/******************************************************************************/ /* Exported functions --------------------------------------------------------*/ +/******************************************************************************/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ /* Initialization/de-initialization functions ********************************/ +/** @defgroup UART_Exported_Functions_Group1 Initialization/de-initialization methods + * @{ + */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); @@ -1004,8 +1123,14 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart); void HAL_UART_MspInit(UART_HandleTypeDef *huart); void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); +/** + * @} + */ /* IO operation functions *****************************************************/ +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); @@ -1021,8 +1146,13 @@ void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); - +/** + * @} + */ /* Peripheral Control and State functions ************************************/ +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control funtions + * @{ + */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); @@ -1031,16 +1161,21 @@ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart); uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart); - -/* Non-User functions ********************************************************/ +/** + * @} + */ void UART_SetConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout); void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); + /** * @} - */ + */ +/** + * @} + */ /** * @} */ diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.c index fd12d9debd8..2ae1b15e878 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_uart_ex.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Extended UART HAL module driver. * * This file provides firmware functions to manage the following @@ -30,7 +30,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -64,7 +64,7 @@ * @{ */ -/** @defgroup UARTEx +/** @addtogroup UARTEx * @brief UARTEx module driver * @{ */ @@ -80,11 +80,11 @@ static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); /* Private functions ---------------------------------------------------------*/ -/** @defgroup UARTEX_Private_Functions +/** @addtogroup UARTEx_Exported_Functions * @{ */ -/** @defgroup UARTEx_Group1 Extended Initialization/de-initialization functions +/** @addtogroup UARTEx_Exported_Functions_Group1 * @brief Extended Initialization and Configuration Functions * @@ -124,7 +124,7 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t temp = 0x0; /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } @@ -175,23 +175,12 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, return (UART_CheckIdleState(huart)); } -/** - * @brief UART wakeup from Stop mode callback - * @param huart: uart handle - * @retval None - */ - __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_WakeupCallback can be implemented in the user file - */ -} /** * @} */ -/** @defgroup UARTEX_Group2 Peripheral Control functions +/** @addtogroup UARTEx_Exported_Functions_Group2 * @brief management functions * @verbatim @@ -318,6 +307,9 @@ HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart) */ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) { + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); /* Check the wake-up selection parameter */ assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); @@ -372,7 +364,7 @@ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huar HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) { /* Check the UART handle allocation */ - if(huart == HAL_NULL) + if(huart == NULL) { return HAL_ERROR; } @@ -424,6 +416,18 @@ static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpType MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); } +/** + * @brief UART wakeup from Stop mode callback + * @param huart: uart handle + * @retval None + */ + __weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_WakeupCallback can be implemented in the user file + */ +} + /** * @} */ @@ -438,3 +442,4 @@ static void UART_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpType */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.h index abb8a6b729b..9cfea24a6c7 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_uart_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_uart_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of UART HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,11 +50,21 @@ * @{ */ -/** @addtogroup UARTEx +/** @defgroup UARTEx UARTEx Extended HAL module driver * @{ */ +/******************************************************************************/ /* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ + + /** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** @defgroup UARTEx_Init_Configuration Extended initialization configuration structure + * @{ + */ /** * @brief UART wake up from stop mode parameters */ @@ -71,12 +81,19 @@ typedef struct uint8_t Address; /*!< UART/USART node address (7-bit long max) */ } UART_WakeUpTypeDef; +/** + * @} + */ +/** + * @} + */ + /* Exported constants --------------------------------------------------------*/ -/** @defgroup UARTEx_Extended_Exported_Constants +/** @defgroup UARTEx_Extended_Exported_Constants UARTEx Exported Constants * @{ */ -/** @defgroup UARTEx_Word_Length +/** @defgroup UARTEx_Word_Length Word length definition * @{ */ #define UART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) @@ -89,7 +106,7 @@ typedef struct * @} */ -/** @defgroup UARTEx_AutoBaud_Rate_Mode +/** @defgroup UARTEx_AutoBaud_Rate_Mode Auto baud rate mode definition * @{ */ #define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x0000) @@ -104,7 +121,7 @@ typedef struct * @} */ -/** @defgroup UARTEx_WakeUp_Address_Length +/** @defgroup UARTEx_WakeUp_Address_Length WakeUp address length definition * @{ */ #define UART_ADDRESS_DETECT_4B ((uint32_t)0x00000000) @@ -116,7 +133,7 @@ typedef struct */ -/** @defgroup UARTEx_WakeUp_Methods +/** @defgroup UARTEx_WakeUp_Methods Wakeup methods definition * @{ */ #define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) @@ -133,7 +150,7 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ -/** @defgroup UARTEx_Extended_Exported_Macros +/** @defgroup UARTEx_Extended_Exported_Macros UARTEx Exported Macros * @{ */ @@ -142,7 +159,54 @@ typedef struct * @param __CLOCKSOURCE__ : output variable * @retval UART clocking source, written in __CLOCKSOURCE__. */ -#define __HAL_UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#if defined (STM32L031xx) || defined (STM32L041xx) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + break; \ + } \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + switch(__HAL_RCC_GET_LPUART1_SOURCE()) \ + { \ + case RCC_LPUART1CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_LPUART1CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_LPUART1CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_LPUART1CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + break; \ + } \ + } \ + } while(0) + +#else /* (STM32L031xx) || defined (STM32L041xx) */ + +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ @@ -205,6 +269,7 @@ typedef struct } \ } \ } while(0) +#endif /* (STM32L031xx) || (STM32L041xx) */ /** @brief Reports the UART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. @@ -213,10 +278,9 @@ typedef struct * This masking operation is not carried out in the case of * DMA transfers. * @param __HANDLE__: specifies the UART Handle - * @param __MASK__ : output variable * @retval mask to apply to UART RDR register value. */ -#define __HAL_UART_MASK_COMPUTATION(__HANDLE__) \ +#define UART_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ { \ @@ -258,22 +322,43 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ +/* Exported functions --------------------------------------------------------*/ /* Initialization/de-initialization functions ********************************/ +/** @defgroup UARTEx_Exported_Functions_Group1 Extended Initialization function + * @{ + */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime); - +/** + * @} + */ /* IO operation functions *****************************************************/ /* Peripheral Control functions **********************************************/ +/** @defgroup UARTEx_Exported_Functions_Group2 Peripheral Control functions + * @{ + */ HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_EnableClockStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_DisableClockStopMode(UART_HandleTypeDef *huart); void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); -/* Aliases for inter STM32 series compatibility */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback /* Peripheral State functions ************************************************/ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ /** * @} @@ -290,3 +375,4 @@ HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *hua #endif /* __STM32L0xx_HAL_UART_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.c index 27ab7d5e8e2..0d96036e3af 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_usart.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief USART HAL module driver. * * This file provides firmware functions to manage the following @@ -53,7 +53,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -87,7 +87,7 @@ * @{ */ -/** @defgroup USART +/** @addtogroup USART * @brief USART Synchronous module driver * @{ */ @@ -100,7 +100,7 @@ #define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \ - USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)) + USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8)) #define USART_CR2_FIELDS ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | \ USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP)) /* Private macro -------------------------------------------------------------*/ @@ -115,16 +115,17 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar static void USART_SetConfig (USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart); +static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart); static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); /* Private functions ---------------------------------------------------------*/ -/** @defgroup USART_Private_Functions +/** @addtogroup USART_Exported_Functions * @{ */ -/** @defgroup USART_Group1 USART Initialization/de-initialization functions +/** @addtogroup USART_Exported_Functions_Group1 * @brief Initialization and Configuration functions * @verbatim @@ -175,7 +176,7 @@ static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) { /* Check the USART handle allocation */ - if(husart == HAL_NULL) + if(husart == NULL) { return HAL_ERROR; } @@ -218,7 +219,7 @@ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart) HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) { /* Check the USART handle allocation */ - if(husart == HAL_NULL) + if(husart == NULL) { return HAL_ERROR; } @@ -272,7 +273,7 @@ HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart) * @} */ -/** @defgroup USART_Group2 IO operation functions +/** @addtogroup USART_Exported_Functions_Group2 * @brief USART Transmit and Receive functions * @verbatim @@ -344,7 +345,7 @@ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxDa if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -412,7 +413,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == HAL_NULL) || (Size == 0)) + if((pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -426,7 +427,7 @@ HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxDat husart->RxXferCount = Size; /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); + USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; /* as long as data have to be received */ @@ -491,7 +492,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -507,7 +508,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t husart->RxXferCount = Size; /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); + USART_MASK_COMPUTATION(husart); uhMask = husart->Mask; /* Check the remain data to be sent */ @@ -574,7 +575,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pT { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL ) || (Size == 0)) + if((pTxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -621,7 +622,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx { if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == HAL_NULL ) || (Size == 0)) + if((pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -632,7 +633,7 @@ HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRx husart->RxXferSize = Size; husart->RxXferCount = Size; - __HAL_USART_MASK_COMPUTATION(husart); + USART_MASK_COMPUTATION(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_RX; @@ -679,7 +680,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint { if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -694,7 +695,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint husart->TxXferCount = Size; /* Computation of USART mask to apply to RDR register */ - __HAL_USART_MASK_COMPUTATION(husart); + USART_MASK_COMPUTATION(husart); husart->ErrorCode = HAL_USART_ERROR_NONE; husart->State = HAL_USART_STATE_BUSY_TX_RX; @@ -735,7 +736,7 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL ) || (Size == 0)) + if((pTxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -762,6 +763,9 @@ HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *p tmp = (uint32_t*)&pTxData; HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->TDR, Size); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); + /* Enable the DMA transfer for transmit request by setting the DMAT bit in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAT; @@ -793,7 +797,7 @@ HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pR if(husart->State == HAL_USART_STATE_READY) { - if((pRxData == HAL_NULL ) || (Size == 0)) + if((pRxData == NULL ) || (Size == 0)) { return HAL_ERROR; } @@ -866,7 +870,7 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin if(husart->State == HAL_USART_STATE_READY) { - if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) + if((pTxData == NULL) || (pRxData == NULL) || (Size == 0)) { return HAL_ERROR; } @@ -910,6 +914,9 @@ HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uin /* Clear the Overrun flag: mandatory for the second transfer in circular mode */ __HAL_USART_CLEAR_IT(husart, USART_CLEAR_OREF); + /* Clear the TC flag in the SR register by writing 0 to it */ + __HAL_USART_CLEAR_FLAG(husart, USART_FLAG_TC); + /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the USART CR3 register */ husart->Instance->CR3 |= USART_CR3_DMAR; @@ -981,12 +988,12 @@ HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart) */ /* Abort the USART DMA tx Stream */ - if(husart->hdmatx != HAL_NULL) + if(husart->hdmatx != NULL) { HAL_DMA_Abort(husart->hdmatx); } /* Abort the USART DMA rx Stream */ - if(husart->hdmarx != HAL_NULL) + if(husart->hdmarx != NULL) { HAL_DMA_Abort(husart->hdmarx); } @@ -1011,7 +1018,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART parity error interrupt occured ------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_PE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE) != RESET)) { - __HAL_USART_CLEAR_IT(husart, USART_IT_PE); + __HAL_USART_CLEAR_PEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_PE; /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; @@ -1020,7 +1027,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART frame error interrupt occured -------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_FE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { - __HAL_USART_CLEAR_IT(husart, USART_IT_FE); + __HAL_USART_CLEAR_FEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_FE; /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; @@ -1029,7 +1036,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART noise error interrupt occured -------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_NE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { - __HAL_USART_CLEAR_IT(husart, USART_IT_NE); + __HAL_USART_CLEAR_NEFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_NE; /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; @@ -1038,7 +1045,7 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) /* USART Over-Run interrupt occured ----------------------------------------*/ if((__HAL_USART_GET_IT(husart, USART_IT_ORE) != RESET) && (__HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR) != RESET)) { - __HAL_USART_CLEAR_IT(husart, USART_IT_ORE); + __HAL_USART_CLEAR_OREFLAG(husart); husart->ErrorCode |= HAL_USART_ERROR_ORE; /* Set the USART state ready to be able to start again the process */ husart->State = HAL_USART_STATE_READY; @@ -1075,6 +1082,12 @@ void HAL_USART_IRQHandler(USART_HandleTypeDef *husart) USART_TransmitReceive_IT(husart); } } + + /* USART in mode Transmitter (transmission end) -----------------------------*/ + if((__HAL_USART_GET_IT(husart, USART_IT_TC) != RESET) &&(__HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC) != RESET)) + { + USART_EndTransmit_IT(husart); + } } /** @@ -1153,7 +1166,7 @@ __weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart) * @} */ -/** @defgroup USART_Group3 Peripheral State functions +/** @addtogroup USART_Exported_Functions_Group3 * @brief USART State functions * @verbatim @@ -1271,37 +1284,23 @@ static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husar static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma) { USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; - /* DMA Normal mode */ - if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) + + husart->TxXferCount = 0; + + if(husart->State == HAL_USART_STATE_BUSY_TX) { - - husart->TxXferCount = 0; - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - /* Wait for USART TC Flag */ - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, HAL_USART_TXDMA_TIMEOUTVALUE) != HAL_OK) - { - /* Timeout Occured */ - husart->State = HAL_USART_STATE_TIMEOUT; - HAL_USART_ErrorCallback(husart); - } - else - { - /* No Timeout */ - /* Disable the DMA transfer for transmit request by setting the DMAT bit - in the USART CR3 register */ - husart->Instance->CR3 &= ~(USART_CR3_DMAT); - husart->State= HAL_USART_STATE_READY; - } - } + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the USART CR3 register */ + husart->Instance->CR3 &= ~(USART_CR3_DMAT); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); } - /* DMA Circular mode */ + /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ else { - if(husart->State == HAL_USART_STATE_BUSY_TX) - { - HAL_USART_TxCpltCallback(husart); - } + husart->State= HAL_USART_STATE_BUSY_RX; + HAL_USART_TxCpltCallback(husart); } } @@ -1329,13 +1328,14 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0) { husart->RxXferCount = 0; - husart->State= HAL_USART_STATE_READY; + if(husart->State == HAL_USART_STATE_BUSY_RX) { /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit in the USART CR3 register */ husart->Instance->CR3 &= ~(USART_CR3_DMAR); + husart->State= HAL_USART_STATE_READY; HAL_USART_RxCpltCallback(husart); } /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/ @@ -1346,6 +1346,7 @@ static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) husart->Instance->CR3 &= ~(USART_CR3_DMAR); husart->Instance->CR3 &= ~(USART_CR3_DMAT); + husart->State= HAL_USART_STATE_READY; HAL_USART_TxRxCpltCallback(husart); } } @@ -1403,48 +1404,37 @@ static void USART_DMAError(DMA_HandleTypeDef *hdma) */ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) { - uint16_t* tmp; + uint16_t* tmp = 0; if(husart->State == HAL_USART_STATE_BUSY_TX) { - if(husart->Init.WordLength == USART_WORDLENGTH_9B) + if(husart->TxXferCount == 0) + { + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); + + /* Enable the USART Transmit Complete Interrupt */ + __HAL_USART_ENABLE_IT(husart, USART_IT_TC); + + return HAL_OK; + } + else { - tmp = (uint16_t*) husart->pTxBuffPtr; - husart->Instance->TDR = (uint16_t)(*tmp & (uint16_t)0x01FF); - if(husart->Init.Parity == USART_PARITY_NONE) + if ((husart->Init.WordLength == USART_WORDLENGTH_9B) && (husart->Init.Parity == USART_PARITY_NONE)) { + tmp = (uint16_t*) husart->pTxBuffPtr; + husart->Instance->TDR = (*tmp & (uint16_t)0x01FF); husart->pTxBuffPtr += 2; } else - { - husart->pTxBuffPtr += 1; - } - } - else - { - husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF); - } - - if(--husart->TxXferCount == 0) - { - /* Disable the USART Transmit data register empty Interrupt */ - __HAL_USART_DISABLE_IT(husart, USART_IT_TXE); - - /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ - __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); - - - if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, HAL_USART_TXDMA_TIMEOUTVALUE) != HAL_OK) { - return HAL_TIMEOUT; - } - husart->State = HAL_USART_STATE_READY; - - HAL_USART_TxCpltCallback(husart); + husart->Instance->TDR = (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0xFF); + } + husart->TxXferCount--; + return HAL_OK; } - return HAL_OK; } else { @@ -1452,6 +1442,27 @@ static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart) } } +/** + * @brief Wraps up transmission in non blocking mode. + * @param husart: pointer to a USART_HandleTypeDef structure that contains + * the configuration information for the specified USART module. + * @retval HAL status + */ +static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart) +{ + /* Disable the USART Transmit Complete Interrupt */ + __HAL_USART_DISABLE_IT(husart, USART_IT_TC); + + /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */ + __HAL_USART_DISABLE_IT(husart, USART_IT_ERR); + + husart->State = HAL_USART_STATE_READY; + + HAL_USART_TxCpltCallback(husart); + + return HAL_OK; +} + /** * @brief Simplex Receive an amount of data in non-blocking mode. * Function called under interruption only, once @@ -1624,8 +1635,9 @@ static void USART_SetConfig(USART_HandleTypeDef *husart) * the USART Word Length, Parity, Mode and oversampling: * set the M bits according to husart->Init.WordLength value * set PCE and PS bits according to husart->Init.Parity value - * set TE and RE bits according to husart->Init.Mode value */ - tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode ; + * set TE and RE bits according to husart->Init.Mode value + * Force OVER8 bit to 1 in order to reach the max USART frequencies */ + tmpreg = (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode | USART_CR1_OVER8; MODIFY_REG(husart->Instance->CR1, USART_CR1_FIELDS, tmpreg); /*---------------------------- USART CR2 Configuration ---------------------*/ @@ -1634,7 +1646,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart) * set CPHA bit according to husart->Init.CLKPhase value * set LBCL bit according to husart->Init.CLKLastBit value * set STOP[13:12] bits according to husart->Init.StopBits value */ - tmpreg = (uint32_t)(USART_CLOCK_ENABLED); + tmpreg = (uint32_t)(USART_CLOCK_ENABLE); tmpreg |= (uint32_t)(husart->Init.CLKPolarity | husart->Init.CLKPhase); tmpreg |= (uint32_t)(husart->Init.CLKLastBit | husart->Init.StopBits); MODIFY_REG(husart->Instance->CR2, USART_CR2_FIELDS, tmpreg); @@ -1643,23 +1655,24 @@ static void USART_SetConfig(USART_HandleTypeDef *husart) /* no CR3 register configuration */ /*-------------------------- USART BRR Configuration -----------------------*/ - __HAL_USART_GETCLOCKSOURCE(husart, clocksource); + /* BRR is filled-up according to OVER8 bit setting which is forced to 1 */ + USART_GETCLOCKSOURCE(husart, clocksource); switch (clocksource) { case USART_CLOCKSOURCE_PCLK1: - husart->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK1Freq() / husart->Init.BaudRate); + husart->Instance->BRR = (uint16_t)((2 * HAL_RCC_GetPCLK1Freq())/ husart->Init.BaudRate); break; case USART_CLOCKSOURCE_PCLK2: - husart->Instance->BRR = (uint16_t)(HAL_RCC_GetPCLK2Freq() / husart->Init.BaudRate); + husart->Instance->BRR = (uint16_t)((2 * HAL_RCC_GetPCLK2Freq()) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_HSI: - husart->Instance->BRR = (uint16_t)(HSI_VALUE / husart->Init.BaudRate); + husart->Instance->BRR = (uint16_t)((2 * HSI_VALUE) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_SYSCLK: - husart->Instance->BRR = (uint16_t)(HAL_RCC_GetSysClockFreq() / husart->Init.BaudRate); + husart->Instance->BRR = (uint16_t)(( 2 * HAL_RCC_GetSysClockFreq()) / husart->Init.BaudRate); break; case USART_CLOCKSOURCE_LSE: - husart->Instance->BRR = (uint16_t)(LSE_VALUE / husart->Init.BaudRate); + husart->Instance->BRR = (uint16_t)((2 * LSE_VALUE) / husart->Init.BaudRate); break; default: break; @@ -1720,3 +1733,4 @@ static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.h index bc36dd1946c..da508a6ff59 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_usart.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of USART HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -56,11 +56,21 @@ * @{ */ -/** @addtogroup USART +/** @defgroup USART USART (Synchronous UART) * @{ */ -/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ +/* Exported types ------------------------------------------------------------*/ +/******************************************************************************/ + + /** @defgroup USART_Exported_Types USART Exported Types + * @{ + */ + +/** @defgroup USART_Init_Configuration USART initialization configuration structure + * @{ + */ /** * @brief USART Init Structure definition */ @@ -97,6 +107,13 @@ typedef struct This parameter can be a value of @ref USART_Last_Bit */ }USART_InitTypeDef; +/** + * @} + */ + +/** @defgroup USART_State_Definition USART state definition + * @{ + */ /** * @brief HAL State structures definition */ @@ -111,20 +128,29 @@ typedef enum HAL_USART_STATE_TIMEOUT = 0x03, /*!< Timeout state */ HAL_USART_STATE_ERROR = 0x04 /*!< Error */ }HAL_USART_StateTypeDef; - +/** + * @} + */ +/** @defgroup USART_Error_Definition USART error definition + * @{ + */ /** - * @brief HAL USART Error Code structure definition + * @brief HAL USART Error Code definition */ -typedef enum -{ - HAL_USART_ERROR_NONE = 0x00, /*!< No error */ - HAL_USART_ERROR_PE = 0x01, /*!< Parity error */ - HAL_USART_ERROR_NE = 0x02, /*!< Noise error */ - HAL_USART_ERROR_FE = 0x04, /*!< frame error */ - HAL_USART_ERROR_ORE = 0x08, /*!< Overrun error */ - HAL_USART_ERROR_DMA = 0x10 /*!< DMA transfer error */ -}HAL_USART_ErrorTypeDef; +#define HAL_USART_ERROR_NONE ((uint32_t)0x00) /*!< No error */ +#define HAL_USART_ERROR_PE ((uint32_t)0x01) /*!< Parity error */ +#define HAL_USART_ERROR_NE ((uint32_t)0x02) /*!< Noise error */ +#define HAL_USART_ERROR_FE ((uint32_t)0x04) /*!< frame error */ +#define HAL_USART_ERROR_ORE ((uint32_t)0x08) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA ((uint32_t)0x10) /*!< DMA transfer error */ + +/** + * @} + */ +/** @defgroup USART_Clock_SourceDefinition USART clock source definition + * @{ + */ /** * @brief USART clock sources definitions */ @@ -136,15 +162,16 @@ typedef enum USART_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */ USART_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */ }USART_ClockSourceTypeDef; - - -/** - * @brief HAL USART Error Code structure definition - */ - +/** + * @} + */ +/** @defgroup USART_handle_Definition Handle structure definition + * @{ + */ /** * @brief USART handle Structure definition - */ + */ + typedef struct { USART_TypeDef *Instance; /*!< USART registers base address */ @@ -173,17 +200,22 @@ typedef struct __IO HAL_USART_StateTypeDef State; /*!< Usart communication state */ - __IO HAL_USART_ErrorTypeDef ErrorCode; /*!< USART Error code */ + __IO uint32_t ErrorCode; /*!< USART Error code */ }USART_HandleTypeDef; - +/** + * @} + */ +/** + * @} + */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_Exported_Constants +/** @defgroup USART_Exported_Constants USART Exported Constants * @{ */ -/** @defgroup USART_Stop_Bits +/** @defgroup USART_Stop_Bits USART stop bit definition * @{ */ #define USART_STOPBITS_1 ((uint32_t)0x0000) @@ -198,7 +230,7 @@ typedef struct * @} */ -/** @defgroup USART_Parity +/** @defgroup USART_Parity USART parity definition * @{ */ #define USART_PARITY_NONE ((uint32_t)0x0000) @@ -211,29 +243,31 @@ typedef struct * @} */ -/** @defgroup USART_Mode +/** @defgroup USART_Mode USART mode definition * @{ */ #define USART_MODE_RX ((uint32_t)USART_CR1_RE) #define USART_MODE_TX ((uint32_t)USART_CR1_TE) #define USART_MODE_TX_RX ((uint32_t)(USART_CR1_TE |USART_CR1_RE)) -#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && ((MODE) != (uint32_t)0x00)) +#define IS_USART_MODE(MODE) (((MODE) == USART_MODE_RX) || \ + ((MODE) == USART_MODE_TX) || \ + ((MODE) == USART_MODE_TX_RX)) /** * @} */ -/** @defgroup USART_Clock +/** @defgroup USART_Clock USART clock activation definition * @{ */ -#define USART_CLOCK_DISABLED ((uint32_t)0x0000) -#define USART_CLOCK_ENABLED ((uint32_t)USART_CR2_CLKEN) -#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \ - ((CLOCK) == USART_CLOCK_ENABLED)) +#define USART_CLOCK_DISABLE ((uint32_t)0x0000) +#define USART_CLOCK_ENABLE ((uint32_t)USART_CR2_CLKEN) +#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLE) || \ + ((CLOCK) == USART_CLOCK_ENABLE)) /** * @} */ -/** @defgroup USART_Clock_Polarity +/** @defgroup USART_Clock_Polarity USART polarity level definition * @{ */ #define USART_POLARITY_LOW ((uint32_t)0x0000) @@ -243,7 +277,7 @@ typedef struct * @} */ -/** @defgroup USART_Clock_Phase +/** @defgroup USART_Clock_Phase USART clock phase definition * @{ */ #define USART_PHASE_1EDGE ((uint32_t)0x0000) @@ -253,7 +287,7 @@ typedef struct * @} */ -/** @defgroup USART_Last_Bit +/** @defgroup USART_Last_Bit USART last bit activation definition * @{ */ #define USART_LASTBIT_DISABLE ((uint32_t)0x0000) @@ -265,7 +299,7 @@ typedef struct */ -/** @defgroup USART_Flags +/** @defgroup USART_Flags USART flag definitions * Elements values convention: 0xXXXX * - 0xXXXX : Flag mask in the ISR register * @{ @@ -288,7 +322,7 @@ typedef struct * @} */ -/** @defgroup USART_Interrupt_definition +/** @defgroup USART_Interrupt_definition USART interrupt definition * Elements values convention: 0000ZZZZ0XXYYYYYb * - YYYYY : Interrupt source position in the XX register (5bits) * - XX : Interrupt source register (2bits) @@ -313,7 +347,7 @@ typedef struct * @} */ -/** @defgroup USART_IT_CLEAR_Flags +/** @defgroup USART_IT_CLEAR_Flags USART interrupt clear flags definition * @{ */ #define USART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ @@ -327,7 +361,7 @@ typedef struct * @} */ -/** @defgroup USART_Request_Parameters +/** @defgroup USART_Request_Parameters USART request parameter definition * @{ */ #define USART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /*!< Receive Data flush Request */ @@ -338,7 +372,7 @@ typedef struct * @} */ -/** @defgroup USART_Interruption_Mask +/** @defgroup USART_Interruption_Mask USART interruption mask definition * @{ */ #define USART_IT_MASK ((uint16_t)0x001F) @@ -353,16 +387,27 @@ typedef struct /* Exported macro ------------------------------------------------------------*/ -/** @defgroup USART_Exported_Macros +/** @defgroup USART_Exported_Macros USART Exported Macros * @{ */ /** @brief Reset USART handle state - * @param __HANDLE__: specifies the UART Handle. + * @param __HANDLE__: specifies the USART Handle. * The Handle Instance which can be USART1 or USART2. * @retval None */ #define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET) +/** @brief Flush the USART Data registers + * @param __HANDLE__: specifies the USART Handle. + */ +#define __HAL_USART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, USART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, USART_TXDATA_FLUSH_REQUEST); \ + } while(0) + + + /** @brief Checks whether the specified USART flag is set or not. * @param __HANDLE__: specifies the USART Handle which can be USART1 or USART2. * @param __FLAG__: specifies the flag to check. @@ -383,6 +428,55 @@ typedef struct */ #define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) +/** @brief Clears the specified USART pending flag. + * @param __HANDLE__: specifies the USART Handle. + * @param __FLAG__: specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg USART_CLEAR_PEF + * @arg USART_CLEAR_FEF + * @arg USART_CLEAR_NEF + * @arg USART_CLEAR_OREF + * @arg USART_CLEAR_IDLEF + * @arg USART_CLEAR_TCF + * @arg USART_CLEAR_LBDF + * @arg USART_CLEAR_CTSF + * @arg USART_CLEAR_RTOF + * @arg USART_CLEAR_EOBF + * @arg USART_CLEAR_CMF + * @arg USART_CLEAR_WUF + * @retval None + */ +#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ~(__FLAG__)) + +/** @brief Clear the USART PE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG(__HANDLE__,USART_CLEAR_PEF) + +/** @brief Clear the USART FE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG(__HANDLE__,USART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG(__HANDLE__,USART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG(__HANDLE__,USART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_FLAG(__HANDLE__,USART_CLEAR_IDLEF) /** @brief Enables the specified USART interrupt. * @param __HANDLE__: specifies the USART Handle which can be USART1 or USART2. @@ -476,7 +570,19 @@ typedef struct * * @retval None */ -#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) +#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__)) + +/** @brief Enables the USART one bit sample method + * @param __HANDLE__: specifies the USART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disables the UART one bit sample method + * @param __HANDLE__: specifies the UART Handle. + * @retval None + */ +#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT)) /** @brief Enable USART * @param __HANDLE__: specifies the USART Handle. @@ -505,17 +611,27 @@ typedef struct * @} */ -/* Include UART HAL Extension module */ +/* Include USART HAL Extension module */ #include "stm32l0xx_hal_usart_ex.h" /* Exported functions --------------------------------------------------------*/ - +/** @defgroup USART_Exported_Functions USART Exported Functions + * @{ + */ /* Initialization/de-initialization functions ********************************/ +/** @defgroup USART_Exported_Functions_Group1 Initialization/de-initialization functions + * @{ + */ HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart); void HAL_USART_MspInit(USART_HandleTypeDef *husart); void HAL_USART_MspDeInit(USART_HandleTypeDef *husart); -void HAL_USART_SetConfig(USART_HandleTypeDef *husart); +/** + * @} + */ /* IO operation functions *****************************************************/ +/** @defgroup USART_Exported_Functions_Group2 IO operation functions + * @{ + */ HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); @@ -535,15 +651,25 @@ void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart); void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart); - +/** + * @} + */ +/* IO operation functions *****************************************************/ +/** @defgroup USART_Exported_Functions_Group3 Peripheral State functions + * @{ + */ /* Peripheral State functions ************************************************/ HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart); uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); - +/** + * @} + */ +/** + * @} + */ /** * @} */ - /** * @} */ @@ -555,3 +681,4 @@ uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart); #endif /* __STM32L0xx_HAL_USART_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart_ex.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart_ex.h index 435800aff25..2aa7746c9ce 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart_ex.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_usart_ex.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -49,18 +49,17 @@ /** @addtogroup STM32L0xx_HAL_Driver * @{ */ - -/** @addtogroup USARTEx +/** @defgroup USARTEx USARTEx Extended USART * @{ - */ + */ /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ -/** @defgroup USARTEx_Exported_Constants +/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants * @{ */ -/** @defgroup USARTEx_Word_Length +/** @defgroup USARTEx_Word_Length Word length definition * @{ */ #define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1) @@ -78,7 +77,7 @@ */ /* Exported macro ------------------------------------------------------------*/ -/** @defgroup USARTEx_Extended_Exported_Macros +/** @defgroup USARTEx_Extended_Exported_Macros USARTEx Exported Macros * @{ */ @@ -87,11 +86,38 @@ * @param __CLOCKSOURCE__ : output variable * @retval the USART clocking source, written in __CLOCKSOURCE__. */ -#define __HAL_USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ +#if defined (STM32L031xx) || defined (STM32L041xx) +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART2) \ + { \ + switch(__HAL_RCC_GET_USART2_SOURCE()) \ + { \ + case RCC_USART2CLKSOURCE_PCLK1: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK1; \ + break; \ + case RCC_USART2CLKSOURCE_HSI: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI; \ + break; \ + case RCC_USART2CLKSOURCE_SYSCLK: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_SYSCLK; \ + break; \ + case RCC_USART2CLKSOURCE_LSE: \ + (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE; \ + break; \ + default: \ + break; \ + } \ + } \ + } while(0) + +#else /* (STM32L031xx) || defined (STM32L041xx) */ + +#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ do { \ if((__HANDLE__)->Instance == USART1) \ { \ - switch(__HAL_RCC_GET_USART1_SOURCE()) \ + switch(__HAL_RCC_GET_USART1_SOURCE()) \ { \ case RCC_USART1CLKSOURCE_PCLK2: \ (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PCLK2; \ @@ -130,6 +156,7 @@ } \ } \ } while(0) +#endif /* (STM32L031xx) || (STM32L041xx) */ /** @brief Reports the USART mask to apply to retrieve the received data * according to the word length and to the parity bits activation. @@ -138,10 +165,9 @@ * This masking operation is not carried out in the case of * DMA transfers. * @param __HANDLE__: specifies the USART Handle - * @param __MASK__ : output variable * @retval mask to apply to USART RDR register value. */ -#define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \ +#define USART_MASK_COMPUTATION(__HANDLE__) \ do { \ if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B) \ { \ @@ -204,3 +230,4 @@ #endif /* __STM32L0xx_HAL_USART_EX_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.c index 4bc1ef1726b..e3085f4191e 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.c +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.c @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32l0xx_hal_wwdg.c * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -36,7 +36,7 @@ ##### How to use this driver ##### ============================================================================== [..] - (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE(). + (+) Enable WWDG APB1 clock using __HAL_RCC_WWDG_CLK_ENABLE(). (+) Set the WWDG prescaler, refresh window and counter value using HAL_WWDG_Init() function. (+) Start the WWDG using HAL_WWDG_Start() function. @@ -65,7 +65,7 @@ ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -99,25 +99,18 @@ * @{ */ -/** @defgroup WWDG +/** @addtogroup WWDG * @brief WWDG HAL module driver. * @{ */ #ifdef HAL_WWDG_MODULE_ENABLED -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup WWDG_Private_Functions +/** @addtogroup WWDG_Exported_Functions WWDG Exported Functions * @{ */ -/** @defgroup WWDG_Group1 Initialization and de-initialization functions +/** @addtogroup WWDG_Exported_Functions_Group1 * @brief Initialization and Configuration functions. * @verbatim @@ -139,16 +132,15 @@ /** * @brief Initializes the WWDG according to the specified * parameters in the WWDG_InitTypeDef and creates the associated handle. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) { - uint32_t tmp = 0; /* Check the WWDG handle allocation */ - if(hwwdg == HAL_NULL) + if(hwwdg == NULL) { return HAL_ERROR; } @@ -165,37 +157,17 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) HAL_WWDG_MspInit(hwwdg); } - /* Change WWDG peripheral state */ + /* Take lock and change peripheral state */ + __HAL_LOCK(hwwdg); hwwdg->State = HAL_WWDG_STATE_BUSY; - /* Set WWDG Prescaler and Window */ - /* Get the CFR register value */ - tmp = hwwdg->Instance->CFR; - - /* Clear WDGTB[1:0] and W[6:0] bits */ - tmp &= ((uint32_t)~(WWDG_CFR_WDGTB | WWDG_CFR_W)); - - /* Prepare the WWDG Prescaler and Window parameters */ - tmp |= hwwdg->Init.Prescaler | hwwdg->Init.Window; - - /* Write to WWDG CFR */ - hwwdg->Instance->CFR = tmp; - - /* Set WWDG Counter */ - /* Get the CR register value */ - tmp = hwwdg->Instance->CR; - - /* Clear T[6:0] bits */ - tmp &= (uint32_t)~((uint32_t)WWDG_CR_T); - - /* Prepare the WWDG Counter parameter */ - tmp |= (hwwdg->Init.Counter); - - /* Write to WWDG CR */ - hwwdg->Instance->CR = tmp; + /* Set WWDG Prescaler and Window and Counter*/ + MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window)); + MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter); - /* Change WWDG peripheral state */ + /* Change peripheral state and release lock*/ hwwdg->State = HAL_WWDG_STATE_READY; + __HAL_UNLOCK(hwwdg); /* Return function status */ return HAL_OK; @@ -203,7 +175,7 @@ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg) /** * @brief DeInitializes the WWDG peripheral. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status */ @@ -212,25 +184,20 @@ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) /* Check the parameters */ assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance)); - /* Change WWDG peripheral state */ + /* Take lock and change peripheral state */ + __HAL_LOCK(hwwdg); hwwdg->State = HAL_WWDG_STATE_BUSY; /* DeInit the low level hardware */ HAL_WWDG_MspDeInit(hwwdg); - /* Reset WWDG Control register */ - hwwdg->Instance->CR = (uint32_t)0x0000007F; - - /* Reset WWDG Configuration register */ - hwwdg->Instance->CFR = (uint32_t)0x0000007F; + /* Reset WWDG Control, configuration and status register */ + MODIFY_REG(hwwdg->Instance->CR, (WWDG_CR_T | WWDG_CR_WDGA),0x0000007F); + MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W | WWDG_CFR_EWI),0x0000007F); + MODIFY_REG(hwwdg->Instance->SR,WWDG_SR_EWIF,0x0); - /* Reset WWDG Status register */ - hwwdg->Instance->SR = 0; - - /* Change WWDG peripheral state */ + /* Change peripheral state and release lock*/ hwwdg->State = HAL_WWDG_STATE_RESET; - - /* Release Lock */ __HAL_UNLOCK(hwwdg); /* Return function status */ @@ -239,7 +206,7 @@ HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg) /** * @brief Initializes the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */ @@ -252,7 +219,7 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) /** * @brief DeInitializes the WWDG MSP. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */ @@ -267,7 +234,7 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) * @} */ -/** @defgroup WWDG_Group2 IO operation functions +/** @addtogroup WWDG_Exported_Functions_Group2 * @brief IO operation functions * @verbatim @@ -286,25 +253,21 @@ __weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg) /** * @brief Starts the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) { - /* Process Locked */ + /* Take lock and change peripheral state */ __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ hwwdg->State = HAL_WWDG_STATE_BUSY; /* Enable the peripheral */ __HAL_WWDG_ENABLE(hwwdg); - /* Change WWDG peripheral state */ + /* Change peripheral state and release lock*/ hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ __HAL_UNLOCK(hwwdg); /* Return function status */ @@ -313,42 +276,39 @@ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg) /** * @brief Starts the WWDG with interrupt enabled. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg) { - /* Process Locked */ + /* Take lock and change peripheral state */ __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ hwwdg->State = HAL_WWDG_STATE_BUSY; /* Enable the Early Wakeup Interrupt */ - __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI); + __HAL_WWDG_ENABLE_IT(hwwdg,WWDG_IT_EWI); /* Enable the peripheral */ __HAL_WWDG_ENABLE(hwwdg); + /* Change peripheral state and release lock*/ + hwwdg->State = HAL_WWDG_STATE_READY; + __HAL_UNLOCK(hwwdg); + /* Return function status */ return HAL_OK; } /** * @brief Refreshes the WWDG. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @param Counter: value of counter to put in WWDG counter * @retval HAL status */ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) { - /* Process Locked */ - __HAL_LOCK(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_BUSY; /* Check the parameters */ assert_param(IS_WWDG_COUNTER(Counter)); @@ -356,12 +316,6 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) /* Write to WWDG CR the WWDG Counter value to refresh with */ MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter); - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); - /* Return function status */ return HAL_OK; } @@ -375,47 +329,42 @@ HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter) * generated and the corresponding Interrupt Service Routine (ISR) can * be used to trigger specific actions (such as communications or data * logging), before resetting the device. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */ void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg) { - /* WWDG Early Wakeup Interrupt occurred */ - if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + /* Check if Early Wakeup Interrupt is enable */ + if(__HAL_WWDG_GET_IT_SOURCE(hwwdg, WWDG_IT_EWI) != RESET) { - /* Early Wakeup callback */ - HAL_WWDG_WakeupCallback(hwwdg); - - /* Change WWDG peripheral state */ - hwwdg->State = HAL_WWDG_STATE_READY; - - /* Clear the WWDG Data Ready flag */ - __HAL_WWDG_CLEAR_IT(hwwdg, WWDG_FLAG_EWIF); - - /* Process Unlocked */ - __HAL_UNLOCK(hwwdg); + /* Check if WWDG Early Wakeup Interrupt occurred */ + if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET) + { + /* Early Wakeup callback */ + HAL_WWDG_WakeupCallback(hwwdg); + + /* Clear the WWDG Data Ready flag */ + __HAL_WWDG_CLEAR_IT(hwwdg, WWDG_FLAG_EWIF); + } } } /** * @brief Early Wakeup WWDG callback. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) { - /* NOTE: This function Should not be modified, when the callback is needed, - the HAL_WWDG_WakeupCallback could be implemented in the user file - */ } /** * @} */ -/** @defgroup WWDG_Group3 Peripheral State functions +/** @addtogroup WWDG_Exported_Functions_Group3 * @brief Peripheral State functions. * @verbatim @@ -432,7 +381,7 @@ __weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg) /** * @brief Returns the WWDG state. - * @param hwwdg: pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval HAL state */ @@ -459,3 +408,4 @@ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg) */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.h index 293e3cffbf5..cea1c35ff5d 100644 --- a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.h +++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/stm32l0xx_hal_wwdg.h @@ -2,13 +2,13 @@ ****************************************************************************** * @file stm32l0xx_hal_wwdg.h * @author MCD Application Team - * @version V1.1.0 - * @date 18-June-2014 + * @version V1.2.0 + * @date 06-February-2015 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention * - *

© COPYRIGHT(c) 2014 STMicroelectronics

+ *

© COPYRIGHT(c) 2015 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -50,7 +50,7 @@ * @{ */ -/** @addtogroup WWDG +/** @defgroup WWDG WWDG (Window watchdog) * @{ */ @@ -59,7 +59,10 @@ /** @defgroup WWDG_Exported_Types WWDG Exported Types * @{ */ - + +/** @defgroup WWDG_State WWDG state definition + * @{ + */ /** * @brief WWDG HAL State Structure definition */ @@ -72,8 +75,15 @@ typedef enum HAL_WWDG_STATE_ERROR = 0x04 /*!< WWDG error state */ }HAL_WWDG_StateTypeDef; +/** + * @} + */ + +/** @defgroup WWDG_Init WWDG init configuration structure + * @{ + */ /** - * @brief WWDG Init structure definition + * @brief WWDG Init configuration structure */ typedef struct { @@ -87,7 +97,13 @@ typedef struct This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */ }WWDG_InitTypeDef; +/** + * @} + */ +/** @defgroup WWDG_handle WWDG handler + * @{ + */ /** * @brief WWDG handle Structure definition */ @@ -103,6 +119,10 @@ typedef struct }WWDG_HandleTypeDef; +/** + * @} + */ + /** * @} */ @@ -120,7 +140,7 @@ typedef struct /* --- CFR Register ---*/ /* Alias word address of EWI bit */ -#define CFR_BASE (uint32_t)(WWDG_BASE + 0x04) +#define WWDG_CFR_BASE (uint32_t)(WWDG_BASE + 0x04) /** * @} @@ -130,9 +150,6 @@ typedef struct * @{ */ #define WWDG_IT_EWI ((uint32_t)WWDG_CFR_EWI) - -#define IS_WWDG_IT(__IT__) ((__IT__) == WWDG_IT_EWI) - /** * @} */ @@ -142,9 +159,6 @@ typedef struct * @{ */ #define WWDG_FLAG_EWIF ((uint32_t)WWDG_SR_EWIF) /*!< Early wakeup interrupt flag */ - -#define IS_WWDG_FLAG(__FLAG__) ((__FLAG__) == WWDG_FLAG_EWIF)) - /** * @} */ @@ -156,34 +170,22 @@ typedef struct #define WWDG_PRESCALER_2 ((uint32_t)WWDG_CFR_WDGTB0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ #define WWDG_PRESCALER_4 ((uint32_t)WWDG_CFR_WDGTB1) /*!< WWDG counter clock = (PCLK1/4096)/4 */ #define WWDG_PRESCALER_8 ((uint32_t)WWDG_CFR_WDGTB) /*!< WWDG counter clock = (PCLK1/4096)/8 */ - +/** + * @} + */ #define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \ ((__PRESCALER__) == WWDG_PRESCALER_2) || \ ((__PRESCALER__) == WWDG_PRESCALER_4) || \ ((__PRESCALER__) == WWDG_PRESCALER_8)) -/** - * @} - */ -/** @defgroup WWDG_Window WWDG Window - * @{ - */ -#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) -/** - * @} - */ +/* Check for window */ +#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F) -/** @defgroup WWDG_Counter WWDG Counter - * @{ - */ +/* Check for counter */ #define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F)) -/** - * @} - */ - /** * @} */ @@ -208,34 +210,44 @@ typedef struct #define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) /** - * @brief Gets the selected WWDG's flag status. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag - * @retval The new state of WWDG_FLAG (SET or RESET). - */ -#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clears the WWDG's pending flags. + * @brief Disables the WWDG peripheral. * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to clear. - * This parameter can be one of the following values: - * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @note WARNING: This is a dummy macro for HAL code alignment. + * Once enable, WWDG Peripheral cannot be disabled except by a system reset. * @retval None */ -#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) +#define __HAL_WWDG_DISABLE(__HANDLE__) /* dummy macro */ /** * @brief Enables the WWDG early wakeup interrupt. + * @param __HANDLE__: WWDG handle * @param __INTERRUPT__: specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt * @note Once enabled this interrupt cannot be disabled except by a system reset. * @retval None */ -#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__) (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__)) +#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CFR |= (__INTERRUPT__)) +/** + * @brief Disables the WWDG early wakeup interrupt. + * @param __HANDLE__: WWDG handle: + * @param __INTERRUPT__: specifies the interrupt to disable. + * @arg WWDG_IT_EWI: Early wakeup interrupt + * @note WARNING: This is a dummy macro for HAL code alignment. + * Once enabled this interrupt cannot be disabled except by a system reset. + * @retval None + */ +#define __HAL_WWDG_DISABLE_IT(__HANDLE__, __INTERRUPT__) /* dummy macro */ + +/** + * @brief Gets the selected WWDG's it status. + * @param __HANDLE__: WWDG handle + * @param __INTERRUPT__: specifies the it to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Clear the WWDG's interrupt pending bits * bits to clear the selected interrupt pending bits. @@ -246,35 +258,78 @@ typedef struct */ #define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__)) +/** + * @brief Gets the selected WWDG's flag status. + * @param __HANDLE__: WWDG handle + * @param __FLAG__: specifies the flag to check. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval The new state of WWDG_FLAG (SET or RESET). + */ +#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__)) + +/** + * @brief Clears the WWDG's pending flags. + * @param __HANDLE__: WWDG handle + * @param __FLAG__: specifies the flag to clear. + * This parameter can be one of the following values: + * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag + * @retval None + */ +#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) + +/** @brief Checks if the specified WWDG interrupt source is enabled or disabled. + * @param __HANDLE__: WWDG Handle. + * @param __INTERRUPT__: specifies the WWDG interrupt source to check. + * This parameter can be one of the following values: + * @arg WWDG_IT_EWI: Early Wakeup Interrupt + * @retval state of __INTERRUPT__ (TRUE or FALSE). + */ +#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR & (__INTERRUPT__)) == (__INTERRUPT__)) + /** * @} */ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup WWDG_Exported_Functions +/** @defgroup WWDG_Exported_Functions WWDG Exported Functions * @{ */ -/* Initialization/de-initialization functions **********************************/ +/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg); HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg); void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg); +/** + * @} + */ -/* I/O operation functions ******************************************************/ +/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions + * @{ + */ HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg); HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg); HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter); void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg); +/** + * @} + */ -/* Peripheral State functions **************************************************/ +/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions + * @{ + */ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); +/** + * @} + */ /** * @} - */ + */ /** * @} @@ -291,3 +346,4 @@ HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg); #endif /* __STM32L0xx_HAL_WWDG_H */ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h index 024a2769094..a4da0f851a2 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/TARGET_TEENSY3_1/PinNames.h @@ -210,40 +210,40 @@ typedef enum { DAC0_OUT = 0xFEFE, /* DAC does not have Pin Name in RM */ // Teensy3.1 Headers - p0 = PTB16, - p1 = PTB17, - p2 = PTD0, - p3 = PTA12, - p4 = PTA13, - p5 = PTD7, - p6 = PTD4, - p7 = PTD2, - p8 = PTD3, - p9 = PTC3, - p10 = PTC4, - p11 = PTC6, - p12 = PTC7, - p13 = PTC5, - p14 = PTD1, - p15 = PTC0, - p16 = PTB0, - p17 = PTB1, - p18 = PTB3, - p19 = PTB2, - p20 = PTD5, - p21 = PTD6, - p22 = PTC1, - p23 = PTC2, - p24 = PTA5, - p25 = PTD19, - p26 = PTE1, - p27 = PTC9, - p28 = PTC8, - p29 = PTC10, - p30 = PTC11, - p31 = PTE0, - p32 = PTB18, - p33 = PTA4, + D0 = PTB16, + D1 = PTB17, + D2 = PTD0, + D3 = PTA12, + D4 = PTA13, + D5 = PTD7, + D6 = PTD4, + D7 = PTD2, + D8 = PTD3, + D9 = PTC3, + D10 = PTC4, + D11 = PTC6, + D12 = PTC7, + D13 = PTC5, + D14 = PTD1, + D15 = PTC0, + D16 = PTB0, + D17 = PTB1, + D18 = PTB3, + D19 = PTB2, + D20 = PTD5, + D21 = PTD6, + D22 = PTC1, + D23 = PTC2, + D24 = PTA5, + D25 = PTB19, + D26 = PTE1, + D27 = PTC9, + D28 = PTC8, + D29 = PTC10, + D30 = PTC11, + D31 = PTE0, + D32 = PTB18, + D33 = PTA4, A0 = PTD1, A1 = PTC0, @@ -255,7 +255,13 @@ typedef enum { A7 = PTD6, A8 = PTC1, A9 = PTC2, - + A15 = PTE1, + A16 = PTC9, + A17 = PTC8, + A18 = PTC10, + A19 = PTC11, + A20 = PTE0, + I2C_SCL = PTB3, I2C_SDA = PTB2, @@ -267,7 +273,18 @@ typedef enum { SERIAL_TX = PTB17, SERIAL_RX = PTB16, - PWM = PTD7, + PWM = PTA12, + PWM1 = PTA13, + PWM2 = PTD7, + PWM3 = PTD4, + PWM4 = PTC3, + PWM5 = PTC4, + PWM6 = PTD5, + PWM7 = PTD6, + PWM8 = PTC1, + PWM9 = PTC2, + PWM10 = PTB19, + PWM11 = PTB18, DAC = DAC0_OUT, diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h index edf5aaa6ce2..6067a60cd57 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/objects.h @@ -41,7 +41,7 @@ struct port_s { struct pwmout_s { __IO uint32_t *MOD; - __IO uint32_t *CNT; + __IO uint32_t *SYNC; __IO uint32_t *CnV; }; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c index fa318980aa7..b3935045912 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/pwmout_api.c @@ -38,26 +38,30 @@ void pwmout_init(pwmout_t* obj, PinName pin) { } pwm_clock = clkval; - unsigned int port = (unsigned int)pin >> PORT_SHIFT; unsigned int ftm_n = (pwm >> TPM_SHIFT); unsigned int ch_n = (pwm & 0xFF); - SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); SIM->SCGC6 |= 1 << (SIM_SCGC6_FTM0_SHIFT + ftm_n); FTM_Type *ftm = (FTM_Type *)(FTM0_BASE + 0x1000 * ftm_n); ftm->CONF |= FTM_CONF_BDMMODE(3); ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(clkdiv); // (clock)MHz / clkdiv ~= (0.75)MHz ftm->CONTROLS[ch_n].CnSC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */ + ftm->MODE = FTM_MODE_FTMEN_MASK; + ftm->SYNC = FTM_SYNC_CNTMIN_MASK; + ftm->SYNCONF = FTM_SYNCONF_SYNCMODE_MASK | FTM_SYNCONF_SWSOC_MASK | FTM_SYNCONF_SWWRBUF_MASK; + + //Without SYNCEN set CnV does not seem to update + ftm->COMBINE = FTM_COMBINE_SYNCEN0_MASK | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN2_MASK | FTM_COMBINE_SYNCEN3_MASK; obj->CnV = &ftm->CONTROLS[ch_n].CnV; obj->MOD = &ftm->MOD; - obj->CNT = &ftm->CNT; + obj->SYNC = &ftm->SYNC; // default to 20ms: standard for servos, and fine for e.g. brightness control pwmout_period_ms(obj, 20); - pwmout_write(obj, 0); - + pwmout_write(obj, 0.0); + // Wire pinout pinmap_pinout(pin, PinMap_PWM); } @@ -70,11 +74,14 @@ void pwmout_write(pwmout_t* obj, float value) { } else if (value > 1.0) { value = 1.0; } - + + while(*obj->SYNC & FTM_SYNC_SWSYNC_MASK); *obj->CnV = (uint32_t)((float)(*obj->MOD + 1) * value); + *obj->SYNC |= FTM_SYNC_SWSYNC_MASK; } float pwmout_read(pwmout_t* obj) { + while(*obj->SYNC & FTM_SYNC_SWSYNC_MASK); float v = (float)(*obj->CnV) / (float)(*obj->MOD + 1); return (v > 1.0) ? (1.0) : (v); } @@ -91,6 +98,7 @@ void pwmout_period_ms(pwmout_t* obj, int ms) { void pwmout_period_us(pwmout_t* obj, int us) { float dc = pwmout_read(obj); *obj->MOD = (uint32_t)(pwm_clock * (float)us) - 1; + *obj->SYNC |= FTM_SYNC_SWSYNC_MASK; pwmout_write(obj, dc); } @@ -104,4 +112,5 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) { void pwmout_pulsewidth_us(pwmout_t* obj, int us) { *obj->CnV = (uint32_t)(pwm_clock * (float)us); + *obj->SYNC |= FTM_SYNC_SWSYNC_MASK; } diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c index 459c7b691a6..d7dd1c8050c 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/rtc.api.c @@ -29,9 +29,15 @@ static void init(void) { void rtc_init(void) { init(); - + // Enable the oscillator +#if defined (TARGET_K20D50M) RTC->CR |= RTC_CR_OSCE_MASK; +#else + // Teensy3.1 requires 20pF MCU loading capacitors for 32KHz RTC oscillator + /* RTC->CR: SC2P=0,SC4P=1,SC8P=0,SC16P=1,CLKO=0,OSCE=1,UM=0,SUP=0,SPE=0,SWR=0 */ + RTC->CR |= RTC_CR_OSCE_MASK |RTC_CR_SC16P_MASK | RTC_CR_SC4P_MASK; +#endif //Configure the TSR. default value: 1 RTC->TSR = 1; diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c index b5e8df31dee..6ccb7e5d888 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20XX/sleep.c @@ -39,13 +39,32 @@ void deepsleep(void) SCB->SCR = 1<C6 & (1<S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */ MCG->C1 &= ~MCG_C1_CLKS_MASK; +#else + // MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 + MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3) | MCG_C1_IRCLKEN_MASK; + // MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 + MCG->C6 = MCG_C6_VDIV0(0); + while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { } // Check that the oscillator is running + while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output + // MCG->C5: PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 + MCG->C5 = MCG_C5_PRDIV0(5); + // MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=3 + MCG->C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV0(3); + while((MCG->S & 0x0Cu) != 0x08u) { } // Wait until external reference clock is selected as MCG output + while((MCG->S & MCG_S_PLLST_MASK) == 0u) { } // Wait until the source of the PLLS clock has switched to the PLL + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked + // MCG->C1: CLKS=0,FRDIV=2,IREFS=0,IRCLKEN=1,IREFSTEN=0 + MCG->C1 = MCG_C1_FRDIV(2) | MCG_C1_IRCLKEN_MASK;; + while((MCG->S & 0x0Cu) != 0x0Cu) { } // Wait until output of the PLL is selected + while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { } // Wait until locked +#endif } - } diff --git a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/serial_api.c b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/serial_api.c index 3043ba29b22..68e3105c006 100644 --- a/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_Freescale/TARGET_KPSDK_MCUS/serial_api.c @@ -96,7 +96,7 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b UART_HAL_SetBitCountPerChar(uart_addrs[obj->index], (uart_bit_count_per_char_t)data_bits); UART_HAL_SetParityMode(uart_addrs[obj->index], (uart_parity_mode_t)parity); #if FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT - UART_HAL_SetStopBitCount(uart_addrs[obj->index], (uart_stop_bit_count_t)stop_bits); + UART_HAL_SetStopBitCount(uart_addrs[obj->index], (uart_stop_bit_count_t)--stop_bits); #endif } diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/analogin_api.c index 92051a6825b..7af8188b0f9 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_DISCO_L053C8/analogin_api.c @@ -65,7 +65,7 @@ void analogin_init(analogin_t *obj, PinName pin) AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV1; AdcHandle.Init.Resolution = ADC_RESOLUTION12b; AdcHandle.Init.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; - AdcHandle.Init.ScanDirection = ADC_SCAN_DIRECTION_UPWARD; + AdcHandle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; AdcHandle.Init.ContinuousConvMode = DISABLE; AdcHandle.Init.DiscontinuousConvMode = DISABLE; @@ -76,7 +76,7 @@ void analogin_init(analogin_t *obj, PinName pin) AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; AdcHandle.Init.LowPowerAutoWait = ENABLE; AdcHandle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz - AdcHandle.Init.LowPowerAutoOff = DISABLE; + AdcHandle.Init.LowPowerAutoPowerOff = DISABLE; HAL_ADC_Init(&AdcHandle); // Calibration diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/analogin_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/analogin_api.c index 92051a6825b..7af8188b0f9 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/analogin_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/analogin_api.c @@ -65,7 +65,7 @@ void analogin_init(analogin_t *obj, PinName pin) AdcHandle.Init.ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV1; AdcHandle.Init.Resolution = ADC_RESOLUTION12b; AdcHandle.Init.SamplingTime = ADC_SAMPLETIME_41CYCLES_5; - AdcHandle.Init.ScanDirection = ADC_SCAN_DIRECTION_UPWARD; + AdcHandle.Init.ScanConvMode = ADC_SCAN_DIRECTION_FORWARD; AdcHandle.Init.DataAlign = ADC_DATAALIGN_RIGHT; AdcHandle.Init.ContinuousConvMode = DISABLE; AdcHandle.Init.DiscontinuousConvMode = DISABLE; @@ -76,7 +76,7 @@ void analogin_init(analogin_t *obj, PinName pin) AdcHandle.Init.Overrun = OVR_DATA_OVERWRITTEN; AdcHandle.Init.LowPowerAutoWait = ENABLE; AdcHandle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz - AdcHandle.Init.LowPowerAutoOff = DISABLE; + AdcHandle.Init.LowPowerAutoPowerOff = DISABLE; HAL_ADC_Init(&AdcHandle); // Calibration diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/analogout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/analogout_api.c index 8dbabd118d9..001c583d502 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/analogout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/analogout_api.c @@ -39,30 +39,44 @@ static DAC_HandleTypeDef DacHandle; +// These variables are used for the "free" function +static int pa4_used = 0; +static int pa5_used = 0; + void analogout_init(dac_t *obj, PinName pin) { DAC_ChannelConfTypeDef sConfig; - DacHandle.Instance = DAC; - - // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object + // Get the peripheral name from the pin and assign it to the object obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC); MBED_ASSERT(obj->dac != (DACName)NC); // Configure GPIO pinmap_pinout(pin, PinMap_DAC); - // Save the channel for future use + // Save the pin for future use obj->pin = pin; // Enable DAC clock __DAC_CLK_ENABLE(); // Configure DAC + DacHandle.Instance = DAC; + sConfig.DAC_Trigger = DAC_TRIGGER_NONE; sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE; - HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); + if (pin == PA_4) { + HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1); + pa4_used = 1; + } + +#if defined(DAC_CHANNEL_2) + if (pin == PA_5) { + HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2); + pa5_used = 1; + } +#endif analogout_write_u16(obj, 0); } @@ -70,9 +84,14 @@ void analogout_init(dac_t *obj, PinName pin) void analogout_free(dac_t *obj) { // Reset DAC and disable clock - __DAC_FORCE_RESET(); - __DAC_RELEASE_RESET(); - __DAC_CLK_DISABLE(); + if (obj->pin == PA_4) pa4_used = 0; + if (obj->pin == PA_5) pa5_used = 0; + + if ((pa4_used == 0) && (pa5_used == 0)) { + __DAC_FORCE_RESET(); + __DAC_RELEASE_RESET(); + __DAC_CLK_DISABLE(); + } // Configure GPIO pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -80,13 +99,32 @@ void analogout_free(dac_t *obj) static inline void dac_write(dac_t *obj, uint16_t value) { - HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); - HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); + if (obj->pin == PA_4) { + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value); + HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1); + } + +#if defined(DAC_CHANNEL_2) + if (obj->pin == PA_5) { + HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value); + HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2); + } +#endif } static inline int dac_read(dac_t *obj) { - return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); + if (obj->pin == PA_4) { + return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1); + } +#if defined(DAC_CHANNEL_2) + else if (obj->pin == PA_5) { + return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2); + } +#endif + else { + return 0; + } } void analogout_write(dac_t *obj, float value) diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/i2c_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/i2c_api.c index 5342c8264f3..dde40d6e52e 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/i2c_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/i2c_api.c @@ -44,11 +44,14 @@ I2C_HandleTypeDef I2cHandle; -int i2c1_inited = 0; -int i2c2_inited = 0; - void i2c_init(i2c_t *obj, PinName sda, PinName scl) { + static int i2c1_inited = 0; + static int i2c2_inited = 0; +#if defined(I2C3_BASE) + static int i2c3_inited = 0; +#endif + // Determine the I2C to use I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA); I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL); @@ -67,6 +70,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pin_mode(sda, OpenDrain); pin_mode(scl, OpenDrain); } + // Enable I2C2 clock and pinout if not done if ((obj->i2c == I2C_2) && !i2c2_inited) { i2c2_inited = 1; @@ -78,6 +82,19 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl) pin_mode(scl, OpenDrain); } +#if defined(I2C3_BASE) + // Enable I2C3 clock and pinout if not done + if ((obj->i2c == I2C_3) && !i2c3_inited) { + i2c3_inited = 1; + __I2C3_CLK_ENABLE(); + // Configure I2C pins + pinmap_pinout(sda, PinMap_I2C_SDA); + pinmap_pinout(scl, PinMap_I2C_SCL); + pin_mode(sda, OpenDrain); + pin_mode(scl, OpenDrain); + } +#endif + // Reset to clear pending flags if any i2c_reset(obj); diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/pwmout_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/pwmout_api.c index 8561653da8d..a260fa6a555 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/pwmout_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/pwmout_api.c @@ -49,6 +49,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) // Enable TIM clock if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE(); +#if defined(TIM3_BASE) + if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE(); +#endif if (obj->pwm == PWM_21) __TIM21_CLK_ENABLE(); if (obj->pwm == PWM_22) __TIM22_CLK_ENABLE(); @@ -109,12 +112,16 @@ void pwmout_write(pwmout_t* obj, float value) break; // Channels 3 case PA_2: + case PB_0: case PB_10: + case PC_8: channel = TIM_CHANNEL_3; break; // Channels 4 case PA_3: + case PB_1: case PB_11: + case PC_9: channel = TIM_CHANNEL_4; break; default: diff --git a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/serial_api.c b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/serial_api.c index 4e9521755b0..9dc817713bd 100644 --- a/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/serial_api.c +++ b/libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L053R8/serial_api.c @@ -37,9 +37,9 @@ #include #include "PeripheralPins.h" -#define UART_NUM (3) +#define UART_NUM (5) -static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0}; +static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0}; static uart_irq_handler irq_handler; @@ -52,7 +52,6 @@ static void init_uart(serial_t *obj) { UartHandle.Instance = (USART_TypeDef *)(obj->uart); - // [TODO] Workaround to be removed after HAL driver is corrected if (obj->uart == LPUART_1) { UartHandle.Init.BaudRate = obj->baudrate >> 1; } else { @@ -90,20 +89,34 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) // Enable UART clock if (obj->uart == UART_1) { - __USART1_CLK_ENABLE(); + __HAL_RCC_USART1_CLK_ENABLE(); obj->index = 0; } if (obj->uart == UART_2) { - __USART2_CLK_ENABLE(); + __HAL_RCC_USART2_CLK_ENABLE(); obj->index = 1; } if (obj->uart == LPUART_1) { - __LPUART1_CLK_ENABLE(); + __HAL_RCC_LPUART1_CLK_ENABLE(); obj->index = 2; } +#if defined(USART4_BASE) + if (obj->uart == UART_4) { + __HAL_RCC_USART4_CLK_ENABLE(); + obj->index = 3; + } +#endif + +#if defined(USART5_BASE) + if (obj->uart == UART_5) { + __HAL_RCC_USART5_CLK_ENABLE(); + obj->index = 4; + } +#endif + // Configure the UART pins pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(rx, PinMap_UART_RX); @@ -135,23 +148,39 @@ void serial_free(serial_t *obj) { // Reset UART and disable clock if (obj->uart == UART_1) { - __USART1_FORCE_RESET(); - __USART1_RELEASE_RESET(); - __USART1_CLK_DISABLE(); + __HAL_RCC_USART1_FORCE_RESET(); + __HAL_RCC_USART1_RELEASE_RESET(); + __HAL_RCC_USART1_CLK_DISABLE(); } if (obj->uart == UART_2) { - __USART2_FORCE_RESET(); - __USART2_RELEASE_RESET(); - __USART2_CLK_DISABLE(); + __HAL_RCC_USART2_FORCE_RESET(); + __HAL_RCC_USART2_RELEASE_RESET(); + __HAL_RCC_USART2_CLK_DISABLE(); } if (obj->uart == LPUART_1) { - __LPUART1_FORCE_RESET(); - __LPUART1_RELEASE_RESET(); - __LPUART1_CLK_DISABLE(); + __HAL_RCC_LPUART1_FORCE_RESET(); + __HAL_RCC_LPUART1_RELEASE_RESET(); + __HAL_RCC_LPUART1_CLK_DISABLE(); } +#if defined(USART4_BASE) + if (obj->uart == UART_4) { + __HAL_RCC_USART4_FORCE_RESET(); + __HAL_RCC_USART4_RELEASE_RESET(); + __HAL_RCC_USART4_CLK_DISABLE(); + } +#endif + +#if defined(USART5_BASE) + if (obj->uart == UART_5) { + __HAL_RCC_USART5_FORCE_RESET(); + __HAL_RCC_USART5_RELEASE_RESET(); + __HAL_RCC_USART5_CLK_DISABLE(); + } +#endif + // Configure GPIOs pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0)); @@ -230,6 +259,20 @@ static void lpuart1_irq(void) uart_irq(LPUART_1, 2); } +#if defined(USART4_BASE) +static void uart4_irq(void) +{ + uart_irq(UART_4, 3); +} +#endif + +#if defined(USART5_BASE) +static void uart5_irq(void) +{ + uart_irq(UART_5, 4); +} +#endif + void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { irq_handler = handler; @@ -258,6 +301,20 @@ void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) vector = (uint32_t)&lpuart1_irq; } +#if defined(USART4_BASE) + if (obj->uart == UART_4) { + irq_n = USART4_5_IRQn; + vector = (uint32_t)&uart4_irq; + } +#endif + +#if defined(USART5_BASE) + if (obj->uart == UART_5) { + irq_n = USART4_5_IRQn; + vector = (uint32_t)&uart5_irq; + } +#endif + if (enable) { if (irq == RxIrq) { diff --git a/workspace_tools/singletest.py b/workspace_tools/singletest.py index f86bca73014..e56bdd36ac2 100644 --- a/workspace_tools/singletest.py +++ b/workspace_tools/singletest.py @@ -221,6 +221,7 @@ def get_version(): _opts_verbose=opts.verbose, _opts_firmware_global_name=opts.firmware_global_name, _opts_only_build_tests=opts.only_build_tests, + _opts_parallel_test_exec=opts.parallel_test_exec, _opts_suppress_summary=opts.suppress_summary, _opts_test_x_toolchain_summary=opts.test_x_toolchain_summary, _opts_copy_method=opts.copy_method, diff --git a/workspace_tools/test_api.py b/workspace_tools/test_api.py index 595bfad3549..e1b531fdafd 100644 --- a/workspace_tools/test_api.py +++ b/workspace_tools/test_api.py @@ -34,7 +34,7 @@ from time import sleep, time from Queue import Queue, Empty from os.path import join, exists, basename -from threading import Thread +from threading import Thread, Lock from subprocess import Popen, PIPE # Imports related to mbed build api @@ -167,6 +167,7 @@ def __init__(self, _opts_verbose=False, _opts_firmware_global_name=None, _opts_only_build_tests=False, + _opts_parallel_test_exec=False, _opts_suppress_summary=False, _opts_test_x_toolchain_summary=False, _opts_copy_method=None, @@ -217,6 +218,7 @@ def __init__(self, self.opts_verbose = _opts_verbose self.opts_firmware_global_name = _opts_firmware_global_name self.opts_only_build_tests = _opts_only_build_tests + self.opts_parallel_test_exec = _opts_parallel_test_exec self.opts_suppress_summary = _opts_suppress_summary self.opts_test_x_toolchain_summary = _opts_test_x_toolchain_summary self.opts_copy_method = _opts_copy_method @@ -257,7 +259,7 @@ def dump_options(self): "shuffle_test_order" : str(self.opts_shuffle_test_order), "shuffle_test_seed" : str(self.opts_shuffle_test_seed), "test_by_names" : str(self.opts_test_by_names), - "peripheral_by_names" : str(self.opts_peripheral_by_names), + "peripheral_by_names" : str(self.opts_peripheral_by_names), "test_only_peripheral" : str(self.opts_test_only_peripheral), "test_only_common" : str(self.opts_test_only_common), "verbose" : str(self.opts_verbose), @@ -284,225 +286,260 @@ def is_shuffle_seed_float(self): result = False return result - def execute(self): - clean = self.test_spec.get('clean', False) - test_ids = self.test_spec.get('test_ids', []) - - # This will store target / toolchain specific properties - test_suite_properties_ext = {} # target : toolchain + # This will store target / toolchain specific properties + test_suite_properties_ext = {} # target : toolchain + # Here we store test results + test_summary = [] + # Here we store test results in extended data structure + test_summary_ext = {} + execute_thread_slice_lock = Lock() + + def execute_thread_slice(self, q, target, toolchains, clean, test_ids): + for toolchain in toolchains: + # print target, toolchain + # Test suite properties returned to external tools like CI + test_suite_properties = {} + test_suite_properties['jobs'] = self.opts_jobs + test_suite_properties['clean'] = clean + test_suite_properties['target'] = target + test_suite_properties['test_ids'] = ', '.join(test_ids) + test_suite_properties['toolchain'] = toolchain + test_suite_properties['shuffle_random_seed'] = self.shuffle_random_seed + + # print '=== %s::%s ===' % (target, toolchain) + # Let's build our test + if target not in TARGET_MAP: + print self.logger.log_line(self.logger.LogType.NOTIF, 'Skipped tests for %s target. Target platform not found'% (target)) + continue - # Here we store test results - test_summary = [] - # Here we store test results in extended data structure - test_summary_ext = {} + T = TARGET_MAP[target] + build_mbed_libs_options = ["analyze"] if self.opts_goanna_for_mbed_sdk else None + clean_mbed_libs_options = True if self.opts_goanna_for_mbed_sdk or clean or self.opts_clean else None - # Generate seed for shuffle if seed is not provided in - self.shuffle_random_seed = round(random.random(), self.SHUFFLE_SEED_ROUND) - if self.opts_shuffle_test_seed is not None and self.is_shuffle_seed_float(): - self.shuffle_random_seed = round(float(self.opts_shuffle_test_seed), self.SHUFFLE_SEED_ROUND) - - for target, toolchains in self.test_spec['targets'].iteritems(): - test_suite_properties_ext[target] = {} - for toolchain in toolchains: - # Test suite properties returned to external tools like CI - test_suite_properties = {} - test_suite_properties['jobs'] = self.opts_jobs - test_suite_properties['clean'] = clean - test_suite_properties['target'] = target - test_suite_properties['test_ids'] = ', '.join(test_ids) - test_suite_properties['toolchain'] = toolchain - test_suite_properties['shuffle_random_seed'] = self.shuffle_random_seed - - # print '=== %s::%s ===' % (target, toolchain) - # Let's build our test - if target not in TARGET_MAP: - print self.logger.log_line(self.logger.LogType.NOTIF, 'Skipped tests for %s target. Target platform not found'% (target)) + try: + build_mbed_libs_result = build_mbed_libs(T, + toolchain, + options=build_mbed_libs_options, + clean=clean_mbed_libs_options, + jobs=self.opts_jobs) + + if not build_mbed_libs_result: + print self.logger.log_line(self.logger.LogType.NOTIF, 'Skipped tests for %s target. Toolchain %s is not yet supported for this target'% (T.name, toolchain)) continue - - T = TARGET_MAP[target] - build_mbed_libs_options = ["analyze"] if self.opts_goanna_for_mbed_sdk else None - clean_mbed_libs_options = True if self.opts_goanna_for_mbed_sdk or clean or self.opts_clean else None - - try: - build_mbed_libs_result = build_mbed_libs(T, - toolchain, - options=build_mbed_libs_options, - clean=clean_mbed_libs_options, - jobs=self.opts_jobs) - - if not build_mbed_libs_result: - print self.logger.log_line(self.logger.LogType.NOTIF, 'Skipped tests for %s target. Toolchain %s is not yet supported for this target'% (T.name, toolchain)) - continue - except ToolException: - print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building MBED libs for %s using %s'% (target, toolchain)) - return test_summary, self.shuffle_random_seed, test_summary_ext, test_suite_properties_ext - - build_dir = join(BUILD_DIR, "test", target, toolchain) - - test_suite_properties['build_mbed_libs_result'] = build_mbed_libs_result - test_suite_properties['build_dir'] = build_dir - test_suite_properties['skipped'] = [] - - # Enumerate through all tests and shuffle test order if requested - test_map_keys = sorted(TEST_MAP.keys()) - if self.opts_shuffle_test_order: - random.shuffle(test_map_keys, self.shuffle_random_func) - # Update database with shuffle seed f applicable - if self.db_logger: - self.db_logger.reconnect(); - if self.db_logger.is_connected(): - self.db_logger.update_build_id_info(self.db_logger_build_id, _shuffle_seed=self.shuffle_random_func()) - self.db_logger.disconnect(); - + except ToolException: + print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building MBED libs for %s using %s'% (target, toolchain)) + #return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext + q.put(target + '_'.join(toolchains)) + return + + build_dir = join(BUILD_DIR, "test", target, toolchain) + + test_suite_properties['build_mbed_libs_result'] = build_mbed_libs_result + test_suite_properties['build_dir'] = build_dir + test_suite_properties['skipped'] = [] + + # Enumerate through all tests and shuffle test order if requested + test_map_keys = sorted(TEST_MAP.keys()) + if self.opts_shuffle_test_order: + random.shuffle(test_map_keys, self.shuffle_random_func) + # Update database with shuffle seed f applicable if self.db_logger: self.db_logger.reconnect(); if self.db_logger.is_connected(): - # Update MUTs and Test Specification in database - self.db_logger.update_build_id_info(self.db_logger_build_id, _muts=self.muts, _test_spec=self.test_spec) - # Update Extra information in database (some options passed to test suite) - self.db_logger.update_build_id_info(self.db_logger_build_id, _extra=json.dumps(self.dump_options())) + self.db_logger.update_build_id_info(self.db_logger_build_id, _shuffle_seed=self.shuffle_random_func()) self.db_logger.disconnect(); + if self.db_logger: + self.db_logger.reconnect(); + if self.db_logger.is_connected(): + # Update MUTs and Test Specification in database + self.db_logger.update_build_id_info(self.db_logger_build_id, _muts=self.muts, _test_spec=self.test_spec) + # Update Extra information in database (some options passed to test suite) + self.db_logger.update_build_id_info(self.db_logger_build_id, _extra=json.dumps(self.dump_options())) + self.db_logger.disconnect(); + + for test_id in test_map_keys: + test = TEST_MAP[test_id] + if self.opts_test_by_names and test_id not in self.opts_test_by_names.split(','): + continue - for test_id in test_map_keys: - test = TEST_MAP[test_id] - - if self.opts_test_by_names and test_id not in self.opts_test_by_names.split(','): - continue + if test_ids and test_id not in test_ids: + continue - if test_ids and test_id not in test_ids: - continue + if self.opts_test_only_peripheral and not test.peripherals: + if self.opts_verbose_skipped_tests: + print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target)) + test_suite_properties['skipped'].append(test_id) + continue - if self.opts_test_only_peripheral and not test.peripherals: - if self.opts_verbose_skipped_tests: - print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target)) - test_suite_properties['skipped'].append(test_id) - continue + if self.opts_peripheral_by_names and test.peripherals and not len([i for i in test.peripherals if i in self.opts_peripheral_by_names.split(',')]): + # We will skip tests not forced with -p option + if self.opts_verbose_skipped_tests: + print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target)) + test_suite_properties['skipped'].append(test_id) + continue - if self.opts_peripheral_by_names and test.peripherals and not len([i for i in test.peripherals if i in self.opts_peripheral_by_names.split(',')]): - # We will skip tests not forced with -p option - if self.opts_verbose_skipped_tests: - print self.logger.log_line(self.logger.LogType.INFO, 'Common test skipped for target %s'% (target)) - test_suite_properties['skipped'].append(test_id) - continue + if self.opts_test_only_common and test.peripherals: + if self.opts_verbose_skipped_tests: + print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral test skipped for target %s'% (target)) + test_suite_properties['skipped'].append(test_id) + continue - if self.opts_test_only_common and test.peripherals: + if test.automated and test.is_supported(target, toolchain): + if test.peripherals is None and self.opts_only_build_tests: + # When users are using 'build only flag' and test do not have + # specified peripherals we can allow test building by default + pass + elif self.opts_peripheral_by_names and test_id not in self.opts_peripheral_by_names.split(','): + # If we force peripheral with option -p we expect test + # to pass even if peripheral is not in MUTs file. + pass + elif not self.is_peripherals_available(target, test.peripherals): if self.opts_verbose_skipped_tests: - print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral test skipped for target %s'% (target)) + if test.peripherals: + print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral %s test skipped for target %s'% (",".join(test.peripherals), target)) + else: + print self.logger.log_line(self.logger.LogType.INFO, 'Test %s skipped for target %s'% (test_id, target)) test_suite_properties['skipped'].append(test_id) continue - if test.automated and test.is_supported(target, toolchain): - if test.peripherals is None and self.opts_only_build_tests: - # When users are using 'build only flag' and test do not have - # specified peripherals we can allow test building by default - pass - elif self.opts_peripheral_by_names and test_id not in self.opts_peripheral_by_names.split(','): - # If we force peripheral with option -p we expect test - # to pass even if peripheral is not in MUTs file. - pass - elif not self.is_peripherals_available(target, test.peripherals): - if self.opts_verbose_skipped_tests: - if test.peripherals: - print self.logger.log_line(self.logger.LogType.INFO, 'Peripheral %s test skipped for target %s'% (",".join(test.peripherals), target)) - else: - print self.logger.log_line(self.logger.LogType.INFO, 'Test %s skipped for target %s'% (test_id, target)) - test_suite_properties['skipped'].append(test_id) - continue - - build_project_options = ["analyze"] if self.opts_goanna_for_tests else None - clean_project_options = True if self.opts_goanna_for_tests or clean or self.opts_clean else None - - # Detect which lib should be added to test - # Some libs have to compiled like RTOS or ETH - libraries = [] - for lib in LIBRARIES: - if lib['build_dir'] in test.dependencies: - libraries.append(lib['id']) - # Build libs for test - for lib_id in libraries: - try: - build_lib(lib_id, - T, - toolchain, - options=build_project_options, - verbose=self.opts_verbose, - clean=clean_mbed_libs_options, - jobs=self.opts_jobs) - except ToolException: - print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building library %s'% (lib_id)) - return test_summary, self.shuffle_random_seed, test_summary_ext, test_suite_properties_ext - - test_suite_properties['test.libs.%s.%s.%s'% (target, toolchain, test_id)] = ', '.join(libraries) - - # TODO: move this 2 below loops to separate function - INC_DIRS = [] - for lib_id in libraries: - if 'inc_dirs_ext' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['inc_dirs_ext']: - INC_DIRS.extend(LIBRARY_MAP[lib_id]['inc_dirs_ext']) - - MACROS = [] - for lib_id in libraries: - if 'macros' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['macros']: - MACROS.extend(LIBRARY_MAP[lib_id]['macros']) - MACROS.append('TEST_SUITE_TARGET_NAME="%s"'% target) - MACROS.append('TEST_SUITE_TEST_ID="%s"'% test_id) - test_uuid = uuid.uuid4() - MACROS.append('TEST_SUITE_UUID="%s"'% str(test_uuid)) - - project_name = self.opts_firmware_global_name if self.opts_firmware_global_name else None + build_project_options = ["analyze"] if self.opts_goanna_for_tests else None + clean_project_options = True if self.opts_goanna_for_tests or clean or self.opts_clean else None + + # Detect which lib should be added to test + # Some libs have to compiled like RTOS or ETH + libraries = [] + for lib in LIBRARIES: + if lib['build_dir'] in test.dependencies: + libraries.append(lib['id']) + # Build libs for test + for lib_id in libraries: try: - path = build_project(test.source_dir, - join(build_dir, test_id), - T, - toolchain, - test.dependencies, - options=build_project_options, - clean=clean_project_options, - verbose=self.opts_verbose, - name=project_name, - macros=MACROS, - inc_dirs=INC_DIRS, - jobs=self.opts_jobs) + build_lib(lib_id, + T, + toolchain, + options=build_project_options, + verbose=self.opts_verbose, + clean=clean_mbed_libs_options, + jobs=self.opts_jobs) except ToolException: - project_name_str = project_name if project_name is not None else test_id - print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str)) - return test_summary, self.shuffle_random_seed, test_summary_ext, test_suite_properties_ext - if self.opts_only_build_tests: - # With this option we are skipping testing phase - continue - - # Test duration can be increased by global value - test_duration = test.duration - if self.opts_extend_test_timeout is not None: - test_duration += self.opts_extend_test_timeout - - # For an automated test the duration act as a timeout after - # which the test gets interrupted - test_spec = self.shape_test_request(target, path, test_id, test_duration) - test_loops = self.get_test_loop_count(test_id) - - test_suite_properties['test.duration.%s.%s.%s'% (target, toolchain, test_id)] = test_duration - test_suite_properties['test.loops.%s.%s.%s'% (target, toolchain, test_id)] = test_loops - test_suite_properties['test.path.%s.%s.%s'% (target, toolchain, test_id)] = path - - # read MUTs, test specification and perform tests - single_test_result, detailed_test_results = self.handle(test_spec, target, toolchain, test_loops=test_loops) - - # Append test results to global test summary - if single_test_result is not None: - test_summary.append(single_test_result) - - # Prepare extended test results data structure (it can be used to generate detailed test report) - if toolchain not in test_summary_ext: - test_summary_ext[toolchain] = {} # test_summary_ext : toolchain - if target not in test_summary_ext[toolchain]: - test_summary_ext[toolchain][target] = {} # test_summary_ext : toolchain : target - if target not in test_summary_ext[toolchain][target]: - test_summary_ext[toolchain][target][test_id] = detailed_test_results # test_summary_ext : toolchain : target : test_it - - test_suite_properties['skipped'] = ', '.join(test_suite_properties['skipped']) - test_suite_properties_ext[target][toolchain] = test_suite_properties + print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building library %s'% (lib_id)) + #return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext + q.put(target + '_'.join(toolchains)) + return + + test_suite_properties['test.libs.%s.%s.%s'% (target, toolchain, test_id)] = ', '.join(libraries) + + # TODO: move this 2 below loops to separate function + INC_DIRS = [] + for lib_id in libraries: + if 'inc_dirs_ext' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['inc_dirs_ext']: + INC_DIRS.extend(LIBRARY_MAP[lib_id]['inc_dirs_ext']) + + MACROS = [] + for lib_id in libraries: + if 'macros' in LIBRARY_MAP[lib_id] and LIBRARY_MAP[lib_id]['macros']: + MACROS.extend(LIBRARY_MAP[lib_id]['macros']) + MACROS.append('TEST_SUITE_TARGET_NAME="%s"'% target) + MACROS.append('TEST_SUITE_TEST_ID="%s"'% test_id) + test_uuid = uuid.uuid4() + MACROS.append('TEST_SUITE_UUID="%s"'% str(test_uuid)) + + project_name = self.opts_firmware_global_name if self.opts_firmware_global_name else None + try: + path = build_project(test.source_dir, + join(build_dir, test_id), + T, + toolchain, + test.dependencies, + options=build_project_options, + clean=clean_project_options, + verbose=self.opts_verbose, + name=project_name, + macros=MACROS, + inc_dirs=INC_DIRS, + jobs=self.opts_jobs) + except ToolException: + project_name_str = project_name if project_name is not None else test_id + print self.logger.log_line(self.logger.LogType.ERROR, 'There were errors while building project %s'% (project_name_str)) + # return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext + q.put(target + '_'.join(toolchains)) + return + if self.opts_only_build_tests: + # With this option we are skipping testing phase + continue + + # Test duration can be increased by global value + test_duration = test.duration + if self.opts_extend_test_timeout is not None: + test_duration += self.opts_extend_test_timeout + + # For an automated test the duration act as a timeout after + # which the test gets interrupted + test_spec = self.shape_test_request(target, path, test_id, test_duration) + test_loops = self.get_test_loop_count(test_id) + + test_suite_properties['test.duration.%s.%s.%s'% (target, toolchain, test_id)] = test_duration + test_suite_properties['test.loops.%s.%s.%s'% (target, toolchain, test_id)] = test_loops + test_suite_properties['test.path.%s.%s.%s'% (target, toolchain, test_id)] = path + + # read MUTs, test specification and perform tests + single_test_result, detailed_test_results = self.handle(test_spec, target, toolchain, test_loops=test_loops) + + # Append test results to global test summary + if single_test_result is not None: + self.test_summary.append(single_test_result) + + # Prepare extended test results data structure (it can be used to generate detailed test report) + if toolchain not in self.test_summary_ext: + self.test_summary_ext[toolchain] = {} # test_summary_ext : toolchain + if target not in self.test_summary_ext[toolchain]: + self.test_summary_ext[toolchain][target] = {} # test_summary_ext : toolchain : target + if target not in self.test_summary_ext[toolchain][target]: + self.test_summary_ext[toolchain][target][test_id] = detailed_test_results # test_summary_ext : toolchain : target : test_it + + test_suite_properties['skipped'] = ', '.join(test_suite_properties['skipped']) + self.test_suite_properties_ext[target][toolchain] = test_suite_properties + # return self.test_summary, self.shuffle_random_seed, test_summary_ext, self.test_suite_properties_ext + q.put(target + '_'.join(toolchains)) + return + + def execute(self): + clean = self.test_spec.get('clean', False) + test_ids = self.test_spec.get('test_ids', []) + q = Queue() + + # Generate seed for shuffle if seed is not provided in + self.shuffle_random_seed = round(random.random(), self.SHUFFLE_SEED_ROUND) + if self.opts_shuffle_test_seed is not None and self.is_shuffle_seed_float(): + self.shuffle_random_seed = round(float(self.opts_shuffle_test_seed), self.SHUFFLE_SEED_ROUND) + + if self.opts_parallel_test_exec: + ################################################################### + # Experimental, parallel test execution per singletest instance. + ################################################################### + execute_threads = [] # Threads used to build mbed SDL, libs, test cases and execute tests + # Note: We are building here in parallel for each target separately! + # So we are not building the same thing multiple times and compilers + # in separate threads do not collide. + # Inside execute_thread_slice() function function handle() will be called to + # get information about available MUTs (per target). + for target, toolchains in self.test_spec['targets'].iteritems(): + self.test_suite_properties_ext[target] = {} + t = threading.Thread(target=self.execute_thread_slice, args = (q, target, toolchains, clean, test_ids)) + t.daemon = True + t.start() + execute_threads.append(t) + + for t in execute_threads: + q.get() # t.join() would block some threads because we should not wait in any order for thread end + else: + # Serialized (not parallel) test execution + for target, toolchains in self.test_spec['targets'].iteritems(): + if target not in self.test_suite_properties_ext: + self.test_suite_properties_ext[target] = {} + self.execute_thread_slice(q, target, toolchains, clean, test_ids) + q.get() if self.db_logger: self.db_logger.reconnect(); @@ -510,7 +547,7 @@ def execute(self): self.db_logger.update_build_id_info(self.db_logger_build_id, _status_fk=self.db_logger.BUILD_ID_STATUS_COMPLETED) self.db_logger.disconnect(); - return test_summary, self.shuffle_random_seed, test_summary_ext, test_suite_properties_ext + return self.test_summary, self.shuffle_random_seed, self.test_summary_ext, self.test_suite_properties_ext def generate_test_summary_by_target(self, test_summary, shuffle_seed=None): """ Prints well-formed summary with results (SQL table like) @@ -641,7 +678,8 @@ def delete_file(self, file_path): def handle(self, test_spec, target_name, toolchain_name, test_loops=1): """ Function determines MUT's mbed disk/port and copies binary to - target. Test is being invoked afterwards. + target. + Test is being invoked afterwards. """ data = json.loads(test_spec) # Get test information, image and test timeout @@ -1527,7 +1565,7 @@ def get_default_test_options_parser(): parser.add_option('-p', '--peripheral-by-names', dest='peripheral_by_names', - help='Forces discovery of particular peripherals. Use comma to separate peripheral names.') + help='Forces discovery of particular peripherals. Use comma to separate peripheral names.') copy_methods = host_tests_plugins.get_plugin_caps('CopyMethod') copy_methods_str = "Plugin support: " + ', '.join(copy_methods) @@ -1592,6 +1630,12 @@ def get_default_test_options_parser(): default=False, help="Only build tests, skips actual test procedures (flashing etc.)") + parser.add_option('', '--parallel', + dest='parallel_test_exec', + default=False, + action="store_true", + help='Experimental, you execute test runners for connected to your host MUTs in parallel (speeds up test result collection)') + parser.add_option('', '--config', dest='verbose_test_configuration_only', default=False,