diff --git a/README.md b/README.md
index 9ee71f51..2e7f8f33 100644
--- a/README.md
+++ b/README.md
@@ -11,12 +11,12 @@ For more information, see [BSA specification](https://developer.arm.com/document
 
 BSA **Architecture Compliance Suite** (ACS) is a collection of self-checking, portable C-based tests.
 This suite includes a set of examples of the invariant behaviors that are provided by the [BSA](https://developer.arm.com/documentation/den0094/latest) specification, so that you can verify if these behaviour have been interpreted correctly.
-Most of the tests are executed from UEFI Shell by executing the BSA UEFI shell application.
+Most of the tests are executed from UEFI (Unified Extensible Firmware Interface) Shell by executing the BSA UEFI shell application.
 A few tests are executed by running the BSA ACS Linux application which in turn depends on the BSA ACS Linux kernel module.
 
 
 ## Release details
- - Code quality: v0.9 Beta
+ - Code quality: v1.0
  - The tests are written for version 1.0 of the BSA specification.
  - The compliance suite is not a substitute for design verification.
  - To review the BSA ACS logs, Arm licensees can contact Arm directly through their partner managers.
@@ -93,8 +93,6 @@ The EFI executable file is generated at <edk2_path>/Build/Shell/DEBUG_GCC49/AARC
 
 ### 2. Test suite execution
 
-The execution of the compliance suite varies depending on the test environment. The below steps assume that the test suite is invoked through the ACS UEFI shell application.
-
 
 #### Prerequisites
 - If the system supports LPIs (Interrupt ID > 8192) then Firmware should support installation of handler for LPI interrupts.
@@ -106,6 +104,8 @@ The execution of the compliance suite varies depending on the test environment.
 >          -mGicNumInterrupts      = ArmGicGetMaxNumInterrupts (mGicDistributorBase);
 >          +mGicNumInterrupts      = ARM_GIC_MAX_NUM_INTERRUPT;
 
+The execution of the compliance suite varies depending on the test environment. The following steps assume that the test suite is invoked through the ACS UEFI shell application.
+
 #### 2.1 Silicon
 
 On a system where a USB port is available and functional, perform the following steps:
@@ -138,11 +138,11 @@ On an emulation environment with secondary storage, perform the following steps:
 2. Load the image file to the secondary storage using a backdoor. The steps to load the image file are emulation environment-specific and beyond the scope of this document.
 3. Boot the system to UEFI shell.
 4. To determine the file system number of the secondary storage, execute 'map -r' command.
-5. Type 'fsx' where 'x' is replaced by the number determined in step 4.
+5. Type 'fs<x>' where '<x>' is replaced by the number determined in step 4.
 6. To start the compliance tests, run the executable Bsa.efi with the appropriate parameters.
 7. Copy the UART console output to a log file for analysis and certification.
 
-  - For information on the BSA uefi shell application parameters, see [User Guide](docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf).
+  - For information on the BSA uefi shell application parameters, see the [User Guide](docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf).
 
 
 #### 2.3 Emulation environment without secondary storage
@@ -152,12 +152,12 @@ On an emulation platform where secondary storage is not available, perform the f
 1. Add the path to 'Bsa.efi' file in the UEFI FD file.
 2. Build UEFI image including the UEFI Shell.
 3. Boot the system to UEFI shell.
-4. Run the executable 'Bsa.efi' to start the compliance tests. For details about the parameters,
+4. Run the executable 'Bsa.efi' to start the compliance tests. For details about the parameters,see the [User Guide](docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf).
 5. Copy the UART console output to a log file for analysis and certification.
 
 
 ## Linux OS-based tests
-Certain Peripheral, PCIe and Memory map tests require Linux operating system with kernel version 5.11 or above.
+Certain Peripheral, PCIe and Memory map tests require Linux operating system with kernel version 5.13 or above.
 This chapter provides information on executing tests from the Linux application.
 
 ### 1. Build steps and environment setup
@@ -166,7 +166,7 @@ The patch for the kernel tree and the Linux PAL are hosted separately on [linux-
 
 ### 1.1 Building the kernel module
 #### Prerequisites
-- Linux kernel source version 5.11.
+- Linux kernel source version 5.13.
 - Linaro GCC tool chain 7.5 or above.
 - Build environment for AArch64 Linux kernel.
 
@@ -175,7 +175,7 @@ The patch for the kernel tree and the Linux PAL are hosted separately on [linux-
 2. git clone https://github.com/ARM-software/bsa-acs.git bsa-acs
 3. git clone https://github.com/torvalds/linux.git -b v5.11
 4. export CROSS_COMPILE=<GCC7.5 toolchain path> pointing to /bin/aarch64-linux-gnu-
-5. git apply <local_dir>/bsa-acs-drv/kernel/src/0001-BSA-ACS-Linux-5.11.patch to your kernel source tree.
+5. git apply <local_dir>/bsa-acs-drv/kernel/src/0001-BSA-ACS-Linux-5.13.patch to your kernel source tree.
 6. make ARCH=arm64 defconfig && make -j $(nproc) ARCH=arm64
 
 #### 1.2 Build steps for BSA kernel module
@@ -185,14 +185,14 @@ The patch for the kernel tree and the Linux PAL are hosted separately on [linux-
 4. ./setup.sh <local_dir/bsa-acs>
 5. ./linux_bsa_acs.sh
 
-Successfull completion of above steps will generate bsa_acs.ko
+Successful completion of above steps will generate bsa_acs.ko
 
 #### 1.3 BSA Linux application build
 1. cd <bsa-acs path>/linux_app/bsa-acs-app
 2. export CROSS_COMPILE=<ARM64 toolchain path>/bin/aarch64-linux-gnu-
 3. make
 
-Successfull completion of above steps will generate executable file bsa
+Successful completion of above steps will generate executable file bsa
 
 ### 2. Loading the kernel module
 Before the BSA ACS Linux application can be run, load the BSA ACS kernel module using the insmod command.
@@ -204,27 +204,36 @@ shell> insmod bsa_acs.ko
 ```sh
 shell> ./bsa
 ```
-  - For information on the BSA Linux application parameters, see [User Guide](docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf).
+  - For information on the BSA Linux application parameters, see the [User Guide](docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf).
 
 ## Security implication
-The Arm System Ready ACS test suite may run at a higher privilege level. An attacker may utilize these tests to elevate the privilege which can potentially reveal the platform security assets. To prevent the leakage of secure information, Arm strongly recommends that you run the ACS test suite only on development platforms. If it is run on production systems, the system should be scrubbed after running the test suite.
+The Arm SystemReady ACS test suite may run at a higher privilege level. An attacker may utilize these tests to elevate the privilege which can potentially reveal the platform security assets. To prevent the leakage of Secure information, Arm strongly recommends that you run the ACS test suite only on development platforms. If it is run on production systems, the system should be scrubbed after running the test suite.
 
 ## Limitations
 
  - PCIE iEP rules are out of scope for current release.
  - ITS rules are available only for systems that present firmware compliant to SBBR.
- - Peripheral rules RB_PER_01,02,03 are not implemented in current release for systems that present firmware compliant to EBBR.
+ - Some PCIe and Exerciser test are dependent on PCIe features supported by the test system.
+   Please fill the required API's with test system information.
+   - pal_pcie_p2p_support : If the test system PCIe supports peer to peer transaction.
+   - pal_pcie_is_cache_present : If the test system supports PCIe address translation cache.
+   - pal_pcie_get_legacy_ir_map : Fill system legacy ir map
+   Below exerciser capabilities are required by exerciser test.
+   - MSI-X interrupt generation.
+   - Incoming Transaction Monitoring(order, type).
+   - Initiating transacions from and to the exerciser.
+   - Ability to check on BDF and register address seen for each configuration address along with access type.
 
 ## License
 BSA ACS is distributed under Apache v2.0 License.
 
 
-## Feedback, contributions and support
+## Feedback, contributions, and support
 
  - For feedback, use the GitHub Issue Tracker that is associated with this repository.
- - For support, please send an email to "support-systemready-acs@arm.com" with details.
+ - For support, send an email to "support-systemready-acs@arm.com" with details.
  - Arm licensees may contact Arm directly through their partner managers.
- - Arm welcomes code contributions through GitHub pull requests. See GitHub documentation on how to raise pull requests.
+ - Arm welcomes code contributions through GitHub pull requests. See the GitHub documentation on how to raise pull requests.
 
 --------------
 
diff --git a/changelog.txt b/changelog.txt
index b7a47531..9813ee5f 100644
--- a/changelog.txt
+++ b/changelog.txt
@@ -12,3 +12,11 @@ v21.07_0.9_BETA
 * BSA: Initial ITS tests for systems presenting firmware which is SBBR complaint
 * BSA: Renamed pal_uefi to pal_uefi_acpi
 * BSA: Bug Fixes on Alpha release
+
+v21.09_1.0
+
+* BSA: Added test for PCIe Rules PCI_PP_02, PCI_PP_08 and RE_ORD_4.
+* BSA : Added test for ITS Rules ITS_DEV_2,ITS_DEV_7 and ITS_DEV_8 for systems presenting firmware which is SBBR complaint.
+* BSA: Added test for Peripherals Rules PER_01,PER_02 and PER_03 for systems presenting firmware which is EBBR complaint.
+* BSA: Bug Fixes on BETA release
+
diff --git a/docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf b/docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf
index 682fc6d4..348d94a7 100644
Binary files a/docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf and b/docs/Arm_Base_System_Architecture_Compliance_User_Guide.pdf differ
diff --git a/docs/Arm_Base_System_Architecture_Compliance_Validation_Methodology.pdf b/docs/Arm_Base_System_Architecture_Compliance_Validation_Methodology.pdf
index 7cc25d86..aa8b0323 100644
Binary files a/docs/Arm_Base_System_Architecture_Compliance_Validation_Methodology.pdf and b/docs/Arm_Base_System_Architecture_Compliance_Validation_Methodology.pdf differ
diff --git a/docs/Arm_Base_System_Architecture_Scenario_ES.pdf b/docs/Arm_Base_System_Architecture_Scenario_ES.pdf
index 6c4859d2..c0c906ee 100644
Binary files a/docs/Arm_Base_System_Architecture_Scenario_ES.pdf and b/docs/Arm_Base_System_Architecture_Scenario_ES.pdf differ
diff --git a/docs/Arm_Base_System_Architecture_Scenario_IR.pdf b/docs/Arm_Base_System_Architecture_Scenario_IR.pdf
index d615f1c8..e3608fe5 100644
Binary files a/docs/Arm_Base_System_Architecture_Scenario_IR.pdf and b/docs/Arm_Base_System_Architecture_Scenario_IR.pdf differ
diff --git a/linux_app/bsa-acs-app/bsa_drv_intf.c b/linux_app/bsa-acs-app/bsa_drv_intf.c
index 967e2640..4948004e 100644
--- a/linux_app/bsa-acs-app/bsa_drv_intf.c
+++ b/linux_app/bsa-acs-app/bsa_drv_intf.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2018,2021 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -43,14 +43,12 @@ call_drv_get_status(unsigned long int *arg0, unsigned long int *arg1, unsigned l
 
 
     fd = fopen("/proc/bsa", "r");
-
-    fseek(fd, 0, SEEK_SET);
-
     if (NULL == fd)
     {
         printf("fopen failed \n");
         return 1;
     }
+
   fread(&test_params,1,sizeof(test_params),fd);
 
   //printf("read back value is %x %lx \n", test_params.api_num, test_params.arg1);
@@ -87,7 +85,6 @@ call_drv_init_test_env(unsigned int print_level)
     bsa_drv_parms_t test_params;
 
     fd = fopen("/proc/bsa", "rw+");
-
     if (NULL == fd)
     {
         printf("fopen failed \n");
@@ -113,7 +110,6 @@ call_drv_clean_test_env()
     bsa_drv_parms_t test_params;
 
     fd = fopen("/proc/bsa", "rw+");
-
     if (NULL == fd)
     {
         printf("fopen failed \n");
@@ -139,7 +135,6 @@ call_drv_execute_test(unsigned int api_num, unsigned int num_pe,
     bsa_drv_parms_t test_params;
 
     fd = fopen("/proc/bsa", "rw+");
-
     if (NULL == fd)
     {
         printf("fopen failed \n");
@@ -166,7 +161,6 @@ call_update_skip_list(unsigned int api_num, int *p_skip_test_num)
     bsa_drv_parms_t test_params;
 
     fd = fopen("/proc/bsa", "rw+");
-
     if (NULL == fd)
     {
         printf("fopen failed \n");
@@ -226,9 +220,6 @@ int read_from_proc_bsa_msg() {
   bsa_msg_parms_t msg_params;
 
   fd = fopen("/proc/bsa_msg", "r");
-
-  fseek(fd, 0, SEEK_SET);
-
   if (NULL == fd) {
     printf("fopen failed \n");
     return 1;
diff --git a/linux_app/bsa-acs-app/include/bsa_app.h b/linux_app/bsa-acs-app/include/bsa_app.h
index ac4711cc..9a455fcd 100644
--- a/linux_app/bsa-acs-app/include/bsa_app.h
+++ b/linux_app/bsa-acs-app/include/bsa_app.h
@@ -20,8 +20,8 @@
 #define __BSA_APP_LINUX_H__
 
 
-#define BSA_APP_VERSION_MAJOR  0
-#define BSA_APP_VERSION_MINOR  9
+#define BSA_APP_VERSION_MAJOR  1
+#define BSA_APP_VERSION_MINOR  0
 
 #define G_SW_OS            0
 #define G_SW_HYP           1
diff --git a/platform/pal_uefi_acpi/include/pal_exerciser.h b/platform/pal_uefi_acpi/include/pal_exerciser.h
index 9d2c5d51..2a5c9f93 100644
--- a/platform/pal_uefi_acpi/include/pal_exerciser.h
+++ b/platform/pal_uefi_acpi/include/pal_exerciser.h
@@ -43,6 +43,9 @@
 #define DMA_BUS_ADDR 0x010
 #define DMA_LEN      0x018
 #define DMASTATUS    0x01C
+#define PASID_VAL    0x020
+#define ATSCTL       0x024
+#define ATS_ADDR     0x028
 #define PCI_MAX_BUS     255
 #define PCI_MAX_DEVICE  31
 
@@ -65,6 +68,7 @@
 #define PASID_VAL_SHIFT     12
 #define PASID_LEN_SHIFT     7
 #define PASID_LEN_MASK      0x7ul
+#define PASID_EN_SHIFT      6
 #define DMA_TO_DEVICE_MASK  0xFFFFFFEF
 
 /* shift_bit */
@@ -85,7 +89,13 @@
 #define PCIE_CAP_DIS_MASK 0xFFFEFFFF
 #define PCIE_CAP_EN_MASK (1 << 16)
 #define PASID_EN_MASK    (1 << 6)
-
+#define RID_CTL_REG    0x3C
+#define RID_VALUE_MASK 0xFFFF
+#define RID_VALID_MASK (1ul << 31)
+#define RID_VALID      1
+#define RID_NOT_VALID  0
+#define ATS_TRIGGER    1
+#define ATS_STATUS     (1ul << 7)
 
 typedef enum {
     TYPE0 = 0x0,
@@ -106,21 +116,22 @@ typedef enum {
 } EXERCISER_DMA_ATTR;
 
 typedef enum {
-    SNOOP_ATTRIBUTES = 0x1,
-    LEGACY_IRQ       = 0x2,
-    MSIX_ATTRIBUTES  = 0x3,
-    DMA_ATTRIBUTES   = 0x4,
-    P2P_ATTRIBUTES   = 0x5,
-    PASID_ATTRIBUTES = 0x6,
+    SNOOP_ATTRIBUTES   = 0x1,
+    LEGACY_IRQ         = 0x2,
+    MSIX_ATTRIBUTES    = 0x3,
+    DMA_ATTRIBUTES     = 0x4,
+    P2P_ATTRIBUTES     = 0x5,
+    PASID_ATTRIBUTES   = 0x6,
     CFG_TXN_ATTRIBUTES = 0x7,
     ATS_RES_ATTRIBUTES = 0x8,
-    TRANSACTION_TYPE  = 0x9,
-    NUM_TRANSACTIONS  = 0xA
+    TRANSACTION_TYPE   = 0x9,
+    NUM_TRANSACTIONS   = 0xA
 } EXERCISER_PARAM_TYPE;
 
 typedef enum {
-    TXN_REQ_ID     = 0x0,
-    TXN_ADDR_TYPE  = 0x1,
+    TXN_REQ_ID       = 0x0,
+    TXN_ADDR_TYPE    = 0x1,
+    TXN_REQ_ID_VALID = 0x2,
 } EXERCISER_TXN_ATTR;
 
 typedef enum {
diff --git a/platform/pal_uefi_acpi/include/pal_uefi.h b/platform/pal_uefi_acpi/include/pal_uefi.h
index 3563138b..62a5e47f 100644
--- a/platform/pal_uefi_acpi/include/pal_uefi.h
+++ b/platform/pal_uefi_acpi/include/pal_uefi.h
@@ -318,8 +318,12 @@ typedef struct {
   UINT32         max_pasids;
   UINT32         baud_rate;
   UINT32         interface_type;
+  UINT32         platform_type;
 }PERIPHERAL_INFO_BLOCK;
 
+#define PLATFORM_TYPE_ACPI   0x0
+#define PLATFORM_TYPE_DT     0x1
+
 /**
   @brief Peripheral Info Structure
 **/
diff --git a/platform/pal_uefi_acpi/src/pal_acpi.c b/platform/pal_uefi_acpi/src/pal_acpi.c
index 28e31d95..02ce45a4 100644
--- a/platform/pal_uefi_acpi/src/pal_acpi.c
+++ b/platform/pal_uefi_acpi/src/pal_acpi.c
@@ -27,10 +27,17 @@
 
 #include "include/pal_uefi.h"
 
+/**
+  @brief Dump DTB to file
+
+  @param None
+
+  @return None
+**/
 VOID
 pal_dump_dtb()
 {
-  bsa_print(ACS_PRINT_ERR, L"DTB dump not available for platform initialized"
+  bsa_print(ACS_PRINT_ERR, L" DTB dump not available for platform initialized"
                                 " with ACPI table \n");
 }
 /**
@@ -96,7 +103,7 @@ pal_get_madt_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_ERR, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_ERR, L" XSDT not found \n");
       return 0;
   }
 
@@ -130,7 +137,7 @@ pal_get_gtdt_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_ERR, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_ERR, L" XSDT not found \n");
       return 0;
   }
 
@@ -163,7 +170,7 @@ pal_get_mcfg_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_ERR, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_ERR, L" XSDT not found \n");
       return 0;
   }
 
@@ -196,7 +203,7 @@ pal_get_spcr_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_ERR, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_ERR, L" XSDT not found \n");
       return 0;
   }
 
@@ -229,7 +236,7 @@ pal_get_iort_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_ERR, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_ERR, L" XSDT not found \n");
       return 0;
   }
 
diff --git a/platform/pal_uefi_acpi/src/pal_exerciser.c b/platform/pal_uefi_acpi/src/pal_exerciser.c
index f306a95a..ea5d9bde 100644
--- a/platform/pal_uefi_acpi/src/pal_exerciser.c
+++ b/platform/pal_uefi_acpi/src/pal_exerciser.c
@@ -42,6 +42,10 @@ pal_pcie_get_mcfg_ecam();
 
 /**
   @brief This API increments the BDF
+
+  @param Bdf Stimulus hardware bdf number
+
+  @return incremented bdf number
 **/
 UINT32
 pal_increment_bus_dev(
@@ -67,7 +71,12 @@ pal_increment_bus_dev(
 }
 
 /**
-  @brief This API will return the ECSR base address of particular BAR Index
+  @brief This API returns the ECSR base address of particular BAR Index
+
+  @param EcsrBase Exerciser Base address
+  @param BarIndex input BAR index
+
+  @return ECSR base address of required BAR Index
 **/
 UINT64
 pal_exerciser_get_ecsr_base (
@@ -78,6 +87,13 @@ pal_exerciser_get_ecsr_base (
   return pal_mmio_read(EcsrBase + BAR0_OFFSET + (BarIndex * 4));
 }
 
+/**
+  @brief This API returns PCI config offset address for input BDF
+
+  @param Bdf BDF value for the device
+
+  @return PCI config offset address
+**/
 UINT64
 pal_exerciser_get_pcie_config_offset(UINT32 Bdf)
 {
@@ -93,6 +109,13 @@ pal_exerciser_get_pcie_config_offset(UINT32 Bdf)
   return cfg_addr;
 }
 
+/**
+  @brief This API checks whether a device specified by BDF is an exerciser or not
+
+  @param bdf BDF value for the device
+
+  @return 1 if device is an exerciser ; 0 if device is not a exerciser
+**/
 UINT32
 pal_is_bdf_exerciser(UINT32 bdf)
 {
@@ -109,6 +132,11 @@ pal_is_bdf_exerciser(UINT32 bdf)
 
 /**
   @brief This function triggers the DMA operation
+
+  @param Base DMA Base address
+  @param Direction Specify DMA direction
+
+  @return status of the DMA
 **/
 UINT32
 pal_exerciser_start_dma_direction (
@@ -139,6 +167,13 @@ pal_exerciser_start_dma_direction (
 
 /**
   @brief This function finds the PCI capability and return 0 if it finds.
+
+  @param ID    PCI capability IF 
+  @param Bdf   BDF value for the device
+  @param Value 1 PCIE capability 0 PCI capability
+  @param Offset capability offset
+
+  @return 0 if PCI capability found ; 1 if PCI capability found
 **/
 UINT32
 pal_exerciser_find_pcie_capability (
@@ -189,7 +224,8 @@ pal_exerciser_find_pcie_capability (
   @param   Type         - Parameter type that needs to be set in the stimulus hadrware
   @param   Value1       - Parameter 1 that needs to be set
   @param   Value2       - Parameter 2 that needs to be set
-  @param   Instance     - Stimulus hardware instance number
+  @param   Bdf          - Stimulus hardware bdf number
+  @param   Ecam         - Ecam base for exerciser under test
   @return  Status       - SUCCESS if the input paramter type is successfully written
 **/
 UINT32 pal_exerciser_set_param (
@@ -200,7 +236,6 @@ UINT32 pal_exerciser_set_param (
   UINT64 Ecam
   )
 {
-  UINT32 Status;
   UINT32 Data;
   UINT64 Base;
   UINT64 EcsrBase; /* Exerciser Base */
@@ -219,9 +254,7 @@ UINT32 pal_exerciser_set_param (
       case DMA_ATTRIBUTES:
           pal_mmio_write(Base + DMA_BUS_ADDR,Value1);// wrting into the DMA Control Register 2
           pal_mmio_write(Base + DMA_LEN,Value2);// writing into the DMA Control Register 3
-          Data = pal_mmio_read(Base + DMASTATUS);// Reading the DMA status register
-          Status = Data & ((MASK_BIT << 1) | MASK_BIT);
-          return Status;
+          return 0;
 
       case P2P_ATTRIBUTES:
           return 0;
@@ -241,9 +274,38 @@ UINT32 pal_exerciser_set_param (
 
             case TXN_REQ_ID:
                 /* Change Requester ID for DMA Transaction.*/
+                Data = (Value2 & RID_VALUE_MASK) | RID_VALID_MASK;
+                pal_mmio_write(Base + RID_CTL_REG, Data);
                 return 0;
+            case TXN_REQ_ID_VALID:
+                switch (Value2)
+                {
+                    case RID_VALID:
+                        Data = pal_mmio_read(Base + RID_CTL_REG);
+                        Data |= RID_VALID_MASK;
+                        pal_mmio_write(Base + RID_CTL_REG, Data);
+                        return 0;
+                    case RID_NOT_VALID:
+                        pal_mmio_write(Base + RID_CTL_REG, 0);
+                        return 0;
+                }
             case TXN_ADDR_TYPE:
                 /* Change Address Type for DMA Transaction.*/
+                switch (Value2)
+                {
+                    case AT_UNTRANSLATED:
+                        Data = 0x1;
+                        pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10));
+                        break;
+                    case AT_TRANSLATED:
+                        Data = 0x2;
+                        pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10));
+                        break;
+                    case AT_RESERVED:
+                        Data = 0x3;
+                        pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10));
+                        break;
+                }
                 return 0;
             default:
                 return 1;
@@ -259,7 +321,8 @@ UINT32 pal_exerciser_set_param (
   @param   Type         - Parameter type that needs to be read from the stimulus hadrware
   @param   Value1       - Parameter 1 that is read from hardware
   @param   Value2       - Parameter 2 that is read from hardware
-  @param   Instance     - Stimulus hardware instance number
+  @param   Bdf          - Stimulus hardware bdf number
+  @param   Ecam         - Ecam base for exerciser under test
   @return  Status       - SUCCESS if the requested paramter type is successfully read
 **/
 UINT32
@@ -300,6 +363,9 @@ pal_exerciser_get_param (
       case MSIX_ATTRIBUTES:
           *Value1 = pal_mmio_read(Base + MSICTL);
           return pal_mmio_read(Base + MSICTL) | MASK_BIT;
+      case ATS_RES_ATTRIBUTES:
+          *Value1 = pal_mmio_read(Base + ATS_ADDR);
+          return 0;
       default:
           return 1;
   }
@@ -341,8 +407,9 @@ pal_exerciser_get_state (
 /**
   @brief   This API performs the input operation using the PCIe stimulus generation hardware
   @param   Ops          - Operation thta needs to be performed with the stimulus hadrware
-  @param   Value        - Additional information to perform the operation
-  @param   Instance     - Stimulus hardware instance number
+  @param   Param        - Additional information to perform the operation
+  @param   Bdf          - Stimulus hardware bdf number
+  @param   Ecam         - Ecam base for exerciser under test
   @return  Status       - SUCCESS if the operation is successfully performed using the hardware
 **/
 UINT32
@@ -401,9 +468,10 @@ pal_exerciser_ops (
 
     case PASID_TLP_START:
         data = pal_mmio_read(Base + DMACTL1);
-        data &= ~(PASID_VAL_MASK << PASID_VAL_SHIFT);
-        data |= (MASK_BIT << 6) | ((Param & PASID_VAL_MASK) << PASID_VAL_SHIFT);
+        data |= (MASK_BIT << PASID_EN_SHIFT);
         pal_mmio_write(Base + DMACTL1, data);
+        data = ((Param & PASID_VAL_MASK));
+        pal_mmio_write(Base + PASID_VAL, data);
 
         if (!pal_exerciser_find_pcie_capability(PASID, Bdf, PCIE, &CapabilityOffset)) {
             pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET,
@@ -430,6 +498,11 @@ pal_exerciser_ops (
         pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1)) & NO_SNOOP_STOP_MASK);//disabling the NO SNOOP
         return 0;
 
+    case ATS_TXN_REQ:
+        pal_mmio_write(Base + DMA_BUS_ADDR, Param);
+        pal_mmio_write(Base + ATSCTL, ATS_TRIGGER);
+        return !(pal_mmio_read(Base + ATSCTL) & ATS_STATUS);
+
     default:
         return 1;
   }
@@ -437,9 +510,10 @@ pal_exerciser_ops (
 
 /**
   @brief   This API returns test specific data from the PCIe stimulus generation hardware
-  @param   type         - data type for which the data needs to be returned
-  @param   data         - test specific data to be be filled by pal layer
-  @param   instance     - Stimulus hardware instance number
+  @param   Type         - data type for which the data needs to be returned
+  @param   Data         - test specific data to be be filled by pal layer
+  @param   Bdf          - Stimulus hardware bdf number
+  @param   Ecam         - Ecam base for exerciser under test
   @return  status       - SUCCESS if the requested data is successfully filled
 **/
 UINT32
@@ -467,8 +541,7 @@ pal_exerciser_get_data (
           for (Index = 0; Index < TEST_REG_COUNT; Index++) {
               Data->cfg_space.reg[Index].offset = (offset_table[Index] + pal_exerciser_get_pcie_config_offset (Bdf));
               Data->cfg_space.reg[Index].attribute = attr_table[Index];
-              Data->cfg_space.reg[Index].value =
-                                pal_mmio_read(EcsrBase +  offset_table[Index]);
+              Data->cfg_space.reg[Index].value = pal_mmio_read(EcsrBase + offset_table[Index]);
           }
           return 0;
       case EXERCISER_DATA_BAR0_SPACE:
diff --git a/platform/pal_uefi_acpi/src/pal_gic.c b/platform/pal_uefi_acpi/src/pal_gic.c
index 81c2cca6..f28da49a 100644
--- a/platform/pal_uefi_acpi/src/pal_gic.c
+++ b/platform/pal_uefi_acpi/src/pal_gic.c
@@ -53,7 +53,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
   UINT32                         TableLength;
 
   if (GicTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input GIC Table Pointer is NULL. Cannot create GIC INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input GIC Table Pointer is NULL. Cannot create GIC INFO \n");
     return;
   }
 
@@ -69,7 +69,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
 
   if (gMadtHdr != NULL) {
     TableLength =  gMadtHdr->Header.Length;
-    bsa_print(ACS_PRINT_INFO, L" MADT is at %x and length is %x \n", gMadtHdr, TableLength);
+    bsa_print(ACS_PRINT_INFO, L"  MADT is at %x and length is %x \n", gMadtHdr, TableLength);
   } else {
     bsa_print(ACS_PRINT_ERR, L" MADT not found \n");
     return;
@@ -85,7 +85,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
       if (Entry->PhysicalBaseAddress != 0) {
         GicEntry->type = ENTRY_TYPE_CPUIF;
         GicEntry->base = Entry->PhysicalBaseAddress;
-        bsa_print(ACS_PRINT_INFO, L"GIC CPUIF base %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC CPUIF base %x \n", GicEntry->base);
         GicEntry++;
       }
 
@@ -93,7 +93,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICC_GICRD;
         GicEntry->base = Entry->GICRBaseAddress;
         GicEntry->length = 0;
-        bsa_print(ACS_PRINT_INFO, L"GIC RD base %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC RD base %x \n", GicEntry->base);
         GicTable->header.num_gicrd++;
         GicEntry++;
       }
@@ -102,7 +102,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICH;
         GicEntry->base = Entry->GICH;
         GicEntry->length = 0;
-        bsa_print(ACS_PRINT_INFO, L"GICH base %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GICH base %lx \n", GicEntry->base);
         GicEntry++;
       }
     }
@@ -111,7 +111,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICD;
         GicEntry->base = ((EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE *)Entry)->PhysicalBaseAddress;
         GicTable->header.gic_version = ((EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE *)Entry)->GicVersion;
-        bsa_print(ACS_PRINT_INFO, L"GIC DIS base %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC DIS base %lx \n", GicEntry->base);
         GicTable->header.num_gicd++;
         GicEntry++;
     }
@@ -120,7 +120,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICR_GICRD;
         GicEntry->base = ((EFI_ACPI_6_1_GICR_STRUCTURE *)Entry)->DiscoveryRangeBaseAddress;
         GicEntry->length = ((EFI_ACPI_6_1_GICR_STRUCTURE *)Entry)->DiscoveryRangeLength;
-        bsa_print(ACS_PRINT_INFO, L"GIC RD base Structure %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC RD base Structure %lx \n", GicEntry->base);
         GicTable->header.num_gicrd++;
         GicEntry++;
     }
@@ -129,8 +129,8 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICITS;
         GicEntry->base = ((EFI_ACPI_6_1_GIC_ITS_STRUCTURE *)Entry)->PhysicalBaseAddress;
         GicEntry->entry_id = ((EFI_ACPI_6_1_GIC_ITS_STRUCTURE *)Entry)->GicItsId;
-        bsa_print(ACS_PRINT_INFO, L"GIC ITS base %x \n", GicEntry->base);
-        bsa_print(ACS_PRINT_INFO, L"GIC ITS ID%x \n", GicEntry->entry_id);
+        bsa_print(ACS_PRINT_INFO, L"  GIC ITS base %lx \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC ITS ID%x \n", GicEntry->entry_id);
         GicTable->header.num_its++;
         GicEntry++;
     }
@@ -142,9 +142,9 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->flags = ((EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE *)Entry)->Flags;
         GicEntry->spi_count = ((EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE *)Entry)->SPICount;
         GicEntry->spi_base = ((EFI_ACPI_6_1_GIC_MSI_FRAME_STRUCTURE *)Entry)->SPIBase;
-        bsa_print(ACS_PRINT_INFO, L"GIC MSI Frame base %x \n", GicEntry->base);
-        bsa_print(ACS_PRINT_INFO, L"GIC MSI SPI base %x \n", GicEntry->spi_base);
-        bsa_print(ACS_PRINT_INFO, L"GIC MSI SPI Count %x \n", GicEntry->spi_count);
+        bsa_print(ACS_PRINT_INFO, L"  GIC MSI Frame base %lx \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC MSI SPI base %x \n", GicEntry->spi_base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC MSI SPI Count %x \n", GicEntry->spi_count);
         GicTable->header.num_msi_frame++;
         GicEntry++;
     }
@@ -251,9 +251,15 @@ pal_gic_set_intr_trigger(UINT32 int_id, INTR_TRIGGER_INFO_TYPE_e trigger_type)
   return 0;
 }
 
-/* Place holder function. Need to be
- * implemented if needed in later releases
- */
+/** Place holder function. Need to be implemented if needed in later releases
+  @brief Registers the interrupt handler for a given IRQ
+
+  @param IrqNum Hardware IRQ number
+  @param MappedIrqNum Mapped IRQ number
+  @param Isr Interrupt Service Routine that returns the status
+
+  @return Status of the operation
+**/
 UINT32
 pal_gic_request_irq(
   UINT32 IrqNum,
@@ -264,9 +270,14 @@ pal_gic_request_irq(
     return 0;
 }
 
-/* Place holder function. Need to be
- * implemented if needed in later releases
- */
+/** Place holder function. Need to be implemented if needed in later releases
+  @brief This function frees the registered interrupt handler for a given IRQ
+
+  @param IrqNum Hardware IRQ number
+  @param MappedIrqNum Mapped IRQ number
+
+  @return none
+**/
 VOID
 pal_gic_free_irq(
   UINT32 IrqNum,
diff --git a/platform/pal_uefi_acpi/src/pal_iovirt.c b/platform/pal_uefi_acpi/src/pal_iovirt.c
index 021f7b1c..5c981a1f 100644
--- a/platform/pal_uefi_acpi/src/pal_iovirt.c
+++ b/platform/pal_uefi_acpi/src/pal_iovirt.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2019,2021 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -33,6 +33,13 @@
 
 UINT64 pal_get_iort_ptr();
 
+/**
+  @brief This API creates iovirt override table
+
+  @param table Address where the iovirt override information needs to be filled
+
+  @return None
+**/
 STATIC VOID
 iovirt_create_override_table(IOVIRT_INFO_TABLE *table) {
   IOVIRT_BLOCK *block;
@@ -45,7 +52,11 @@ iovirt_create_override_table(IOVIRT_INFO_TABLE *table) {
 }
 
 /**
-  @brief  Dump the input block
+  @brief Dump the input block
+
+  @param block Pointer to block
+
+  @return None
 **/
 STATIC VOID
 dump_block(IOVIRT_BLOCK *block) {
@@ -53,36 +64,48 @@ dump_block(IOVIRT_BLOCK *block) {
   NODE_DATA_MAP *map = &block->data_map[0];
   switch(block->type) {
       case IOVIRT_NODE_ITS_GROUP:
-      bsa_print(ACS_PRINT_INFO, L"\nITS Group:\n Num ITS : %d", block->data.its_count);
+      bsa_print(ACS_PRINT_INFO, L"  ITS Group Num ITS: %d\n",
+                                                        block->data.its_count);
       for(i = 0; i < block->data.its_count; i++)
-          bsa_print(ACS_PRINT_INFO, L"\n ITS ID : %d", (*map).id[i]);
-      bsa_print(ACS_PRINT_INFO, L"\n");
+          bsa_print(ACS_PRINT_INFO, L"  ITS ID: %d\n", (*map).id[i]);
       return;
       case IOVIRT_NODE_NAMED_COMPONENT:
-      bsa_print(ACS_PRINT_INFO, L"\nNamed Component:\n Device Name:%a\n", block->data.name);
+      bsa_print(ACS_PRINT_INFO, L"  Named Component Device Name:%a\n",
+                                                            block->data.name);
       break;
       case IOVIRT_NODE_PCI_ROOT_COMPLEX:
-      bsa_print(ACS_PRINT_INFO, L"\nRoot Complex:\n Segment Num:%d\n", block->data.rc.segment);
+      bsa_print(ACS_PRINT_INFO, L"  Root Complex  Segment Num:%d\n",
+                                                      block->data.rc.segment);
       break;
       case IOVIRT_NODE_SMMU:
       case IOVIRT_NODE_SMMU_V3:
-      bsa_print(ACS_PRINT_INFO, L"\nSMMU:\n Major Rev:%d\n Base Address:0x%x\n",
+      bsa_print(ACS_PRINT_INFO, L"  SMMU: Major Rev:%d Base Address:0x%x\n",
                  block->data.smmu.arch_major_rev, block->data.smmu.base);
       break;
       case IOVIRT_NODE_PMCG:
-      bsa_print(ACS_PRINT_INFO, L"\nPMCG:\n Base:0x%x\n Overflow GSIV:0x%x\n Node Reference:0x%x\n",
-                 block->data.pmcg.base, block->data.pmcg.overflow_gsiv, block->data.pmcg.node_ref);
+      bsa_print(ACS_PRINT_INFO, L"  PMCG: Base:0x%x Overflow GSIV:0x%x"
+                               " Node Reference:0x%x\n", block->data.pmcg.base,
+                block->data.pmcg.overflow_gsiv, block->data.pmcg.node_ref);
       break;
   }
-  bsa_print(ACS_PRINT_INFO, L"\nNumber of ID Mappings:%d\n", block->num_data_map);
+  bsa_print(ACS_PRINT_INFO, L"  Number of ID Mappings:%d\n", block->num_data_map);
   for(i = 0; i < block->num_data_map; i++, map++) {
-      bsa_print(ACS_PRINT_INFO, L"\n input_base:0x%x\n id_count:0x%x\n output_base:0x%x\n output ref:0x%x\n",
+      bsa_print(ACS_PRINT_INFO, L"  input_base:0x%x id_count:0x%x\n"
+                                "  output_base:0x%x output ref:0x%x\n",
             (*map).map.input_base, (*map).map.id_count,
             (*map).map.output_base, (*map).map.output_ref);
   }
   bsa_print(ACS_PRINT_INFO, L"\n");
 }
 
+/**
+  @brief This API checks if the context bank interrupt ids for the smmu node are unique
+
+  @param ctx_int Array of context bank interrupt ids
+  @param ctx_int_cnt Context bank interrupt count
+
+  @return 0 if context bank interrupt ids are not unique ; 1 if context bank interrupt ids are unique
+**/
 STATIC UINTN
 smmu_ctx_int_distinct(UINT64 *ctx_int, INTN ctx_int_cnt) {
   INTN i, j;
@@ -95,19 +118,29 @@ smmu_ctx_int_distinct(UINT64 *ctx_int, INTN ctx_int_cnt) {
   return 1;
 }
 
+/**
+  @brief This API dumps the iovirt table
+
+  @param iovirt Pointer to iovirt info table
+
+  @return None
+**/
 STATIC VOID
 dump_iort_table(IOVIRT_INFO_TABLE *iovirt)
 {
   UINT32 i;
   IOVIRT_BLOCK *block = &iovirt->blocks[0];
-  bsa_print(ACS_PRINT_INFO, L"Number of IOVIRT blocks = %d\n", iovirt->num_blocks);
+  bsa_print(ACS_PRINT_INFO, L"  Number of IOVIRT blocks = %d\n", iovirt->num_blocks);
   for(i = 0; i < iovirt->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block))
     dump_block(block);
 }
 
 /**
   @brief  Check ID mappings in all blocks for any overlap of ID ranges
+
   @param iort IoVirt table
+
+  @return None
 **/
 STATIC VOID
 check_mapping_overlap(IOVIRT_INFO_TABLE *iovirt)
@@ -156,13 +189,13 @@ check_mapping_overlap(IOVIRT_INFO_TABLE *iovirt)
             if(tmp->type == IOVIRT_NODE_ITS_GROUP) {
                key_block->flags |= (1 << IOVIRT_FLAG_DEVID_OVERLAP_SHIFT);
                block->flags |= (1 << IOVIRT_FLAG_DEVID_OVERLAP_SHIFT);
-               bsa_print(ACS_PRINT_INFO, L"\nOverlapping device ids %x-%x and %x-%x \n",
+               bsa_print(ACS_PRINT_INFO, L"\n Overlapping device ids %x-%x and %x-%x \n",
                           key_start, key_end, start, end);
             }
             else {
                key_block->flags |= (1 << IOVIRT_FLAG_STRID_OVERLAP_SHIFT);
                block->flags |= (1 << IOVIRT_FLAG_STRID_OVERLAP_SHIFT);
-               bsa_print(ACS_PRINT_INFO, L"\nOverlapping stream ids %x-%x and %x-%x \n",
+               bsa_print(ACS_PRINT_INFO, L"\n Overlapping stream ids %x-%x and %x-%x \n",
                           key_start, key_end, start, end);
             }
           }
@@ -226,7 +259,7 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt
   NODE_DATA *data = &((*block)->data);
   VOID *node_data = &(iort_node->node_data[0]);
 
-  bsa_print(ACS_PRINT_INFO, L"IORT node offset:%x, type: %d\n", (UINT8*)iort_node - (UINT8*)iort, iort_node->type);
+  bsa_print(ACS_PRINT_INFO, L"  IORT node offset:%x, type: %d\n", (UINT8*)iort_node - (UINT8*)iort, iort_node->type);
 
   SetMem(data, sizeof(NODE_DATA), 0);
 
@@ -277,7 +310,7 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt
       count = &IoVirtTable->num_pmcgs;
       break;
     default:
-       bsa_print(ACS_PRINT_ERR, L"Invalid IORT node type\n");
+       bsa_print(ACS_PRINT_ERR, L" Invalid IORT node type\n");
        return (UINT32) -1;
   }
 
@@ -345,7 +378,11 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt
 }
 
 /**
-  @brief  Parses ACPI IORT table and populates the local iovirt table
+  @brief Parses ACPI IORT table and populates the local iovirt table
+
+  @param IoVirtTable Address where the IOVIRT information must be filled
+
+  @return None
 **/
 VOID
 pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *IoVirtTable)
@@ -387,7 +424,7 @@ pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *IoVirtTable)
   /* Create iovirt block for each IORT node*/
   for (i = 0; i < iort->node_count; i++) {
     if (iort_node >= iort_end) {
-      bsa_print(ACS_PRINT_ERR, L"Bad IORT table \n");
+      bsa_print(ACS_PRINT_ERR, L" Bad IORT table \n");
       return;
     }
     iort_add_block(iort, iort_node, IoVirtTable, &next_block);
@@ -432,29 +469,79 @@ pal_iovirt_unique_rid_strid_map(UINT64 rc_block)
   return 1;
 }
 
+/**
+ @brief This API returns the base address of SMMU if a Root Complex is
+          behind an SMMU, otherwise returns NULL
+
+ @param Iovirt IO Virt Table base address pointer
+ @param RcSegmentNum Root complex segment number
+ @param rid Unique requester ID
+
+ @return base address of SMMU if a Root Complex is behind an SMMU, otherwise returns NULL
+**/
 UINT64
 pal_iovirt_get_rc_smmu_base (
   IOVIRT_INFO_TABLE *Iovirt,
-  UINT32 RcSegmentNum
+  UINT32 RcSegmentNum,
+  UINT32 rid
   )
 {
-  UINT32 i;
+  UINT32 i, j;
   IOVIRT_BLOCK *block;
+  NODE_DATA_MAP *map;
+  UINT32 mapping_found;
+  UINT32 oref, sid, id = 0;
 
-  /* As per IORT acpi table, it is assumed that
-   * PCI segment numbers have a one-to-one mapping
-   * with root complexes. Each segment number can
-   * represent only one root complex.
-   */
+  /* Search for root complex block with same segment number, and in whose id */
+  /* mapping range 'rid' falls. Calculate the output id */
   block = &(Iovirt->blocks[0]);
-  for(i = 0; i < Iovirt->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) {
-    if (block->data.rc.segment == RcSegmentNum) {
-      return block->data.rc.smmu_base;
-    }
+  mapping_found = 0;
+
+  for (i = 0; i < Iovirt->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block))
+  {
+      if (block->type == IOVIRT_NODE_PCI_ROOT_COMPLEX
+          && block->data.rc.segment == RcSegmentNum)
+      {
+          for (j = 0, map = &block->data_map[0]; j < block->num_data_map; j++, map++)
+          {
+              if (rid >= (*map).map.input_base
+                      && rid <= ((*map).map.input_base + (*map).map.id_count))
+              {
+                  id =  rid - (*map).map.input_base + (*map).map.output_base;
+                  oref = (*map).map.output_ref;
+                  mapping_found = 1;
+                  break;
+              }
+          }
+      }
+  }
+
+  if (!mapping_found) {
+      bsa_print(ACS_PRINT_ERR,
+               L"\n       RID to Stream ID/Dev ID map not found ", 0);
+      return 0xFFFFFFFF;
+  }
+
+  block = (IOVIRT_BLOCK*)((UINT8*)Iovirt + oref);
+  if (block->type == IOVIRT_NODE_SMMU || block->type == IOVIRT_NODE_SMMU_V3)
+  {
+      sid = id;
+      id = 0;
+      for (i = 0, map = &block->data_map[0]; i < block->num_data_map; i++, map++)
+      {
+          if (sid >= (*map).map.input_base && sid <= ((*map).map.input_base +
+                                                    (*map).map.id_count))
+          {
+              bsa_print(ACS_PRINT_DEBUG, L"\n       RC block->data.smmu."
+                                "base: %llx    ", block->data.smmu.base);
+              return block->data.smmu.base;
+          }
+      }
   }
 
   /* The Root Complex represented by rc_seg_num
    * is not behind any SMMU. Return NULL pointer
    */
+  bsa_print(ACS_PRINT_DEBUG, L" No SMMU found behind the RootComplex with seg :%x", RcSegmentNum);
   return 0;
 }
diff --git a/platform/pal_uefi_acpi/src/pal_misc.c b/platform/pal_uefi_acpi/src/pal_misc.c
index 038ed130..66ba63a4 100644
--- a/platform/pal_uefi_acpi/src/pal_misc.c
+++ b/platform/pal_uefi_acpi/src/pal_misc.c
@@ -27,6 +27,15 @@
 
 UINT8   *gSharedMemory;
 
+/**
+ @brief This API provides a single point of abstraction to write 8-bit
+        data to all memory-mapped I/O addresses.
+
+ @param addr 64-bit address
+ @param data 8-bit data write to address
+
+ @return None
+**/
 VOID
 pal_mmio_write8(UINT64 addr, UINT8 data)
 {
@@ -35,6 +44,15 @@ pal_mmio_write8(UINT64 addr, UINT8 data)
 
 }
 
+/**
+  @brief This API provides a single point of abstraction to write 16-bit
+         data to all memory-mapped I/O addresses.
+
+  @param addr 64-bit address
+  @param data 16-bit data write to address
+
+  @return None
+**/
 VOID
 pal_mmio_write16(UINT64 addr, UINT16 data)
 {
@@ -43,6 +61,15 @@ pal_mmio_write16(UINT64 addr, UINT16 data)
 
 }
 
+/**
+   @brief This API provides a single point of abstraction to write 64-bit
+          data to all memory-mapped I/O addresses.
+
+   @param addr 64-bit address
+   @param data 64-bit data write to address
+
+   @return None
+**/
 VOID
 pal_mmio_write64(UINT64 addr, UINT64 data)
 {
@@ -51,6 +78,14 @@ pal_mmio_write64(UINT64 addr, UINT64 data)
 
 }
 
+/**
+  @brief This API provides a single point of abstraction to read 8-bit data
+         from all memory-mapped I/O addresses.
+
+  @param addr 64-bit input address
+
+  @return 8-bit data read from the input address
+**/
 UINT8
 pal_mmio_read8(UINT64 addr)
 {
@@ -62,6 +97,14 @@ pal_mmio_read8(UINT64 addr)
   return data;
 }
 
+/**
+  @brief This API provides a single point of abstraction to read 16-bit data
+         from all memory-mapped I/O addresses.
+
+  @param addr 64-bit input address
+
+  @return 16-bit data read from the input address
+**/
 UINT16
 pal_mmio_read16(UINT64 addr)
 {
@@ -73,6 +116,14 @@ pal_mmio_read16(UINT64 addr)
   return data;
 }
 
+/**
+  @brief This API provides a single point of abstraction to read 64-bit data
+         from all memory-mapped I/O addresses.
+
+  @param addr 64-bit input address
+
+  @return 64-bit data read from the input address
+**/
 UINT64
 pal_mmio_read64(UINT64 addr)
 {
@@ -144,7 +195,7 @@ pal_print(CHAR8 *string, UINT64 data)
     AsciiPrint(Buffer);
     Status = ShellWriteFile(g_bsa_log_file_handle, &BufferSize, (VOID*)Buffer);
     if(EFI_ERROR(Status))
-      bsa_print(ACS_PRINT_ERR, L"Error in writing to log file\n");
+      bsa_print(ACS_PRINT_ERR, L" Error in writing to log file\n");
   } else
       AsciiPrint(string, data);
 }
@@ -153,6 +204,7 @@ pal_print(CHAR8 *string, UINT64 data)
   @brief  Sends a string to the output console without using UEFI print function
           This function will get COMM port address and directly writes to the addr char-by-char
 
+  @param  addr    Address to be written
   @param  string  An ASCII string
   @param  data    data for the formatted output
 
@@ -259,10 +311,10 @@ pal_mem_allocate_shared(UINT32 num_pe, UINT32 sizeofentry)
                                (num_pe * sizeofentry),
                                (VOID **) &gSharedMemory );
 
-  bsa_print(ACS_PRINT_INFO, L"Shared memory is %llx \n", gSharedMemory);
+  bsa_print(ACS_PRINT_INFO, L" Shared memory is %llx \n", gSharedMemory);
 
   if (EFI_ERROR(Status)) {
-    bsa_print(ACS_PRINT_ERR, L"Allocate Pool shared memory failed %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Allocate Pool shared memory failed %x \n", Status);
   }
   pal_pe_data_cache_ops_by_va((UINT64)&gSharedMemory, CLEAN_AND_INVALIDATE);
 
@@ -299,13 +351,13 @@ pal_mem_free_shared()
 }
 
 /**
- * @brief  Allocates requested buffer size in bytes in a contiguous memory
- *         and returns the base address of the range.
- *
- * @param  Size         allocation size in bytes
- * @retval if SUCCESS   pointer to allocated memory
- * @retval if FAILURE   NULL
- */
+  @brief  Allocates requested buffer size in bytes in a contiguous memory
+          and returns the base address of the range.
+
+  @param  Size         allocation size in bytes
+
+  @return if SUCCESS   pointer to allocated memory ;  if FAILURE   NULL
+**/
 VOID *
 pal_mem_alloc (
   UINT32 Size
@@ -321,7 +373,7 @@ pal_mem_alloc (
                               (VOID **) &Buffer);
   if (EFI_ERROR(Status))
   {
-    bsa_print(ACS_PRINT_ERR, L"Allocate Pool failed %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Allocate Pool failed %x \n", Status);
     return NULL;
   }
 
@@ -330,14 +382,15 @@ pal_mem_alloc (
 }
 
 /**
- * @brief  Allocates requested buffer size in bytes in a contiguous cacheable
- *         memory and returns the base address of the range.
- *
- * @param  Size         allocation size in bytes
- * @param  Pa           Pointer to Physical Addr
- * @retval if SUCCESS   Pointer to Virtual Addr
- * @retval if FAILURE   NULL
- */
+  @brief  Allocates requested buffer size in bytes in a contiguous cacheable
+          memory and returns the base address of the range.
+
+  @param  Bdf          Bus, Device, and Function of the requesting PCIe device
+  @param  Size         allocation size in bytes
+  @param  Pa           Pointer to Physical Addr
+
+  @return if SUCCESS   Pointer to Virtual Addr ; if FAILURE   NULL
+**/
 VOID *
 pal_mem_alloc_cacheable (
   UINT32 Bdf,
@@ -354,14 +407,14 @@ pal_mem_alloc_cacheable (
                                EFI_SIZE_TO_PAGES(Size),
                                &Address);
   if (EFI_ERROR(Status)) {
-    bsa_print(ACS_PRINT_ERR, L"Allocate Pool failed %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Allocate Pool failed %x \n", Status);
     return NULL;
   }
 
   /* Check Whether Cpu architectural protocol is installed */
   Status = gBS->LocateProtocol ( &gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);
   if (EFI_ERROR(Status)) {
-    bsa_print(ACS_PRINT_ERR, L"Could not get Cpu Arch Protocol %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Could not get Cpu Arch Protocol %x \n", Status);
     return NULL;
   }
 
@@ -371,7 +424,7 @@ pal_mem_alloc_cacheable (
                                      Size,
                                      EFI_MEMORY_WB);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_ERR, L"Could not Set Memory Attribute %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Could not Set Memory Attribute %x \n", Status);
     return NULL;
   }
 
@@ -380,13 +433,15 @@ pal_mem_alloc_cacheable (
 }
 
 /**
- * @brief  Free the cacheable memory region allocated above
- *
- * @param  Size         allocation size in bytes
- * @param  Va           Pointer to Virtual Addr
- * @param  Pa           Pointer to Physical Addr
- * @retval None
- */
+  @brief  Free the cacheable memory region allocated above
+
+  @param  Bdf          Bus, Device, and Function of the requesting PCIe device
+  @param  Size         allocation size in bytes
+  @param  Va           Pointer to Virtual Addr
+  @param  Pa           Pointer to Physical Addr
+
+  @return None
+**/
 VOID
 pal_mem_free_cacheable (
   UINT32 Bdf,
@@ -398,9 +453,13 @@ pal_mem_free_cacheable (
   gBS->FreePages((EFI_PHYSICAL_ADDRESS)(UINTN)Va, EFI_SIZE_TO_PAGES(Size));
 }
 
-/* Place holder function. Need to be
- * implemented if needed in later releases
- */
+/** Place holder function. Need to be implemented if needed in later releases
+  @brief This API returns the physical address of the input virtual address.
+
+  @param Va virtual address of the memory to be converted
+
+  @return Returns the physical address
+**/
 VOID *
 pal_mem_virt_to_phys (
   VOID *Va
@@ -409,6 +468,13 @@ pal_mem_virt_to_phys (
   return Va;
 }
 
+/**
+ @brief Returns the virtual address of the input physical address.
+
+ @param Pa Physical Address of the memory to be converted
+
+ @return Pointer to virtual address space
+**/
 VOID *
 pal_mem_phys_to_virt (
   UINT64 Pa
@@ -472,12 +538,26 @@ pal_time_delay_ms (
   return gBS->Stall(MicroSeconds);
 }
 
+/**
+ @brief Returns the memory page size (in bytes) used by the platform.
+
+ @param None
+
+ @return Size of memory page
+**/
 UINT32
 pal_mem_page_size()
 {
     return EFI_PAGE_SIZE;
 }
 
+/**
+  @brief Allocates the requested number of memory pages
+
+  @param NumPages Number of memory pages needed
+
+  @return Address of the allocated space
+**/
 VOID *
 pal_mem_alloc_pages (
   UINT32 NumPages
@@ -492,13 +572,21 @@ pal_mem_alloc_pages (
                                &PageBase);
   if (EFI_ERROR(Status))
   {
-    bsa_print(ACS_PRINT_ERR, L"Allocate Pages failed %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Allocate Pages failed %x \n", Status);
     return NULL;
   }
 
   return (VOID*)(UINTN)PageBase;
 }
 
+/**
+  @brief Free number of pages in the memory as requested.
+
+  @param PageBase Address from where we need to free
+  @param NumPages Number of memory pages needed
+
+  @return None
+**/
 VOID
 pal_mem_free_pages(
   VOID *PageBase,
diff --git a/platform/pal_uefi_acpi/src/pal_pcie.c b/platform/pal_uefi_acpi/src/pal_pcie.c
index e844e815..ac6eaf7c 100644
--- a/platform/pal_uefi_acpi/src/pal_pcie.c
+++ b/platform/pal_uefi_acpi/src/pal_pcie.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2020,2021 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -53,7 +53,7 @@ pal_pcie_get_mcfg_ecam()
   gMcfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *) pal_get_mcfg_ptr();
 
   if (gMcfgHdr == NULL) {
-      bsa_print(ACS_PRINT_WARN, L"ACPI - MCFG Table not found. Setting ECAM Base to 0. \n");
+      bsa_print(ACS_PRINT_WARN, L" ACPI - MCFG Table not found. Setting ECAM Base to 0. \n");
       return 0x0;
   }
 
@@ -79,7 +79,7 @@ pal_pcie_create_info_table(PCIE_INFO_TABLE *PcieTable)
   UINT32 i = 0;
 
   if (PcieTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input PCIe Table Pointer is NULL. Cannot create PCIe INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input PCIe Table Pointer is NULL. Cannot create PCIe INFO \n");
     return;
   }
 
@@ -88,7 +88,7 @@ pal_pcie_create_info_table(PCIE_INFO_TABLE *PcieTable)
   gMcfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *) pal_get_mcfg_ptr();
 
   if (gMcfgHdr == NULL) {
-      bsa_print(ACS_PRINT_DEBUG, L"ACPI - MCFG Table not found. \n");
+      bsa_print(ACS_PRINT_DEBUG, L" ACPI - MCFG Table not found. \n");
       return;
   }
 
@@ -109,11 +109,11 @@ pal_pcie_create_info_table(PCIE_INFO_TABLE *PcieTable)
       PcieTable->block[i].segment_num   = Entry->PciSegmentGroupNumber;
       PcieTable->block[i].start_bus_num = Entry->StartBusNumber;
       PcieTable->block[i].end_bus_num   = Entry->EndBusNumber;
-      bsa_print(ACS_PRINT_INFO, L"\nEcam Index = %d", i);
-      bsa_print(ACS_PRINT_INFO, L"\n Base Address = 0x%llx", Entry->BaseAddress);
-      bsa_print(ACS_PRINT_INFO, L"\n Segment   = 0x%llx", Entry->PciSegmentGroupNumber);
-      bsa_print(ACS_PRINT_INFO, L"\n Start Bus = 0x%llx", Entry->StartBusNumber);
-      bsa_print(ACS_PRINT_INFO, L"\n End Bus   = 0x%llx", Entry->EndBusNumber);
+      bsa_print(ACS_PRINT_INFO, L"  Ecam Index = %d\n", i);
+      bsa_print(ACS_PRINT_INFO, L"  Base Address = 0x%llx\n", Entry->BaseAddress);
+      bsa_print(ACS_PRINT_INFO, L"  Segment   = 0x%llx\n", Entry->PciSegmentGroupNumber);
+      bsa_print(ACS_PRINT_INFO, L"  Start Bus = 0x%llx\n", Entry->StartBusNumber);
+      bsa_print(ACS_PRINT_INFO, L"  End Bus   = 0x%llx\n", Entry->EndBusNumber);
       length += sizeof(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE);
       Entry++;
       i++;
@@ -147,7 +147,7 @@ pal_pcie_io_read_cfg(UINT32 Bdf, UINT32 offset, UINT32 *data)
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_INFO,L"No PCI devices found in the system\n");
+    bsa_print(ACS_PRINT_INFO,L" No PCI devices found in the system\n");
     return PCIE_NO_MAPPING;
   }
 
@@ -196,7 +196,7 @@ pal_pcie_io_write_cfg(UINT32 Bdf, UINT32 offset, UINT32 data)
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_INFO,L"No PCI devices found in the system\n");
+    bsa_print(ACS_PRINT_INFO,L" No PCI devices found in the system\n");
     return;
   }
 
@@ -236,8 +236,13 @@ pal_pcie_p2p_support()
 /**
   @brief   This API checks the PCIe device P2P support
            1. Caller       -  Test Suite
-  @param   bdf      - PCIe BUS/Device/Function
-  @return  1 - P2P feature not supported 0 - P2P feature supported
+
+  @param   Seg       PCI segment number
+  @param   Bus        PCI bus address
+  @param   Dev        PCI device address
+  @param   Fn         PCI function number
+  @retval 0 P2P feature supported
+  @retval 1 P2P feature not supported
 **/
 UINT32
 pal_pcie_dev_p2p_support (
@@ -259,10 +264,11 @@ pal_pcie_dev_p2p_support (
 /**
     @brief   Create a list of MSI(X) vectors for a device
 
-    @param   bus        PCI bus address
-    @param   dev        PCI device address
-    @param   fn         PCI function number
-    @param   mvector    pointer to a MSI(X) list address
+    @param   Seg        PCI segment number
+    @param   Bus        PCI bus address
+    @param   Dev        PCI device address
+    @param   Fn         PCI function number
+    @param   MVector    pointer to a MSI(X) list address
 
     @return  mvector    list of MSI(X) vectors
     @return  number of MSI(X) vectors
@@ -282,10 +288,11 @@ pal_get_msi_vectors (
 /**
     @brief   Get legacy IRQ routing for a PCI device
 
-    @param   bus        PCI bus address
-    @param   dev        PCI device address
-    @param   fn         PCI function number
-    @param   irq_map    pointer to IRQ map structure
+    @param   Seg        PCI segment number
+    @param   Bus        PCI bus address
+    @param   Dev        PCI device address
+    @param   Fn         PCI function number
+    @param   Irq_Map    pointer to IRQ map structure
 
     @return  irq_map    IRQ routing map
     @return  status code
@@ -302,9 +309,17 @@ pal_pcie_get_legacy_irq_map (
   return 1; /* not implemented */
 }
 
-/* Place holder function. Need to be
- * implemented if needed in later releases
- */
+/** Place holder function. Need to be implemented if needed in later releases
+  @brief Returns the Bus, Device, and Function values of the Root Port of the device.
+
+  @param   Seg        PCI segment number
+  @param   Bus        PCI bus address
+  @param   Dev        PCI device address
+  @param   Fn         PCI function number
+
+  @return 0 if success; 1 if input BDF device cannot be found
+          2 if root Port for the input device cannot be determined
+**/
 UINT32
 pal_pcie_get_root_port_bdf (
   UINT32 *Seg,
@@ -320,8 +335,14 @@ pal_pcie_get_root_port_bdf (
   @brief   Platform dependent API checks the Address Translation
            Cache Support for BDF
            1. Caller       -  Test Suite
-  @return  0 - ATC not supported 1 - ATC supported
-**/
+
+  @param   Seg        PCI segment number
+  @param   Bus        PCI bus address
+  @param   Dev        PCI device address
+  @param   Fn         PCI function number
+  @retval 0 ATC supported
+  @retval 1 ATC not supported
+  **/
 UINT32
 pal_pcie_is_cache_present (
   UINT32 Seg,
@@ -330,17 +351,19 @@ pal_pcie_is_cache_present (
   UINT32 Fn
   )
 {
-  return 0;
+  return 1;
 }
 
 /**
     @brief   Checks if device is behind SMMU
 
+    @param   seg        PCI segment number
     @param   bus        PCI bus address
     @param   dev        PCI device address
     @param   fn         PCI function number
 
-    @return  staus code:0 -> not present, nonzero -> present
+    @retval 1 if device is behind SMMU
+    @retval 0 if device is not behind SMMU or SMMU is in bypass mode
 **/
 UINT32
 pal_pcie_is_device_behind_smmu(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
@@ -351,11 +374,13 @@ pal_pcie_is_device_behind_smmu(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
 /**
     @brief   Return the DMA addressability of the device
 
+    @param   seg        PCI segment number
     @param   bus        PCI bus address
     @param   dev        PCI device address
     @param   fn         PCI function number
 
-    @return  DMA Mask : 0, 0xffffffff or 0xffffffffffff
+    @retval 0 if does not support 64-bit transfers
+    @retval 1 if supports 64-bit transfers
 **/
 UINT32
 pal_pcie_is_devicedma_64bit(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
@@ -366,14 +391,16 @@ pal_pcie_is_devicedma_64bit(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
 /**
     @brief   Get the PCIe device type
 
+    @param   seg        PCI segment number
     @param   bus        PCI bus address
     @param   dev        PCI device address
     @param   fn         PCI function number
 
-    @return  staus code:
-             1: Normal PCIe device, 2: PCIe Host bridge,
-             3: PCIe bridge device, else: INVALID
-**/
+    @retval 0 if Error: could not determine device structures
+    @retval 1 if normal PCIe device
+    @retval 2 if PCIe host bridge
+    @retval 3 if PCIe bridge
+    **/
 UINT32
 pal_pcie_get_device_type(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
 {
@@ -402,8 +429,8 @@ pal_bsa_pcie_enumerate()
     @param   fn         PCI function number
     @param   seg        PCI segment number
 
-    @return  0 if rp not involved in transaction forwarding
-             1 if rp is involved in transaction forwarding
+    @return  1 if rp not involved in transaction forwarding
+             0 if rp is involved in transaction forwarding
 **/
 UINT32
 pal_pcie_get_rp_transaction_frwd_support(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
diff --git a/platform/pal_uefi_acpi/src/pal_pcie_enumeration.c b/platform/pal_uefi_acpi/src/pal_pcie_enumeration.c
index ce372f54..8d7afe7f 100644
--- a/platform/pal_uefi_acpi/src/pal_pcie_enumeration.c
+++ b/platform/pal_uefi_acpi/src/pal_pcie_enumeration.c
@@ -83,7 +83,7 @@ palPcieGetBdf(UINT32 ClassCode, UINT32 StartBdf)
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_INFO,L"No PCI devices found in the system\n");
+    bsa_print(ACS_PRINT_INFO,L" No PCI devices found in the system\n");
     return EFI_SUCCESS;
   }
 
@@ -107,7 +107,8 @@ palPcieGetBdf(UINT32 ClassCode, UINT32 StartBdf)
           Status = Pci->Pci.Read (Pci, EfiPciIoWidthUint32, 0, sizeof (PciHeader)/sizeof (UINT32), &PciHeader);
           if (!EFI_ERROR (Status)) {
             Hdr = &PciHeader.Bridge.Hdr;
-            bsa_print(ACS_PRINT_INFO,L"\n%03d.%02d.%02d class_code = %d %d", Bus, Dev, Index, Hdr->ClassCode[1], Hdr->ClassCode[2]);
+            bsa_print(ACS_PRINT_INFO,L"  %03d.%02d.%02d class_code = %d %d\n",
+                        Bus, Dev, Index, Hdr->ClassCode[1], Hdr->ClassCode[2]);
             if (Hdr->ClassCode[2] == ((ClassCode >> 16) & 0xFF)) {
               if (Hdr->ClassCode[1] == ((ClassCode >> 8) & 0xFF)) {
                  /* Found our device */
@@ -167,7 +168,7 @@ palPcieGetBase(UINT32 bdf, UINT32 bar_index)
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_INFO,L"No PCI devices found in the system\n");
+    bsa_print(ACS_PRINT_INFO,L" No PCI devices found in the system\n");
     return EFI_SUCCESS;
   }
 
@@ -195,6 +196,13 @@ palPcieGetBase(UINT32 bdf, UINT32 bar_index)
   return 0;
 }
 
+/**
+  @brief Returns the PCI device structure for the given bdf
+
+  @param Bdf PCI Bus, Device, and Function
+
+  @return Pointer to device structure for the input bdf
+**/
 VOID *
 pal_pci_bdf_to_dev (
  UINT32 Bdf
@@ -203,6 +211,15 @@ pal_pci_bdf_to_dev (
   return NULL;
 }
 
+/**
+  @brief Reads 1 byte from the PCI configuration space for the current BDF at given offset.
+
+  @param Bdf PCI Bus, Device, and Function
+  @param Offset offset in the PCI configuration space for that BDF
+  @param Val return value
+
+  @return None
+**/
 VOID
 pal_pci_read_config_byte (
   UINT32 Bdf,
@@ -213,6 +230,13 @@ pal_pci_read_config_byte (
 
 }
 
+/**
+  @brief This API performs the PCI enumeration
+
+  @param None
+
+  @return None
+**/
 VOID pal_pcie_enumerate(VOID)
 {
   /**Implemented functionality only for Baremetal support
diff --git a/platform/pal_uefi_acpi/src/pal_pe.c b/platform/pal_uefi_acpi/src/pal_pe.c
index c20a6261..f8b9cc92 100644
--- a/platform/pal_uefi_acpi/src/pal_pe.c
+++ b/platform/pal_uefi_acpi/src/pal_pe.c
@@ -82,8 +82,7 @@ PalGetMaxMpidr()
   @brief  Allocate memory region for secondary PE stack use. SIZE of stack for each PE
           is a #define
 
-  @param  Number of PEs
-
+  @param  mpidr Pass MIPDR register content
   @return  None
 **/
 VOID
@@ -130,7 +129,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
 
 
   if (PeTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input PE Table Pointer is NULL. Cannot create PE INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input PE Table Pointer is NULL. Cannot create PE INFO \n");
     return;
   }
 
@@ -138,9 +137,9 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
 
   if (gMadtHdr != NULL) {
     TableLength =  gMadtHdr->Header.Length;
-    bsa_print(ACS_PRINT_INFO, L" MADT is at %x and length is %x \n", gMadtHdr, TableLength);
+    bsa_print(ACS_PRINT_INFO, L"  MADT is at %x and length is %x \n", gMadtHdr, TableLength);
   } else {
-    bsa_print(ACS_PRINT_ERR, L"MADT not found \n");
+    bsa_print(ACS_PRINT_ERR, L" MADT not found \n");
     return;
   }
 
@@ -158,7 +157,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
       Ptr->pe_num     = PeTable->header.num_of_pe;
       Ptr->pmu_gsiv   = Entry->PerformanceInterruptGsiv;
       Ptr->gmain_gsiv = Entry->VGICMaintenanceInterrupt;
-      bsa_print(ACS_PRINT_DEBUG, L" MPIDR %x PE num %x \n", Ptr->mpidr, Ptr->pe_num);
+      bsa_print(ACS_PRINT_DEBUG, L"  MPIDR %x PE num %x \n", Ptr->mpidr, Ptr->pe_num);
       pal_pe_data_cache_ops_by_va((UINT64)Ptr, CLEAN_AND_INVALIDATE);
       Ptr++;
       PeTable->header.num_of_pe++;
diff --git a/platform/pal_uefi_acpi/src/pal_peripherals.c b/platform/pal_uefi_acpi/src/pal_peripherals.c
index 5c81016f..1486cba2 100644
--- a/platform/pal_uefi_acpi/src/pal_peripherals.c
+++ b/platform/pal_uefi_acpi/src/pal_peripherals.c
@@ -58,7 +58,8 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
   EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE *spcr = NULL;
 
   if (peripheralInfoTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input Peripheral Table Pointer is NULL. Cannot create Peripheral INFO \n");
+    bsa_print(ACS_PRINT_ERR,
+              L" Input Peripheral Table Pointer is NULL. Cannot create Peripheral INFO \n");
     return;
   }
 
@@ -76,7 +77,9 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
           per_info->type  = PERIPHERAL_TYPE_USB;
           per_info->base0 = palPcieGetBase(DeviceBdf, BAR0);
           per_info->bdf   = DeviceBdf;
-          bsa_print(ACS_PRINT_INFO, L"Found a USB controller %4x \n", per_info->base0);
+          per_info->platform_type = PLATFORM_TYPE_ACPI;
+          bsa_print(ACS_PRINT_INFO, L"  Found a USB controller %4x\n",
+                                                            per_info->base0);
           peripheralInfoTable->header.num_usb++;
           per_info++;
        }
@@ -93,7 +96,9 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
           per_info->type  = PERIPHERAL_TYPE_SATA;
           per_info->base0 = palPcieGetBase(DeviceBdf, BAR0);
           per_info->bdf   = DeviceBdf;
-          bsa_print(ACS_PRINT_INFO, L"Found a SATA controller %4x \n", per_info->base0);
+          per_info->platform_type = PLATFORM_TYPE_ACPI;
+          bsa_print(ACS_PRINT_INFO, L"  Found a SATA controller %4x\n",
+                                                            per_info->base0);
           peripheralInfoTable->header.num_sata++;
           per_info++;
        }
@@ -210,7 +215,7 @@ IsDeviceMemory(EFI_MEMORY_TYPE type)
   @brief  This API fills in the MEMORY_INFO_TABLE with information about memory in the
           system. This is achieved by parsing the UEFI memory map.
 
-  @param  peripheralInfoTable  - Address where the Peripheral information needs to be filled.
+  @param  memory_info_table Address where the memory info table is created
 
   @return  None
 **/
@@ -230,7 +235,7 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable)
   UINT32                Index, i = 0;
 
   if (memoryInfoTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input Memory Table Pointer is NULL. Cannot create Memory INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input Memory Table Pointer is NULL. Cannot create Memory INFO \n");
     return;
   }
 
@@ -256,7 +261,7 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable)
   if (!EFI_ERROR (Status)) {
     MemoryMapPtr = MemoryMap;
     for (Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++) {
-          bsa_print(ACS_PRINT_INFO, L"Reserved region of type %d [0x%lX, 0x%lX]\n",
+          bsa_print(ACS_PRINT_INFO, L"  Reserved region of type %d [0x%lX, 0x%lX]\n",
             MemoryMapPtr->Type, (UINTN)MemoryMapPtr->PhysicalStart,
             (UINTN)(MemoryMapPtr->PhysicalStart + MemoryMapPtr->NumberOfPages * EFI_PAGE_SIZE));
       if (IsUefiMemory ((EFI_MEMORY_TYPE)MemoryMapPtr->Type)) {
@@ -277,7 +282,7 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable)
       memoryInfoTable->info[i].size      = (MemoryMapPtr->NumberOfPages * EFI_PAGE_SIZE);
       i++;
       if (i >= MEM_INFO_TBL_MAX_ENTRY) {
-        bsa_print(ACS_PRINT_DEBUG, L"Memory Info tbl limit exceeded, Skipping remaining\n", 0);
+        bsa_print(ACS_PRINT_DEBUG, L"  Memory Info tbl limit exceeded, Skipping remaining\n", 0);
         break;
       }
 
@@ -288,6 +293,15 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable)
 
 }
 
+/**
+  @brief Maps the physical memory region into the virtual address space
+
+  @param ptr Pointer to physical memory region
+  @param size Size
+  @param attr Attributes
+
+  @return Pointer to mapped virtual address space
+**/
 UINT64
 pal_memory_ioremap(VOID *ptr, UINT32 size, UINT32 attr)
 {
@@ -296,7 +310,13 @@ pal_memory_ioremap(VOID *ptr, UINT32 size, UINT32 attr)
   return (UINT64)ptr;
 }
 
+/**
+  @brief Removes the physical memory to virtual address space mapping
+
+  @param ptr Pointer to mapped space
 
+  @return None
+**/
 VOID
 pal_memory_unmap(VOID *ptr)
 {
@@ -337,7 +357,7 @@ pal_memory_get_unpopulated_addr(UINT64 *addr, UINT32 instance)
         if (*addr == 0)
           continue;
 
-        bsa_print(ACS_PRINT_INFO,L"Unpopulated region with base address 0x%lX found\n", *addr);
+        bsa_print(ACS_PRINT_INFO,L" Unpopulated region with base address 0x%lX found\n", *addr);
         return EFI_SUCCESS;
       }
 
diff --git a/platform/pal_uefi_acpi/src/pal_timer_wd.c b/platform/pal_uefi_acpi/src/pal_timer_wd.c
index 050e1e15..444372a0 100644
--- a/platform/pal_uefi_acpi/src/pal_timer_wd.c
+++ b/platform/pal_uefi_acpi/src/pal_timer_wd.c
@@ -31,7 +31,14 @@ static EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE *gGtdtHdr;
 UINT64
 pal_get_gtdt_ptr();
 
-/* Information about only one timer can be mentioned as an Override */
+/**
+  @brief This API overrides the timer specified by TimerTable
+         Note: Information about only one timer can be mentioned as an Override
+
+  @param TimerTable Pointer to timer info table
+
+  @return None
+**/
 static
 VOID
 pal_timer_platform_override(TIMER_INFO_TABLE *TimerTable)
@@ -70,7 +77,7 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
   UINT32                      num_of_entries;
 
   if (TimerTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input Timer Table Pointer is NULL. Cannot create Timer INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input Timer Table Pointer is NULL. Cannot create Timer INFO \n");
     return;
   }
 
@@ -80,10 +87,10 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
   gGtdtHdr = (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE *) pal_get_gtdt_ptr();
 
   if (gGtdtHdr == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"GTDT not found \n");
+    bsa_print(ACS_PRINT_ERR, L" GTDT not found \n");
     return;
   }
-  bsa_print(ACS_PRINT_INFO, L" GTDT is at %x and length is %x \n", gGtdtHdr, gGtdtHdr->Header.Length);
+  bsa_print(ACS_PRINT_INFO, L"  GTDT is at %x and length is %x \n", gGtdtHdr, gGtdtHdr->Header.Length);
 
   //Fill in our internal table
   TimerTable->header.s_el1_timer_flag  = gGtdtHdr->SecurePL1TimerFlags;
@@ -103,21 +110,21 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
   while(num_of_entries) {
 
     if (Entry->Type == EFI_ACPI_6_1_GTDT_GT_BLOCK) {
-      bsa_print(ACS_PRINT_INFO, L"Found block entry \n");
+      bsa_print(ACS_PRINT_INFO, L"  Found block entry \n");
       GtEntry->type = TIMER_TYPE_SYS_TIMER;
       GtEntry->block_cntl_base = Entry->CntCtlBase;
       GtEntry->timer_count     = Entry->GTBlockTimerCount;
-      bsa_print(ACS_PRINT_DEBUG, L" CNTCTLBase = %x \n", GtEntry->block_cntl_base);
+      bsa_print(ACS_PRINT_DEBUG, L"  CNTCTLBase = %x \n", GtEntry->block_cntl_base);
       GtBlockTimer = (EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE *)(((UINT8 *)Entry) + Entry->GTBlockTimerOffset);
       for (i = 0; i < GtEntry->timer_count; i++) {
-        bsa_print(ACS_PRINT_INFO, L"Found timer entry \n");
+        bsa_print(ACS_PRINT_INFO, L"  Found timer entry \n");
         GtEntry->frame_num[i]    = GtBlockTimer->GTFrameNumber;
         GtEntry->GtCntBase[i]    = GtBlockTimer->CntBaseX;
         GtEntry->GtCntEl0Base[i] = GtBlockTimer->CntEL0BaseX;
         GtEntry->gsiv[i]         = GtBlockTimer->GTxPhysicalTimerGSIV;
         GtEntry->virt_gsiv[i]    = GtBlockTimer->GTxVirtualTimerGSIV;
         GtEntry->flags[i]        = GtBlockTimer->GTxPhysicalTimerFlags | (GtBlockTimer->GTxVirtualTimerFlags << 8) | (GtBlockTimer->GTxCommonFlags << 16);
-        bsa_print(ACS_PRINT_DEBUG, L" CNTBaseN = %x for sys counter = %d\n",
+        bsa_print(ACS_PRINT_DEBUG, L"  CNTBaseN = %x for sys counter = %d\n",
                                                      GtEntry->GtCntBase[i], i);
         GtBlockTimer++;
         TimerTable->header.num_platform_timer++;
@@ -138,7 +145,14 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
 
 }
 
-/* Only one watchdog information can be assigned as an override */
+/**
+  @brief This API overrides the watch dog timer specified by WdTable
+         Note: Only one watchdog information can be assigned as an override
+
+  @param WdTable Pointer to watch dog timer info table
+
+  @return None
+**/
 VOID
 pal_wd_platform_override(WD_INFO_TABLE *WdTable)
 {
@@ -173,7 +187,8 @@ pal_wd_create_info_table(WD_INFO_TABLE *WdTable)
   UINT32                      num_of_entries;
 
   if (WdTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input Watchdog Table Pointer is NULL. Cannot create Watchdog INFO \n");
+    bsa_print(ACS_PRINT_ERR,
+              L" Input Watchdog Table Pointer is NULL. Cannot create Watchdog INFO \n");
     return;
   }
 
@@ -182,7 +197,7 @@ pal_wd_create_info_table(WD_INFO_TABLE *WdTable)
   gGtdtHdr = (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE *) pal_get_gtdt_ptr();
 
   if (gGtdtHdr == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"GTDT not found \n");
+    bsa_print(ACS_PRINT_ERR, L" GTDT not found \n");
     return;
   }
 
@@ -204,7 +219,7 @@ pal_wd_create_info_table(WD_INFO_TABLE *WdTable)
       WdEntry->wd_gsiv         = Entry->WatchdogTimerGSIV;
       WdEntry->wd_flags        = Entry->WatchdogTimerFlags;
       WdTable->header.num_wd++;
-      bsa_print(ACS_PRINT_DEBUG, L" Watchdog base = 0x%x INTID = 0x%x \n",
+      bsa_print(ACS_PRINT_DEBUG, L"  Watchdog base = 0x%x INTID = 0x%x \n",
                                       WdEntry->wd_ctrl_base, WdEntry->wd_gsiv);
       WdEntry++;
     }
diff --git a/platform/pal_uefi_dt/include/pal_dt_spec.h b/platform/pal_uefi_dt/include/pal_dt_spec.h
index dcca4496..4baa210a 100644
--- a/platform/pal_uefi_dt/include/pal_dt_spec.h
+++ b/platform/pal_uefi_dt/include/pal_dt_spec.h
@@ -81,4 +81,10 @@
 #define ARM_SBSA_GENERIC_UART     0xE
 #define COMPATIBLE_GENERIC_16550  0x12
 
+#define USB_TYPE_OHCI             0x1
+#define USB_TYPE_EHCI             0x2
+#define USB_TYPE_XHCI             0x3
+
+#define SATA_TYPE_AHCI            0x1
+
 #endif
diff --git a/platform/pal_uefi_dt/include/pal_exerciser.h b/platform/pal_uefi_dt/include/pal_exerciser.h
index 9d2c5d51..2a5c9f93 100644
--- a/platform/pal_uefi_dt/include/pal_exerciser.h
+++ b/platform/pal_uefi_dt/include/pal_exerciser.h
@@ -43,6 +43,9 @@
 #define DMA_BUS_ADDR 0x010
 #define DMA_LEN      0x018
 #define DMASTATUS    0x01C
+#define PASID_VAL    0x020
+#define ATSCTL       0x024
+#define ATS_ADDR     0x028
 #define PCI_MAX_BUS     255
 #define PCI_MAX_DEVICE  31
 
@@ -65,6 +68,7 @@
 #define PASID_VAL_SHIFT     12
 #define PASID_LEN_SHIFT     7
 #define PASID_LEN_MASK      0x7ul
+#define PASID_EN_SHIFT      6
 #define DMA_TO_DEVICE_MASK  0xFFFFFFEF
 
 /* shift_bit */
@@ -85,7 +89,13 @@
 #define PCIE_CAP_DIS_MASK 0xFFFEFFFF
 #define PCIE_CAP_EN_MASK (1 << 16)
 #define PASID_EN_MASK    (1 << 6)
-
+#define RID_CTL_REG    0x3C
+#define RID_VALUE_MASK 0xFFFF
+#define RID_VALID_MASK (1ul << 31)
+#define RID_VALID      1
+#define RID_NOT_VALID  0
+#define ATS_TRIGGER    1
+#define ATS_STATUS     (1ul << 7)
 
 typedef enum {
     TYPE0 = 0x0,
@@ -106,21 +116,22 @@ typedef enum {
 } EXERCISER_DMA_ATTR;
 
 typedef enum {
-    SNOOP_ATTRIBUTES = 0x1,
-    LEGACY_IRQ       = 0x2,
-    MSIX_ATTRIBUTES  = 0x3,
-    DMA_ATTRIBUTES   = 0x4,
-    P2P_ATTRIBUTES   = 0x5,
-    PASID_ATTRIBUTES = 0x6,
+    SNOOP_ATTRIBUTES   = 0x1,
+    LEGACY_IRQ         = 0x2,
+    MSIX_ATTRIBUTES    = 0x3,
+    DMA_ATTRIBUTES     = 0x4,
+    P2P_ATTRIBUTES     = 0x5,
+    PASID_ATTRIBUTES   = 0x6,
     CFG_TXN_ATTRIBUTES = 0x7,
     ATS_RES_ATTRIBUTES = 0x8,
-    TRANSACTION_TYPE  = 0x9,
-    NUM_TRANSACTIONS  = 0xA
+    TRANSACTION_TYPE   = 0x9,
+    NUM_TRANSACTIONS   = 0xA
 } EXERCISER_PARAM_TYPE;
 
 typedef enum {
-    TXN_REQ_ID     = 0x0,
-    TXN_ADDR_TYPE  = 0x1,
+    TXN_REQ_ID       = 0x0,
+    TXN_ADDR_TYPE    = 0x1,
+    TXN_REQ_ID_VALID = 0x2,
 } EXERCISER_TXN_ATTR;
 
 typedef enum {
diff --git a/platform/pal_uefi_dt/include/pal_uefi.h b/platform/pal_uefi_dt/include/pal_uefi.h
index 07b66b19..c72cfd68 100644
--- a/platform/pal_uefi_dt/include/pal_uefi.h
+++ b/platform/pal_uefi_dt/include/pal_uefi.h
@@ -319,6 +319,7 @@ typedef struct {
   UINT32         max_pasids;
   UINT32         baud_rate;
   UINT32         interface_type;
+  UINT32         platform_type;
 }PERIPHERAL_INFO_BLOCK;
 
 /**
@@ -329,6 +330,9 @@ typedef struct {
   PERIPHERAL_INFO_BLOCK   info[]; ///< Array of Information blocks - instantiated for each peripheral
 }PERIPHERAL_INFO_TABLE;
 
+#define PLATFORM_TYPE_ACPI   0x0
+#define PLATFORM_TYPE_DT     0x1
+
 /**
   @brief MSI(X) controllers info structure
 **/
diff --git a/platform/pal_uefi_dt/src/pal_acpi.c b/platform/pal_uefi_dt/src/pal_acpi.c
index 92048aaf..e8dadc20 100644
--- a/platform/pal_uefi_dt/src/pal_acpi.c
+++ b/platform/pal_uefi_dt/src/pal_acpi.c
@@ -75,7 +75,7 @@ pal_get_madt_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_DEBUG, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_INFO, L" XSDT not found \n");
       return 0;
   }
 
@@ -109,7 +109,7 @@ pal_get_gtdt_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_DEBUG, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_INFO, L" XSDT not found \n");
       return 0;
   }
 
@@ -142,7 +142,7 @@ pal_get_mcfg_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_DEBUG, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_INFO, L" XSDT not found \n");
       return 0;
   }
 
@@ -175,7 +175,6 @@ pal_get_spcr_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_DEBUG, L"XSDT not found \n");
       return 0;
   }
 
@@ -208,7 +207,7 @@ pal_get_iort_ptr()
 
   Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
   if (Xsdt == NULL) {
-      bsa_print(ACS_PRINT_DEBUG, L"XSDT not found \n");
+      bsa_print(ACS_PRINT_INFO, L" XSDT not found \n");
       return 0;
   }
 
diff --git a/platform/pal_uefi_dt/src/pal_dt.c b/platform/pal_uefi_dt/src/pal_dt.c
index e06d5f95..8dc0c2dd 100644
--- a/platform/pal_uefi_dt/src/pal_dt.c
+++ b/platform/pal_uefi_dt/src/pal_dt.c
@@ -61,7 +61,7 @@ pal_get_dt_ptr()
   for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {
     if (CompareGuid (&gFdtTableGuid, &(gST->ConfigurationTable[Index].VendorGuid))) {
       DTB = gST->ConfigurationTable[Index].VendorTable;
-      bsa_print(ACS_PRINT_DEBUG, L" Platform DTB PTR %x \n", DTB);
+      bsa_print(ACS_PRINT_DEBUG, L"  Platform DTB PTR %x \n", DTB);
       break;
     }
   }
@@ -72,7 +72,7 @@ pal_get_dt_ptr()
   }
 
   if (fdt_check_header(DTB)) {
-    bsa_print(ACS_PRINT_ERR, L"fdt hdr check failed \n");
+    bsa_print(ACS_PRINT_ERR, L" fdt hdr check failed \n");
     return 0;
   }
 
@@ -131,7 +131,7 @@ int fdt_interrupt_cells(const void *fdt, int nodeoffset)
   } while (nodeoffset >= 0);
 
   if (nodeoffset < 0) {
-      bsa_print(ACS_PRINT_DEBUG, L"No interrupt cell found \n");
+      bsa_print(ACS_PRINT_DEBUG, L"  No interrupt cell found \n");
       return 3; /* default value 3*/
   }
 
@@ -185,11 +185,11 @@ pal_dump_dtb()
 
     BufferSize = fdt_totalsize(dtb);
     if (!BufferSize) {
-        bsa_print(ACS_PRINT_ERR, L"dtb size 0\n");
+        bsa_print(ACS_PRINT_ERR, L" dtb size 0\n");
         return;
     }
     Status = ShellWriteFile(g_dtb_log_file_handle, &BufferSize, (VOID *)dtb);
     if (EFI_ERROR(Status))
-      bsa_print(ACS_PRINT_ERR, L"Error in writing to dtb log file\n");
+      bsa_print(ACS_PRINT_ERR, L" Error in writing to dtb log file\n");
   }
 }
diff --git a/platform/pal_uefi_dt/src/pal_dt_debug.c b/platform/pal_uefi_dt/src/pal_dt_debug.c
index 2e190710..d5615f63 100644
--- a/platform/pal_uefi_dt/src/pal_dt_debug.c
+++ b/platform/pal_uefi_dt/src/pal_dt_debug.c
@@ -37,17 +37,17 @@ dt_dump_pe_table(PE_INFO_TABLE *PeTable)
     return;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************PE TABLE DUMP************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************PE TABLE DUMP************ \n");
   bsa_print(ACS_PRINT_DEBUG, L" NUM PE %d \n", PeTable->header.num_of_pe);
 
   while (Index < PeTable->header.num_of_pe) {
     bsa_print(ACS_PRINT_DEBUG, L" PE NUM      :%x\n", PeTable->pe_info[Index].pe_num);
-    bsa_print(ACS_PRINT_DEBUG, L"    MPIDR    :%x\n", PeTable->pe_info[Index].mpidr);
+    bsa_print(ACS_PRINT_DEBUG, L" MPIDR       :%x\n", PeTable->pe_info[Index].mpidr);
 //    bsa_print(ACS_PRINT_DEBUG, L"    ATTR     :%x\n", PeTable->pe_info[Index].attr);
-    bsa_print(ACS_PRINT_DEBUG, L"    PMU GSIV :%x\n", PeTable->pe_info[Index].pmu_gsiv);
+    bsa_print(ACS_PRINT_DEBUG, L" PMU GSIV    :%x\n", PeTable->pe_info[Index].pmu_gsiv);
     Index++;
   }
-  bsa_print(ACS_PRINT_DEBUG, L"************************************* \n\n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************************************* \n");
 }
 
 /**
@@ -67,7 +67,7 @@ dt_dump_gic_table(GIC_INFO_TABLE *GicTable)
     return;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************GIC TABLE************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************GIC TABLE************ \n");
   bsa_print(ACS_PRINT_DEBUG, L" GIC version %d \n", GicTable->header.gic_version);
   bsa_print(ACS_PRINT_DEBUG, L" GIC num D %d \n", GicTable->header.num_gicd);
   bsa_print(ACS_PRINT_DEBUG, L" GIC num RD %d \n", GicTable->header.num_gicrd);
@@ -75,12 +75,12 @@ dt_dump_gic_table(GIC_INFO_TABLE *GicTable)
 
   while (GicTable->gic_info[Index].type != 0xFF) {
     bsa_print(ACS_PRINT_DEBUG, L" GIC TYPE     :%x\n", GicTable->gic_info[Index].type);
-    bsa_print(ACS_PRINT_DEBUG, L"     BASE     :%x\n", GicTable->gic_info[Index].base);
-    bsa_print(ACS_PRINT_DEBUG, L"     LEN      :%x\n", GicTable->gic_info[Index].length);
+    bsa_print(ACS_PRINT_DEBUG, L" BASE         :%x\n", GicTable->gic_info[Index].base);
+    bsa_print(ACS_PRINT_DEBUG, L" LEN          :%x\n", GicTable->gic_info[Index].length);
 //    bsa_print(ACS_PRINT_DEBUG, L"     ITS ID   :%x\n", GicTable->gic_info[Index].entry_id);
     Index++;
   }
-  bsa_print(ACS_PRINT_DEBUG, L"************************************* \n\n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************************************* \n");
 }
 
 /**
@@ -100,17 +100,17 @@ dt_dump_wd_table(WD_INFO_TABLE *WdTable)
     return;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************WD TABLE************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************WD TABLE************ \n");
   bsa_print(ACS_PRINT_DEBUG, L" NUM WD %d \n", WdTable->header.num_wd);
 
   while (Index < WdTable->header.num_wd) {
-    bsa_print(ACS_PRINT_DEBUG, L" WD REFRESH BASE  :%x\n", WdTable->wd_info[Index].wd_refresh_base);
-    bsa_print(ACS_PRINT_DEBUG, L"    CONTROL BASE  :%x\n", WdTable->wd_info[Index].wd_ctrl_base);
-    bsa_print(ACS_PRINT_DEBUG, L"    GSIV          :%x\n", WdTable->wd_info[Index].wd_gsiv);
-    bsa_print(ACS_PRINT_DEBUG, L"    FLAGS         :%x\n", WdTable->wd_info[Index].wd_flags);
+    bsa_print(ACS_PRINT_DEBUG, L" REFRESH BASE  :%x\n", WdTable->wd_info[Index].wd_refresh_base);
+    bsa_print(ACS_PRINT_DEBUG, L" CONTROL BASE  :%x\n", WdTable->wd_info[Index].wd_ctrl_base);
+    bsa_print(ACS_PRINT_DEBUG, L" GSIV          :%x\n", WdTable->wd_info[Index].wd_gsiv);
+    bsa_print(ACS_PRINT_DEBUG, L" FLAGS         :%x\n", WdTable->wd_info[Index].wd_flags);
     Index++;
   }
-  bsa_print(ACS_PRINT_DEBUG, L"************************************* \n\n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************************************* \n");
 }
 
 /**
@@ -131,17 +131,17 @@ dt_dump_pcie_table(PCIE_INFO_TABLE *PcieTable)
     return;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************PCIE TABLE************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************PCIE TABLE************ \n");
   bsa_print(ACS_PRINT_DEBUG, L" NUM ECAM %d \n", PcieTable->num_entries);
 
   while (Index < PcieTable->num_entries) {
     bsa_print(ACS_PRINT_DEBUG, L" ECAM BASE          :%x\n", PcieTable->block[Index].ecam_base);
-    bsa_print(ACS_PRINT_DEBUG, L"      START BUS     :%x\n", PcieTable->block[Index].start_bus_num);
-    bsa_print(ACS_PRINT_DEBUG, L"      END BUS       :%x\n", PcieTable->block[Index].end_bus_num);
+    bsa_print(ACS_PRINT_DEBUG, L" START BUS          :%x\n", PcieTable->block[Index].start_bus_num);
+    bsa_print(ACS_PRINT_DEBUG, L" END BUS            :%x\n", PcieTable->block[Index].end_bus_num);
 //    bsa_print(ACS_PRINT_DEBUG, L"      SEGMENT NUM   :%x\n", PcieTable->block[Index].segment_num);
     Index++;
   }
-  bsa_print(ACS_PRINT_DEBUG, L"************************************* \n\n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************************************* \n");
 }
 
 /**
@@ -161,19 +161,19 @@ dt_dump_memory_table(MEMORY_INFO_TABLE *memoryInfoTable)
     return;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************MEMORY TABLE************ \n");
-  bsa_print(ACS_PRINT_DEBUG, L" MEMORY dram base  :%x\n", memoryInfoTable->dram_base);
-  bsa_print(ACS_PRINT_DEBUG, L"        dram size  :%x\n", memoryInfoTable->dram_size);
+  bsa_print(ACS_PRINT_DEBUG, L" ************MEMORY TABLE************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" dram base  :%x\n", memoryInfoTable->dram_base);
+  bsa_print(ACS_PRINT_DEBUG, L" dram size  :%x\n", memoryInfoTable->dram_size);
 
   while (memoryInfoTable->info[Index].type < 0x1004) {
-    bsa_print(ACS_PRINT_DEBUG, L" MEMORY Type      :%x\n", memoryInfoTable->info[Index].type);
-    bsa_print(ACS_PRINT_DEBUG, L"        PHY addr  :%x\n", memoryInfoTable->info[Index].phy_addr);
-    bsa_print(ACS_PRINT_DEBUG, L"        VIRT addr :%x\n", memoryInfoTable->info[Index].virt_addr);
-    bsa_print(ACS_PRINT_DEBUG, L"        size      :%x\n", memoryInfoTable->info[Index].size);
-    bsa_print(ACS_PRINT_DEBUG, L"        flags     :%x\n", memoryInfoTable->info[Index].flags);
+    bsa_print(ACS_PRINT_DEBUG, L" Type      :%x\n", memoryInfoTable->info[Index].type);
+    bsa_print(ACS_PRINT_DEBUG, L" PHY addr  :%x\n", memoryInfoTable->info[Index].phy_addr);
+    bsa_print(ACS_PRINT_DEBUG, L" VIRT addr :%x\n", memoryInfoTable->info[Index].virt_addr);
+    bsa_print(ACS_PRINT_DEBUG, L" size      :%x\n", memoryInfoTable->info[Index].size);
+    bsa_print(ACS_PRINT_DEBUG, L" flags     :%x\n", memoryInfoTable->info[Index].flags);
     Index++;
   }
-  bsa_print(ACS_PRINT_DEBUG, L"************************************* \n\n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************************************* \n");
 }
 
 /**
@@ -193,7 +193,7 @@ dt_dump_timer_table(TIMER_INFO_TABLE *TimerTable)
     return;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************TIMER TABLE************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************TIMER TABLE************ \n");
   bsa_print(ACS_PRINT_DEBUG, L" Num of system timers %d \n", TimerTable->header.num_platform_timer);
   bsa_print(ACS_PRINT_DEBUG, L" s_el1_timer_flag %x \n", TimerTable->header.s_el1_timer_flag);
   bsa_print(ACS_PRINT_DEBUG, L" ns_el1_timer_flag %x \n", TimerTable->header.ns_el1_timer_flag);
@@ -208,15 +208,15 @@ dt_dump_timer_table(TIMER_INFO_TABLE *TimerTable)
   bsa_print(ACS_PRINT_DEBUG, L" CNTBase             %x\n", TimerTable->gt_info->block_cntl_base);
 
   while (Index < TimerTable->gt_info->timer_count) {
-    bsa_print(ACS_PRINT_DEBUG, L" TIMER Frame num :%x\n", TimerTable->gt_info->frame_num[Index]);
-    bsa_print(ACS_PRINT_DEBUG, L"     GtCntBase   :%x\n", TimerTable->gt_info->GtCntBase[Index]);
-    bsa_print(ACS_PRINT_DEBUG, L"     GtCntEl0Base:%x\n", TimerTable->gt_info->GtCntEl0Base[Index]);
-    bsa_print(ACS_PRINT_DEBUG, L"       gsiv      :%x\n", TimerTable->gt_info->gsiv[Index]);
-    bsa_print(ACS_PRINT_DEBUG, L"       virt_gsiv :%x\n", TimerTable->gt_info->virt_gsiv[Index]);
-    bsa_print(ACS_PRINT_DEBUG, L"       flags     :%x\n", TimerTable->gt_info->flags[Index]);
+    bsa_print(ACS_PRINT_DEBUG, L" Frame num   :%x\n", TimerTable->gt_info->frame_num[Index]);
+    bsa_print(ACS_PRINT_DEBUG, L" GtCntBase   :%x\n", TimerTable->gt_info->GtCntBase[Index]);
+    bsa_print(ACS_PRINT_DEBUG, L" GtCntEl0Base:%x\n", TimerTable->gt_info->GtCntEl0Base[Index]);
+    bsa_print(ACS_PRINT_DEBUG, L" gsiv        :%x\n", TimerTable->gt_info->gsiv[Index]);
+    bsa_print(ACS_PRINT_DEBUG, L" virt_gsiv   :%x\n", TimerTable->gt_info->virt_gsiv[Index]);
+    bsa_print(ACS_PRINT_DEBUG, L" flags       :%x\n", TimerTable->gt_info->flags[Index]);
     Index++;
   }
-  bsa_print(ACS_PRINT_DEBUG, L"************************************* \n\n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************************************* \n");
 }
 
 /**
@@ -236,40 +236,40 @@ dt_dump_peripheral_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
     return;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************USB TABLE************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************USB TABLE************ \n");
   bsa_print(ACS_PRINT_DEBUG, L" NUM USB %d \n", peripheralInfoTable->header.num_usb);
 
   while (Index < peripheralInfoTable->header.num_usb) {
-    bsa_print(ACS_PRINT_DEBUG, L"    TYPE          :%x\n", peripheralInfoTable->info[Index].type);
-    bsa_print(ACS_PRINT_DEBUG, L"    CONTROL BASE  :%x\n", peripheralInfoTable->info[Index].base0);
-    bsa_print(ACS_PRINT_DEBUG, L"    GSIV          :%d\n", peripheralInfoTable->info[Index].irq);
-    bsa_print(ACS_PRINT_DEBUG, L"    FLAGS         :%x\n", peripheralInfoTable->info[Index].flags);
-    bsa_print(ACS_PRINT_DEBUG, L"    BDF           :%x\n", peripheralInfoTable->info[Index].bdf);
+    bsa_print(ACS_PRINT_DEBUG, L" TYPE          :%x\n", peripheralInfoTable->info[Index].type);
+    bsa_print(ACS_PRINT_DEBUG, L" CONTROL BASE  :%x\n", peripheralInfoTable->info[Index].base0);
+    bsa_print(ACS_PRINT_DEBUG, L" GSIV          :%d\n", peripheralInfoTable->info[Index].irq);
+    bsa_print(ACS_PRINT_DEBUG, L" FLAGS         :%x\n", peripheralInfoTable->info[Index].flags);
+    bsa_print(ACS_PRINT_DEBUG, L" BDF           :%x\n", peripheralInfoTable->info[Index].bdf);
     Index++;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************SATA TABLE************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************SATA TABLE************ \n");
   bsa_print(ACS_PRINT_DEBUG, L" NUM SATA %d \n", peripheralInfoTable->header.num_sata);
 
   while (Index < (peripheralInfoTable->header.num_sata + peripheralInfoTable->header.num_usb)) {
-    bsa_print(ACS_PRINT_DEBUG, L"    TYPE          :%x\n", peripheralInfoTable->info[Index].type);
-    bsa_print(ACS_PRINT_DEBUG, L"    CONTROL BASE  :%x\n", peripheralInfoTable->info[Index].base0);
-    bsa_print(ACS_PRINT_DEBUG, L"    GSIV          :%d\n", peripheralInfoTable->info[Index].irq);
-    bsa_print(ACS_PRINT_DEBUG, L"    FLAGS         :%x\n", peripheralInfoTable->info[Index].flags);
-    bsa_print(ACS_PRINT_DEBUG, L"    BDF           :%x\n", peripheralInfoTable->info[Index].bdf);
+    bsa_print(ACS_PRINT_DEBUG, L" TYPE          :%x\n", peripheralInfoTable->info[Index].type);
+    bsa_print(ACS_PRINT_DEBUG, L" CONTROL BASE  :%x\n", peripheralInfoTable->info[Index].base0);
+    bsa_print(ACS_PRINT_DEBUG, L" GSIV          :%d\n", peripheralInfoTable->info[Index].irq);
+    bsa_print(ACS_PRINT_DEBUG, L" FLAGS         :%x\n", peripheralInfoTable->info[Index].flags);
+    bsa_print(ACS_PRINT_DEBUG, L" BDF           :%x\n", peripheralInfoTable->info[Index].bdf);
     Index++;
   }
 
-  bsa_print(ACS_PRINT_DEBUG, L"************UART TABLE************ \n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************UART TABLE************ \n");
   bsa_print(ACS_PRINT_DEBUG, L" NUM UART %d \n", peripheralInfoTable->header.num_uart);
 
   while (Index < (peripheralInfoTable->header.num_sata + peripheralInfoTable->header.num_usb +
       peripheralInfoTable->header.num_uart)) {
-    bsa_print(ACS_PRINT_DEBUG, L"    TYPE          :%x\n", peripheralInfoTable->info[Index].type);
-    bsa_print(ACS_PRINT_DEBUG, L"    CONTROL BASE  :%x\n", peripheralInfoTable->info[Index].base0);
-    bsa_print(ACS_PRINT_DEBUG, L"    GSIV          :%d\n", peripheralInfoTable->info[Index].irq);
-    bsa_print(ACS_PRINT_DEBUG, L"    FLAGS         :%x\n", peripheralInfoTable->info[Index].flags);
+    bsa_print(ACS_PRINT_DEBUG, L" TYPE          :%x\n", peripheralInfoTable->info[Index].type);
+    bsa_print(ACS_PRINT_DEBUG, L" CONTROL BASE  :%x\n", peripheralInfoTable->info[Index].base0);
+    bsa_print(ACS_PRINT_DEBUG, L" GSIV          :%d\n", peripheralInfoTable->info[Index].irq);
+    bsa_print(ACS_PRINT_DEBUG, L" FLAGS         :%x\n", peripheralInfoTable->info[Index].flags);
     Index++;
   }
-  bsa_print(ACS_PRINT_DEBUG, L"************************************* \n\n");
+  bsa_print(ACS_PRINT_DEBUG, L" ************************************* \n");
 }
diff --git a/platform/pal_uefi_dt/src/pal_exerciser.c b/platform/pal_uefi_dt/src/pal_exerciser.c
index f306a95a..70b792e7 100644
--- a/platform/pal_uefi_dt/src/pal_exerciser.c
+++ b/platform/pal_uefi_dt/src/pal_exerciser.c
@@ -42,6 +42,10 @@ pal_pcie_get_mcfg_ecam();
 
 /**
   @brief This API increments the BDF
+
+  @param Bdf Stimulus hardware bdf number
+
+  @return incremented bdf number
 **/
 UINT32
 pal_increment_bus_dev(
@@ -67,7 +71,12 @@ pal_increment_bus_dev(
 }
 
 /**
-  @brief This API will return the ECSR base address of particular BAR Index
+  @brief This API returns the ECSR base address of particular BAR Index
+
+  @param EcsrBase Exerciser Base address
+  @param BarIndex input BAR index
+
+  @return ECSR base address of required BAR Index
 **/
 UINT64
 pal_exerciser_get_ecsr_base (
@@ -78,6 +87,13 @@ pal_exerciser_get_ecsr_base (
   return pal_mmio_read(EcsrBase + BAR0_OFFSET + (BarIndex * 4));
 }
 
+/**
+  @brief This API returns PCI config offset address for input BDF
+
+  @param Bdf BDF value for the device
+
+  @return PCI config offset address
+**/
 UINT64
 pal_exerciser_get_pcie_config_offset(UINT32 Bdf)
 {
@@ -93,6 +109,13 @@ pal_exerciser_get_pcie_config_offset(UINT32 Bdf)
   return cfg_addr;
 }
 
+/**
+  @brief This API checks whether a device specified by BDF is an exerciser or not
+
+  @param bdf BDF value for the device
+
+  @return 1 if device is an exerciser ; 0 if device is not a exerciser
+**/
 UINT32
 pal_is_bdf_exerciser(UINT32 bdf)
 {
@@ -109,6 +132,11 @@ pal_is_bdf_exerciser(UINT32 bdf)
 
 /**
   @brief This function triggers the DMA operation
+
+  @param Base DMA Base address
+  @param Direction Specify DMA direction
+
+  @return status of the DMA
 **/
 UINT32
 pal_exerciser_start_dma_direction (
@@ -139,6 +167,13 @@ pal_exerciser_start_dma_direction (
 
 /**
   @brief This function finds the PCI capability and return 0 if it finds.
+
+  @param ID    PCI capability IF 
+  @param Bdf   BDF value for the device
+  @param Value 1 PCIE capability 0 PCI capability
+  @param Offset capability offset
+
+  @return 0 if PCI capability found ; 1 if PCI capability found
 **/
 UINT32
 pal_exerciser_find_pcie_capability (
@@ -189,7 +224,8 @@ pal_exerciser_find_pcie_capability (
   @param   Type         - Parameter type that needs to be set in the stimulus hadrware
   @param   Value1       - Parameter 1 that needs to be set
   @param   Value2       - Parameter 2 that needs to be set
-  @param   Instance     - Stimulus hardware instance number
+  @param   Bdf          - Stimulus hardware bdf number
+  @param   Ecam         - Ecam base for exerciser under test
   @return  Status       - SUCCESS if the input paramter type is successfully written
 **/
 UINT32 pal_exerciser_set_param (
@@ -200,7 +236,6 @@ UINT32 pal_exerciser_set_param (
   UINT64 Ecam
   )
 {
-  UINT32 Status;
   UINT32 Data;
   UINT64 Base;
   UINT64 EcsrBase; /* Exerciser Base */
@@ -219,9 +254,7 @@ UINT32 pal_exerciser_set_param (
       case DMA_ATTRIBUTES:
           pal_mmio_write(Base + DMA_BUS_ADDR,Value1);// wrting into the DMA Control Register 2
           pal_mmio_write(Base + DMA_LEN,Value2);// writing into the DMA Control Register 3
-          Data = pal_mmio_read(Base + DMASTATUS);// Reading the DMA status register
-          Status = Data & ((MASK_BIT << 1) | MASK_BIT);
-          return Status;
+          return 0;
 
       case P2P_ATTRIBUTES:
           return 0;
@@ -241,9 +274,38 @@ UINT32 pal_exerciser_set_param (
 
             case TXN_REQ_ID:
                 /* Change Requester ID for DMA Transaction.*/
+                Data = (Value2 & RID_VALUE_MASK) | RID_VALID_MASK;
+                pal_mmio_write(Base + RID_CTL_REG, Data);
                 return 0;
+            case TXN_REQ_ID_VALID:
+                switch (Value2)
+                {
+                    case RID_VALID:
+                        Data = pal_mmio_read(Base + RID_CTL_REG);
+                        Data |= RID_VALID_MASK;
+                        pal_mmio_write(Base + RID_CTL_REG, Data);
+                        return 0;
+                    case RID_NOT_VALID:
+                        pal_mmio_write(Base + RID_CTL_REG, 0);
+                        return 0;
+                }
             case TXN_ADDR_TYPE:
                 /* Change Address Type for DMA Transaction.*/
+                switch (Value2)
+                {
+                    case AT_UNTRANSLATED:
+                        Data = 0x1;
+                        pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10));
+                        break;
+                    case AT_TRANSLATED:
+                        Data = 0x2;
+                        pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10));
+                        break;
+                    case AT_RESERVED:
+                        Data = 0x3;
+                        pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10));
+                        break;
+                }
                 return 0;
             default:
                 return 1;
@@ -259,7 +321,8 @@ UINT32 pal_exerciser_set_param (
   @param   Type         - Parameter type that needs to be read from the stimulus hadrware
   @param   Value1       - Parameter 1 that is read from hardware
   @param   Value2       - Parameter 2 that is read from hardware
-  @param   Instance     - Stimulus hardware instance number
+  @param   Bdf          - Stimulus hardware bdf number
+  @param   Ecam         - Ecam base for exerciser under test
   @return  Status       - SUCCESS if the requested paramter type is successfully read
 **/
 UINT32
@@ -300,6 +363,9 @@ pal_exerciser_get_param (
       case MSIX_ATTRIBUTES:
           *Value1 = pal_mmio_read(Base + MSICTL);
           return pal_mmio_read(Base + MSICTL) | MASK_BIT;
+      case ATS_RES_ATTRIBUTES:
+          *Value1 = pal_mmio_read(Base + ATS_ADDR);
+          return 0;
       default:
           return 1;
   }
@@ -340,9 +406,10 @@ pal_exerciser_get_state (
 
 /**
   @brief   This API performs the input operation using the PCIe stimulus generation hardware
-  @param   Ops          - Operation thta needs to be performed with the stimulus hadrware
-  @param   Value        - Additional information to perform the operation
-  @param   Instance     - Stimulus hardware instance number
+  @param   Ops          - Operation that needs to be performed with the stimulus hadrware
+  @param   Param        - Additional information to perform the operation
+  @param   Bdf          - Stimulus hardware bdf number
+  @param   Ecam         - Ecam base for exerciser under test
   @return  Status       - SUCCESS if the operation is successfully performed using the hardware
 **/
 UINT32
@@ -401,9 +468,10 @@ pal_exerciser_ops (
 
     case PASID_TLP_START:
         data = pal_mmio_read(Base + DMACTL1);
-        data &= ~(PASID_VAL_MASK << PASID_VAL_SHIFT);
-        data |= (MASK_BIT << 6) | ((Param & PASID_VAL_MASK) << PASID_VAL_SHIFT);
+        data |= (MASK_BIT << PASID_EN_SHIFT);
         pal_mmio_write(Base + DMACTL1, data);
+        data = ((Param & PASID_VAL_MASK));
+        pal_mmio_write(Base + PASID_VAL, data);
 
         if (!pal_exerciser_find_pcie_capability(PASID, Bdf, PCIE, &CapabilityOffset)) {
             pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET,
@@ -430,6 +498,11 @@ pal_exerciser_ops (
         pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1)) & NO_SNOOP_STOP_MASK);//disabling the NO SNOOP
         return 0;
 
+    case ATS_TXN_REQ:
+        pal_mmio_write(Base + DMA_BUS_ADDR, Param);
+        pal_mmio_write(Base + ATSCTL, ATS_TRIGGER);
+        return !(pal_mmio_read(Base + ATSCTL) & ATS_STATUS);
+
     default:
         return 1;
   }
@@ -437,9 +510,10 @@ pal_exerciser_ops (
 
 /**
   @brief   This API returns test specific data from the PCIe stimulus generation hardware
-  @param   type         - data type for which the data needs to be returned
-  @param   data         - test specific data to be be filled by pal layer
-  @param   instance     - Stimulus hardware instance number
+  @param   Type         - data type for which the data needs to be returned
+  @param   Data         - test specific data to be be filled by pal layer
+  @param   Bdf          - Stimulus hardware bdf number
+  @param   Ecam         - Ecam base for exerciser under test
   @return  status       - SUCCESS if the requested data is successfully filled
 **/
 UINT32
@@ -467,8 +541,7 @@ pal_exerciser_get_data (
           for (Index = 0; Index < TEST_REG_COUNT; Index++) {
               Data->cfg_space.reg[Index].offset = (offset_table[Index] + pal_exerciser_get_pcie_config_offset (Bdf));
               Data->cfg_space.reg[Index].attribute = attr_table[Index];
-              Data->cfg_space.reg[Index].value =
-                                pal_mmio_read(EcsrBase +  offset_table[Index]);
+              Data->cfg_space.reg[Index].value = pal_mmio_read(EcsrBase + offset_table[Index]);
           }
           return 0;
       case EXERCISER_DATA_BAR0_SPACE:
diff --git a/platform/pal_uefi_dt/src/pal_gic.c b/platform/pal_uefi_dt/src/pal_gic.c
index 243d72ba..d5d40837 100644
--- a/platform/pal_uefi_dt/src/pal_gic.c
+++ b/platform/pal_uefi_dt/src/pal_gic.c
@@ -94,11 +94,11 @@ pal_pe_info_table_gmaint_gsiv_dt(PE_INFO_TABLE *PeTable)
       /* Search for GICv3 nodes*/
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, gicv3_dt_arr[i]);
       if (offset < 0) {
-        bsa_print(ACS_PRINT_DEBUG, L" GICv3 compatible value not found for index : %d\n", i);
+        bsa_print(ACS_PRINT_DEBUG, L"  GICv3 compatible value not found for index : %d\n", i);
         continue; /* Search for next compatible item*/
       }
       else {
-        bsa_print(ACS_PRINT_DEBUG, L" NODE Int Ctrl offset  %x  \n", offset);
+        bsa_print(ACS_PRINT_DEBUG, L"  GIC_V3: NODE Int Ctrl offset  %x  \n", offset);
         break;
       }
   }
@@ -108,32 +108,33 @@ pal_pe_info_table_gmaint_gsiv_dt(PE_INFO_TABLE *PeTable)
           /* Search for GICv2 nodes*/
           offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, gicv2_dt_arr[i]);
           if (offset < 0) {
-              bsa_print(ACS_PRINT_DEBUG, L" GICv2 compatible value not found for index : %d\n", i);
+              bsa_print(ACS_PRINT_DEBUG, L"  GICv2 compatible value not found for index : %d\n", i);
               continue; /* Search for next compatible item*/
           }
           else {
-            bsa_print(ACS_PRINT_DEBUG, L" NODE Int Ctrl offset  %x  \n", offset);
+            bsa_print(ACS_PRINT_DEBUG, L"  GIC_V2: NODE Int Ctrl offset  %x  \n", offset);
             break;
           }
       }
   }
 
   if (offset < 0) {
-      bsa_print(ACS_PRINT_DEBUG, L"GIC compatible node not found\n");
+      bsa_print(ACS_PRINT_DEBUG, L"  GIC compatible node not found\n");
       return;
   }
 
   /* read the interrupt property value */
   Pintr = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "interrupts", 10, &prop_len);
   if ((prop_len < 0) || (Pintr == NULL)) {
-      bsa_print(ACS_PRINT_ERR, L" PROPERTY interrupts offset %x, Error %d\n", offset, prop_len);
+      bsa_print(ACS_PRINT_DEBUG, L"  PROPERTY interrupts read Error %d\n",
+                    prop_len);
       return;
   }
 
   interrupt_cell = fdt_interrupt_cells((const void *)dt_ptr, offset);
-  bsa_print(ACS_PRINT_DEBUG, L" interrupt_cell  %d\n", interrupt_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  interrupt_cell  %d\n", interrupt_cell);
   if (interrupt_cell < INTERRUPT_CELLS_MIN || interrupt_cell > INTERRUPT_CELLS_MAX) {
-      bsa_print(ACS_PRINT_ERR, L" Invalid interrupt cell : %d \n", interrupt_cell);
+      bsa_print(ACS_PRINT_ERR, L"  Invalid interrupt cell : %d \n", interrupt_cell);
       return;
   }
 
@@ -142,7 +143,7 @@ pal_pe_info_table_gmaint_gsiv_dt(PE_INFO_TABLE *PeTable)
           if (Pintr[0])
               Ptr->gmain_gsiv = fdt32_to_cpu(Pintr[1]) + PPI_OFFSET;
           else
-              bsa_print(ACS_PRINT_WARN, L" Int is not PPI \n", 0);
+              bsa_print(ACS_PRINT_WARN, L"  Int is not PPI \n", 0);
       }
       else
           Ptr->gmain_gsiv = fdt32_to_cpu(Pintr[0]) + PPI_OFFSET;
@@ -178,16 +179,15 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
   GicTable->header.num_its = 0;
   GicTable->header.num_msi_frame = 0;
 
+  pal_gic_create_info_table_dt(GicTable);
+  dt_dump_gic_table(GicTable);
+  return;
+
   gMadtHdr = (EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *) pal_get_madt_ptr();
 
   if (gMadtHdr != NULL) {
     TableLength =  gMadtHdr->Header.Length;
-    bsa_print(ACS_PRINT_INFO, L" MADT is at %x and length is %x \n", gMadtHdr, TableLength);
-  } else {
-    bsa_print(ACS_PRINT_DEBUG, L" MADT not found. Checking DT table \n");
-    pal_gic_create_info_table_dt(GicTable);
-    dt_dump_gic_table(GicTable);
-    return;
+    bsa_print(ACS_PRINT_INFO, L"  MADT is at %x and length is %x \n", gMadtHdr, TableLength);
   }
 
   Entry = (EFI_ACPI_6_1_GIC_STRUCTURE *) (gMadtHdr + 1);
@@ -200,7 +200,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
       if (Entry->PhysicalBaseAddress != 0) {
         GicEntry->type = ENTRY_TYPE_CPUIF;
         GicEntry->base = Entry->PhysicalBaseAddress;
-        bsa_print(ACS_PRINT_INFO, L" GIC CPUIF base %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC CPUIF base %x \n", GicEntry->base);
         GicEntry++;
       }
 
@@ -208,7 +208,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICC_GICRD;
         GicEntry->base = Entry->GICRBaseAddress;
         GicEntry->length = 0;
-        bsa_print(ACS_PRINT_INFO, L" GIC RD base %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC RD base %x \n", GicEntry->base);
         GicTable->header.num_gicrd++;
         GicEntry++;
       }
@@ -218,7 +218,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICD;
         GicEntry->base = ((EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE *)Entry)->PhysicalBaseAddress;
         GicTable->header.gic_version = ((EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE *)Entry)->GicVersion;
-        bsa_print(ACS_PRINT_INFO, L" GIC DIS base %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC DIS base %x \n", GicEntry->base);
         GicTable->header.num_gicd++;
         GicEntry++;
     }
@@ -227,7 +227,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICR_GICRD;
         GicEntry->base = ((EFI_ACPI_6_1_GICR_STRUCTURE *)Entry)->DiscoveryRangeBaseAddress;
         GicEntry->length = ((EFI_ACPI_6_1_GICR_STRUCTURE *)Entry)->DiscoveryRangeLength;
-        bsa_print(ACS_PRINT_INFO, L" GIC RD base Structure %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC RD base Structure %x \n", GicEntry->base);
         GicTable->header.num_gicrd++;
         GicEntry++;
     }
@@ -236,8 +236,8 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
         GicEntry->type = ENTRY_TYPE_GICITS;
         GicEntry->base = ((EFI_ACPI_6_1_GIC_ITS_STRUCTURE *)Entry)->PhysicalBaseAddress;
         GicEntry->entry_id = ((EFI_ACPI_6_1_GIC_ITS_STRUCTURE *)Entry)->GicItsId;
-        bsa_print(ACS_PRINT_INFO, L" GIC ITS base %x \n", GicEntry->base);
-        bsa_print(ACS_PRINT_INFO, L" GIC ITS ID%x \n", GicEntry->entry_id);
+        bsa_print(ACS_PRINT_INFO, L"  GIC ITS base %x \n", GicEntry->base);
+        bsa_print(ACS_PRINT_INFO, L"  GIC ITS ID%x \n", GicEntry->entry_id);
         GicTable->header.num_its++;
         GicEntry++;
     }
@@ -344,9 +344,15 @@ pal_gic_set_intr_trigger(UINT32 int_id, INTR_TRIGGER_INFO_TYPE_e trigger_type)
   return 0;
 }
 
-/* Place holder function. Need to be
- * implemented if needed in later releases
- */
+/** Place holder function. Need to be implemented if needed in later releases
+  @brief Registers the interrupt handler for a given IRQ
+
+  @param IrqNum Hardware IRQ number
+  @param MappedIrqNum Mapped IRQ number
+  @param Isr Interrupt Service Routine that returns the status
+
+  @return Status of the operation
+**/
 UINT32
 pal_gic_request_irq (
   UINT32 IrqNum,
@@ -357,9 +363,14 @@ pal_gic_request_irq (
     return 0;
 }
 
-/* Place holder function. Need to be
- * implemented if needed in later releases
- */
+/** Place holder function. Need to be implemented if needed in later releases
+  @brief This function frees the registered interrupt handler for a given IRQ
+
+  @param IrqNum Hardware IRQ number
+  @param MappedIrqNum Mapped IRQ number
+
+  @return none
+**/
 VOID
 pal_gic_free_irq (
   UINT32 IrqNum,
@@ -372,7 +383,7 @@ pal_gic_free_irq (
 /**
   @brief  This API fills in the GIC_INFO Table with information about the GIC in the
           system. This is achieved by parsing the DT blob.
-  @param  PeTable  - Address where the GIC information needs to be filled.
+  @param  GicTable  - Address where the GIC information needs to be filled.
   @return  None
 **/
 VOID
@@ -399,27 +410,27 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
       /* Search for GICv3 nodes*/
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, gicv3_dt_arr[i]);
       if (offset < 0) {
-        bsa_print(ACS_PRINT_DEBUG, L" GICv3 compatible value not found for index : %d\n", i);
+        bsa_print(ACS_PRINT_DEBUG, L"  GICv3 compatible value not found for index : %d\n", i);
         continue; /* Search for next compatible item*/
       }
       else {
-        bsa_print(ACS_PRINT_DEBUG, L" NODE Int Ctrl offset  %x  \n", offset);
+        bsa_print(ACS_PRINT_DEBUG, L"  NODE Int Ctrl offset  %x  \n", offset);
         GicTable->header.gic_version = 3;
         break;
       }
   }
 
   if (offset < 0) {
-      bsa_print(ACS_PRINT_DEBUG, L" GIC v3 compatible node not found\n");
+      bsa_print(ACS_PRINT_DEBUG, L"  GIC v3 compatible node not found\n");
       for (i = 0; i < (sizeof(gicv2_dt_arr)/GIC_COMPATIBLE_STR_LEN); i++) {
           /* Search for GICv2 nodes*/
           offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, gicv2_dt_arr[i]);
           if (offset < 0) {
-            bsa_print(ACS_PRINT_DEBUG, L" GICv2 compatible value not found for index : %d\n", i);
+            bsa_print(ACS_PRINT_DEBUG, L"  GICv2 compatible value not found for index : %d\n", i);
             continue; /* Search for next compatible item*/
           }
           else {
-            bsa_print(ACS_PRINT_DEBUG, L" NODE Int Ctrl offset  %x  \n", offset);
+            bsa_print(ACS_PRINT_DEBUG, L"  NODE Int Ctrl offset  %x  \n", offset);
             GicTable->header.gic_version = 2;
             break;
           }
@@ -427,7 +438,7 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
   }
 
   if (offset < 0) {
-      bsa_print(ACS_PRINT_DEBUG, L" GIC v2 compatible node not found\n");
+      bsa_print(ACS_PRINT_DEBUG, L"  GIC v2 compatible node not found\n");
       return;
   }
 
@@ -435,28 +446,28 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
   parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
 
   size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-  bsa_print(ACS_PRINT_DEBUG, L" NODE gic size cell %d\n", size_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  NODE gic size cell %d\n", size_cell);
   if (size_cell < 0) {
-      bsa_print(ACS_PRINT_ERR, L" Invalid size cell for node gic\n");
+      bsa_print(ACS_PRINT_ERR, L"  Invalid size cell for node gic\n");
       return;
   }
 
   addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-  bsa_print(ACS_PRINT_DEBUG, L" NODE gic addr cell %d\n", addr_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  NODE gic addr cell %d\n", addr_cell);
   if (addr_cell < 0) {
-      bsa_print(ACS_PRINT_ERR, L" Invalid address cell for node gic\n");
+      bsa_print(ACS_PRINT_ERR, L"  Invalid address cell for node gic\n");
       return;
   }
 
   /* read the reg property value */
   Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
   if ((prop_len < 0) || (Preg_val == NULL)) {
-      bsa_print(ACS_PRINT_ERR, L" PROPERTY reg offset %x, Error %d\n", offset, prop_len);
+      bsa_print(ACS_PRINT_ERR, L"  PROPERTY reg offset %x, Error %d\n", offset, prop_len);
       return;
   }
 
   num_gic_interfaces = (prop_len/sizeof(int))/(addr_cell + size_cell);
-  bsa_print(ACS_PRINT_DEBUG, L" Gic frame count : %d \n", num_gic_interfaces);
+  bsa_print(ACS_PRINT_DEBUG, L"  Gic frame count : %d \n", num_gic_interfaces);
 
   /* Fill details for Distributor */
   GicEntry->type = ENTRY_TYPE_GICD;
@@ -472,7 +483,7 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
   } else
     GicEntry->length = fdt32_to_cpu(Preg_val[Index++]);
 
-  bsa_print(ACS_PRINT_DEBUG, L"GIC DIS base %x \n", GicEntry->base);
+  bsa_print(ACS_PRINT_DEBUG, L"  GIC DIS base %lx \n", GicEntry->base);
   GicTable->header.num_gicd++;
   GicEntry++;
 
@@ -481,12 +492,12 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
       Prdregions_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset,
                                     "redistributor-regions", 21, &prop_len);
       if (prop_len < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" Single redistributor regions present \n");
+          bsa_print(ACS_PRINT_DEBUG, L"  Single redistributor regions present \n");
           num_of_rd = 1;
       } else
           num_of_rd = fdt32_to_cpu(Prdregions_val[0]);
 
-      bsa_print(ACS_PRINT_DEBUG, L" NUM GIC RD %d \n", num_of_rd);
+      bsa_print(ACS_PRINT_DEBUG, L"  NUM GIC RD %d \n", num_of_rd);
       i = num_of_rd;
       /* Fill details for Redistributor */
       while (i--) {
@@ -503,7 +514,7 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
           } else
               GicEntry->length = fdt32_to_cpu(Preg_val[Index++]);
 
-          bsa_print(ACS_PRINT_DEBUG, L"GIC RD base %x \n", GicEntry->base);
+          bsa_print(ACS_PRINT_DEBUG, L"  GIC RD base %lx \n", GicEntry->base);
           GicTable->header.num_gicrd++;
           GicEntry++;
     }
@@ -524,18 +535,18 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
         cpuif_length = fdt32_to_cpu(Preg_val[Index++]);
 
       num_of_pe = pal_pe_get_num();
+      bsa_print(ACS_PRINT_DEBUG, L"  GIC CPUIF base %lx \n", cpuif_base);
       while (num_of_pe--) {
-        GicEntry->type = ENTRY_TYPE_CPUIF;
-        GicEntry->base = cpuif_base;
-        GicEntry->length = cpuif_length;
-        bsa_print(ACS_PRINT_DEBUG, L"GIC CPUIF base %x \n", GicEntry->base);
-        GicEntry++;
+          GicEntry->type = ENTRY_TYPE_CPUIF;
+          GicEntry->base = cpuif_base;
+          GicEntry->length = cpuif_length;
+          GicEntry++;
       }
   } else
-    bsa_print(ACS_PRINT_WARN, L" GIC CPUIF not present\n");
+    bsa_print(ACS_PRINT_WARN, L"  GIC CPUIF not present\n");
 
   num_gic_interfaces -= (num_of_rd + 1);
-  bsa_print(ACS_PRINT_INFO, L" Number of gic interface %d\n", num_gic_interfaces);
+  bsa_print(ACS_PRINT_INFO, L"  Number of gic interface %d\n", num_gic_interfaces);
 
   if (GicTable->header.gic_version == 2) { /* parse v2m frame if present */
       /* fill details of GICH needed for gic v2 */
@@ -552,14 +563,14 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
             GicEntry->length = (GicEntry->length << 32) | fdt32_to_cpu(Preg_val[Index++]);
           } else
             GicEntry->length = fdt32_to_cpu(Preg_val[Index++]);
-          bsa_print(ACS_PRINT_DEBUG, L"GICH base %x \n", GicEntry->base);
+          bsa_print(ACS_PRINT_DEBUG, L"  GICH base %x \n", GicEntry->base);
           GicEntry++;
       }
 
       /* Search for GICv2m-frame nodes*/
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, gicv2m_frame_dt_arr[0]);
       if (offset < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" No v2m-frame present\n", 0);
+          bsa_print(ACS_PRINT_DEBUG, L"  No v2m-frame present\n", 0);
           GicEntry->type = 0xFF;
           return;
       }
@@ -568,26 +579,26 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" NODE gic size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  NODE gic size cell %d\n", size_cell);
       if (size_cell < 0) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid size cell for node gic\n");
+          bsa_print(ACS_PRINT_ERR, L"  Invalid size cell for node gic\n");
           return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" NODE gic addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  NODE gic addr cell %d\n", addr_cell);
       if (addr_cell < 0) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid address cell for node gic\n");
+          bsa_print(ACS_PRINT_ERR, L"  Invalid address cell for node gic\n");
           return;
       }
 
       while (offset != -FDT_ERR_NOTFOUND) {
-          bsa_print(ACS_PRINT_DEBUG, L" NODE v2m frame offset %x  \n", offset);
+          bsa_print(ACS_PRINT_DEBUG, L"  NODE v2m frame offset %x  \n", offset);
           Index = 0;
           /* read the reg property value */
           Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
           if ((prop_len < 0) || (Preg_val == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY reg offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY reg offset %x, Error %d\n", offset, prop_len);
               return;
           }
 
@@ -607,13 +618,13 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
           } else
              GicEntry->length = fdt32_to_cpu(Preg_val[Index++]);
 
-          bsa_print(ACS_PRINT_DEBUG, L"GIC v2m frame base %x \n", GicEntry->base);
+          bsa_print(ACS_PRINT_DEBUG, L"  GIC v2m frame base %x \n", GicEntry->base);
 
           /* read the arm,msi-base-spi property value */
           Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "arm,msi-base-spi", 16,
                                                     &prop_len);
           if ((prop_len < 0) || (Preg_val == NULL)) {
-              bsa_print(ACS_PRINT_WARN, L" PROPERTY arm,msi-base-spi Error %d\n", prop_len);
+              bsa_print(ACS_PRINT_DEBUG, L"  PROPERTY arm,msi-base-spi Error %d\n", prop_len);
               GicEntry->spi_base = 0;
           } else
               GicEntry->spi_base = fdt32_to_cpu(Preg_val[0]);
@@ -622,7 +633,7 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
           Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "arm,msi-num-spis", 16,
                                                     &prop_len);
           if ((prop_len < 0) || (Preg_val == NULL)) {
-              bsa_print(ACS_PRINT_WARN, L" PROPERTY arm,msi-num-spis Error %d\n", prop_len);
+              bsa_print(ACS_PRINT_DEBUG, L"  PROPERTY arm,msi-num-spis Error %d\n", prop_len);
               GicEntry->spi_count = 0;
           } else
               GicEntry->spi_count = fdt32_to_cpu(Preg_val[0]);
@@ -631,14 +642,14 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
           offset = fdt_node_offset_by_compatible((const void *)dt_ptr, offset,
                                                  gicv2m_frame_dt_arr[0]);
       }
-      bsa_print(ACS_PRINT_DEBUG, L" Num of v2m frame %x \n", GicTable->header.num_msi_frame);
+      bsa_print(ACS_PRINT_DEBUG, L"  Num of v2m frame %x \n", GicTable->header.num_msi_frame);
   }
 
   if (GicTable->header.gic_version == 3) { /* Check if ITS sub-node present */
       /* Search for its nodes*/
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, its_dt_arr[0]);
       if (offset < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" No its present\n", 0);
+          bsa_print(ACS_PRINT_DEBUG, L"  No ITS present\n", 0);
           GicEntry->type = 0xFF;
           return;
       }
@@ -646,7 +657,7 @@ pal_gic_create_info_table_dt(GIC_INFO_TABLE *GicTable)
           GicTable->header.num_its++;
           offset = fdt_node_offset_by_compatible((const void *)dt_ptr, offset, its_dt_arr[0]);
       }
-      bsa_print(ACS_PRINT_DEBUG, L" Num of its frame %x \n", GicTable->header.num_its);
+      bsa_print(ACS_PRINT_DEBUG, L"  Num of ITS frame %x \n", GicTable->header.num_its);
   }
 
   /* Mark end of table */
diff --git a/platform/pal_uefi_dt/src/pal_iovirt.c b/platform/pal_uefi_dt/src/pal_iovirt.c
index 9ad64068..bc2d280d 100644
--- a/platform/pal_uefi_dt/src/pal_iovirt.c
+++ b/platform/pal_uefi_dt/src/pal_iovirt.c
@@ -43,6 +43,13 @@ static char smmu3_dt_arr[][SMMU_COMPATIBLE_STR_LEN] = {
 
 UINT64 pal_get_iort_ptr();
 
+/**
+  @brief This API creates iovirt override table
+
+  @param table Address where the iovirt override information needs to be filled
+
+  @return None
+**/
 STATIC VOID
 iovirt_create_override_table(IOVIRT_INFO_TABLE *table) {
   IOVIRT_BLOCK *block;
@@ -55,7 +62,11 @@ iovirt_create_override_table(IOVIRT_INFO_TABLE *table) {
 }
 
 /**
-  @brief  Dump the input block
+  @brief Dump the input block
+
+  @param block Pointer to block
+
+  @return None
 **/
 STATIC VOID
 dump_block(IOVIRT_BLOCK *block) {
@@ -63,29 +74,29 @@ dump_block(IOVIRT_BLOCK *block) {
   NODE_DATA_MAP *map = &block->data_map[0];
   switch(block->type) {
       case IOVIRT_NODE_ITS_GROUP:
-      bsa_print(ACS_PRINT_INFO, L"\nITS Group:\n Num ITS:%d\n", (*map).id[0]);
+      bsa_print(ACS_PRINT_INFO, L"\n ITS Group:\n Num ITS:%d\n", (*map).id[0]);
       for(i = 0; i < block->data.its_count; i++)
-          bsa_print(ACS_PRINT_INFO, L"%d ", (*map).id[i]);
+          bsa_print(ACS_PRINT_INFO, L"  %d ", (*map).id[i]);
       bsa_print(ACS_PRINT_INFO, L"\n");
       return;
       case IOVIRT_NODE_NAMED_COMPONENT:
-      bsa_print(ACS_PRINT_INFO, L"\nNamed Component:\n Device Name:%a\n", block->data.name);
+      bsa_print(ACS_PRINT_INFO, L"\n Named Component:\n Device Name:%a\n", block->data.name);
       break;
       case IOVIRT_NODE_PCI_ROOT_COMPLEX:
-      bsa_print(ACS_PRINT_INFO, L"\nRoot Complex:\n PCI segment number:%d\n",
+      bsa_print(ACS_PRINT_INFO, L"\n Root Complex:\n PCI segment number:%d\n",
                                 block->data.rc.segment);
       break;
       case IOVIRT_NODE_SMMU:
       case IOVIRT_NODE_SMMU_V3:
-      bsa_print(ACS_PRINT_INFO, L"\nSMMU:\n Major Rev:%d\n Base Address:0x%x\n",
+      bsa_print(ACS_PRINT_INFO, L"\n SMMU:\n Major Rev:%d\n Base Address:0x%x\n",
                  block->data.smmu.arch_major_rev, block->data.smmu.base);
       break;
       case IOVIRT_NODE_PMCG:
-      bsa_print(ACS_PRINT_INFO, L"\nPMCG:\n Base:0x%x\n Overflow GSIV:0x%x\n Node Reference:0x%x\n",
+      bsa_print(ACS_PRINT_INFO, L"\n PMCG:\n Base:0x%x\n Overflow GSIV:0x%x\n Node Reference:0x%x\n",
                  block->data.pmcg.base, block->data.pmcg.overflow_gsiv, block->data.pmcg.node_ref);
       break;
   }
-  bsa_print(ACS_PRINT_INFO, L"Number of ID Mappings:%d\n", block->num_data_map);
+  bsa_print(ACS_PRINT_INFO, L" Number of ID Mappings:%d\n", block->num_data_map);
   for(i = 0; i < block->num_data_map; i++, map++) {
       bsa_print(ACS_PRINT_INFO, L"\n input_base:0x%x\n id_count:0x%x\n output_base:0x%x\n",
             (*map).map.input_base, (*map).map.id_count, (*map).map.output_base);
@@ -95,6 +106,14 @@ dump_block(IOVIRT_BLOCK *block) {
   bsa_print(ACS_PRINT_INFO, L"\n");
 }
 
+/**
+  @brief This API checks if the context bank interrupt ids for the smmu node are unique
+
+  @param ctx_int Array of context bank interrupt ids
+  @param ctx_int_cnt Context bank interrupt count
+
+  @return 0 if context bank interrupt ids are not unique ; 1 if context bank interrupt ids are unique
+**/
 STATIC UINTN
 smmu_ctx_int_distinct(UINT64 *ctx_int, INTN ctx_int_cnt) {
   INTN i, j;
@@ -107,19 +126,29 @@ smmu_ctx_int_distinct(UINT64 *ctx_int, INTN ctx_int_cnt) {
   return 1;
 }
 
+/**
+  @brief This API dumps the iovirt table
+
+  @param iovirt Pointer to iovirt info table
+
+  @return None
+**/
 STATIC VOID
 dump_iort_table(IOVIRT_INFO_TABLE *iovirt)
 {
   UINT32 i;
   IOVIRT_BLOCK *block = &iovirt->blocks[0];
-  bsa_print(ACS_PRINT_INFO, L"Number of IOVIRT blocks = %d\n", iovirt->num_blocks);
+  bsa_print(ACS_PRINT_INFO, L" Number of IOVIRT blocks = %d\n", iovirt->num_blocks);
   for(i = 0; i < iovirt->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block))
     dump_block(block);
 }
 
 /**
   @brief  Check ID mappings in all blocks for any overlap of ID ranges
+
   @param iort IoVirt table
+
+  @return None
 **/
 STATIC VOID
 check_mapping_overlap(IOVIRT_INFO_TABLE *iovirt)
@@ -168,13 +197,13 @@ check_mapping_overlap(IOVIRT_INFO_TABLE *iovirt)
             if(tmp->type == IOVIRT_NODE_ITS_GROUP) {
                key_block->flags |= (1 << IOVIRT_FLAG_DEVID_OVERLAP_SHIFT);
                block->flags |= (1 << IOVIRT_FLAG_DEVID_OVERLAP_SHIFT);
-               bsa_print(ACS_PRINT_INFO, L"\nOverlapping device ids %x-%x and %x-%x \n",
+               bsa_print(ACS_PRINT_INFO, L"\n Overlapping device ids %x-%x and %x-%x \n",
                           key_start, key_end, start, end);
             }
             else {
                key_block->flags |= (1 << IOVIRT_FLAG_STRID_OVERLAP_SHIFT);
                block->flags |= (1 << IOVIRT_FLAG_STRID_OVERLAP_SHIFT);
-               bsa_print(ACS_PRINT_INFO, L"\nOverlapping stream ids %x-%x and %x-%x \n",
+               bsa_print(ACS_PRINT_INFO, L"\n Overlapping stream ids %x-%x and %x-%x \n",
                           key_start, key_end, start, end);
             }
           }
@@ -238,7 +267,7 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt
   NODE_DATA *data = &((*block)->data);
   VOID *node_data = &(iort_node->node_data[0]);
 
-  bsa_print(ACS_PRINT_INFO, L"IORT node offset:%x, type: %d\n", (UINT8*)iort_node - (UINT8*)iort, iort_node->type);
+  bsa_print(ACS_PRINT_INFO, L" IORT node offset:%x, type: %d\n", (UINT8*)iort_node - (UINT8*)iort, iort_node->type);
 
   SetMem(data, sizeof(NODE_DATA), 0);
 
@@ -289,7 +318,7 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt
       count = &IoVirtTable->num_pmcgs;
       break;
     default:
-       bsa_print(ACS_PRINT_ERR, L"Invalid IORT node type\n");
+       bsa_print(ACS_PRINT_ERR, L" Invalid IORT node type\n");
        return (UINT32) -1;
   }
 
@@ -357,7 +386,11 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt
 }
 
 /**
-  @brief  Parses ACPI IORT table and populates the local iovirt table
+  @brief Parses ACPI IORT table and populates the local iovirt table
+
+  @param IoVirtTable Address where the IOVIRT information must be filled
+
+  @return None
 **/
 VOID
 pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *IoVirtTable)
@@ -383,13 +416,10 @@ pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *IoVirtTable)
     return;
   }
 
-  iort = (IORT_TABLE *)pal_get_iort_ptr();
+  pal_iovirt_create_info_table_dt(IoVirtTable);
+  return;
 
-  if (iort == NULL) {
-    bsa_print(ACS_PRINT_DEBUG, L"No IORT table found. Check DT table \n");
-    pal_iovirt_create_info_table_dt(IoVirtTable);
-    return;
-  }
+  iort = (IORT_TABLE *)pal_get_iort_ptr();
 
   /* Point to the first Iovirt table block */
   next_block = &(IoVirtTable->blocks[0]);
@@ -401,7 +431,7 @@ pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *IoVirtTable)
   /* Create iovirt block for each IORT node*/
   for (i = 0; i < iort->node_count; i++) {
     if (iort_node >= iort_end) {
-      bsa_print(ACS_PRINT_ERR, L"Bad IORT table \n");
+      bsa_print(ACS_PRINT_ERR, L" Bad IORT table \n");
       return;
     }
     iort_add_block(iort, iort_node, IoVirtTable, &next_block);
@@ -446,35 +476,91 @@ pal_iovirt_unique_rid_strid_map(UINT64 rc_block)
   return 1;
 }
 
+/**
+ @brief This API returns the base address of SMMU if a Root Complex is
+          behind an SMMU, otherwise returns NULL
+
+ @param Iovirt IO Virt Table base address pointer
+ @param RcSegmentNum Root complex segment number
+ @param rid Unique requester ID
+
+ @return base address of SMMU if a Root Complex is behind an SMMU, otherwise returns NULL
+**/
 UINT64
 pal_iovirt_get_rc_smmu_base (
   IOVIRT_INFO_TABLE *Iovirt,
-  UINT32 RcSegmentNum
+  UINT32 RcSegmentNum,
+  UINT32 rid
   )
 {
-  UINT32 i;
+  UINT32 i, j;
   IOVIRT_BLOCK *block;
+  NODE_DATA_MAP *map;
+  UINT32 mapping_found;
+  UINT32 oref, sid, id = 0;
 
-  /* As per IORT acpi table, it is assumed that
-   * PCI segment numbers have a one-to-one mapping
-   * with root complexes. Each segment number can
-   * represent only one root complex.
-   */
+  /* Search for root complex block with same segment number, and in whose id */
+  /* mapping range 'rid' falls. Calculate the output id */
   block = &(Iovirt->blocks[0]);
-  for(i = 0; i < Iovirt->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) {
-    if (block->data.rc.segment == RcSegmentNum) {
-      return block->data.rc.smmu_base;
-    }
+  mapping_found = 0;
+  for (i = 0; i < Iovirt->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block))
+  {
+      if (block->type == IOVIRT_NODE_PCI_ROOT_COMPLEX
+          && block->data.rc.segment == RcSegmentNum)
+      {
+          for (j = 0, map = &block->data_map[0]; j < block->num_data_map; j++, map++)
+          {
+              if(rid >= (*map).map.input_base
+                      && rid <= ((*map).map.input_base + (*map).map.id_count))
+              {
+                  id =  rid - (*map).map.input_base + (*map).map.output_base;
+                  oref = (*map).map.output_ref;
+                  mapping_found = 1;
+                  break;
+              }
+          }
+      }
+  }
+
+  if (!mapping_found) {
+      bsa_print(ACS_PRINT_ERR,
+               L"\n       RID to Stream ID/Dev ID map not found ", 0);
+      return 0xFFFFFFFF;
+  }
+
+  block = (IOVIRT_BLOCK*)((UINT8*)Iovirt + oref);
+  if(block->type == IOVIRT_NODE_SMMU || block->type == IOVIRT_NODE_SMMU_V3)
+  {
+      sid = id;
+      id = 0;
+      for(i = 0, map = &block->data_map[0]; i < block->num_data_map; i++, map++)
+      {
+          if(sid >= (*map).map.input_base && sid <= ((*map).map.input_base +
+                                                    (*map).map.id_count))
+          {
+              bsa_print(ACS_PRINT_DEBUG,
+                        L"  find RC block->data.smmu.base : %llx",
+                        block->data.smmu.base);
+              return block->data.smmu.base;
+          }
+      }
   }
 
   /* The Root Complex represented by rc_seg_num
    * is not behind any SMMU. Return NULL pointer
    */
+  bsa_print(ACS_PRINT_DEBUG, L"  No SMMU found behind the RootComplex with segment :%d",
+                                                                            RcSegmentNum);
   return 0;
+
 }
 
 /**
-  @brief  Parses DT SMMU table and populates the local iovirt table
+ @brief Parses DT SMMU table and populates the local iovirt table
+
+ @param IoVirtTable Address where the IOVIRT information must be filled
+
+ @return None
 **/
 VOID
 pal_iovirt_create_info_table_dt(IOVIRT_INFO_TABLE *IoVirtTable)
@@ -518,29 +604,29 @@ pal_iovirt_create_info_table_dt(IOVIRT_INFO_TABLE *IoVirtTable)
           continue; /* Search for next compatible smmuv3*/
 
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-      bsa_print(ACS_PRINT_DEBUG, L" Parent Node offset %d\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  Parent Node offset %d\n", offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  size cell %d\n", size_cell);
       if (size_cell < 1) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid size cell :%d\n", size_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid size cell :%d\n", size_cell);
           return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  addr cell %d\n", addr_cell);
       if (addr_cell < 1) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid address cell : %d \n", addr_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid address cell : %d \n", addr_cell);
           return;
       }
 
       while (offset != -FDT_ERR_NOTFOUND) {
-          bsa_print(ACS_PRINT_DEBUG, L" SMMUv3 node:%d offset:%d \n", IoVirtTable->num_smmus,
+          bsa_print(ACS_PRINT_DEBUG, L"  SMMUv3 node:%d offset:%d \n", IoVirtTable->num_smmus,
                     offset);
 
           Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
           if ((prop_len < 0) || (Preg_val == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY reg offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY reg offset %x, Error %d\n", offset, prop_len);
               return;
           }
 
@@ -573,29 +659,29 @@ pal_iovirt_create_info_table_dt(IOVIRT_INFO_TABLE *IoVirtTable)
           continue; /* Search for next compatible smmuv2*/
 
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-      bsa_print(ACS_PRINT_DEBUG, L" Parent Node offset %d\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  Parent Node offset %d\n", offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  size cell %d\n", size_cell);
       if (size_cell < 1) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid size cell :%d\n", size_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid size cell :%d\n", size_cell);
           return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  addr cell %d\n", addr_cell);
       if (addr_cell < 1) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid address cell : %d \n", addr_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid address cell : %d \n", addr_cell);
           return;
       }
 
       while (offset != -FDT_ERR_NOTFOUND) {
-          bsa_print(ACS_PRINT_DEBUG, L" SMMUv2 node:%d offset:%d \n", IoVirtTable->num_smmus,
+          bsa_print(ACS_PRINT_DEBUG, L"  SMMUv2 node:%d offset:%d \n", IoVirtTable->num_smmus,
                     offset);
 
           Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
           if ((prop_len < 0) || (Preg_val == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY reg offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY reg offset %x, Error %d\n", offset, prop_len);
               return;
           }
 
@@ -623,30 +709,30 @@ pal_iovirt_create_info_table_dt(IOVIRT_INFO_TABLE *IoVirtTable)
   /* Parse PCIe node and add smmu base to rc node */
   offset = fdt_node_offset_by_prop_value((const void *) dt_ptr, -1, "device_type", "pci", 4);
   if (offset < 0) {
-    bsa_print(ACS_PRINT_DEBUG, L" PCIE node not found %d\n", offset);
+    bsa_print(ACS_PRINT_DEBUG, L"  PCIE node not found %d\n", offset);
     return;
   }
 
   parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-  bsa_print(ACS_PRINT_DEBUG, L" NODE pcie offset %d\n", offset);
+  bsa_print(ACS_PRINT_DEBUG, L"  NODE pcie offset %d\n", offset);
 
   size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-  bsa_print(ACS_PRINT_DEBUG, L" NODE pcie size cell %d\n", size_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  NODE pcie size cell %d\n", size_cell);
   if (size_cell < 0) {
-    bsa_print(ACS_PRINT_ERR, L" Invalid size cell \n");
+    bsa_print(ACS_PRINT_ERR, L"  Invalid size cell \n");
     return;
   }
 
   addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-  bsa_print(ACS_PRINT_DEBUG, L" NODE pcie addr cell %d\n", addr_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  NODE pcie addr cell %d\n", addr_cell);
   if (addr_cell <= 0 || addr_cell > 2) {
-    bsa_print(ACS_PRINT_ERR, L" Invalid address cell \n");
+    bsa_print(ACS_PRINT_ERR, L"  Invalid address cell \n");
     return;
   }
 
   /* Perform a DT traversal till all pcie node are parsed */
   while (offset != -FDT_ERR_NOTFOUND) {
-      bsa_print(ACS_PRINT_DEBUG, L" SUBNODE  offset %x\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  SUBNODE  offset %x\n", offset);
 
       /* parse iommu-map is present */
       Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "iommu-map", 9, &prop_len);
diff --git a/platform/pal_uefi_dt/src/pal_misc.c b/platform/pal_uefi_dt/src/pal_misc.c
index f923681e..2a1bebab 100644
--- a/platform/pal_uefi_dt/src/pal_misc.c
+++ b/platform/pal_uefi_dt/src/pal_misc.c
@@ -27,6 +27,15 @@
 
 UINT8   *gSharedMemory;
 
+/**
+ @brief This API provides a single point of abstraction to write 8-bit
+        data to all memory-mapped I/O addresses.
+
+ @param addr 64-bit address
+ @param data 8-bit data write to address
+
+ @return None
+**/
 VOID
 pal_mmio_write8(UINT64 addr, UINT8 data)
 {
@@ -35,6 +44,15 @@ pal_mmio_write8(UINT64 addr, UINT8 data)
 
 }
 
+/**
+  @brief This API provides a single point of abstraction to write 16-bit
+         data to all memory-mapped I/O addresses.
+
+  @param addr 64-bit address
+  @param data 16-bit data write to address
+
+  @return None
+**/
 VOID
 pal_mmio_write16(UINT64 addr, UINT16 data)
 {
@@ -43,6 +61,15 @@ pal_mmio_write16(UINT64 addr, UINT16 data)
 
 }
 
+/**
+   @brief This API provides a single point of abstraction to write 64-bit
+          data to all memory-mapped I/O addresses.
+
+   @param addr 64-bit address
+   @param data 64-bit data write to address
+
+   @return None
+**/
 VOID
 pal_mmio_write64(UINT64 addr, UINT64 data)
 {
@@ -51,6 +78,14 @@ pal_mmio_write64(UINT64 addr, UINT64 data)
 
 }
 
+/**
+  @brief This API provides a single point of abstraction to read 8-bit data
+         from all memory-mapped I/O addresses.
+
+  @param addr 64-bit input address
+
+  @return 8-bit data read from the input address
+**/
 UINT8
 pal_mmio_read8(UINT64 addr)
 {
@@ -62,6 +97,14 @@ pal_mmio_read8(UINT64 addr)
   return data;
 }
 
+/**
+  @brief This API provides a single point of abstraction to read 16-bit data
+         from all memory-mapped I/O addresses.
+
+  @param addr 64-bit input address
+
+  @return 16-bit data read from the input address
+**/
 UINT16
 pal_mmio_read16(UINT64 addr)
 {
@@ -73,6 +116,14 @@ pal_mmio_read16(UINT64 addr)
   return data;
 }
 
+/**
+  @brief This API provides a single point of abstraction to read 64-bit data
+         from all memory-mapped I/O addresses.
+
+  @param addr 64-bit input address
+
+  @return 64-bit data read from the input address
+**/
 UINT64
 pal_mmio_read64(UINT64 addr)
 {
@@ -144,7 +195,7 @@ pal_print(CHAR8 *string, UINT64 data)
     AsciiPrint(Buffer);
     Status = ShellWriteFile(g_bsa_log_file_handle, &BufferSize, (VOID*)Buffer);
     if(EFI_ERROR(Status))
-      bsa_print(ACS_PRINT_ERR, L"Error in writing to log file\n");
+      bsa_print(ACS_PRINT_ERR, L" Error in writing to log file\n");
   } else
       AsciiPrint(string, data);
 }
@@ -153,6 +204,7 @@ pal_print(CHAR8 *string, UINT64 data)
   @brief  Sends a string to the output console without using UEFI print function
           This function will get COMM port address and directly writes to the addr char-by-char
 
+  @param  addr    Address to be written
   @param  string  An ASCII string
   @param  data    data for the formatted output
 
@@ -259,10 +311,10 @@ pal_mem_allocate_shared(UINT32 num_pe, UINT32 sizeofentry)
                                (num_pe * sizeofentry),
                                (VOID **) &gSharedMemory );
 
-  bsa_print(ACS_PRINT_INFO, L"Shared memory is %llx \n", gSharedMemory);
+  bsa_print(ACS_PRINT_INFO, L" Shared memory is %llx \n", gSharedMemory);
 
   if (EFI_ERROR(Status)) {
-    bsa_print(ACS_PRINT_ERR, L"Allocate Pool shared memory failed %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Allocate Pool shared memory failed %x \n", Status);
   }
   pal_pe_data_cache_ops_by_va((UINT64)&gSharedMemory, CLEAN_AND_INVALIDATE);
 
@@ -299,13 +351,13 @@ pal_mem_free_shared()
 }
 
 /**
- * @brief  Allocates requested buffer size in bytes in a contiguous memory
- *         and returns the base address of the range.
- *
- * @param  Size         allocation size in bytes
- * @retval if SUCCESS   pointer to allocated memory
- * @retval if FAILURE   NULL
- */
+  @brief  Allocates requested buffer size in bytes in a contiguous memory
+          and returns the base address of the range.
+
+  @param  Size         allocation size in bytes
+
+  @return if SUCCESS   pointer to allocated memory ;  if FAILURE   NULL
+**/
 VOID *
 pal_mem_alloc (
   UINT32 Size
@@ -321,7 +373,7 @@ pal_mem_alloc (
                               (VOID **) &Buffer);
   if (EFI_ERROR(Status))
   {
-    bsa_print(ACS_PRINT_ERR, L"Allocate Pool failed %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Allocate Pool failed %x \n", Status);
     return NULL;
   }
 
@@ -330,14 +382,15 @@ pal_mem_alloc (
 }
 
 /**
- * @brief  Allocates requested buffer size in bytes in a contiguous cacheable
- *         memory and returns the base address of the range.
- *
- * @param  Size         allocation size in bytes
- * @param  Pa           Pointer to Physical Addr
- * @retval if SUCCESS   Pointer to Virtual Addr
- * @retval if FAILURE   NULL
- */
+  @brief  Allocates requested buffer size in bytes in a contiguous cacheable
+          memory and returns the base address of the range.
+
+  @param  Bdf          Bus, Device, and Function of the requesting PCIe device
+  @param  Size         allocation size in bytes
+  @param  Pa           Pointer to Physical Addr
+
+  @return if SUCCESS   Pointer to Virtual Addr ; if FAILURE   NULL
+**/
 VOID *
 pal_mem_alloc_cacheable (
   UINT32 Bdf,
@@ -353,7 +406,7 @@ pal_mem_alloc_cacheable (
                                EFI_SIZE_TO_PAGES(Size),
                                &Address);
   if (EFI_ERROR(Status)) {
-    bsa_print(ACS_PRINT_ERR, L"Allocate Pool failed %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Allocate Pool failed %x \n", Status);
     return NULL;
   }
 
@@ -363,13 +416,15 @@ pal_mem_alloc_cacheable (
 }
 
 /**
- * @brief  Free the cacheable memory region allocated above
- *
- * @param  Size         allocation size in bytes
- * @param  Va           Pointer to Virtual Addr
- * @param  Pa           Pointer to Physical Addr
- * @retval None
- */
+  @brief  Free the cacheable memory region allocated above
+
+  @param  Bdf          Bus, Device, and Function of the requesting PCIe device
+  @param  Size         allocation size in bytes
+  @param  Va           Pointer to Virtual Addr
+  @param  Pa           Pointer to Physical Addr
+
+  @return None
+**/
 VOID
 pal_mem_free_cacheable (
   UINT32 Bdf,
@@ -381,9 +436,13 @@ pal_mem_free_cacheable (
   gBS->FreePages((EFI_PHYSICAL_ADDRESS)(UINTN)Va, EFI_SIZE_TO_PAGES(Size));
 }
 
-/* Place holder function. Need to be
- * implemented if needed in later releases
- */
+/** Place holder function. Need to be implemented if needed in later releases
+  @brief This API returns the physical address of the input virtual address.
+
+  @param Va virtual address of the memory to be converted
+
+  @return Returns the physical address
+**/
 VOID *
 pal_mem_virt_to_phys (
   VOID *Va
@@ -392,6 +451,13 @@ pal_mem_virt_to_phys (
   return Va;
 }
 
+/**
+ @brief Returns the virtual address of the input physical address.
+
+ @param Pa Physical Address of the memory to be converted
+
+ @return Pointer to virtual address space
+**/
 VOID *
 pal_mem_phys_to_virt (
   UINT64 Pa
@@ -455,12 +521,26 @@ pal_time_delay_ms (
   return gBS->Stall(MicroSeconds);
 }
 
+/**
+ @brief Returns the memory page size (in bytes) used by the platform.
+
+ @param None
+
+ @return Size of memory page
+**/
 UINT32
 pal_mem_page_size()
 {
     return EFI_PAGE_SIZE;
 }
 
+/**
+  @brief Allocates the requested number of memory pages
+
+  @param NumPages Number of memory pages needed
+
+  @return Address of the allocated space
+**/
 VOID *
 pal_mem_alloc_pages (
   UINT32 NumPages
@@ -475,13 +555,21 @@ pal_mem_alloc_pages (
                                &PageBase);
   if (EFI_ERROR(Status))
   {
-    bsa_print(ACS_PRINT_ERR, L"Allocate Pages failed %x \n", Status);
+    bsa_print(ACS_PRINT_ERR, L" Allocate Pages failed %x \n", Status);
     return NULL;
   }
 
   return (VOID*)(UINTN)PageBase;
 }
 
+/**
+  @brief Free number of pages in the memory as requested.
+
+  @param PageBase Address from where we need to free
+  @param NumPages Number of memory pages needed
+
+  @return None
+**/
 VOID
 pal_mem_free_pages(
   VOID *PageBase,
diff --git a/platform/pal_uefi_dt/src/pal_pcie.c b/platform/pal_uefi_dt/src/pal_pcie.c
index a9da9765..5cf39bfd 100644
--- a/platform/pal_uefi_dt/src/pal_pcie.c
+++ b/platform/pal_uefi_dt/src/pal_pcie.c
@@ -80,20 +80,17 @@ pal_pcie_create_info_table(PCIE_INFO_TABLE *PcieTable)
   UINT32 i = 0;
 
   if (PcieTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input PCIe Table Pointer is NULL. Cannot create PCIe INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input PCIe Table Pointer is NULL. Cannot create PCIe INFO \n");
     return;
   }
 
   g_pal_pcie_info_table = PcieTable;
   PcieTable->num_entries = 0;
 
-  gMcfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *) pal_get_mcfg_ptr();
+  pal_pcie_create_info_table_dt(PcieTable);
+  return;
 
-  if (gMcfgHdr == NULL) {
-      bsa_print(ACS_PRINT_DEBUG, L"ACPI - MCFG Table not found. Check DT \n");
-      pal_pcie_create_info_table_dt(PcieTable);
-      return;
-  }
+  gMcfgHdr = (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER *) pal_get_mcfg_ptr();
 
   if(PLATFORM_OVERRIDE_PCIE_ECAM_BASE) {
       PcieTable->block[i].ecam_base = PLATFORM_OVERRIDE_PCIE_ECAM_BASE;
@@ -145,7 +142,7 @@ pal_pcie_io_read_cfg(UINT32 Bdf, UINT32 offset, UINT32 *data)
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_INFO,L"No PCI devices found in the system\n");
+    bsa_print(ACS_PRINT_INFO,L" No PCI devices found in the system\n");
     return PCIE_NO_MAPPING;
   }
 
@@ -194,7 +191,7 @@ pal_pcie_io_write_cfg(UINT32 Bdf, UINT32 offset, UINT32 data)
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_INFO,L"No PCI devices found in the system\n");
+    bsa_print(ACS_PRINT_INFO,L" No PCI devices found in the system\n");
     return;
   }
 
@@ -234,7 +231,11 @@ pal_pcie_p2p_support()
 /**
   @brief   This API checks the PCIe device P2P support
            1. Caller       -  Test Suite
-  @param   bdf      - PCIe BUS/Device/Function
+
+  @param   Seg       PCI segment number
+  @param   Bus        PCI bus address
+  @param   Dev        PCI device address
+  @param   Fn         PCI function number
   @return  1 - P2P feature not supported 0 - P2P feature supported
 **/
 UINT32
@@ -256,10 +257,11 @@ pal_pcie_dev_p2p_support (
 /**
     @brief   Create a list of MSI(X) vectors for a device
 
-    @param   bus        PCI bus address
-    @param   dev        PCI device address
-    @param   fn         PCI function number
-    @param   mvector    pointer to a MSI(X) list address
+    @param   Seg        PCI segment number
+    @param   Bus        PCI bus address
+    @param   Dev        PCI device address
+    @param   Fn         PCI function number
+    @param   MVector    pointer to a MSI(X) list address
 
     @return  mvector    list of MSI(X) vectors
     @return  number of MSI(X) vectors
@@ -279,10 +281,11 @@ pal_get_msi_vectors (
 /**
     @brief   Get legacy IRQ routing for a PCI device
 
-    @param   bus        PCI bus address
-    @param   dev        PCI device address
-    @param   fn         PCI function number
-    @param   irq_map    pointer to IRQ map structure
+    @param   Seg      - PCI segment number
+    @param   Bus        PCI bus address
+    @param   Dev        PCI device address
+    @param   Fn         PCI function number
+    @param   Irq_Map    pointer to IRQ map structure
 
     @return  irq_map    IRQ routing map
     @return  status code
@@ -299,9 +302,17 @@ pal_pcie_get_legacy_irq_map (
   return 1; /* not implemented */
 }
 
-/* Place holder function. Need to be
- * implemented if needed in later releases
- */
+/** Place holder function. Need to be implemented if needed in later releases
+  @brief Returns the Bus, Device, and Function values of the Root Port of the device.
+
+  @param   Seg        PCI segment number
+  @param   Bus        PCI bus address
+  @param   Dev        PCI device address
+  @param   Fn         PCI function number
+
+  @return 0 if success; 1 if input BDF device cannot be found
+          2 if root Port for the input device cannot be determined
+**/
 UINT32
 pal_pcie_get_root_port_bdf (
   UINT32 *Seg,
@@ -317,8 +328,14 @@ pal_pcie_get_root_port_bdf (
   @brief   Platform dependent API checks the Address Translation
            Cache Support for BDF
            1. Caller       -  Test Suite
-  @return  0 - ATC not supported 1 - ATC supported
-**/
+
+  @param   Seg        PCI segment number
+  @param   Bus        PCI bus address
+  @param   Dev        PCI device address
+  @param   Fn         PCI function number
+  @retval 0 ATC supported
+  @retval 1 ATC not supported
+  **/
 UINT32
 pal_pcie_is_cache_present (
   UINT32 Seg,
@@ -327,17 +344,19 @@ pal_pcie_is_cache_present (
   UINT32 Fn
   )
 {
-  return 0;
+  return 1;
 }
 
 /**
     @brief   Checks if device is behind SMMU
 
+    @param   seg        PCI segment number
     @param   bus        PCI bus address
     @param   dev        PCI device address
     @param   fn         PCI function number
 
-    @return  staus code:0 -> not present, nonzero -> present
+    @retval 1 if device is behind SMMU
+    @retval 0 if device is not behind SMMU or SMMU is in bypass mode
 **/
 UINT32
 pal_pcie_is_device_behind_smmu(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
@@ -348,11 +367,13 @@ pal_pcie_is_device_behind_smmu(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
 /**
     @brief   Return the DMA addressability of the device
 
+    @param   seg        PCI segment number
     @param   bus        PCI bus address
     @param   dev        PCI device address
     @param   fn         PCI function number
 
-    @return  DMA Mask : 0, 0xffffffff or 0xffffffffffff
+    @retval 0 if does not support 64-bit transfers
+    @retval 1 if supports 64-bit transfers
 **/
 UINT32
 pal_pcie_is_devicedma_64bit(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
@@ -363,14 +384,16 @@ pal_pcie_is_devicedma_64bit(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
 /**
     @brief   Get the PCIe device type
 
+    @param   seg        PCI segment number
     @param   bus        PCI bus address
     @param   dev        PCI device address
     @param   fn         PCI function number
 
-    @return  staus code:
-             1: Normal PCIe device, 2: PCIe Host bridge,
-             3: PCIe bridge device, else: INVALID
-**/
+    @retval 0 if Error: could not determine device structures
+    @retval 1 if normal PCIe device
+    @retval 2 if PCIe host bridge
+    @retval 3 if PCIe bridge
+    **/
 UINT32
 pal_pcie_get_device_type(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
 {
@@ -407,24 +430,24 @@ pal_pcie_create_info_table_dt(PCIE_INFO_TABLE *PcieTable)
   for (i = 0; i < sizeof(pci_dt_arr)/PCI_COMPATIBLE_STR_LEN ; i++) {
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, pci_dt_arr[i]);
       if (offset < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" PCI node offset not found %d \n", offset);
+          bsa_print(ACS_PRINT_DEBUG, L"  PCI node offset not found %d \n", offset);
           continue; /* Search for next compatible node*/
       }
 
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-      bsa_print(ACS_PRINT_DEBUG, L" NODE pcie offset %d\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  NODE pcie offset %d\n", offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" NODE pcie size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  NODE pcie size cell %d\n", size_cell);
       if (size_cell < 0) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid size cell \n");
+          bsa_print(ACS_PRINT_ERR, L"  Invalid size cell \n");
           return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" NODE pcie addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  NODE pcie addr cell %d\n", addr_cell);
       if (addr_cell <= 0 || addr_cell > 2) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid address cell \n");
+          bsa_print(ACS_PRINT_ERR, L"  Invalid address cell \n");
           return;
       }
 
@@ -433,7 +456,7 @@ pal_pcie_create_info_table_dt(PCIE_INFO_TABLE *PcieTable)
 
           Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
           if ((Preg_val == NULL) || prop_len < 0) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY reg offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY reg offset %x, Error %d\n", offset, prop_len);
               return;
           }
 
@@ -445,7 +468,7 @@ pal_pcie_create_info_table_dt(PCIE_INFO_TABLE *PcieTable)
           Pbus_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "bus-range", 9,
                                                                 &prop_len);
           if ((Pbus_val == NULL) || prop_len < 0) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY reg offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY reg offset %x, Error %d\n", offset, prop_len);
               return;
           }
           PcieTable->block[PcieTable->num_entries].segment_num = 0;
@@ -481,8 +504,8 @@ pal_bsa_pcie_enumerate()
     @param   fn         PCI function number
     @param   seg        PCI segment number
 
-    @return  0 if rp not involved in transaction forwarding
-             1 if rp is involved in transaction forwarding
+    @return  1 if rp not involved in transaction forwarding
+             0 if rp is involved in transaction forwarding
 **/
 UINT32
 pal_pcie_get_rp_transaction_frwd_support(UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn)
diff --git a/platform/pal_uefi_dt/src/pal_pcie_enumeration.c b/platform/pal_uefi_dt/src/pal_pcie_enumeration.c
index ce372f54..e7428280 100644
--- a/platform/pal_uefi_dt/src/pal_pcie_enumeration.c
+++ b/platform/pal_uefi_dt/src/pal_pcie_enumeration.c
@@ -83,7 +83,7 @@ palPcieGetBdf(UINT32 ClassCode, UINT32 StartBdf)
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_INFO,L"No PCI devices found in the system\n");
+    bsa_print(ACS_PRINT_INFO,L" No PCI devices found in the system\n");
     return EFI_SUCCESS;
   }
 
@@ -167,7 +167,7 @@ palPcieGetBase(UINT32 bdf, UINT32 bar_index)
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
-    bsa_print(ACS_PRINT_INFO,L"No PCI devices found in the system\n");
+    bsa_print(ACS_PRINT_INFO,L" No PCI devices found in the system\n");
     return EFI_SUCCESS;
   }
 
@@ -195,6 +195,13 @@ palPcieGetBase(UINT32 bdf, UINT32 bar_index)
   return 0;
 }
 
+/**
+  @brief Returns the PCI device structure for the given bdf
+
+  @param Bdf PCI Bus, Device, and Function
+
+  @return Pointer to device structure for the input bdf
+**/
 VOID *
 pal_pci_bdf_to_dev (
  UINT32 Bdf
@@ -203,6 +210,15 @@ pal_pci_bdf_to_dev (
   return NULL;
 }
 
+/**
+  @brief Reads 1 byte from the PCI configuration space for the current BDF at given offset.
+
+  @param Bdf PCI Bus, Device, and Function
+  @param Offset offset in the PCI configuration space for that BDF
+  @param Val return value
+
+  @return None
+**/
 VOID
 pal_pci_read_config_byte (
   UINT32 Bdf,
@@ -213,6 +229,13 @@ pal_pci_read_config_byte (
 
 }
 
+/**
+  @brief This API performs the PCI enumeration
+
+  @param None
+
+  @return None
+**/
 VOID pal_pcie_enumerate(VOID)
 {
   /**Implemented functionality only for Baremetal support
diff --git a/platform/pal_uefi_dt/src/pal_pe.c b/platform/pal_uefi_dt/src/pal_pe.c
index 28e24a7a..09c99be3 100644
--- a/platform/pal_uefi_dt/src/pal_pe.c
+++ b/platform/pal_uefi_dt/src/pal_pe.c
@@ -104,8 +104,7 @@ PalGetMaxMpidr()
   @brief  Allocate memory region for secondary PE stack use. SIZE of stack for each PE
           is a #define
 
-  @param  Number of PEs
-
+  @param  mpidr Pass MIPDR register content
   @return  None
 **/
 VOID
@@ -152,19 +151,17 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
 
 
   if (PeTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input PE Table Pointer is NULL. Cannot create PE INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input PE Table Pointer is NULL. Cannot create PE INFO \n");
     return;
   }
+  pal_pe_create_info_table_dt(PeTable);
+  return;
 
   gMadtHdr = (EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *) pal_get_madt_ptr();
 
   if (gMadtHdr != NULL) {
     TableLength =  gMadtHdr->Header.Length;
-    bsa_print(ACS_PRINT_INFO, L" MADT is at %x and length is %x \n", gMadtHdr, TableLength);
-  } else {
-    bsa_print(ACS_PRINT_DEBUG, L"MADT not found..Checking DT \n");
-    pal_pe_create_info_table_dt(PeTable);
-    return;
+    bsa_print(ACS_PRINT_INFO, L"  MADT is at %x and length is %x \n", gMadtHdr, TableLength);
   }
 
   PeTable->header.num_of_pe = 0;
@@ -180,7 +177,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
       Ptr->mpidr    = Entry->MPIDR;
       Ptr->pe_num   = PeTable->header.num_of_pe;
       Ptr->pmu_gsiv = Entry->PerformanceInterruptGsiv;
-      bsa_print(ACS_PRINT_DEBUG, L"MPIDR %x PE num %x \n", Ptr->mpidr, Ptr->pe_num);
+      bsa_print(ACS_PRINT_DEBUG, L"  MPIDR %x PE num %d \n", Ptr->mpidr, Ptr->pe_num);
       pal_pe_data_cache_ops_by_va((UINT64)Ptr, CLEAN_AND_INVALIDATE);
       Ptr++;
       PeTable->header.num_of_pe++;
@@ -376,7 +373,7 @@ pal_pe_info_table_pmu_gsiv_dt(PE_INFO_TABLE *PeTable)
 
   dt_ptr = pal_get_dt_ptr();
   if (dt_ptr == 0) {
-      bsa_print(ACS_PRINT_ERR, L"dt_ptr is NULL \n");
+      bsa_print(ACS_PRINT_ERR, L" dt_ptr is NULL \n");
       return;
   }
 
@@ -387,7 +384,7 @@ pal_pe_info_table_pmu_gsiv_dt(PE_INFO_TABLE *PeTable)
       /* Search for pmu nodes*/
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, pmu_dt_arr[i]);
       if (offset < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" PMU compatible value not found for index:%d\n", i);
+          bsa_print(ACS_PRINT_DEBUG, L"  PMU compatible value not found for index:%d\n", i);
           continue; /* Search for next compatible item*/
       }
 
@@ -396,23 +393,23 @@ pal_pe_info_table_pmu_gsiv_dt(PE_INFO_TABLE *PeTable)
           Pintr = (UINT32 *)
                     fdt_getprop_namelen((void *)dt_ptr, offset, "interrupts", 10, &prop_len);
           if ((prop_len < 0) || (Pintr == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY interrupts offset %x, Error %d\n",
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY interrupts offset %x, Error %d\n",
                         offset, prop_len);
               return;
           }
 
           interrupt_cell = fdt_interrupt_cells((const void *)dt_ptr, offset);
-          bsa_print(ACS_PRINT_DEBUG, L" interrupt_cell  %d\n", interrupt_cell);
+          bsa_print(ACS_PRINT_DEBUG, L"  interrupt_cell  %d\n", interrupt_cell);
           if (interrupt_cell < INTERRUPT_CELLS_MIN || interrupt_cell > INTERRUPT_CELLS_MAX) {
-              bsa_print(ACS_PRINT_ERR, L" Invalid interrupt cell : %d \n", interrupt_cell);
+              bsa_print(ACS_PRINT_ERR, L"  Invalid interrupt cell : %d \n", interrupt_cell);
               return;
           }
 
           interrupt_frame_count = ((prop_len/sizeof(int))/interrupt_cell);
-          bsa_print(ACS_PRINT_DEBUG, L" interrupt frame count : %d \n", interrupt_frame_count);
+          bsa_print(ACS_PRINT_DEBUG, L"  interrupt frame count : %d \n", interrupt_frame_count);
 
           if (interrupt_frame_count == 0) {
-              bsa_print(ACS_PRINT_ERR, L" interrupt_frame_count is invalid\n");
+              bsa_print(ACS_PRINT_ERR, L"  interrupt_frame_count is invalid\n");
               return;
           }
 
@@ -433,12 +430,12 @@ pal_pe_info_table_pmu_gsiv_dt(PE_INFO_TABLE *PeTable)
                     Ptr->pmu_gsiv = 0; /* Set to zero*/
                     Ptr++;
                 }
-                bsa_print(ACS_PRINT_WARN, L" PMU interrupt type not mentioned\n");
+                bsa_print(ACS_PRINT_WARN, L"  PMU interrupt type not mentioned\n");
                 return;
               }
 
-              bsa_print(ACS_PRINT_DEBUG, L" intr_type    : %d \n", intr_type);
-              bsa_print(ACS_PRINT_DEBUG, L" pmu_intr_num : %d \n", curr_pmu_intr_num);
+              bsa_print(ACS_PRINT_DEBUG, L"  intr_type    : %d \n", intr_type);
+              bsa_print(ACS_PRINT_DEBUG, L"  pmu_intr_num : %d \n", curr_pmu_intr_num);
 
               if (intr_type == INTERRUPT_TYPE_PPI) {
                 curr_pmu_intr_num += PPI_OFFSET;
@@ -448,7 +445,7 @@ pal_pe_info_table_pmu_gsiv_dt(PE_INFO_TABLE *PeTable)
                       Ptr->pmu_gsiv = 0; /* Set to zero*/
                       Ptr++;
                     }
-                    bsa_print(ACS_PRINT_WARN, L" PMU interrupt number mismatch found\n");
+                    bsa_print(ACS_PRINT_WARN, L"  PMU interrupt number mismatch found\n");
                     return;
                 }
                 if (prev_pmu_intr_num == 0) { /* Update table first time with same id*/
@@ -504,23 +501,23 @@ pal_pe_create_info_table_dt(PE_INFO_TABLE *PeTable)
 
   if (offset != -FDT_ERR_NOTFOUND) {
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-      bsa_print(ACS_PRINT_DEBUG, L" NODE cpu offset %d\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  NODE cpu offset %d\n", offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" NODE cpu size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  NODE cpu size cell %d\n", size_cell);
       if (size_cell != 0) {
-        bsa_print(ACS_PRINT_ERR, L" Invalid size cell for node cpu\n");
+        bsa_print(ACS_PRINT_ERR, L"  Invalid size cell for node cpu\n");
         return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" NODE cpu  addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  NODE cpu  addr cell %d\n", addr_cell);
       if (addr_cell <= 0 || addr_cell > 2) {
-        bsa_print(ACS_PRINT_ERR, L" Invalid address cell for node cpu\n");
+        bsa_print(ACS_PRINT_ERR, L"  Invalid address cell for node cpu\n");
         return;
       }
   } else {
-        bsa_print(ACS_PRINT_ERR, L" No CPU node found \n");
+        bsa_print(ACS_PRINT_ERR, L"  No CPU node found \n");
         return;
   }
 
@@ -528,19 +525,19 @@ pal_pe_create_info_table_dt(PE_INFO_TABLE *PeTable)
 
   /* Perform a DT traversal till all cpu node are parsed */
   while (offset != -FDT_ERR_NOTFOUND) {
-      bsa_print(ACS_PRINT_DEBUG, L" SUBNODE cpu%d offset %x\n", PeTable->header.num_of_pe, offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  SUBNODE cpu%d offset %x\n", PeTable->header.num_of_pe, offset);
 
       prop_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
       if ((prop_len < 0) || (prop_val == NULL)) {
-        bsa_print(ACS_PRINT_ERR, L" PROPERTY reg offset %x, Error %d\n", offset, prop_len);
+        bsa_print(ACS_PRINT_ERR, L"  PROPERTY reg offset %x, Error %d\n", offset, prop_len);
         return;
       }
 
       reg_val[0] = fdt32_to_cpu(prop_val[0]);
-      bsa_print(ACS_PRINT_DEBUG, L" reg_val<0> = %x\n", reg_val[0]);
+      bsa_print(ACS_PRINT_DEBUG, L"  reg_val<0> = %x\n", reg_val[0]);
       if (addr_cell == 2) {
         reg_val[1] = fdt32_to_cpu(prop_val[1]);
-        bsa_print(ACS_PRINT_DEBUG, L" reg_val<1> = %x\n", reg_val[1]);
+        bsa_print(ACS_PRINT_DEBUG, L"  reg_val<1> = %x\n", reg_val[1]);
         Ptr->mpidr = (((INT64)(reg_val[0] & PROPERTY_MASK_PE_AFF3) << 32) |
                      (reg_val[1] & PROPERTY_MASK_PE_AFF0_AFF2));
       } else {
diff --git a/platform/pal_uefi_dt/src/pal_peripherals.c b/platform/pal_uefi_dt/src/pal_peripherals.c
index a1cc4984..fd8a2c1c 100644
--- a/platform/pal_uefi_dt/src/pal_peripherals.c
+++ b/platform/pal_uefi_dt/src/pal_peripherals.c
@@ -49,7 +49,8 @@ pal_strncmp(CHAR8 *str1, CHAR8 *str2, UINT32 len);
 
 static char usb_dt_compatible[][USB_COMPATIBLE_STR_LEN] = {
     "generic-ohci",
-    "generic-ehci"
+    "generic-ehci",
+    "generic-xhci"
 };
 
 static char sata_dt_compatible[][SATA_COMPATIBLE_STR_LEN] = {
@@ -87,7 +88,7 @@ pal_peripheral_usb_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTab
 
   dt_ptr = pal_get_dt_ptr();
   if (dt_ptr == 0) {
-      bsa_print(ACS_PRINT_ERR, L"dt_ptr is NULL \n");
+      bsa_print(ACS_PRINT_ERR, L" dt_ptr is NULL \n");
       return;
   }
 
@@ -99,25 +100,25 @@ pal_peripheral_usb_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTab
       /* Search for USB nodes*/
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, usb_dt_compatible[i]);
       if (offset < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" USB compatible value not found for index:%d\n", i);
+          bsa_print(ACS_PRINT_DEBUG, L"  USB compatible value not found for index:%d\n", i);
           continue; /* Search for next compatible item*/
       }
 
       /* Get Address_cell & Size_cell length to parse reg property of timer*/
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-      bsa_print(ACS_PRINT_DEBUG, L" Parent Node offset %d\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  Parent Node offset %d\n", offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  size cell %d\n", size_cell);
       if (size_cell < 0) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid size cell :%d\n", size_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid size cell :%d\n", size_cell);
           return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  addr cell %d\n", addr_cell);
       if (addr_cell < 1 || addr_cell > 2) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid address cell : %d \n", addr_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid address cell : %d \n", addr_cell);
           return;
       }
       while (offset != -FDT_ERR_NOTFOUND) {
@@ -127,7 +128,7 @@ pal_peripheral_usb_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTab
           /* Get reg property to update base */
           Preg = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
           if ((prop_len < 0) || (Preg == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY REG offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY REG offset %x, Error %d\n", offset, prop_len);
               return;
           }
 
@@ -135,15 +136,15 @@ pal_peripheral_usb_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTab
           Pintr = (UINT32 *)
                     fdt_getprop_namelen((void *)dt_ptr, offset, "interrupts", 10, &prop_len);
           if ((prop_len < 0) || (Pintr == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY interrupts offset %x, Error %d\n",
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY interrupts offset %x, Error %d\n",
                         offset, prop_len);
               return;
           }
 
           interrupt_cell = fdt_interrupt_cells((const void *)dt_ptr, offset);
-          bsa_print(ACS_PRINT_DEBUG, L" interrupt_cell  %d\n", interrupt_cell);
+          bsa_print(ACS_PRINT_DEBUG, L"  interrupt_cell  %d\n", interrupt_cell);
           if (interrupt_cell < INTERRUPT_CELLS_MIN || interrupt_cell > INTERRUPT_CELLS_MAX) {
-              bsa_print(ACS_PRINT_ERR, L" Invalid interrupt cell : %d \n", interrupt_cell);
+              bsa_print(ACS_PRINT_ERR, L"  Invalid interrupt cell : %d \n", interrupt_cell);
               return;
           }
 
@@ -167,6 +168,15 @@ pal_peripheral_usb_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTab
 
           per_info->bdf   = 0; /* NA in DT*/
           per_info->flags = 0; /* NA in DT*/
+          per_info->platform_type = PLATFORM_TYPE_DT;
+
+          if (!(pal_strncmp(uart_dt_compatible[i], "generic-ohci", sizeof("generic-ohci"))))
+            per_info->interface_type = USB_TYPE_OHCI;
+          else if (!(pal_strncmp(uart_dt_compatible[i], "generic-ehci", sizeof("generic-ehci"))))
+            per_info->interface_type = USB_TYPE_EHCI;
+          else if (!(pal_strncmp(uart_dt_compatible[i], "generic-xhci", sizeof("generic-xhci"))))
+            per_info->interface_type = USB_TYPE_XHCI;
+
           peripheralInfoTable->header.num_usb++;
           per_info++;
           offset =
@@ -198,7 +208,7 @@ pal_peripheral_sata_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
 
   dt_ptr = pal_get_dt_ptr();
   if (dt_ptr == 0) {
-      bsa_print(ACS_PRINT_ERR, L"dt_ptr is NULL \n");
+      bsa_print(ACS_PRINT_ERR, L" dt_ptr is NULL \n");
       return;
   }
 
@@ -211,25 +221,25 @@ pal_peripheral_sata_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
       /* Search for sata node*/
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, sata_dt_compatible[i]);
       if (offset < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" SATA compatible value not found for index:%d\n", i);
+          bsa_print(ACS_PRINT_DEBUG, L"  SATA compatible value not found for index:%d\n", i);
           continue; /* Search for next compatible item*/
       }
 
       /* Get Address_cell & Size_cell length to parse reg property of timer*/
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-      bsa_print(ACS_PRINT_DEBUG, L" Parent Node offset %d\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  Parent Node offset %d\n", offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  size cell %d\n", size_cell);
       if (size_cell < 0) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid size cell :%d\n", size_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid size cell :%d\n", size_cell);
           return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  addr cell %d\n", addr_cell);
       if (addr_cell < 1 || addr_cell > 2) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid address cell : %d \n", addr_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid address cell : %d \n", addr_cell);
           return;
       }
       while (offset != -FDT_ERR_NOTFOUND) {
@@ -239,7 +249,7 @@ pal_peripheral_sata_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
           /* Get reg property to update base */
           Preg = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
           if ((prop_len < 0) || (Preg == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY REG offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY REG offset %x, Error %d\n", offset, prop_len);
               return;
           }
 
@@ -247,13 +257,13 @@ pal_peripheral_sata_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
           Pintr = (UINT32 *)
                     fdt_getprop_namelen((void *)dt_ptr, offset, "interrupts", 10, &prop_len);
           if ((prop_len < 0) || (Pintr == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY interrupts offset %x, Error %d\n",
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY interrupts offset %x, Error %d\n",
                         offset, prop_len);
               return;
           }
 
           interrupt_cell = fdt_interrupt_cells((const void *)dt_ptr, offset);
-          bsa_print(ACS_PRINT_DEBUG, L" interrupt_cell  %d\n", interrupt_cell);
+          bsa_print(ACS_PRINT_DEBUG, L"  interrupt_cell  %d\n", interrupt_cell);
           if (interrupt_cell < INTERRUPT_CELLS_MIN || interrupt_cell > INTERRUPT_CELLS_MAX) {
               bsa_print(ACS_PRINT_ERR, L" Invalid interrupt cell : %d \n", interrupt_cell);
               return;
@@ -279,6 +289,11 @@ pal_peripheral_sata_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
 
           per_info->bdf   = 0; /* NA in DT*/
           per_info->flags = 0; /* NA in DT*/
+          per_info->platform_type = PLATFORM_TYPE_DT;
+
+          if (!(pal_strncmp(sata_dt_compatible[i], "generic-ahci", sizeof("generic-ahci"))))
+            per_info->interface_type = SATA_TYPE_AHCI;
+
           peripheralInfoTable->header.num_sata++;
           per_info++;
           offset =
@@ -317,7 +332,7 @@ pal_peripheral_uart_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
 
   dt_ptr = pal_get_dt_ptr();
   if (dt_ptr == 0) {
-      bsa_print(ACS_PRINT_ERR, L"dt_ptr is NULL \n");
+      bsa_print(ACS_PRINT_ERR, L" dt_ptr is NULL \n");
       return;
   }
 
@@ -331,25 +346,25 @@ pal_peripheral_uart_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
       /* Search for uart nodes*/
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, uart_dt_compatible[i]);
       if (offset < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" UART compatible value not found for index:%d\n", i);
+          bsa_print(ACS_PRINT_DEBUG, L"  UART compatible value not found for index:%d\n", i);
           continue; /* Search for next compatible item*/
       }
 
       /* Get Address_cell & Size_cell length to parse reg property of uart*/
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-      bsa_print(ACS_PRINT_DEBUG, L" Parent Node offset %d\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  Parent Node offset %d\n", offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  size cell %d\n", size_cell);
       if (size_cell < 0) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid size cell :%d\n", size_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid size cell :%d\n", size_cell);
           return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  addr cell %d\n", addr_cell);
       if (addr_cell < 1 || addr_cell > 2) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid address cell : %d \n", addr_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid address cell : %d \n", addr_cell);
           return;
       }
       while (offset != -FDT_ERR_NOTFOUND) {
@@ -358,9 +373,9 @@ pal_peripheral_uart_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
              Status fields either not present or if present should not be disabled */
           Pstatus = (CHAR8 *)fdt_getprop_namelen((void *)dt_ptr, offset, "status", 6, &prop_len);
           if ((prop_len > 0) && (Pstatus != NULL)) {
-              bsa_print(ACS_PRINT_DEBUG, L" Status field length %d\n", prop_len);
+              bsa_print(ACS_PRINT_DEBUG, L"  Status field length %d\n", prop_len);
               if (pal_strncmp(Pstatus, "disabled", 9) == 0) {
-                  bsa_print(ACS_PRINT_DEBUG, L" UART access is secure \n");
+                  bsa_print(ACS_PRINT_DEBUG, L"  UART access is secure \n");
                   offset = fdt_node_offset_by_compatible((const void *)dt_ptr, offset,
                                                           uart_dt_compatible[i]);
                   continue;
@@ -370,7 +385,7 @@ pal_peripheral_uart_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
           /* Get reg property to update base */
           Preg = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
           if ((prop_len < 0) || (Preg == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY REG offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY REG offset %x, Error %d\n", offset, prop_len);
               return;
           }
 
@@ -397,15 +412,15 @@ pal_peripheral_uart_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
           while (range_node_left > 0) {
               Pranges = (UINT32 *)
                   fdt_getprop_namelen((void *)dt_ptr, range_parent_offset, "ranges", 6, &prop_len);
-              bsa_print(ACS_PRINT_DEBUG, L" Parent ranges length %d \n", prop_len);
+              bsa_print(ACS_PRINT_DEBUG, L"  Parent ranges length %d \n", prop_len);
               if ((prop_len < 0) || (Pranges == NULL)) {
-                  bsa_print(ACS_PRINT_DEBUG, L" No ranges is present \n");
+                  bsa_print(ACS_PRINT_DEBUG, L"  No ranges is present \n");
                   range_node_left = 0;
                   break;
               }
               range_node_left--;
               if ((Pranges != NULL) && (prop_len == 0)) {// Empty ranges
-                  bsa_print(ACS_PRINT_DEBUG, L" Empty ranges is present \n");
+                  bsa_print(ACS_PRINT_DEBUG, L"  Empty ranges is present \n");
                   range_parent_offset = fdt_parent_offset((const void *) dt_ptr,
                                                                              range_parent_offset);
               } else {
@@ -416,9 +431,9 @@ pal_peripheral_uart_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
                   parent_addr_cell = fdt_address_cells((const void *) dt_ptr, range_parent_offset);
                   child_size_cell = fdt_size_cells((const void *) dt_ptr, range_node_offset);
 
-                  bsa_print(ACS_PRINT_DEBUG, L" child addr cell %d\n", child_addr_cell);
-                  bsa_print(ACS_PRINT_DEBUG, L" parent addr cell %d\n", parent_addr_cell);
-                  bsa_print(ACS_PRINT_DEBUG, L" child size cell %d\n", child_size_cell);
+                  bsa_print(ACS_PRINT_DEBUG, L"  child addr cell %d\n", child_addr_cell);
+                  bsa_print(ACS_PRINT_DEBUG, L"  parent addr cell %d\n", parent_addr_cell);
+                  bsa_print(ACS_PRINT_DEBUG, L"  child size cell %d\n", child_size_cell);
                   if ((child_addr_cell < 1 || child_addr_cell > 2) ||
                      (parent_addr_cell < 1 || parent_addr_cell > 2) || (child_size_cell < 0))
                       return;
@@ -429,26 +444,26 @@ pal_peripheral_uart_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
                       if (parent_addr_cell == 2)
                           range_node_addr = (range_node_addr << 32) |
                                                 fdt32_to_cpu(Pranges[range_index++]);
-                      bsa_print(ACS_PRINT_DEBUG, L" range node addr %lx\n", range_node_addr);
+                      bsa_print(ACS_PRINT_DEBUG, L"  range node addr %lx\n", range_node_addr);
                       continue;
                   }
                   while (range_index < (prop_len / 4)) {
-                      bsa_print(ACS_PRINT_DEBUG, L" range_index %d\n", range_index);
+                      bsa_print(ACS_PRINT_DEBUG, L"  range_index %d\n", range_index);
                       temp_child_addr = fdt32_to_cpu(Pranges[range_index++]);
                       if (child_addr_cell == 2)
                           temp_child_addr = (temp_child_addr << 32) |
                                                     fdt32_to_cpu(Pranges[range_index++]);
-                      bsa_print(ACS_PRINT_DEBUG, L" temp node addr %lx\n", temp_child_addr);
+                      bsa_print(ACS_PRINT_DEBUG, L"  temp node addr %lx\n", temp_child_addr);
                       if (temp_child_addr == range_node_addr) {
                           parent_offset_addr = fdt32_to_cpu(Pranges[range_index++]);
-                      bsa_print(ACS_PRINT_DEBUG, L" parent offset addr %lx\n", parent_offset_addr);
-                      bsa_print(ACS_PRINT_DEBUG, L" range index %d\n", range_index);
+                      bsa_print(ACS_PRINT_DEBUG, L"  parent offset addr %lx\n", parent_offset_addr);
+                      bsa_print(ACS_PRINT_DEBUG, L"  range index %d\n", range_index);
                           if (parent_addr_cell == 2) {
                               parent_offset_addr = (parent_offset_addr << 32) |
                                                             fdt32_to_cpu(Pranges[range_index++]);
-                      bsa_print(ACS_PRINT_DEBUG, L" 2 parent offset addr %lx\n",
+                      bsa_print(ACS_PRINT_DEBUG, L"  2 parent offset addr %lx\n",
                                                                               parent_offset_addr);
-                      bsa_print(ACS_PRINT_DEBUG, L" 2 range index %d\n", range_index);
+                      bsa_print(ACS_PRINT_DEBUG, L"  2 range index %d\n", range_index);
                           }
                           break;
                       }
@@ -458,22 +473,22 @@ pal_peripheral_uart_create_info_table_dt(PERIPHERAL_INFO_TABLE *peripheralInfoTa
               }
           }
 
-         bsa_print(ACS_PRINT_DEBUG, L" parent offset addr  %lx\n", parent_offset_addr);
+         bsa_print(ACS_PRINT_DEBUG, L"  parent offset addr  %lx\n", parent_offset_addr);
          per_info->base0 += parent_offset_addr;
 
           /* Get interrupts property from frame */
           Pintr = (UINT32 *)
                     fdt_getprop_namelen((void *)dt_ptr, offset, "interrupts", 10, &prop_len);
           if ((prop_len < 0) || (Pintr == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY interrupts offset %x, Error %d\n",
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY interrupts offset %x, Error %d\n",
                         offset, prop_len);
               return;
           }
 
           interrupt_cell = fdt_interrupt_cells((const void *)dt_ptr, offset);
-          bsa_print(ACS_PRINT_DEBUG, L" interrupt_cell  %d\n", interrupt_cell);
+          bsa_print(ACS_PRINT_DEBUG, L"  interrupt_cell  %d\n", interrupt_cell);
           if (interrupt_cell < INTERRUPT_CELLS_MIN || interrupt_cell > INTERRUPT_CELLS_MAX) {
-              bsa_print(ACS_PRINT_ERR, L" Invalid interrupt cell : %d \n", interrupt_cell);
+              bsa_print(ACS_PRINT_ERR, L"  Invalid interrupt cell : %d \n", interrupt_cell);
               return;
           }
 
@@ -523,7 +538,8 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
   EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE *spcr = NULL;
 
   if (peripheralInfoTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input Peripheral Table Pointer is NULL. Cannot create Peripheral INFO \n");
+    bsa_print(ACS_PRINT_ERR,
+              L" Input Peripheral Table Pointer is NULL. Cannot create Peripheral INFO \n");
     return;
   }
 
@@ -541,7 +557,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
           per_info->type  = PERIPHERAL_TYPE_USB;
           per_info->base0 = palPcieGetBase(DeviceBdf, BAR0);
           per_info->bdf   = DeviceBdf;
-          bsa_print(ACS_PRINT_INFO, L"Found a USB controller %4x \n", per_info->base0);
+          bsa_print(ACS_PRINT_INFO, L"  Found a USB controller %4x \n", per_info->base0);
           peripheralInfoTable->header.num_usb++;
           per_info++;
        }
@@ -563,7 +579,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
           per_info->type  = PERIPHERAL_TYPE_SATA;
           per_info->base0 = palPcieGetBase(DeviceBdf, BAR0);
           per_info->bdf   = DeviceBdf;
-          bsa_print(ACS_PRINT_INFO, L"Found a SATA controller %4x \n", per_info->base0);
+          bsa_print(ACS_PRINT_INFO, L"  Found a SATA controller %4x \n", per_info->base0);
           peripheralInfoTable->header.num_sata++;
           per_info++;
        }
@@ -683,8 +699,7 @@ IsDeviceMemory(EFI_MEMORY_TYPE type)
   @brief  This API fills in the MEMORY_INFO_TABLE with information about memory in the
           system. This is achieved by parsing the UEFI memory map.
 
-  @param  peripheralInfoTable  - Address where the Peripheral information needs to be filled.
-
+  @param  memory_info_table Address where the memory info table is created
   @return  None
 **/
 VOID
@@ -703,7 +718,7 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable)
   UINT32                Index, i = 0;
 
   if (memoryInfoTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input Memory Table Pointer is NULL. Cannot create Memory INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input Memory Table Pointer is NULL. Cannot create Memory INFO \n");
     return;
   }
 
@@ -729,7 +744,7 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable)
   if (!EFI_ERROR (Status)) {
     MemoryMapPtr = MemoryMap;
     for (Index = 0; Index < (MemoryMapSize / DescriptorSize); Index++) {
-          bsa_print(ACS_PRINT_INFO, L"Reserved region of type %d [0x%lX, 0x%lX]\n",
+          bsa_print(ACS_PRINT_INFO, L"  Reserved region of type %d [0x%lX, 0x%lX]\n",
             MemoryMapPtr->Type, (UINTN)MemoryMapPtr->PhysicalStart,
             (UINTN)(MemoryMapPtr->PhysicalStart + MemoryMapPtr->NumberOfPages * EFI_PAGE_SIZE));
       if (IsUefiMemory ((EFI_MEMORY_TYPE)MemoryMapPtr->Type)) {
@@ -750,7 +765,7 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable)
       memoryInfoTable->info[i].size      = (MemoryMapPtr->NumberOfPages * EFI_PAGE_SIZE);
       i++;
       if (i >= MEM_INFO_TBL_MAX_ENTRY) {
-        bsa_print(ACS_PRINT_DEBUG, L"Memory Info tbl limit exceeded, Skipping remaining\n", 0);
+        bsa_print(ACS_PRINT_DEBUG, L"  Memory Info tbl limit exceeded, Skipping remaining\n", 0);
         break;
       }
 
@@ -761,6 +776,15 @@ pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable)
 
 }
 
+/**
+  @brief Maps the physical memory region into the virtual address space
+
+  @param ptr Pointer to physical memory region
+  @param size Size
+  @param attr Attributes
+
+  @return Pointer to mapped virtual address space
+**/
 UINT64
 pal_memory_ioremap(VOID *ptr, UINT32 size, UINT32 attr)
 {
@@ -769,7 +793,13 @@ pal_memory_ioremap(VOID *ptr, UINT32 size, UINT32 attr)
   return (UINT64)ptr;
 }
 
+/**
+  @brief Removes the physical memory to virtual address space mapping
+
+  @param ptr Pointer to mapped space
 
+  @return None
+**/
 VOID
 pal_memory_unmap(VOID *ptr)
 {
@@ -812,7 +842,7 @@ pal_memory_get_unpopulated_addr(UINT64 *addr, UINT32 instance)
         if (*addr == 0)
           continue;
 
-        bsa_print(ACS_PRINT_INFO,L"Unpopulated region with base address 0x%lX found\n", *addr);
+        bsa_print(ACS_PRINT_INFO,L"  Unpopulated region with base address 0x%lX found\n", *addr);
         return EFI_SUCCESS;
       }
 
diff --git a/platform/pal_uefi_dt/src/pal_timer_wd.c b/platform/pal_uefi_dt/src/pal_timer_wd.c
index dc7ac667..55836bb6 100644
--- a/platform/pal_uefi_dt/src/pal_timer_wd.c
+++ b/platform/pal_uefi_dt/src/pal_timer_wd.c
@@ -48,7 +48,14 @@ static char wd_dt_arr[][WD_COMPATIBLE_STR_LEN] = {
 UINT64
 pal_get_gtdt_ptr();
 
-/* Information about only one timer can be mentioned as an Override */
+/**
+  @brief This API overrides the timer specified by TimerTable
+         Note: Information about only one timer can be mentioned as an Override
+
+  @param TimerTable Pointer to timer info table
+
+  @return None
+**/
 static
 VOID
 pal_timer_platform_override(TIMER_INFO_TABLE *TimerTable)
@@ -87,20 +94,18 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
   UINT32                      num_of_entries;
 
   if (TimerTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input Timer Table Pointer is NULL. Cannot create Timer INFO \n");
+    bsa_print(ACS_PRINT_ERR, L" Input Timer Table Pointer is NULL. Cannot create Timer INFO \n");
     return;
   }
 
   GtEntry = TimerTable->gt_info;
   TimerTable->header.num_platform_timer = 0;
 
+  pal_timer_create_info_table_dt(TimerTable);
+  return;
+
   gGtdtHdr = (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE *) pal_get_gtdt_ptr();
 
-  if (gGtdtHdr == NULL) {
-    bsa_print(ACS_PRINT_DEBUG, L"GTDT not found & Searching for DT\n");
-    pal_timer_create_info_table_dt(TimerTable);
-    return;
-  }
   bsa_print(ACS_PRINT_INFO, L" GTDT is at %x and length is %x \n", gGtdtHdr, gGtdtHdr->Header.Length);
 
   //Fill in our internal table
@@ -121,21 +126,21 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
   while(num_of_entries) {
 
     if (Entry->Type == EFI_ACPI_6_1_GTDT_GT_BLOCK) {
-      bsa_print(ACS_PRINT_INFO, L"Found block entry \n");
+      bsa_print(ACS_PRINT_INFO, L"  Found block entry \n");
       GtEntry->type = TIMER_TYPE_SYS_TIMER;
       GtEntry->block_cntl_base = Entry->CntCtlBase;
       GtEntry->timer_count     = Entry->GTBlockTimerCount;
-      bsa_print(ACS_PRINT_DEBUG, L"CNTCTLBase = %x \n", GtEntry->block_cntl_base);
+      bsa_print(ACS_PRINT_DEBUG, L"  CNTCTLBase = %x \n", GtEntry->block_cntl_base);
       GtBlockTimer = (EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE *)(((UINT8 *)Entry) + Entry->GTBlockTimerOffset);
       for (i = 0; i < GtEntry->timer_count; i++) {
-        bsa_print(ACS_PRINT_INFO, L"Found timer entry \n");
+        bsa_print(ACS_PRINT_INFO, L"  Found timer entry \n");
         GtEntry->frame_num[i]    = GtBlockTimer->GTFrameNumber;
         GtEntry->GtCntBase[i]    = GtBlockTimer->CntBaseX;
         GtEntry->GtCntEl0Base[i] = GtBlockTimer->CntEL0BaseX;
         GtEntry->gsiv[i]         = GtBlockTimer->GTxPhysicalTimerGSIV;
         GtEntry->virt_gsiv[i]    = GtBlockTimer->GTxVirtualTimerGSIV;
         GtEntry->flags[i]        = GtBlockTimer->GTxPhysicalTimerFlags | (GtBlockTimer->GTxVirtualTimerFlags << 8) | (GtBlockTimer->GTxCommonFlags << 16);
-        bsa_print(ACS_PRINT_DEBUG, L"CNTBaseN = %x for sys counter = %d\n", GtEntry->GtCntBase[i], i);
+        bsa_print(ACS_PRINT_DEBUG, L"  CNTBaseN = %x for sys counter = %d\n", GtEntry->GtCntBase[i], i);
         GtBlockTimer++;
         TimerTable->header.num_platform_timer++;
       }
@@ -155,7 +160,14 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
 
 }
 
-/* Only one watchdog information can be assigned as an override */
+/**
+  @brief This API overrides the watch dog timer specified by WdTable
+         Note: Only one watchdog information can be assigned as an override
+
+  @param WdTable Pointer to watch dog timer info table
+
+  @return None
+**/
 VOID
 pal_wd_platform_override(WD_INFO_TABLE *WdTable)
 {
@@ -190,19 +202,18 @@ pal_wd_create_info_table(WD_INFO_TABLE *WdTable)
   UINT32                      num_of_entries;
 
   if (WdTable == NULL) {
-    bsa_print(ACS_PRINT_ERR, L"Input Watchdog Table Pointer is NULL. Cannot create Watchdog INFO \n");
+    bsa_print(ACS_PRINT_ERR,
+              L" Input Watchdog Table Pointer is NULL. Cannot create Watchdog INFO \n");
     return;
   }
 
   WdEntry = WdTable->wd_info;
   WdTable->header.num_wd = 0;
-  gGtdtHdr = (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE *) pal_get_gtdt_ptr();
 
-  if (gGtdtHdr == NULL) {
-    bsa_print(ACS_PRINT_DEBUG, L"GTDT not found & Searching for DT\n");
-    pal_wd_create_info_table_dt(WdTable);
-    return;
-  }
+  pal_wd_create_info_table_dt(WdTable);
+  return;
+
+  gGtdtHdr = (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE *) pal_get_gtdt_ptr();
 
   Length         = gGtdtHdr->PlatformTimerOffset;
   Entry          = (EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE *) ((UINT8 *)gGtdtHdr + Length);
@@ -222,7 +233,10 @@ pal_wd_create_info_table(WD_INFO_TABLE *WdTable)
       WdEntry->wd_gsiv         = Entry->WatchdogTimerGSIV;
       WdEntry->wd_flags        = Entry->WatchdogTimerFlags;
       WdTable->header.num_wd++;
-      bsa_print(ACS_PRINT_DEBUG, L"Watchdog base = 0x%x INTID = 0x%x \n", WdEntry->wd_ctrl_base, WdEntry->wd_gsiv);
+      bsa_print(ACS_PRINT_DEBUG,
+                L"  Watchdog base = 0x%x INTID = 0x%x \n",
+                WdEntry->wd_ctrl_base,
+                WdEntry->wd_gsiv);
       WdEntry++;
     }
     Entry = (EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE *) ((UINT8 *)Entry + (Entry->Length));
@@ -262,55 +276,55 @@ pal_wd_create_info_table_dt(WD_INFO_TABLE *WdTable)
 
   dt_ptr = pal_get_dt_ptr();
   if (dt_ptr == 0) {
-    bsa_print(ACS_PRINT_ERR, L"dt_ptr is NULL \n");
+    bsa_print(ACS_PRINT_ERR, L" dt_ptr is NULL \n");
     return;
   }
 
   for (i = 0; i < sizeof(wd_dt_arr)/WD_COMPATIBLE_STR_LEN ; i++) {
       offset = fdt_node_offset_by_compatible((const void *)dt_ptr, -1, wd_dt_arr[i]);
       if (offset < 0) {
-          bsa_print(ACS_PRINT_DEBUG, L" WD node offset not found %d \n", offset);
+          bsa_print(ACS_PRINT_DEBUG, L"  WD node offset not found %d \n", offset);
           continue; /* Search for next compatible wd*/
       }
 
       parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-      bsa_print(ACS_PRINT_DEBUG, L" Parent Node offset %d\n", offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  Parent Node offset %d\n", offset);
 
       size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" size cell %d\n", size_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  size cell %d\n", size_cell);
       if (size_cell < 1 || size_cell > 2) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid size cell :%d\n", size_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid size cell :%d\n", size_cell);
           return;
       }
 
       addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" addr cell %d\n", addr_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  addr cell %d\n", addr_cell);
       if (addr_cell < 1 || addr_cell > 2) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid address cell : %d \n", addr_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid address cell : %d \n", addr_cell);
           return;
       }
 
       while (offset != -FDT_ERR_NOTFOUND) {
-          bsa_print(ACS_PRINT_DEBUG, L" WD node:%d offset:%d \n", WdTable->header.num_wd, offset);
+          bsa_print(ACS_PRINT_DEBUG, L"  WD node:%d offset:%d \n", WdTable->header.num_wd, offset);
 
           Preg_val = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
           if ((prop_len < 0) || (Preg_val == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY reg offset %x, Error %d\n", offset, prop_len);
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY reg offset %x, Error %d\n", offset, prop_len);
               return;
           }
 
           Pintr_val =
               (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "interrupts", 10, &prop_len);
           if ((prop_len < 0) || (Pintr_val == NULL)) {
-              bsa_print(ACS_PRINT_ERR, L" PROPERTY interrupts offset %x, Error %d\n",
+              bsa_print(ACS_PRINT_ERR, L"  PROPERTY interrupts offset %x, Error %d\n",
                         offset, prop_len);
               return;
           }
 
           interrupt_cell = fdt_interrupt_cells((const void *)dt_ptr, offset);
-          bsa_print(ACS_PRINT_DEBUG, L" interrupt_cell  %d\n", interrupt_cell);
+          bsa_print(ACS_PRINT_DEBUG, L"  interrupt_cell  %d\n", interrupt_cell);
           if (interrupt_cell < INTERRUPT_CELLS_MIN || interrupt_cell > INTERRUPT_CELLS_MAX) {
-              bsa_print(ACS_PRINT_ERR, L" Invalid interrupt cell : %d \n", interrupt_cell);
+              bsa_print(ACS_PRINT_ERR, L"  Invalid interrupt cell : %d \n", interrupt_cell);
               return;
           }
 
@@ -347,7 +361,7 @@ pal_wd_create_info_table_dt(WD_INFO_TABLE *WdTable)
           switch (intr_flg) /* Interrupt flag*/
           {
             case IRQ_TYPE_NONE:
-              bsa_print(ACS_PRINT_DEBUG, L" interrupt type none\n");
+              bsa_print(ACS_PRINT_DEBUG, L"  interrupt type none\n");
               wd_mode = INTERRUPT_IS_LEVEL_TRIGGERED; /* Set default*/
               wd_polarity = INTERRUPT_IS_ACTIVE_HIGH;
               break;
@@ -368,7 +382,7 @@ pal_wd_create_info_table_dt(WD_INFO_TABLE *WdTable)
               wd_polarity = INTERRUPT_IS_ACTIVE_LOW;
               break;
             default:
-              bsa_print(ACS_PRINT_ERR, L" interrupt type invalid :%X \n",
+              bsa_print(ACS_PRINT_ERR, L"  interrupt type invalid :%X \n",
                         fdt32_to_cpu(Pintr_val[2]));
               return;
           }
@@ -407,7 +421,7 @@ pal_timer_create_info_table_dt(TIMER_INFO_TABLE *TimerTable)
 
   dt_ptr = pal_get_dt_ptr();
   if (dt_ptr == 0) {
-      bsa_print(ACS_PRINT_ERR, L"dt_ptr is NULL \n");
+      bsa_print(ACS_PRINT_ERR, L" dt_ptr is NULL \n");
       return;
   }
 
@@ -435,20 +449,20 @@ pal_timer_create_info_table_dt(TIMER_INFO_TABLE *TimerTable)
   }
   /* Return if Timer node not found*/
   if (offset < 0) {
-      bsa_print(ACS_PRINT_ERR, L" timer node offset not found \n");
+      bsa_print(ACS_PRINT_ERR, L"  timer node offset not found \n");
       return;
   }
   interrupt_cell = fdt_interrupt_cells((const void *)dt_ptr, offset);
-  bsa_print(ACS_PRINT_DEBUG, L" interrupt_cell  %d\n", interrupt_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  interrupt_cell  %d\n", interrupt_cell);
   if (interrupt_cell < INTERRUPT_CELLS_MIN || interrupt_cell > INTERRUPT_CELLS_MAX) {
-      bsa_print(ACS_PRINT_ERR, L" Invalid interrupt cell : %d \n", interrupt_cell);
+      bsa_print(ACS_PRINT_ERR, L"  Invalid interrupt cell : %d \n", interrupt_cell);
       return;
   }
 
     /* Get Interrupt property of timer node*/
   Pintr = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "interrupts", 10, &prop_len);
   if ((prop_len < 0) || (Pintr == NULL)) {
-      bsa_print(ACS_PRINT_ERR, L" PROPERTY interrupts offset %x, Error %d\n", offset, prop_len);
+      bsa_print(ACS_PRINT_ERR, L"  PROPERTY interrupts offset %x, Error %d\n", offset, prop_len);
       return;
   }
 
@@ -492,7 +506,7 @@ pal_timer_create_info_table_dt(TIMER_INFO_TABLE *TimerTable)
       TimerTable->header.virtual_timer_flag  = TIMER_FLAG_ALWAYS_ON;
   }
   else
-    bsa_print(ACS_PRINT_DEBUG, L" PROPERTY always-on not found\n");
+    bsa_print(ACS_PRINT_DEBUG, L"  PROPERTY always-on not found\n");
 
   /* Search for mem mapped timers*/
   for (i = 0; i < sizeof(memtimer_dt_arr)/MEMTIMER_COMPATIBLE_STR_LEN ; i++) {
@@ -501,32 +515,32 @@ pal_timer_create_info_table_dt(TIMER_INFO_TABLE *TimerTable)
         break;
   }
   if (offset < 0) {
-      bsa_print(ACS_PRINT_ERR, L" MEM timer node offset not found \n");
+      bsa_print(ACS_PRINT_ERR, L"  MEM timer node offset not found \n");
       return;
   }
 
   /* Get Address_cell & Size_cell length to parse reg property of timer*/
   parent_offset = fdt_parent_offset((const void *) dt_ptr, offset);
-  bsa_print(ACS_PRINT_DEBUG, L" Parent Node offset %d\n", offset);
+  bsa_print(ACS_PRINT_DEBUG, L"  Parent Node offset %d\n", offset);
 
   size_cell = fdt_size_cells((const void *) dt_ptr, parent_offset);
-  bsa_print(ACS_PRINT_DEBUG, L" size cell %d\n", size_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  size cell %d\n", size_cell);
   if (size_cell < 0) {
-      bsa_print(ACS_PRINT_ERR, L" Invalid size cell :%d\n", size_cell);
+      bsa_print(ACS_PRINT_ERR, L"  Invalid size cell :%d\n", size_cell);
       return;
   }
 
   addr_cell = fdt_address_cells((const void *) dt_ptr, parent_offset);
-  bsa_print(ACS_PRINT_DEBUG, L" addr cell %d\n", addr_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  addr cell %d\n", addr_cell);
   if (addr_cell < 1 || addr_cell > 2) {
-      bsa_print(ACS_PRINT_ERR, L" Invalid address cell : %d \n", addr_cell);
+      bsa_print(ACS_PRINT_ERR, L"  Invalid address cell : %d \n", addr_cell);
       return;
   }
 
   /* Get reg property to update block_cntl_base */
   Preg = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, offset, "reg", 3, &prop_len);
   if ((prop_len < 0) || (Preg == NULL)) {
-      bsa_print(ACS_PRINT_ERR, L" PROPERTY REG offset %x, Error %d\n", offset, prop_len);
+      bsa_print(ACS_PRINT_ERR, L"  PROPERTY REG offset %x, Error %d\n", offset, prop_len);
       return;
   }
 
@@ -539,35 +553,35 @@ pal_timer_create_info_table_dt(TIMER_INFO_TABLE *TimerTable)
 
   /* Get Address_cell & Size_cell length to parse reg property of frame*/
   size_cell = fdt_size_cells((const void *) dt_ptr, offset);
-  bsa_print(ACS_PRINT_DEBUG, L" size cell %d\n", size_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  size cell %d\n", size_cell);
   if (size_cell < 0) {
-      bsa_print(ACS_PRINT_ERR, L" Invalid size cell for timer node :%d\n", size_cell);
+      bsa_print(ACS_PRINT_ERR, L"  Invalid size cell for timer node :%d\n", size_cell);
       return;
   }
 
   addr_cell = fdt_address_cells((const void *) dt_ptr, offset);
-  bsa_print(ACS_PRINT_DEBUG, L" addr cell %d\n", addr_cell);
+  bsa_print(ACS_PRINT_DEBUG, L"  addr cell %d\n", addr_cell);
   if (addr_cell < 1 || addr_cell > 2) {
-      bsa_print(ACS_PRINT_ERR, L" Invalid address cell for timer node: %d \n", addr_cell);
+      bsa_print(ACS_PRINT_ERR, L"  Invalid address cell for timer node: %d \n", addr_cell);
       return;
   }
 
   /* Get frame sub node*/
   subnode_offset = fdt_subnode_offset((const void *)dt_ptr, offset, "frame");
   if (subnode_offset < 0) {
-      bsa_print(ACS_PRINT_DEBUG, L" frame node offset not found %d \n", subnode_offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  frame node offset not found %d \n", subnode_offset);
       return;
   }
 
   while (subnode_offset != -FDT_ERR_NOTFOUND) {
       /* Get frame number*/
       frame_number = fdt_frame_number((const void *)dt_ptr, subnode_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" Frame number is  %d \n", frame_number);
+      bsa_print(ACS_PRINT_DEBUG, L"  Frame number is  %d \n", frame_number);
 
       /* Get reg property from frame to update GtCntBase */
       Preg = (UINT32 *)fdt_getprop_namelen((void *)dt_ptr, subnode_offset, "reg", 3, &prop_len);
       if ((prop_len < 0) || (Preg == NULL)) {
-          bsa_print(ACS_PRINT_ERR, L" PROPERTY REG offset %x, Error %d\n", offset, prop_len);
+          bsa_print(ACS_PRINT_ERR, L"  PROPERTY REG offset %x, Error %d\n", offset, prop_len);
           return;
       }
 
@@ -575,15 +589,15 @@ pal_timer_create_info_table_dt(TIMER_INFO_TABLE *TimerTable)
       Pintr = (UINT32 *)
               fdt_getprop_namelen((void *)dt_ptr, subnode_offset, "interrupts", 10, &prop_len);
       if ((prop_len < 0) || (Pintr == NULL)) {
-          bsa_print(ACS_PRINT_ERR, L" PROPERTY interrupts offset %x, Error %d\n",
+          bsa_print(ACS_PRINT_ERR, L"  PROPERTY interrupts offset %x, Error %d\n",
                     offset, prop_len);
           return;
       }
 
       interrupt_cell = fdt_interrupt_cells((const void *)dt_ptr, subnode_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" interrupt_cell for subnode  %d\n", interrupt_cell);
+      bsa_print(ACS_PRINT_DEBUG, L"  interrupt_cell for subnode  %d\n", interrupt_cell);
       if (interrupt_cell < INTERRUPT_CELLS_MIN || interrupt_cell > INTERRUPT_CELLS_MAX) {
-          bsa_print(ACS_PRINT_ERR, L" Invalid interrupt cell subnode: %d \n", interrupt_cell);
+          bsa_print(ACS_PRINT_ERR, L"  Invalid interrupt cell subnode: %d \n", interrupt_cell);
           return;
       }
 
@@ -633,9 +647,9 @@ pal_timer_create_info_table_dt(TIMER_INFO_TABLE *TimerTable)
       GtEntry->timer_count++;
 
       subnode_offset = fdt_next_subnode((const void *)dt_ptr, subnode_offset);
-      bsa_print(ACS_PRINT_DEBUG, L" timer-mem-fram next node offset %d \n", subnode_offset);
+      bsa_print(ACS_PRINT_DEBUG, L"  timer-mem-fram next node offset %d \n", subnode_offset);
   }
-  bsa_print(ACS_PRINT_DEBUG, L" GT block timer count %d \n", GtEntry->timer_count);
+  bsa_print(ACS_PRINT_DEBUG, L"  GT block timer count %d \n", GtEntry->timer_count);
   TimerTable->header.num_platform_timer = GtEntry->timer_count;
 
   dt_dump_timer_table(TimerTable);
diff --git a/platform/pal_uefi_dt/src_gic_its/bsa_gic_its.c b/platform/pal_uefi_dt/src_gic_its/bsa_gic_its.c
deleted file mode 100644
index edf067ae..00000000
--- a/platform/pal_uefi_dt/src_gic_its/bsa_gic_its.c
+++ /dev/null
@@ -1,591 +0,0 @@
-/** @file
- * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
-**/
-
-#include <Library/ArmGicLib.h>
-#include <Library/ArmLib.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiLib.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-
-#include "Include/IndustryStandard/Acpi61.h"
-#include <Protocol/AcpiTable.h>
-#include <Protocol/HardwareInterrupt.h>
-#include <Protocol/HardwareInterrupt2.h>
-
-#include "bsa_gic_its.h"
-#include "include/pal_uefi.h"
-
-UINT64 ArmReadMpidr(VOID);
-
-extern GIC_ITS_INFO    *g_gic_its_info;
-static UINT32          *g_cwriter_ptr;
-static UINT32           g_its_setup_done = 0;
-
-UINT64
-GetCurrentCpuRDBase (
-  UINT64     mGicRedistributorBase,
-  UINT32     length
-  )
-{
-  UINT64     Mpidr;
-  UINT32     Affinity, CpuAffinity;
-  UINT32     GicRedistributorGranularity;
-  UINT64     GicCpuRedistributorBase;
-
-  Mpidr = ArmReadMpidr();
-
-  CpuAffinity = (Mpidr & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) |
-                ((Mpidr & ARM_CORE_AFF3) >> 8);
-
-  GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE
-                                  + ARM_GICR_SGI_PPI_FRAME_SIZE;
-
-  GicCpuRedistributorBase = mGicRedistributorBase;
-
-  /* If information is present in GICC Structure */
-  if (length == 0)
-  {
-      Affinity = MmioRead32(GicCpuRedistributorBase + ARM_GICR_TYPER + NEXT_DW_OFFSET);
-      if (Affinity == CpuAffinity) {
-        return GicCpuRedistributorBase;
-      }
-      return 0;
-  }
-
-  /* If information is present in GICR Structure */
-  while (GicCpuRedistributorBase < (mGicRedistributorBase + length))
-  {
-    Affinity = MmioRead32(GicCpuRedistributorBase + ARM_GICR_TYPER + NEXT_DW_OFFSET);
-    if (Affinity == CpuAffinity) {
-      return GicCpuRedistributorBase;
-    }
-
-    /* Move to the next GIC Redistributor frame */
-    GicCpuRedistributorBase += GicRedistributorGranularity;
-  }
-
-  return 0;
-}
-
-EFIAPI
-UINT32
-ArmGICDSupportsLPIs (
-  IN  UINT64    GicDistributorBase
-  )
-{
-  return (MmioRead32(GicDistributorBase + ARM_GICD_TYPER) & ARM_GICD_TYPER_LPIS);
-}
-
-EFIAPI
-UINT32
-ArmGICRSupportsLPIs (
-  IN  UINT64    GicRedistributorBase
-  )
-{
-  return (MmioRead32(GicRedistributorBase + ARM_GICR_TYPER) & ARM_GICR_TYPER_PLPIS);
-}
-
-EFIAPI
-EFI_STATUS
-ArmGicSetItsCommandQueueBase (
-  IN  UINT32     ItsIndex
-  )
-{
-  /* Allocate Memory for Command queue. Set command queue base in GITS_CBASER. */
-  EFI_PHYSICAL_ADDRESS      Address;
-  UINT64                    write_value;
-  UINT64                    ItsBase;
-
-  ItsBase = g_gic_its_info->GicIts[ItsIndex].Base;
-
-  Address = (EFI_PHYSICAL_ADDRESS)AllocateAlignedPages(EFI_SIZE_TO_PAGES(NUM_PAGES_8 * SIZE_4KB), SIZE_64KB);
-  if (!Address) {
-    DEBUG ((DEBUG_ERROR, "\n       ITS : Could Not Allocate Memory For Command Q. Test may not pass."));
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  ZeroMem((VOID *)Address, (NUM_PAGES_8*SIZE_4KB));
-
-  g_gic_its_info->GicIts[ItsIndex].CommandQBase = Address;
-  DEBUG((DEBUG_INFO, "%a Address Allocated : %x\n", __func__, Address));
-
-  write_value = MmioRead64(ItsBase + ARM_GITS_CBASER) & (~ARM_GITS_CBASER_PA_MASK);
-  write_value = write_value | (Address & ARM_GITS_CBASER_PA_MASK);
-  write_value = write_value | ARM_GITS_CBASER_VALID;
-  MmioWrite64(ItsBase + ARM_GITS_CBASER, write_value);
-
-  return EFI_SUCCESS;
-}
-
-EFIAPI
-EFI_STATUS
-ArmGicSetItsTables (
-  IN  UINT32     ItsIndex
-  )
-{
-  UINT32                Pages;
-  UINT32                TableSize, entry_size;
-  UINT64                its_baser, its_typer;
-  UINT8                 it, table_type;
-  UINT64                write_value;
-  UINT32                DevBits, CIDBits;
-  EFI_PHYSICAL_ADDRESS  Address;
-  UINT64                ItsBase;
-
-  ItsBase = g_gic_its_info->GicIts[ItsIndex].Base;
-
-  /* Allocate Memory for Table Depending on the Type of the table in GITS_BASER<n>. */
-  for(it=0; it<ARM_NUM_GITS_BASER; it++) {
-
-    its_baser = MmioRead64(ItsBase + ARM_GITS_BASER(it));
-    table_type = ARM_GITS_BASER_GET_TYPE(its_baser);
-    entry_size = ARM_GITS_BASER_GET_ENTRY_SIZE(its_baser);
-
-    its_typer = MmioRead64(ItsBase + ARM_GITS_TYPER);
-    DevBits = ARM_GITS_TYPER_DevBits(its_typer);
-    CIDBits = ARM_GITS_TYPER_CIDBits(its_typer);
-
-    if (table_type == ARM_GITS_TBL_TYPE_DEVICE) {
-      TableSize = (1 << (DevBits+1))*(entry_size+1); // Assuming Single Level Table
-
-    } else if (table_type == ARM_GITS_TBL_TYPE_CLCN) {
-      TableSize = (1 << (CIDBits+1))*(entry_size+1); // Assuming Single Level Table
-
-    } else {
-      continue;
-    }
-
-    Pages = EFI_SIZE_TO_PAGES (TableSize);
-    Address = (EFI_PHYSICAL_ADDRESS)AllocateAlignedPages(Pages, SIZE_64KB);
-    if (!Address) {
-      DEBUG ((DEBUG_ERROR, "\n       ITS : Could Not Allocate Memory For DT/CT. Test may not pass."));
-      return EFI_OUT_OF_RESOURCES;
-    }
-
-    ZeroMem((VOID *)Address, EFI_PAGES_TO_SIZE(Pages));
-
-    write_value = MmioRead64(ItsBase + ARM_GITS_BASER(it));
-    write_value = write_value & (~ARM_GITS_BASER_PA_MASK);
-    write_value = write_value | (Address & ARM_GITS_BASER_PA_MASK);
-    write_value = write_value | ARM_GITS_BASER_VALID;
-    write_value = write_value | (Pages-1);
-    MmioWrite64(ItsBase + ARM_GITS_BASER(it), write_value);
-
-  }
-
-  /* Allocate Memory for Interrupt Translation Table */
-  Address = (EFI_PHYSICAL_ADDRESS)AllocateAlignedPages(EFI_SIZE_TO_PAGES(NUM_PAGES_8 * SIZE_4KB), SIZE_64KB);
-  if (!Address) {
-    DEBUG ((DEBUG_ERROR, "\n       ITS : Could Not Allocate Memory For ITT. Test may not pass."));
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  ZeroMem((VOID *)Address, (NUM_PAGES_8*SIZE_4KB));
-
-  g_gic_its_info->GicIts[ItsIndex].ITTBase = Address;
-
-  return EFI_SUCCESS;
-}
-
-EFIAPI
-VOID
-EnableITS (
-  IN  UINT64    GicItsBase
-  )
-{
-  /* Set GITS_CTLR.Enable as 1 to enable the ITS */
-  UINT32    value;
-
-  value = MmioRead32(GicItsBase + ARM_GITS_CTLR);
-  MmioWrite32(GicItsBase + ARM_GITS_CTLR, (value | ARM_GITS_CTLR_ENABLE));
-}
-
-VOID
-WriteCmdQMAPD (
-  IN UINT32     ItsIndex,
-  IN UINT64     *CMDQ_BASE,
-  IN UINT64     DevID,
-  IN UINT64     ITT_BASE,
-  IN UINT32     Size,
-  IN UINT64     Valid
-  )
-{
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex]), (UINT64)((DevID << ITS_CMD_SHIFT_DEVID) | ARM_ITS_CMD_MAPD));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 1), (UINT64)(Size));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 2), (UINT64)((Valid << ITS_CMD_SHIFT_VALID) | (ITT_BASE & ITT_PAR_MASK)));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0));
-    g_cwriter_ptr[ItsIndex] = g_cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR;
-}
-
-VOID
-WriteCmdQMAPC (
-  IN UINT32     ItsIndex,
-  IN UINT64     *CMDQ_BASE,
-  IN UINT32     DevID,
-  IN UINT32     Clctn_ID,
-  IN UINT32     RDBase,
-  IN UINT64     Valid
-  )
-{
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] ), (UINT64)(ARM_ITS_CMD_MAPC));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 1), (UINT64)(0x0));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 2), (UINT64)((Valid << ITS_CMD_SHIFT_VALID) | RDBase | Clctn_ID));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0));
-    g_cwriter_ptr[ItsIndex] = g_cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR;
-}
-
-VOID
-WriteCmdQMAPI (
-  IN UINT32     ItsIndex,
-  IN UINT64     *CMDQ_BASE,
-  IN UINT64     DevID,
-  IN UINT32     IntID,
-  IN UINT32     Clctn_ID
-  )
-{
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex]), (UINT64)((DevID << ITS_CMD_SHIFT_DEVID) | ARM_ITS_CMD_MAPI));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 1), (UINT64)(IntID));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 2), (UINT64)(Clctn_ID));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0));
-    g_cwriter_ptr[ItsIndex] = g_cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR;
-}
-
-VOID
-WriteCmdQINV (
-  IN UINT32     ItsIndex,
-  IN UINT64     *CMDQ_BASE,
-  IN UINT64     DevID,
-  IN UINT32     IntID
-  )
-{
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex]), (UINT64)((DevID << ITS_CMD_SHIFT_DEVID) | ARM_ITS_CMD_INV));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 1), (UINT64)(IntID));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 2), (UINT64)(0x0));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0));
-    g_cwriter_ptr[ItsIndex] = g_cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR;
-}
-
-VOID
-WriteCmdQDISCARD (
-  IN UINT32     ItsIndex,
-  IN UINT64     *CMDQ_BASE,
-  IN UINT64     DevID,
-  IN UINT32     IntID
-  )
-{
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex]), (UINT64)((DevID << ITS_CMD_SHIFT_DEVID) | ARM_ITS_CMD_DISCARD));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 1), (UINT64)(IntID));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 2), (UINT64)(0x0));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0));
-    g_cwriter_ptr[ItsIndex] = g_cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR;
-}
-
-
-VOID
-WriteCmdQSYNC (
-  IN UINT32     ItsIndex,
-  IN UINT64     *CMDQ_BASE,
-  IN UINT32     RDBase
-  )
-{
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex]), (UINT64)(ARM_ITS_CMD_SYNC));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 1), (UINT64)(0x0));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 2), (UINT64)(RDBase));
-    MmioWrite64((UINT64)(CMDQ_BASE + g_cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0));
-    g_cwriter_ptr[ItsIndex] = g_cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR;
-}
-
-VOID
-PollTillCommandQueueDone (
-  IN UINT32     ItsIndex
-  )
-{
-  UINT32    count;
-  UINT64    creadr_value;
-  UINT64    stall_value;
-  UINT64    cwriter_value;
-  UINT64    ItsBase;
-
-  count = 0;
-  ItsBase = g_gic_its_info->GicIts[ItsIndex].Base;
-  cwriter_value = MmioRead64(ItsBase + ARM_GITS_CWRITER);
-  creadr_value = MmioRead64(ItsBase + ARM_GITS_CREADR);
-
-  while (creadr_value != cwriter_value) {
-    /* Check Stall Value */
-    stall_value = creadr_value & ARM_GITS_CREADR_STALL;
-
-    if (stall_value) {
-      /* Retry */
-      MmioWrite64((ItsBase + ARM_GITS_CWRITER),
-                  (cwriter_value | ARM_GITS_CWRITER_RETRY)
-                 );
-    }
-
-    count++;
-    if (count > WAIT_ITS_COMMAND_DONE) {
-      DEBUG ((DEBUG_ERROR, "\n       ITS : Command Queue READR not moving, Test may not pass."));
-      break;
-    }
-
-    creadr_value = MmioRead64(ItsBase + ARM_GITS_CREADR);
-  }
-
-}
-
-UINT64
-GetRDBaseFormat (
-  IN UINT32     ItsIndex
-  )
-{
-  UINT32    value;
-  UINT64    ItsBase;
-
-  ItsBase = g_gic_its_info->GicIts[ItsIndex].Base;
-
-  /* Check GITS_TYPER.PTA.
-     If PTA = 1 then RDBase = Physical Address,
-     Else RDBase = GICR_TYPER.Processor_Number
-  */
-  value = MmioRead64(ItsBase + ARM_GITS_TYPER);
-  if (value & ARM_GITS_TYPER_PTA) {
-    return g_gic_its_info->GicRdBase;
-  } else {
-    value = MmioRead64(g_gic_its_info->GicRdBase + ARM_GICR_TYPER);
-    return (value & ARM_GICR_TYPER_PN_MASK);
-  }
-}
-
-EFIAPI
-VOID
-ArmGicItsClearLpiMappings (
-  IN UINT32     ItsIndex,
-  IN UINT32     DevID,
-  IN UINT32     IntID
-  )
-{
-  UINT64    value;
-  UINT64    RDBase;
-  UINT64    ItsBase;
-  UINT64    ItsCommandBase;
-
-  if (!g_its_setup_done)
-    return;
-
-  ItsBase        = g_gic_its_info->GicIts[ItsIndex].Base;
-  ItsCommandBase = g_gic_its_info->GicIts[ItsIndex].CommandQBase;
-
-  /* Clear Config table for LPI=IntID */
-  ClearConfigTable(IntID);
-
-  /* Get RDBase Depending on GITS_TYPER.PTA */
-  RDBase = GetRDBaseFormat(ItsIndex);
-
-  /* Discard Mappings */
-  WriteCmdQDISCARD(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, IntID);
-  /* ITS SYNC Command */
-  WriteCmdQSYNC(ItsIndex, (UINT64 *)(ItsCommandBase), RDBase);
-
-  /* Update the CWRITER Register so that all the commands from Command queue gets executed.*/
-  value = ((g_cwriter_ptr[ItsIndex] * NUM_BYTES_IN_DW));
-  MmioWrite64((ItsBase + ARM_GITS_CWRITER), value);
-
-  /* Check CREADR value which ensures Command Queue is processed */
-  PollTillCommandQueueDone(ItsIndex);
-
-}
-
-EFIAPI
-VOID
-ArmGicItsCreateLpiMap (
-  IN UINT32     ItsIndex,
-  IN UINT32     DevID,
-  IN UINT32     IntID,
-  IN UINT32     Priority
-  )
-{
-  UINT64    value;
-  UINT64    RDBase;
-  UINT64    ItsBase;
-  UINT64    ItsCommandBase;
-
-  if (!g_its_setup_done)
-    return;
-
-  ItsBase        = g_gic_its_info->GicIts[ItsIndex].Base;
-  ItsCommandBase = g_gic_its_info->GicIts[ItsIndex].CommandQBase;
-
-  /* Set Config table with enable the LPI = IntID, Priority. */
-  SetConfigTable(IntID, Priority);
-
-  /* Enable Redistributor */
-  EnableLPIsRD(g_gic_its_info->GicRdBase);
-
-  /* Enable ITS */
-  EnableITS(ItsBase);
-
-  /* Get RDBase Depending on GITS_TYPER.PTA */
-  RDBase = GetRDBaseFormat(ItsIndex);
-
-  /* Map Device using MAPD */
-  WriteCmdQMAPD(ItsIndex, (UINT64 *)(ItsCommandBase), DevID,
-                g_gic_its_info->GicIts[ItsIndex].ITTBase,
-                g_gic_its_info->GicIts[ItsIndex].IDBits, 0x1 /*Valid*/);
-  /* Map Collection using MAPC */
-  WriteCmdQMAPC(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, 0x1 /*Clctn_ID*/, RDBase, 0x1 /*Valid*/);
-  /* Map Interrupt using MAPI */
-  WriteCmdQMAPI(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, IntID, 0x1 /*Clctn_ID*/);
-  /* Invalid Entry */
-  WriteCmdQINV(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, IntID);
-  /* ITS SYNC Command */
-  WriteCmdQSYNC(ItsIndex, (UINT64 *)(ItsCommandBase), RDBase);
-
-  /* Update the CWRITER Register so that all the commands from Command queue gets executed.*/
-  value = ((g_cwriter_ptr[ItsIndex] * NUM_BYTES_IN_DW));
-  MmioWrite64((ItsBase + ARM_GITS_CWRITER), value);
-
-  /* Check CREADR value which ensures Command Queue is processed */
-  PollTillCommandQueueDone(ItsIndex);
-
-}
-
-EFIAPI
-UINT32
-ArmGicItsGetMaxLpiID (
-  )
-{
-  UINT32    index;
-  UINT32    min_idbits = ARM_LPI_MAX_IDBITS;
-
-  if ((g_gic_its_info == NULL) || (g_gic_its_info->GicNumIts == 0))
-    return 0;
-
-  if (!g_its_setup_done)
-    return 0;
-
-  /* Return The Minimum IDBits supported in ITS */
-  for (index=0; index<g_gic_its_info->GicNumIts; index++)
-  {
-    min_idbits = (min_idbits < g_gic_its_info->GicIts[index].IDBits)?
-                 (min_idbits):
-                 (g_gic_its_info->GicIts[index].IDBits);
-  }
-  return ((1 << (min_idbits+1)) - 1);
-}
-
-EFIAPI
-UINT64
-ArmGicItsGetGITSTranslatorAddress (
-  IN UINT32     ItsIndex
-  )
-{
-  return (g_gic_its_info->GicIts[ItsIndex].Base + ARM_GITS_TRANSLATER);
-}
-
-EFIAPI
-EFI_STATUS
-SetInitialConfiguration (
-  UINT32     ItsIndex
-  )
-{
-  /* Program GIC Redistributor with the Min ID bits supported. */
-  UINT32    gicd_typer_idbits, gits_typer_bits;
-  UINT64    write_value;
-  UINT64    ItsBase;
-
-  ItsBase = g_gic_its_info->GicIts[ItsIndex].Base;
-
-  gicd_typer_idbits = ARM_GICD_TYPER_IDbits(MmioRead32(g_gic_its_info->GicDBase + ARM_GICD_TYPER));
-  gits_typer_bits = ARM_GITS_TYPER_IDbits(MmioRead64(ItsBase + ARM_GITS_TYPER));
-
-  /* Check least bits implemented is 14 if LPIs are supported. */
-  if (GET_MIN(gicd_typer_idbits, gits_typer_bits) < ARM_LPI_MIN_IDBITS) {
-    return EFI_UNSUPPORTED;
-  }
-
-  write_value = MmioRead64(g_gic_its_info->GicRdBase + ARM_GICR_PROPBASER);
-  write_value |= GET_MIN(gicd_typer_idbits, gits_typer_bits);
-
-  g_gic_its_info->GicIts[ItsIndex].IDBits = GET_MIN(gicd_typer_idbits, gits_typer_bits);
-
-  MmioWrite64((g_gic_its_info->GicRdBase + ARM_GICR_PROPBASER), write_value);
-
-  return EFI_SUCCESS;
-}
-
-EFIAPI
-EFI_STATUS
-ArmGicItsConfiguration (
-  )
-{
-  EFI_STATUS    Status;
-  UINT32        index;
-
-  g_cwriter_ptr = AllocatePool(sizeof(UINT32) * (g_gic_its_info->GicNumIts));
-  if (g_cwriter_ptr == NULL) {
-    DEBUG ((DEBUG_ERROR, "\n       ITS : Could Not Allocate Memory CWriteR. Test may not pass."));
-    return EFI_OUT_OF_RESOURCES;
-  }
-  for (index=0; index<g_gic_its_info->GicNumIts; index++)
-    g_cwriter_ptr[index] = 0;
-
-  for (index=0; index<g_gic_its_info->GicNumIts; index++)
-  {
-    /* Set Initial configuration */
-    Status = SetInitialConfiguration(index);
-    if (EFI_ERROR(Status)) {
-      return Status;
-    }
-  }
-
-  /* Configure Redistributor For LPIs */
-  Status = ArmGicRedistributorConfigurationForLPI(g_gic_its_info->GicDBase, g_gic_its_info->GicRdBase);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  for (index=0; index<g_gic_its_info->GicNumIts; index++)
-  {
-    /* Set Command Queue Base */
-    Status = ArmGicSetItsCommandQueueBase(index);
-    if (EFI_ERROR(Status)) {
-      return Status;
-    }
-
-    /* Set Up the ITS tables */
-    Status = ArmGicSetItsTables(index);
-    if (EFI_ERROR(Status)) {
-      return Status;
-    }
-  }
-
-  g_its_setup_done = 1;
-
-  DEBUG ((DEBUG_INFO, "\n       ITS : Info Block "));
-  for (index=0; index<g_gic_its_info->GicNumIts; index++)
-  {
-      DEBUG ((DEBUG_INFO, "\nGIC ITS Index : %x", index));
-      DEBUG ((DEBUG_INFO, "\nGIC ITS ID : %x", g_gic_its_info->GicIts[index].ID));
-      DEBUG ((DEBUG_INFO, "\nGIC ITS Base : %x\n\n", g_gic_its_info->GicIts[index].Base));
-  }
-
-  return EFI_SUCCESS;
-}
diff --git a/platform/pal_uefi_dt/src_gic_its/bsa_gic_its.h b/platform/pal_uefi_dt/src_gic_its/bsa_gic_its.h
deleted file mode 100644
index a22691bb..00000000
--- a/platform/pal_uefi_dt/src_gic_its/bsa_gic_its.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/** @file
- * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
-**/
-
-#ifndef __BSA_GIC_ITS_H
-#define __BSA_GIC_ITS_H
-
-#include <Library/ArmGicArchLib.h>
-
-#define ARM_LPI_MINID       8192
-#define ARM_LPI_MIN_IDBITS  14
-#define ARM_LPI_MAX_IDBITS  31
-
-#define WAIT_ITS_COMMAND_DONE   10000
-
-/* GICv3 specific registers */
-
-/* Distributor Interrupt Controller Type Register */
-#define ARM_GICD_TYPER          0x0004
-
-/* GICD_TYPER bits */
-#define ARM_GICD_TYPER_LPIS                 (1 << 17) /* LPIS Enable */
-#define ARM_GICD_TYPER_IDbits(GICD_Typer)   ((GICD_Typer >> 19) & 0x1F) /* IDBits implemented */
-
-/* GIC Redistributor Control frame */
-#define ARM_GICR_CTLR           0x0000  /* Redistributor Control Register      */
-#define ARM_GICR_PROPBASER      0x0070  /* Redistributor Config base Register  */
-#define ARM_GICR_PENDBASER      0x0078  /* Redistributor Pending base Register */
-
-#define ARM_GICR_CTLR_ENABLE_LPIS   (1 << 0)
-
-/* GICR_TYPER Bits */
-#define NEXT_DW_OFFSET          0x4         /* Used to read Upper 4 Bytes of GICR_TYPER */
-#define ARM_GICR_TYPER_PLPIS    (1 << 0)
-#define ARM_GICR_TYPER_VLPIS    (1 << 1)
-#define ARM_GICR_TYPER_PN_MASK  (0xFFFF00)
-
-/* GICR_PROPBASER Bits */
-#define ARM_GICR_PROPBASER_IDbits(Propbaser)    (Propbaser & 0x1F) /* IDBits implemented */
-#define PROPBASER_PA_SHIFT                      12
-#define PROPBASER_PA_LEN                        40
-#define ARM_GICR_PROPBASER_PA_MASK              (((1ul << PROPBASER_PA_LEN) - 1) << PROPBASER_PA_SHIFT)
-
-#define PENDBASER_PA_SHIFT                      16
-#define PENDBASER_PA_LEN                        36
-#define ARM_GICR_PENDBASER_PA_MASK              (((1ul << PENDBASER_PA_LEN) - 1) << PENDBASER_PA_SHIFT)
-
-/* GIC ITS Register Offset from ITS_CTRL_BASE */
-#define ARM_GITS_CTLR               0x0000
-#define ARM_GITS_IIDR               0x0004
-#define ARM_GITS_TYPER              0x0008
-#define ARM_GITS_CBASER             0x0080
-#define ARM_GITS_CWRITER            0x0088
-#define ARM_GITS_CREADR             0x0090
-#define ARM_GITS_BASER(n)           (0x0100 + 8*n)
-
-#define ARM_GITS_TRANSLATER         0x10040
-
-/* GITS_CTLR Register Bits */
-#define ARM_GITS_CTLR_ENABLE        (1 << 0)
-
-/* GITS_BASER Register Bits */
-#define ARM_NUM_GITS_BASER                          8
-#define ARM_GITS_BASER_INDIRECT                     (1ul << 62)
-#define ARM_GITS_BASER_GET_TYPE(gits_baser)         ((gits_baser >> 56) & 0x7)
-#define ARM_GITS_BASER_GET_ENTRY_SIZE(gits_baser)   ((gits_baser >> 48) & 0x1F)
-#define BASER_PA_SHIFT                              12
-#define BASER_PA_LEN                                36
-#define ARM_GITS_BASER_PA_MASK                      (((1ul << BASER_PA_LEN) - 1) << BASER_PA_SHIFT)
-#define ARM_GITS_BASER_VALID                        (1ul << 63)
-
-#define ARM_GITS_TBL_TYPE_DEVICE    0x1
-#define ARM_GITS_TBL_TYPE_CLCN      0x4
-
-/* GITS_TYPER Bits */
-#define ARM_GITS_TYPER_DevBits(its_typer)           ((its_typer >> 13) & 0x1F)
-#define ARM_GITS_TYPER_CIDBits(its_typer)           ((its_typer >> 32) & 0xF)
-#define ARM_GITS_TYPER_IDbits(its_typer)            ((its_typer >> 8) & 0x1F)
-#define ARM_GITS_TYPER_PTA                          (1 << 19)
-
-/* GITS_CREADR Bits */
-#define ARM_GITS_CREADR_STALL       (1 << 0)
-
-/* GITS_CWRITER Bits */
-#define ARM_GITS_CWRITER_RETRY      (1 << 0)
-
-/* GITS_CBASER Bits */
-#define ARM_GITS_CBASER_VALID           (1ul << 63)
-#define CBASER_PA_SHIFT                 12
-#define CBASER_PA_LEN                   40
-#define ARM_GITS_CBASER_PA_MASK         (((1ul << CBASER_PA_LEN) - 1) << CBASER_PA_SHIFT)
-#define ITT_PAR_SHIFT                   8
-#define ITT_PAR_LEN                     44
-#define ITT_PAR_MASK                    (((1ul << ITT_PAR_LEN) - 1) << ITT_PAR_SHIFT)
-
-#define GET_CONFIG_TABLE_SIZE_BY_BITS(gicd_idbits, gicr_idbits)  ((gicd_idbits < gicr_idbits)?((1 << (gicd_idbits+1)) - 8192):((1 << (gicr_idbits+1)) - 8192))
-#define GET_MIN(a,b)    ((a<b)?a:b)
-#define GET_PENDING_TABLE_SIZE_BY_BITS(gicd_idbits, gicr_idbits)  ((gicd_idbits < gicr_idbits)?((1 << (gicd_idbits+1))/8):((1 << (gicr_idbits+1))/8))
-
-#define LPI_ID1     0x203A
-#define LPI_ID2     0x203B
-#define LPI_ID3     0x203C
-#define LPI_ID4     0x203D
-
-#define LPI_PRIORITY1       0x50
-#define LPI_PRIORITY2       0x60
-#define LPI_PRIORITY3       0x70
-#define LPI_PRIORITY4       0x80
-#define LPI_PRIORITY_MASK   0xFC
-#define LPI_ENABLE          (1 << 0)
-#define LPI_DISABLE         0x0
-
-#define ARM_ITS_CMD_MAPD    0x8
-#define ARM_ITS_CMD_MAPC    0x9
-#define ARM_ITS_CMD_MAPI    0xB
-#define ARM_ITS_CMD_INV     0xC
-#define ARM_ITS_CMD_DISCARD 0xF
-#define ARM_ITS_CMD_SYNC    0x5
-
-#define NUM_PAGES_8         8
-
-#define ITS_CMD_SHIFT_DEVID 32
-#define ITS_CMD_SHIFT_VALID 63
-#define ITS_NEXT_CMD_PTR    4
-#define NUM_BYTES_IN_DW     8
-
-EFIAPI
-EFI_STATUS
-ArmGicRedistributorConfigurationForLPI (
-  IN  UINT64    GicDistributorBase,
-  IN  UINT64    GicRedistributorBase
-  );
-
-EFIAPI
-VOID
-ClearConfigTable (
-  IN  UINT32    IntID
-  );
-
-EFIAPI
-VOID
-SetConfigTable (
-  IN  UINT32    IntID,
-  IN  UINT32    Priority
-  );
-
-EFIAPI
-UINT32
-ArmGICDSupportsLPIs (
-  IN  UINT64    GicDistributorBase
-  );
-
-EFIAPI
-UINT32
-ArmGICRSupportsLPIs (
-  IN  UINT64    GicRedistributorBase
-  );
-
-EFIAPI
-VOID
-ArmGicItsClearLpiMappings (
-  IN UINT32     ItsIndex,
-  IN UINT32     DevID,
-  IN UINT32     IntID
-  );
-
-EFIAPI
-VOID
-ArmGicItsCreateLpiMap (
-  IN UINT32     ItsIndex,
-  IN UINT32     DevID,
-  IN UINT32     IntID,
-  IN UINT32     Priority
-  );
-
-EFIAPI
-UINT64
-ArmGicItsGetGITSTranslatorAddress (
-  IN UINT32     ItsIndex
-  );
-
-EFIAPI
-UINT32
-ArmGicItsGetMaxLpiID (
-  );
-
-EFIAPI
-EFI_STATUS
-ArmGicItsConfiguration (
-  );
-
-UINT64
-GetCurrentCpuRDBase (
-  UINT64    mGicRedistributorBase,
-  UINT32    length
-  );
-
-EFIAPI
-VOID
-EnableLPIsRD (
-  IN  UINT64    GicRedistributorBase
-  );
-
-typedef struct {
- UINT32     ID;
- UINT64     Base;
- UINT64     CommandQBase;
- UINT32     IDBits;
- UINT64     ITTBase;
-} GIC_ITS_BLOCK;
-
-typedef struct {
- UINT64         GicDBase;
- UINT64         GicRdBase;
- UINT32         GicNumIts;
- GIC_ITS_BLOCK  GicIts[];
-} GIC_ITS_INFO;
-
-#endif
diff --git a/platform/pal_uefi_dt/src_gic_its/bsa_gic_redistributor.c b/platform/pal_uefi_dt/src_gic_its/bsa_gic_redistributor.c
deleted file mode 100644
index 2a735057..00000000
--- a/platform/pal_uefi_dt/src_gic_its/bsa_gic_redistributor.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/** @file
- * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
-**/
-
-#include <Library/ArmGicLib.h>
-#include <Library/BaseLib.h>
-#include <Library/BaseMemoryLib.h>
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/MemoryAllocationLib.h>
-#include <Library/UefiLib.h>
-#include <Library/IoLib.h>
-#include <Library/DebugLib.h>
-
-#include "Include/IndustryStandard/Acpi61.h"
-#include <Protocol/AcpiTable.h>
-#include <Protocol/HardwareInterrupt.h>
-#include <Protocol/HardwareInterrupt2.h>
-
-#include "bsa_gic_its.h"
-
-static UINT64 ConfigBase;
-
-EFIAPI
-EFI_STATUS
-ArmGicSetItsConfigTableBase (
-  IN  UINT64    GicDistributorBase,
-  IN  UINT64    GicRedistributorBase
-  )
-{
-  /* Allocate Memory for Redistributor Configuration Table */
-  /* Set GICR_PROPBASER with the Config table base */
-  EFI_STATUS            Status;
-  EFI_PHYSICAL_ADDRESS  Address;
-  UINT32                Pages;
-  UINT32                ConfigTableSize;
-  UINT64                write_value;
-  UINT32                gicr_propbaser_idbits;
-
-  /* Get Memory size by reading the GICR_PROPBASER.IDBits field */
-  gicr_propbaser_idbits = ARM_GICR_PROPBASER_IDbits(MmioRead64(GicRedistributorBase + ARM_GICR_PROPBASER));
-  ConfigTableSize = ((1 << (gicr_propbaser_idbits+1)) - ARM_LPI_MINID);
-
-  Pages = EFI_SIZE_TO_PAGES (ConfigTableSize) + 1;
-
-  Status = gBS->AllocatePages (
-                    AllocateAnyPages,
-                    EfiBootServicesData,
-                    Pages,
-                    &Address
-                    );
-  if (EFI_ERROR (Status)) {
-      DEBUG ((DEBUG_ERROR, "\n       ITS : Could Not Allocate Memory For Config Table. Test may not pass."));
-      return Status;
-  }
-  ZeroMem((VOID *)Address, EFI_PAGES_TO_SIZE(Pages));
-
-  write_value = MmioRead64(GicRedistributorBase + ARM_GICR_PROPBASER);
-  write_value = write_value & (~ARM_GICR_PROPBASER_PA_MASK);
-  write_value = write_value | (Address & ARM_GICR_PROPBASER_PA_MASK);
-  MmioWrite64(GicRedistributorBase + ARM_GICR_PROPBASER, write_value);
-
-  ConfigBase = Address;
-
-  return EFI_SUCCESS;
-}
-
-EFIAPI
-EFI_STATUS
-ArmGicSetItsPendingTableBase (
-  IN  UINT64    GicDistributorBase,
-  IN  UINT64    GicRedistributorBase
-  )
-{
-  /* Allocate Memory for Pending Table for each Redistributor*/
-  /* Set GICR_PENDBASER with the Config table base */
-  EFI_PHYSICAL_ADDRESS  Address;
-  UINT32                Pages;
-  UINT32                PendingTableSize;
-  UINT64                write_value;
-  UINT32                gicr_propbaser_idbits;
-
-  /* Get Memory size by reading the GICD_TYPER.IDBits, GICR_PROPBASER.IDBits field */
-  gicr_propbaser_idbits = ARM_GICR_PROPBASER_IDbits(MmioRead64(GicRedistributorBase + ARM_GICR_PROPBASER));
-  PendingTableSize = ((1 << (gicr_propbaser_idbits+1))/8);
-
-  Pages = EFI_SIZE_TO_PAGES (PendingTableSize) + 1;
-
-  Address = (EFI_PHYSICAL_ADDRESS)AllocateAlignedPages(Pages, SIZE_64KB);
-  if (!Address) {
-    DEBUG ((DEBUG_ERROR, "\n       ITS : Could Not Allocate Memory For Pending Table. Test may not pass."));
-    return EFI_OUT_OF_RESOURCES;
-  }
-
-  ZeroMem((VOID *)Address, EFI_PAGES_TO_SIZE(Pages));
-
-  write_value = MmioRead64(GicRedistributorBase + ARM_GICR_PENDBASER);
-  write_value = write_value & (~ARM_GICR_PENDBASER_PA_MASK);
-  write_value = write_value | (Address & ARM_GICR_PENDBASER_PA_MASK);
-  MmioWrite64(GicRedistributorBase + ARM_GICR_PENDBASER, write_value);
-
-  return EFI_SUCCESS;
-}
-
-EFIAPI
-VOID
-ClearConfigTable (
-  IN  UINT32          IntID
-  )
-{
-  MmioWrite8(ConfigBase + (IntID - ARM_LPI_MINID), LPI_DISABLE);
-}
-
-EFIAPI
-VOID
-SetConfigTable (
-  IN  UINT32          IntID,
-  IN  UINT32          Priority
-  )
-{
-  UINT8    value;
-
-  value = (Priority & LPI_PRIORITY_MASK) | LPI_ENABLE;
-  MmioWrite8(ConfigBase + (IntID - ARM_LPI_MINID), value);
-}
-
-EFIAPI
-VOID
-EnableLPIsRD (
-  IN  UINT64    GicRedistributorBase
-  )
-{
-  UINT32    value;
-  value = MmioRead32(GicRedistributorBase + ARM_GICR_CTLR);
-
-  MmioWrite32(GicRedistributorBase + ARM_GICR_CTLR,
-              (value | ARM_GICR_CTLR_ENABLE_LPIS));
-}
-
-EFIAPI
-EFI_STATUS
-ArmGicRedistributorConfigurationForLPI (
-  IN  UINT64    GicDistributorBase,
-  IN  UINT64    GicRedistributorBase
-  )
-{
-  EFI_STATUS    Status;
-  /* Set Configuration Table Base */
-  Status = ArmGicSetItsConfigTableBase(GicDistributorBase, GicRedistributorBase);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  /* Set Pending Table Base For Each Redistributor */
-  Status = ArmGicSetItsPendingTableBase(GicDistributorBase, GicRedistributorBase);
-  if (EFI_ERROR(Status)) {
-    return Status;
-  }
-
-  return Status;
-}
diff --git a/test_pool/exerciser/operating_system/test_os_e001.c b/test_pool/exerciser/operating_system/test_os_e001.c
index 02bfe5d1..ad223ba5 100644
--- a/test_pool/exerciser/operating_system/test_os_e001.c
+++ b/test_pool/exerciser/operating_system/test_os_e001.c
@@ -24,6 +24,7 @@
 #include "val/include/bsa_acs_smmu.h"
 #include "val/include/bsa_acs_memory.h"
 #include "val/include/bsa_acs_exerciser.h"
+#include "val/include/bsa_acs_pcie.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 1)
 #define TEST_RULE  "PCI_PP_04"
@@ -39,6 +40,9 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf,
   uint32_t e_bdf;
   uint32_t instance;
   uint32_t cap_base;
+  uint32_t req_rp_ecam_index;
+  uint32_t erp_ecam_index;
+  uint32_t status;
 
   instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
 
@@ -68,6 +72,23 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf,
 
       if (req_rp_bdf != erp_bdf)
       {
+          status = val_pcie_get_ecam_index(req_rp_bdf, &req_rp_ecam_index);
+          if (status)
+          {
+             val_print(ACS_PRINT_ERR, "\n       Error Ecam index for req RP BDF: 0x%x", req_rp_bdf);
+             goto clean_fail;
+          }
+
+          status = val_pcie_get_ecam_index(erp_bdf, &erp_ecam_index);
+          if (status)
+          {
+             val_print(ACS_PRINT_ERR, "\n       Error Ecam index for tgt RP BDF: 0x%x", erp_bdf);
+             goto clean_fail;
+          }
+
+          if (req_rp_ecam_index != erp_ecam_index)
+              continue;
+
           *tgt_e_bdf = e_bdf;
           *tgt_rp_bdf = erp_bdf;
 
@@ -80,6 +101,7 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf,
       }
   }
 
+clean_fail:
   /* Return failure if No Such Exerciser Found */
   *tgt_e_bdf = 0;
   *tgt_rp_bdf = 0;
@@ -102,7 +124,7 @@ check_source_validation (uint32_t req_instance, uint32_t req_e_bdf,
   val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)bar_base, 1, req_instance);
 
   if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance)) {
-      val_print(ACS_PRINT_DEBUG, "\n       DMA failure from exerciser %4x", req_instance);
+      val_print(ACS_PRINT_ERR, "\nSrc Validation 1st DMA failure from exerciser %4x", req_instance);
       return ACS_STATUS_FAIL;
   }
 
@@ -117,12 +139,13 @@ check_source_validation (uint32_t req_instance, uint32_t req_e_bdf,
   sub_bus = (reg_value >> SUBBN_SHIFT) & SUBBN_MASK;
   new_bdf = PCIE_CREATE_BDF(PCIE_EXTRACT_BDF_SEG(req_rp_bdf),
                             (sub_bus+1), 0, 0);
+  new_bdf = PCIE_CREATE_BDF_PACKED(new_bdf);
 
   val_exerciser_set_param(CFG_TXN_ATTRIBUTES, TXN_REQ_ID, new_bdf, req_instance);
   val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)bar_base, 1, req_instance);
 
-  if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance)) {
-      val_print(ACS_PRINT_DEBUG, "\n       DMA failure from exerciser %4x", req_instance);
+  if (!val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance)) {
+      val_print(ACS_PRINT_ERR, "\nSrc Validation 2nd DMA failure from exerciser %4x", req_instance);
       return ACS_STATUS_FAIL;
   }
 
@@ -132,7 +155,7 @@ check_source_validation (uint32_t req_instance, uint32_t req_e_bdf,
   if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) &&
      (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) {
       /* Fail the part */
-      val_print(ACS_PRINT_DEBUG,
+      val_print(ACS_PRINT_ERR,
                      "\n       Src Validation Expected Error RootPort : 0x%x", req_rp_bdf);
       return ACS_STATUS_FAIL;
   }
@@ -157,8 +180,8 @@ check_transaction_blocking (uint32_t req_instance, uint32_t req_e_bdf,
   val_exerciser_set_param(CFG_TXN_ATTRIBUTES, TXN_ADDR_TYPE, AT_RESERVED, req_instance);
   val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)bar_base, 1, req_instance);
 
-  if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance)) {
-      val_print(ACS_PRINT_DEBUG, "\n       DMA failure from exerciser %4x", req_instance);
+  if (!val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance)) {
+      val_print(ACS_PRINT_ERR, "\n Traxn blocking DMA failure from exerciser %4x", req_instance);
       return ACS_STATUS_FAIL;
   }
 
@@ -168,7 +191,7 @@ check_transaction_blocking (uint32_t req_instance, uint32_t req_e_bdf,
   if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) &&
      (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) {
       /* Fail the part */
-      val_print(ACS_PRINT_DEBUG,
+      val_print(ACS_PRINT_ERR,
                       "\n       Traxn Blocking Expected Error RootPort : 0x%x", req_rp_bdf);
       return ACS_STATUS_FAIL;
   }
@@ -203,7 +226,7 @@ payload(void)
   /* Check If PCIe Hierarchy supports P2P. */
   if (val_pcie_p2p_support())
   {
-    val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+    val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
     return;
   }
 
@@ -235,27 +258,34 @@ payload(void)
       /* Find another exerciser on other rootport,
          Break from the test if no such exerciser if found */
       if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base))
-          break;
+          continue;
 
-      /* If Both RP's Supports ACS Then Only Run Otherwise Skip the EP */
+      /* Enable Source Validation & Transaction Blocking */
+      val_pcie_read_cfg(tgt_rp_bdf, cap_base + ACSCR_OFFSET, &reg_value);
+      reg_value = reg_value | (1 << ACS_CTRL_SVE_SHIFT) | (1 << ACS_CTRL_TBE_SHIFT);
+      val_pcie_write_cfg(tgt_rp_bdf, cap_base + ACSCR_OFFSET, reg_value);
       test_skip = 0;
 
       /* Check For ACS Functionality */
       status = check_source_validation(instance, req_e_bdf, req_rp_bdf, tgt_e_bdf, bar_base);
       if (status == ACS_STATUS_SKIP)
-          val_print(ACS_PRINT_DEBUG, "\n     ACS Source Validation Skipped for 0x%x", req_rp_bdf);
+          val_print(ACS_PRINT_DEBUG, "\n       ACS Source Validation Skipped for 0x%x", req_rp_bdf);
       else if (status)
           curr_bdf_failed++;
 
+      val_exerciser_set_param(CFG_TXN_ATTRIBUTES, TXN_REQ_ID, RID_NOT_VALID, instance);
+
       status = check_transaction_blocking(instance, req_e_bdf, req_rp_bdf, tgt_e_bdf, bar_base);
       if (status == ACS_STATUS_SKIP)
           val_print(ACS_PRINT_DEBUG,
-                    "\n     ACS Transaction Blocking Skipped for 0x%x", req_rp_bdf);
+                    "\n       ACS Transaction Blocking Skipped for 0x%x", req_rp_bdf);
       else if (status)
           curr_bdf_failed++;
 
       if (curr_bdf_failed > 0) {
-          val_print(ACS_PRINT_ERR, "\n     ACS Functional Check Failed, RP Bdf : 0x%x", req_rp_bdf);
+          val_print(ACS_PRINT_ERR,
+                    "\n       ACS Functional Check Failed, RP Bdf : 0x%x",
+                    req_rp_bdf);
           curr_bdf_failed = 0;
           fail_cnt++;
       }
@@ -265,11 +295,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/exerciser/operating_system/test_os_e002.c b/test_pool/exerciser/operating_system/test_os_e002.c
index c4193802..e6422d3a 100644
--- a/test_pool/exerciser/operating_system/test_os_e002.c
+++ b/test_pool/exerciser/operating_system/test_os_e002.c
@@ -132,7 +132,8 @@ create_va_pa_mapping (uint64_t txn_va, uint64_t txn_pa,
      val_smmu_enable(instance);
 
   /* Get SMMU node index for this exerciser instance */
-  master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf));
+  master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf),
+                                                    PCIE_CREATE_BDF_PACKED(e_bdf));
 
   if (master.smmu_index != ACS_INVALID_INDEX &&
       val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, master.smmu_index) == 3) {
@@ -167,7 +168,7 @@ create_va_pa_mapping (uint64_t txn_va, uint64_t txn_pa,
       /* Configure SMMU tables for this exerciser to use this page table for VA to PA translations*/
       if (val_smmu_map(master, pgt_desc))
       {
-          val_print(ACS_PRINT_DEBUG, "\n      SMMU mapping failed (%x)     ", e_bdf);
+          val_print(ACS_PRINT_DEBUG, "\n       SMMU mapping failed (%x)     ", e_bdf);
           return ACS_STATUS_FAIL;
       }
       return ACS_STATUS_PASS;
@@ -330,7 +331,7 @@ payload(void)
   /* Check If PCIe Hierarchy supports P2P. */
   if (val_pcie_p2p_support())
   {
-    val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+    val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
     return;
   }
 
@@ -367,9 +368,9 @@ payload(void)
       }
 
       /* Find another exerciser on other rootport,
-         Break from the test if no such exerciser if found */
+         Skip the current exerciser if no such exerciser if found */
       if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base))
-          break;
+          continue;
 
       /* If Both RP's Supports ACS Then Only Run Otherwise Skip the EP */
       test_skip = 0;
@@ -387,11 +388,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/exerciser/operating_system/test_os_e003.c b/test_pool/exerciser/operating_system/test_os_e003.c
index eb061cb1..34a6469b 100644
--- a/test_pool/exerciser/operating_system/test_os_e003.c
+++ b/test_pool/exerciser/operating_system/test_os_e003.c
@@ -293,7 +293,7 @@ barspace_transactions_order_check(void)
 
     if (!baseptr) {
         val_print(ACS_PRINT_ERR, "\n       Failed in BAR ioremap for instance %x", instance);
-        continue;;
+        continue;
     }
 
     /* Test Scenario 1 : Transactions on incremental aligned address */
@@ -322,14 +322,14 @@ payload(void)
   barspace_transactions_order_check();
 
   if (!run_flag) {
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
   if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/exerciser/operating_system/test_os_e004.c b/test_pool/exerciser/operating_system/test_os_e004.c
index 48cce235..5a7b7609 100644
--- a/test_pool/exerciser/operating_system/test_os_e004.c
+++ b/test_pool/exerciser/operating_system/test_os_e004.c
@@ -18,6 +18,7 @@
 #include "val/include/val_interface.h"
 
 #include "val/include/bsa_acs_pcie.h"
+#include "val/include/bsa_acs_gic.h"
 #include "val/include/bsa_acs_memory.h"
 #include "val/include/bsa_acs_iovirt.h"
 #include "val/include/bsa_acs_smmu.h"
@@ -25,7 +26,7 @@
 #include "val/include/bsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 4)
-#define TEST_RULE  "PCI_MSI_2"
+#define TEST_RULE  "PCI_MSI_2,ITS_DEV_6"
 #define TEST_DESC  "MSI(-X) triggers intr with unique ID  "
 
 static uint32_t irq_pending;
@@ -59,16 +60,16 @@ payload (void)
   uint32_t msi_index = 0;
   uint32_t msi_cap_offset = 0;
 
-  uint32_t req_id = 0;
   uint32_t device_id = 0;
   uint32_t stream_id = 0;
   uint32_t its_id = 0;
+  uint64_t its_base = 0;
 
   index = val_pe_get_index_mpid (val_pe_get_mpid());
 
   if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) {
-      val_print(ACS_PRINT_DEBUG, "\n      No ITS, Skipping Test.\n", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_print(ACS_PRINT_DEBUG, "\n       No ITS, Skipping Test.\n", 0);
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -99,16 +100,13 @@ payload (void)
     test_skip = 0;
 
     /* Get DeviceID & ITS_ID for this device */
-    req_id = GET_DEVICE_ID(PCIE_EXTRACT_BDF_BUS(e_bdf),
-                           PCIE_EXTRACT_BDF_DEV(e_bdf),
-                           PCIE_EXTRACT_BDF_FUNC(e_bdf));
-
-    status = val_iovirt_get_device_info(req_id, PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id,
+    status = val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf),
+                                        PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id,
                                         &stream_id, &its_id);
     if (status) {
         val_print(ACS_PRINT_ERR,
             "\n       Could not get device info for BDF : 0x%x", e_bdf);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
         return;
     }
 
@@ -116,7 +114,7 @@ payload (void)
     if (status) {
         val_print(ACS_PRINT_ERR,
             "\n       MSI Assignment failed for bdf : 0x%x", e_bdf);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
         return;
     }
 
@@ -125,14 +123,41 @@ payload (void)
     if (status) {
         val_print(ACS_PRINT_ERR,
             "\n       Intr handler registration failed Interrupt : 0x%x", lpi_int_id + instance);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
         return;
     }
 
     /* Set the interrupt trigger status to pending */
     irq_pending = 1;
 
-    /* Trigger the interrupt */
+    /* Get ITS Base for current ITS */
+    if (val_gic_its_get_base(its_id, &its_base)) {
+        val_print(ACS_PRINT_ERR,
+            "\n       Could not find ITS Base for its_id : 0x%x", its_id);
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
+        return;
+    }
+
+    /* Part 1 : ITS_DEV_6 */
+    /* Trigger the interrupt by writing to GITS_TRANSLATER from PE */
+    val_mmio_write(its_base + GITS_TRANSLATER, lpi_int_id + instance);
+
+    /* PE busy polls to check the completion of interrupt service routine */
+    timeout = TIMEOUT_MEDIUM;
+    while ((--timeout > 0) && irq_pending)
+        {};
+
+    /* Interrupt should not be generated */
+    if (irq_pending == 0) {
+        val_print(ACS_PRINT_ERR,
+            "\n       Interrupt triggered from PE for bdf : 0x%x, ", e_bdf);
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 5));
+        val_gic_free_msi(e_bdf, device_id, its_id, lpi_int_id + instance, msi_index);
+        return;
+    }
+
+    /* Part 2: PCI_MSI_2 */
+    /* Trigger the interrupt for this Exerciser instance */
     val_exerciser_ops(GENERATE_MSI, msi_index, instance);
 
     /* PE busy polls to check the completion of interrupt service routine */
@@ -145,7 +170,7 @@ payload (void)
             "\n       Interrupt trigger failed for : 0x%x, ", lpi_int_id + instance);
         val_print(ACS_PRINT_ERR,
             "BDF : 0x%x   ", e_bdf);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 6));
         val_gic_free_msi(e_bdf, device_id, its_id, lpi_int_id + instance, msi_index);
         return;
     }
@@ -156,12 +181,12 @@ payload (void)
   }
 
   if (test_skip) {
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
   /* Pass Test */
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/exerciser/operating_system/test_os_e005.c b/test_pool/exerciser/operating_system/test_os_e005.c
index 78a93c9a..8b625f84 100644
--- a/test_pool/exerciser/operating_system/test_os_e005.c
+++ b/test_pool/exerciser/operating_system/test_os_e005.c
@@ -99,7 +99,8 @@ payload(void)
   memory_region_descriptor_t mem_desc_array[2], *mem_desc;
   smmu_master_attributes_t master = {0, 0, 0, 0, 0};
   pgt_descriptor_t pgt_desc;
-  uint64_t ttbr, exerciser_ssid_bits;
+  uint64_t ttbr;
+  uint32_t exerciser_ssid_bits, status;
   uint64_t pgt_base_pasid1 = 0;
   uint64_t pgt_base_pasid2 = 0;
 
@@ -116,8 +117,8 @@ payload(void)
   /* Allocate 2 test buffers, one for each pasid */
   dram_buf_base_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES * 2);
   if (!dram_buf_base_virt) {
-      val_print(ACS_PRINT_ERR, "\n      Cacheable mem alloc failure %x", 02);
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+      val_print(ACS_PRINT_ERR, "\n       Cacheable mem alloc failure %x", 2);
+      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
       return;
   }
 
@@ -135,14 +136,14 @@ payload(void)
   /* Get translation attributes via TCR and translation table base via TTBR */
   if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr))
   {
-    val_print(ACS_PRINT_ERR, "\n      TCR read failure %x", 03);
-    val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03));
+    val_print(ACS_PRINT_ERR, "\n       TCR read failure %x", 3);
+    val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3));
     return;
   }
   if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr))
   {
-    val_print(ACS_PRINT_ERR, "\n      TTBR0 read failure %x", 04);
-    val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04));
+    val_print(ACS_PRINT_ERR, "\n       TTBR0 read failure %x", 4);
+    val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4));
     return;
   }
   pgt_desc.pgt_base = (ttbr & AARCH64_TTBR_ADDR_MASK);
@@ -168,7 +169,8 @@ payload(void)
     e_bdf = val_exerciser_get_bdf(instance);
 
     /* Find SMMU node index for this pcie endpoint */
-    master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf));
+    master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf),
+                                                     PCIE_CREATE_BDF_PACKED(e_bdf));
     if (master.smmu_index == ACS_INVALID_INDEX) {
         continue;
     }
@@ -185,7 +187,19 @@ payload(void)
     /* We just want to test minimum pasid size (16-bits) functionality.
      * Make sure exerciser supports at least that
      */
-    val_exerciser_get_param(PASID_ATTRIBUTES, &exerciser_ssid_bits, NULL, instance);
+    status = val_pcie_get_max_pasid_width(e_bdf, &exerciser_ssid_bits);
+    if (status == PCIE_CAP_NOT_FOUND)
+    {
+        val_print(ACS_PRINT_ERR, "\n       PASID extended capability not found for BDF: %x", e_bdf);
+        goto test_fail;
+    }
+    else if (status)
+    {
+        val_print(ACS_PRINT_ERR,
+                  "\n       Error in obtaining the PASID max width for BDF: %x",
+                  e_bdf);
+        goto test_fail;
+    }
     if (exerciser_ssid_bits < MIN_PASID_BITS)
     {
         val_print(ACS_PRINT_ERR, "exerciser substreamid support error %d\n", exerciser_ssid_bits);
@@ -194,51 +208,55 @@ payload(void)
 
     master.ssid_bits = MIN_PASID_BITS;
 
-    /* Need to know input and output address sizes before creating page table */
-    pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index);
-    if (pgt_desc.ias == 0)
-        goto test_fail;
-
-    pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index);
-    if (pgt_desc.oas == 0)
-        goto test_fail;
-
     val_smmu_enable(master.smmu_index);
 
     /* Increment the exerciser count with pasid support */
     e_valid_cnt++;
 
-    if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf),
-                                   PCIE_EXTRACT_BDF_SEG(e_bdf),
-                                   &device_id, &master.streamid,
-                                   &its_id))
-        continue;
-
-    /* Intent is to do DMA with PASID1 and PASID2 sequentially, with same IOVA.
-     * SMMU does virtual to physical address translation using
-     * tables configured for each pasid.
-     * Here we setup memory descriptor for creating page tables for pasid1.
-     */
-    mem_desc->virtual_address = (uint64_t)dram_buf_base_virt;
-    mem_desc->physical_address = dram_buf_pasid1_base_phys;
-    mem_desc->length = test_data_blk_size;
-    mem_desc->attributes |= PGT_STAGE1_AP_RW;
-
-    if (val_pgt_create(mem_desc, &pgt_desc))
-        goto test_fail;
-
-    pgt_base_pasid1 = pgt_desc.pgt_base;
-
-    master.substreamid = TEST_PASID1;
-    if (val_smmu_map(master, pgt_desc))
-    {
-        val_print(ACS_PRINT_ERR, "\n      SMMU mapping failed (%d)     ", master.substreamid);
-        goto test_fail;
+    if (master.smmu_index != ACS_INVALID_INDEX &&
+        val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, master.smmu_index) == 3) {
+
+        if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf),
+                                       PCIE_EXTRACT_BDF_SEG(e_bdf),
+                                       &device_id, &master.streamid,
+                                       &its_id))
+            continue;
+
+        /* Intent is to do DMA with PASID1 and PASID2 sequentially, with same IOVA.
+         * SMMU does virtual to physical address translation using
+         * tables configured for each pasid.
+         * Here we setup memory descriptor for creating page tables for pasid1.
+         */
+        mem_desc->virtual_address = (uint64_t)dram_buf_base_virt;
+        mem_desc->physical_address = dram_buf_pasid1_base_phys;
+        mem_desc->length = test_data_blk_size;
+        mem_desc->attributes |= PGT_STAGE1_AP_RW;
+
+        /* Need to know input and output address sizes before creating page table */
+        pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index);
+        if (pgt_desc.ias == 0)
+            goto test_fail;
+
+        pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index);
+        if (pgt_desc.oas == 0)
+            goto test_fail;
+
+        if (val_pgt_create(mem_desc, &pgt_desc))
+            goto test_fail;
+
+        pgt_base_pasid1 = pgt_desc.pgt_base;
+
+        master.substreamid = TEST_PASID1;
+        if (val_smmu_map(master, pgt_desc))
+        {
+            val_print(ACS_PRINT_ERR, "\n       SMMU mapping failed (%d)     ", master.substreamid);
+            goto test_fail;
+        }
+
+        dram_buf_in_iova = mem_desc->virtual_address;
+        dram_buf_out_iova = dram_buf_in_iova + (test_data_blk_size / 2);
     }
 
-    dram_buf_in_iova = mem_desc->virtual_address;
-    dram_buf_out_iova = dram_buf_in_iova + (test_data_blk_size / 2);
-
     write_test_data(dram_buf_pasid1_in_virt, dma_len);
 
     /* Program exerciser to start sending TLPs
@@ -252,34 +270,34 @@ payload(void)
     }
 
     if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA attributes setting failure %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA attributes setting failure %4x", instance);
         goto test_fail;
     }
 
     /* Trigger DMA from input buffer to exerciser memory */
     if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA write failure to exerciser %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA write failure to exerciser %4x", instance);
         goto test_fail;
     }
 
     if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA attributes setting failure %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA attributes setting failure %4x", instance);
         goto test_fail;
     }
 
     /* Trigger DMA from exerciser memory to output buffer*/
     if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA read failure from exerciser %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA read failure from exerciser %4x", instance);
         goto test_fail;
     }
 
     if (val_memory_compare(dram_buf_pasid1_in_virt, dram_buf_pasid1_out_virt, dma_len)) {
-        val_print(ACS_PRINT_ERR, "\n        Data Comparision failure for Exerciser %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       Data Comparision failure for Exerciser %4x", instance);
         goto test_fail;
     }
 
     if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA attributes setting failure %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA attributes setting failure %4x", instance);
         goto test_fail;
     }
 
@@ -307,7 +325,7 @@ payload(void)
     master.substreamid = TEST_PASID2;
     if (val_smmu_map(master, pgt_desc))
     {
-        val_print(ACS_PRINT_ERR, "\n      SMMU mapping failed (%d)     ", master.substreamid);
+        val_print(ACS_PRINT_ERR, "\n       SMMU mapping failed (%d)     ", master.substreamid);
         goto test_fail;
     }
 
@@ -327,24 +345,24 @@ payload(void)
     }
 
     if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA attributes setting failure %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA attributes setting failure %4x", instance);
         goto test_fail;
     }
 
     /* Trigger DMA from input buffer to exerciser memory */
     if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA write failure to exerciser %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA write failure to exerciser %4x", instance);
         goto test_fail;
     }
 
     if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA attributes setting failure %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA attributes setting failure %4x", instance);
         goto test_fail;
     }
 
     /* Trigger DMA from exerciser memory to output buffer */
     if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) {
-        val_print(ACS_PRINT_ERR, "\n      DMA read failure from exerciser %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       DMA read failure from exerciser %4x", instance);
         goto test_fail;
     }
 
@@ -354,38 +372,27 @@ payload(void)
     }
 
     if (val_memory_compare(dram_buf_pasid2_in_virt, dram_buf_pasid2_out_virt, dma_len)) {
-        val_print(ACS_PRINT_ERR, "\n        Data Comparasion failure for Exerciser %4x", instance);
+        val_print(ACS_PRINT_ERR, "\n       Data Comparison failure for Exerciser %4x", instance);
         goto test_fail;
     }
 
     val_smmu_unmap(master);
-    pgt_desc.pgt_base = pgt_base_pasid1;
-    val_pgt_destroy(pgt_desc);
-    pgt_desc.pgt_base = pgt_base_pasid2;
-    val_pgt_destroy(pgt_desc);
     val_smmu_disable(master.smmu_index);
-    pgt_base_pasid1 = pgt_base_pasid2 = 0;
   }
   if (e_valid_cnt) {
-    val_set_status (pe_index, RESULT_PASS (TEST_NUM, 01));
+    val_set_status(pe_index, RESULT_PASS (TEST_NUM, 1));
   } else {
     val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 00));
   }
   goto test_clean;
 
 test_fail:
-  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));;
+  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
 
 test_clean:
   val_memory_free_pages(dram_buf_base_virt, TEST_DATA_NUM_PAGES * 2);
-  if (pgt_base_pasid1 != 0)
-  {
-    pgt_desc.pgt_base = pgt_base_pasid1;
-    val_pgt_destroy(pgt_desc);
-  }
-  if (pgt_base_pasid1 != 0)
+  if ((pgt_base_pasid1 != 0) || (pgt_base_pasid2 != 0))
   {
-    pgt_desc.pgt_base = pgt_base_pasid2;
     val_pgt_destroy(pgt_desc);
   }
 }
diff --git a/test_pool/exerciser/operating_system/test_os_e006.c b/test_pool/exerciser/operating_system/test_os_e006.c
index 9eb589eb..9b389405 100644
--- a/test_pool/exerciser/operating_system/test_os_e006.c
+++ b/test_pool/exerciser/operating_system/test_os_e006.c
@@ -63,8 +63,8 @@ payload (void)
 /* Allocate memory for interrupt mappings */
   e_intr_map = val_memory_alloc(sizeof(PERIPHERAL_IRQ_MAP));
   if (!e_intr_map) {
-    val_print (ACS_PRINT_ERR, "\n       Memory allocation error", 00);
-    val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 02));
+    val_print(ACS_PRINT_ERR, "\n       Memory allocation error", 00);
+    val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 2));
     return;
   }
 
@@ -81,7 +81,7 @@ payload (void)
     e_bdf = val_exerciser_get_bdf(instance);
 
     val_pcie_read_cfg(e_bdf, PCIE_INTERRUPT_LINE, &e_intr_pin);
-    val_print (ACS_PRINT_DEBUG, "  e_intr_pin %x", e_intr_pin);
+    val_print(ACS_PRINT_DEBUG, "\n       e_intr_pin %x", e_intr_pin);
 
     if (((e_intr_pin >> 8) == 0) || ((e_intr_pin >> 8) > 4))
         continue;
@@ -115,17 +115,17 @@ payload (void)
         val_gic_free_irq(e_intr_line, 0);
 
    } else {
-        val_print (ACS_PRINT_ERR, "\n       Legacy interrupt mapping Read error", status);
+        val_print(ACS_PRINT_ERR, "\n       Legacy interrupt mapping Read error", status);
         goto test_fail;
    }
  }
 
   val_memory_free(e_intr_map);
-  val_set_status (pe_index, RESULT_PASS (TEST_NUM, 01));
+  val_set_status(pe_index, RESULT_PASS (TEST_NUM, 1));
   return;
 
 test_fail:
-  val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 02));
+  val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 2));
   val_memory_free(e_intr_map);
   return;
 
diff --git a/test_pool/exerciser/operating_system/test_os_e007.c b/test_pool/exerciser/operating_system/test_os_e007.c
index 7382d314..64456713 100644
--- a/test_pool/exerciser/operating_system/test_os_e007.c
+++ b/test_pool/exerciser/operating_system/test_os_e007.c
@@ -42,7 +42,7 @@
 #include "val/include/bsa_acs_pcie_enumeration.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 7)
-#define TEST_RULE  "PCI_IC_01, PCI_IC_03, PCI_IC_06-08"
+#define TEST_RULE  "PCI_IC_01, PCI_IC_03, PCI_IC_06, PCI_IC_07, PCI_IC_08"
 #define TEST_DESC  "Check PCIe I/O Coherency              "
 
 #define TEST_DATA_BLK_SIZE  (4*1024)
@@ -73,14 +73,14 @@ test_sequence2(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3
   /* Perform DMA OUT to copy contents of dram_buf2 to exerciser memory */
   val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf2_phys, dma_len, instance);
   if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) {
-      val_print(ACS_PRINT_ERR, "\n      DMA write failure to exerciser %4x", instance);
+      val_print(ACS_PRINT_ERR, "\n       DMA write failure to exerciser %4x", instance);
       return 1;
   }
 
   /* Perform DMA IN to copy content back from exerciser memory to dram_buf1 */
   val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance);
   if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) {
-      val_print(ACS_PRINT_ERR, "\n      DMA read failure from exerciser %4x", instance);
+      val_print(ACS_PRINT_ERR, "\n       DMA read failure from exerciser %4x", instance);
       return 1;
   }
 
@@ -118,14 +118,14 @@ test_sequence1(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3
   /* Perform DMA OUT to copy contents of dram_buf1 to exerciser memory */
   val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance);
   if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) {
-      val_print(ACS_PRINT_ERR, "\n      DMA write failure to exerciser %4x", instance);
+      val_print(ACS_PRINT_ERR, "\n       DMA write failure to exerciser %4x", instance);
       return 1;
   }
 
   /* Perform DMA IN to copy the content from exerciser memory to dram_buf1 */
   val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance);
   if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) {
-      val_print(ACS_PRINT_ERR, "\n      DMA read failure from exerciser %4x", instance);
+      val_print(ACS_PRINT_ERR, "\n       DMA read failure from exerciser %4x", instance);
       return 1;
   }
 
@@ -176,7 +176,8 @@ payload (void)
     e_bdf = val_exerciser_get_bdf(instance);
 
     /* Find SMMU node index for this exerciser instance */
-    smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf));
+    smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf),
+                                              PCIE_CREATE_BDF_PACKED(e_bdf));
 
     /* Disable SMMU globally so that the transaction passes
      * through the SMMU without any address modification.
@@ -188,7 +189,7 @@ payload (void)
     if (smmu_index != ACS_INVALID_INDEX) {
         if (val_smmu_disable(smmu_index)) {
             val_print(ACS_PRINT_ERR, "\n       Exerciser %x smmu disable error", instance);
-            val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+            val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
             return;
         }
     }
@@ -196,8 +197,8 @@ payload (void)
     /* Get a WB, outer shareable DDR Buffer of size TEST_DATA_BLK_SIZE */
     dram_buf1_virt = val_memory_alloc_cacheable(e_bdf, TEST_DATA_BLK_SIZE, &dram_buf1_phys);
     if (!dram_buf1_virt) {
-      val_print(ACS_PRINT_ERR, "\n       WB and OSH mem alloc failure %x", 02);
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+      val_print(ACS_PRINT_ERR, "\n       WB and OSH mem alloc failure %x", 2);
+      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
       return;
     }
 
@@ -223,7 +224,7 @@ payload (void)
   return;
 
 test_fail:
-  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
   val_memory_free_cacheable(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys);
   return;
 }
diff --git a/test_pool/exerciser/operating_system/test_os_e008.c b/test_pool/exerciser/operating_system/test_os_e008.c
index 27e0f3a0..701ca580 100644
--- a/test_pool/exerciser/operating_system/test_os_e008.c
+++ b/test_pool/exerciser/operating_system/test_os_e008.c
@@ -33,7 +33,7 @@
 #include "val/include/bsa_acs_pcie_enumeration.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 8)
-#define TEST_RULE  "PCI_IC_04"
+#define TEST_RULE  "PCI_IC_04, RE_ORD_4"
 #define TEST_DESC  "Check PCIe Software Coherency         "
 
 #define TEST_DATA_BLK_SIZE  (4*1024)
@@ -48,6 +48,7 @@ test_sequence2(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3
   uint32_t dma_len;
   void *dram_buf2_virt;
   void *dram_buf2_phys;
+  uint32_t tp_bit;
 
   /* Set up a second dram buffer to send NEWEST_DATA to exerciser memory */
   dram_buf2_virt = dram_buf1_virt + (TEST_DATA_BLK_SIZE / 2);
@@ -72,6 +73,13 @@ test_sequence2(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3
       return 1;
   }
 
+  /* Check if the transaction pending bit is cleared */
+  tp_bit = val_is_transaction_pending_set(e_bdf);
+  if (tp_bit) {
+      val_print(ACS_PRINT_ERR, "\n       Transaction still pending in function %4x", instance);
+      return 1;
+  }
+
   /* Invalidate dram_buf1 and dram_buf2 contents present in CPU caches */
   val_data_cache_ops_by_va((addr_t)dram_buf1_virt, INVALIDATE);
   val_data_cache_ops_by_va((addr_t)dram_buf2_virt, INVALIDATE);
@@ -94,6 +102,7 @@ test_sequence1(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3
   uint32_t dma_len;
   void *dram_buf2_virt;
   void *dram_buf2_phys;
+  uint32_t tp_bit;
 
   dram_buf2_virt = dram_buf1_virt + (TEST_DATA_BLK_SIZE / 2);
   dram_buf2_phys = dram_buf1_phys + (TEST_DATA_BLK_SIZE / 2);
@@ -119,6 +128,13 @@ test_sequence1(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, uint3
       return 1;
   }
 
+  /* Check if the transaction pending bit is cleared */
+  tp_bit = val_is_transaction_pending_set(e_bdf);
+  if (tp_bit) {
+      val_print(ACS_PRINT_ERR, "\n       Transaction still pending in function %4x", instance);
+      return 1;
+  }
+
   /* Invalidate dram_buf2 contents present in CPU caches */
   val_data_cache_ops_by_va((addr_t)dram_buf2_virt, INVALIDATE);
 
@@ -163,7 +179,8 @@ payload (void)
     e_bdf = val_exerciser_get_bdf(instance);
 
     /* Find SMMU node index for this exerciser instance */
-    smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf));
+    smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf),
+                                              PCIE_CREATE_BDF_PACKED(e_bdf));
 
     /* Disable SMMU globally so that the transaction passes
      * through the SMMU without any address modification.
@@ -175,7 +192,7 @@ payload (void)
     if (smmu_index != ACS_INVALID_INDEX) {
         if (val_smmu_disable(smmu_index)) {
             val_print(ACS_PRINT_ERR, "\n       Exerciser %x smmu disable error", instance);
-            val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+            val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
             return;
         }
     }
@@ -185,8 +202,8 @@ payload (void)
 
     if (!dram_buf1_virt) {
 
-      val_print(ACS_PRINT_ERR, "\n       WB and OSH mem alloc failure %x", 02);
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+      val_print(ACS_PRINT_ERR, "\n       WB and OSH mem alloc failure %x", 2);
+      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
       return;
     }
 
@@ -212,7 +229,7 @@ payload (void)
   return;
 
 test_fail:
-  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
   val_memory_free_cacheable(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys);
   return;
 }
diff --git a/test_pool/exerciser/operating_system/test_os_e009.c b/test_pool/exerciser/operating_system/test_os_e009.c
index 323921b2..8f4c691a 100644
--- a/test_pool/exerciser/operating_system/test_os_e009.c
+++ b/test_pool/exerciser/operating_system/test_os_e009.c
@@ -165,7 +165,7 @@ payload(void)
   if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/exerciser/operating_system/test_os_e010.c b/test_pool/exerciser/operating_system/test_os_e010.c
index ba55eba7..5762783e 100644
--- a/test_pool/exerciser/operating_system/test_os_e010.c
+++ b/test_pool/exerciser/operating_system/test_os_e010.c
@@ -77,7 +77,7 @@ payload(void)
   if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/exerciser/operating_system/test_os_e011.c b/test_pool/exerciser/operating_system/test_os_e011.c
index c424c9d3..7e64059c 100644
--- a/test_pool/exerciser/operating_system/test_os_e011.c
+++ b/test_pool/exerciser/operating_system/test_os_e011.c
@@ -25,7 +25,7 @@
 #include "val/include/bsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 11)
-#define TEST_RULE  "ITS_03, ITS_04"
+#define TEST_RULE  "ITS_03,ITS_04,ITS_06,ITS_07,ITS_08,ITS_DEV_1,ITS_DEV_5"
 #define TEST_DESC  "MSI to Any ITS Blk in assigned group  "
 
 static uint32_t irq_pending;
@@ -58,7 +58,6 @@ payload (void)
   uint32_t msi_index = 0;
   uint32_t msi_cap_offset = 0;
 
-  uint32_t req_id = 0;
   uint32_t device_id = 0;
   uint32_t stream_id = 0;
   uint32_t its_id = 0;
@@ -67,7 +66,7 @@ payload (void)
 
   if (val_gic_get_info(GIC_INFO_NUM_ITS) < 2) {
       val_print(ACS_PRINT_DEBUG, "\n       Skipping Test as multiple ITS not available", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -96,16 +95,13 @@ payload (void)
     }
 
     /* Get DeviceID & ITS_ID for this device */
-    req_id = GET_DEVICE_ID(PCIE_EXTRACT_BDF_BUS(e_bdf),
-                           PCIE_EXTRACT_BDF_DEV(e_bdf),
-                           PCIE_EXTRACT_BDF_FUNC(e_bdf));
-
-    status = val_iovirt_get_device_info(req_id, PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id,
+    status = val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf),
+                                        PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id,
                                         &stream_id, &its_id);
     if (status) {
         val_print(ACS_PRINT_ERR,
             "\n       Could not get device info for BDF : 0x%x", e_bdf);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
         return;
     }
 
@@ -134,12 +130,13 @@ payload (void)
           continue;
       }
 
-      val_print(ACS_PRINT_DEBUG, "\n       ITS Check for ITS ID : %x", its_id);
+      val_print(ACS_PRINT_DEBUG, "\n       ITS Check for ITS ID : %x        "
+                                    "      ", its_id);
       status = val_gic_request_msi(e_bdf, device_id, its_id, base_lpi_id + instance, msi_index);
       if (status) {
           val_print(ACS_PRINT_ERR,
               "\n       MSI Assignment failed for bdf : 0x%x", e_bdf);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           return;
       }
 
@@ -148,7 +145,7 @@ payload (void)
       if (status) {
           val_print(ACS_PRINT_ERR,
               "\n       Intr handler registration fail, Interrupt : 0x%x", base_lpi_id + instance);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
           return;
       }
 
@@ -171,7 +168,7 @@ payload (void)
               "\n       BDF : 0x%x, ", e_bdf);
           val_print(ACS_PRINT_ERR,
               "its_id : 0x%x", its_id);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
           val_gic_free_msi(e_bdf, device_id, its_id, base_lpi_id + instance, msi_index);
           return;
       }
@@ -183,12 +180,12 @@ payload (void)
   }
 
   if (test_skip) {
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
   /* Pass Test */
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/exerciser/operating_system/test_os_e012.c b/test_pool/exerciser/operating_system/test_os_e012.c
index 5713cc9e..f3eacc09 100644
--- a/test_pool/exerciser/operating_system/test_os_e012.c
+++ b/test_pool/exerciser/operating_system/test_os_e012.c
@@ -59,7 +59,6 @@ payload (void)
   uint32_t msi_index = 0;
   uint32_t msi_cap_offset = 0;
 
-  uint32_t req_id = 0;
   uint32_t device_id = 0;
   uint32_t stream_id = 0;
   uint32_t its_id = 0;
@@ -69,7 +68,7 @@ payload (void)
   status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group);
   if (status || (num_group < 2)) {
       val_print(ACS_PRINT_DEBUG, "\n       Number of ITS Group < 2, Skipping Test", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -100,16 +99,13 @@ payload (void)
     test_skip = 0;
 
     /* Get DeviceID & ITS_ID for this device */
-    req_id = GET_DEVICE_ID(PCIE_EXTRACT_BDF_BUS(e_bdf),
-                           PCIE_EXTRACT_BDF_DEV(e_bdf),
-                           PCIE_EXTRACT_BDF_FUNC(e_bdf));
-
-    status = val_iovirt_get_device_info(req_id, PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id,
+    status = val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf),
+                                        PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id,
                                         &stream_id, &its_id);
     if (status) {
         val_print(ACS_PRINT_ERR,
             "\n       Could not get device info for BDF : 0x%x", e_bdf);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
         return;
     }
 
@@ -133,7 +129,7 @@ payload (void)
     if (status) {
         val_print(ACS_PRINT_ERR,
             "\n       MSI Assignment failed for bdf : 0x%x", e_bdf);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
         return;
     }
 
@@ -142,7 +138,7 @@ payload (void)
     if (status) {
         val_print(ACS_PRINT_ERR,
             "\n       Intr handler registration failed Interrupt : 0x%x", base_lpi_id + instance);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
         return;
     }
 
@@ -163,7 +159,7 @@ payload (void)
             "\n       Interrupt triggered for int_id : 0x%x, ", base_lpi_id + instance);
         val_print(ACS_PRINT_ERR,
             "BDF : 0x%x   ", e_bdf);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
         val_gic_free_msi(e_bdf, device_id, get_value, base_lpi_id + instance, msi_index);
         return;
     }
@@ -174,12 +170,12 @@ payload (void)
   }
 
   if (test_skip) {
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
   /* Pass Test */
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/exerciser/operating_system/test_os_e013.c b/test_pool/exerciser/operating_system/test_os_e013.c
index 74f780c8..2d6cb42a 100644
--- a/test_pool/exerciser/operating_system/test_os_e013.c
+++ b/test_pool/exerciser/operating_system/test_os_e013.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2020,2021 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2018, 2021, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -14,402 +14,225 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  **/
-
 #include "val/include/bsa_acs_val.h"
 #include "val/include/val_interface.h"
 
-#include "val/include/bsa_acs_pcie_enumeration.h"
 #include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_smmu.h"
-#include "val/include/bsa_acs_pgt.h"
-#include "val/include/bsa_acs_iovirt.h"
+#include "val/include/bsa_acs_gic.h"
 #include "val/include/bsa_acs_memory.h"
+#include "val/include/bsa_acs_iovirt.h"
+#include "val/include/bsa_acs_smmu.h"
+#include "val/include/bsa_acs_pcie_enumeration.h"
 #include "val/include/bsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 13)
-#define TEST_DESC  "PCI_PP_04: Check ACS Redirect Req Valid               "
+#define TEST_RULE  "ITS_DEV_4"
+#define TEST_DESC  "MSI originating from different master "
+
+static uint32_t irq_pending;
+static uint32_t lpi_int_id = 0x204C;
+static uint32_t instance;
 
 static
-uint32_t
-get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf,
-                    uint32_t *tgt_rp_bdf, uint64_t *bar_base)
+void
+intr_handler(void)
 {
+  /* Clear the interrupt pending state */
+  irq_pending = 0;
 
-  uint32_t erp_bdf;
-  uint32_t e_bdf;
-  uint32_t instance;
-  uint32_t cap_base;
-
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
-
-  while (instance-- != 0)
-  {
-      /* if init fail moves to next exerciser */
-      if (val_exerciser_init(instance))
-          continue;
-
-      e_bdf = val_exerciser_get_bdf(instance);
-
-      /* Read e_bdf BAR Register to get the Address to perform P2P */
-      /* If No BAR Space, continue */
-      val_pcie_get_mmio_bar(e_bdf, bar_base);
-      if (*bar_base == 0)
-          continue;
-
-      /* Get RP of the exerciser */
-      if (val_pcie_get_rootport(e_bdf, &erp_bdf))
-          continue;
-
-      /* It ACS Not Supported, continue */
-      if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) {
-          val_print(ACS_PRINT_DEBUG, "\n       ACS Not Supported for BDF : 0x%x", erp_bdf);
-          continue;
-      }
-
-      if (req_rp_bdf != erp_bdf)
-      {
-          *tgt_e_bdf = e_bdf;
-          *tgt_rp_bdf = erp_bdf;
-
-          /* Enable Bus Master Enable */
-          val_pcie_enable_bme(e_bdf);
-          /* Enable Memory Space Access */
-          val_pcie_enable_msa(e_bdf);
-
-          return ACS_STATUS_PASS;
-      }
-  }
-
-  /* Return failure if No Such Exerciser Found */
-  *tgt_e_bdf = 0;
-  *tgt_rp_bdf = 0;
-  *bar_base = 0;
-  return ACS_STATUS_FAIL;
+  val_print(ACS_PRINT_INFO, "\n       Received MSI interrupt %x       ", lpi_int_id + instance);
+  val_gic_end_of_interrupt(lpi_int_id + instance);
+  return;
 }
 
+static
 uint32_t
-create_va_pa_mapping (uint64_t txn_va, uint64_t txn_pa,
-                      smmu_master_attributes_t *smmu_master,
-                      pgt_descriptor_t *pgt_descriptor,
-                      uint32_t e_bdf, uint32_t pgt_ap)
+get_exerciser_in_its_group(uint32_t its_id, uint32_t *req_instance)
 {
-  smmu_master_attributes_t master;
-  pgt_descriptor_t pgt_desc;
-  memory_region_descriptor_t mem_desc_array[2], *mem_desc;
-  uint64_t ttbr;
-  uint32_t num_smmus;
-  uint32_t instance;
-  uint32_t device_id, its_id;
-
-  master = *smmu_master;
-  pgt_desc = *pgt_descriptor;
-
-  val_memory_set(&master, sizeof(master), 0);
-  val_memory_set(mem_desc_array, sizeof(mem_desc_array), 0);
-  mem_desc = &mem_desc_array[0];
-
-  /* Get translation attributes via TCR and translation table base via TTBR */
-  if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr))
-    return ACS_STATUS_FAIL;
-  if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr))
-    return ACS_STATUS_FAIL;
-  pgt_desc.pgt_base = (ttbr & AARCH64_TTBR_ADDR_MASK);
-  pgt_desc.mair = val_pe_reg_read(MAIR_ELx);
-  pgt_desc.stage = PGT_STAGE1;
-
-  /* Get memory attributes of the test buffer, we'll use the same attibutes to create
-   * our own page table later.
-   */
-  if (val_pgt_get_attributes(pgt_desc, (uint64_t)txn_va, &mem_desc->attributes))
-    return ACS_STATUS_FAIL;
+  uint32_t num_cards, index;
+  uint32_t bdf, req_its_id;
+  uint32_t status;
+  uint32_t device_id = 0;
 
-  num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0);
+  /* Read the number of excerciser cards */
+  num_cards = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
 
-  /* Enable all SMMUs */
-  for (instance = 0; instance < num_smmus; ++instance)
-     val_smmu_enable(instance);
-
-  /* Get SMMU node index for this exerciser instance */
-  master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf));
-
-  if (master.smmu_index != ACS_INVALID_INDEX &&
-      val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, master.smmu_index) == 3) {
-      if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf),
-                                     PCIE_EXTRACT_BDF_SEG(e_bdf),
-                                     &device_id, &master.streamid,
-                                     &its_id))
-          return ACS_STATUS_FAIL;
-
-      /* Each exerciser instance accesses a unique IOVA, which, because of SMMU translations,
-       * will point to the same physical address. We create the requisite page tables and
-       * configure the SMMU for each exerciser as such.
-       */
-
-      mem_desc->virtual_address = (uint64_t)txn_va;
-      mem_desc->physical_address = txn_pa;
-      mem_desc->length = 4; /* 4 Bytes */
-      mem_desc->attributes |= pgt_ap;
-
-      /* Need to know input and output address sizes before creating page table */
-      pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index);
-      if (pgt_desc.ias == 0)
-        return ACS_STATUS_FAIL;
-
-      pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index);
-      if (pgt_desc.oas == 0)
-        return ACS_STATUS_FAIL;
-
-      if (val_pgt_create(mem_desc, &pgt_desc))
-        return ACS_STATUS_FAIL;
-
-      /* Configure SMMU tables for this exerciser to use this page table for VA to PA translations*/
-      if (val_smmu_map(master, pgt_desc))
-      {
-          val_print(ACS_PRINT_DEBUG, "\n      SMMU mapping failed (%x)     ", e_bdf);
-          return ACS_STATUS_FAIL;
-      }
-      return ACS_STATUS_PASS;
+  for (index = 0; index < num_cards; index++)
+  {
+    if (index == instance)
+      continue;
+
+    /* Get the exerciser BDF */
+    bdf = val_exerciser_get_bdf(index);
+
+    /* Get DeviceID & ITS_ID for this device */
+    status = val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(bdf),
+                                        PCIE_EXTRACT_BDF_SEG(bdf), &device_id,
+                                        NULL, &req_its_id);
+    if (status) {
+        val_print(ACS_PRINT_ERR,
+            "\n       Could not get device info for BDF : 0x%x", bdf);
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
+        return 1;
+    }
+
+    if (its_id == req_its_id) {
+      *req_instance = index;
+      return 0;
+    }
   }
-  return ACS_STATUS_FAIL;
+
+  /* Did not find exerciser with Same ITS Group */
+  return 1;
 }
 
-uint32_t
-check_redirected_req_validation (uint32_t req_instance, uint32_t req_e_bdf,
-                                 uint32_t req_rp_bdf, uint32_t tgt_e_bdf,
-                                 uint64_t bar_base)
+static
+void
+payload (void)
 {
-  uint64_t txn_va;
-  uint32_t instance;
-  uint32_t e_bdf;
-  uint32_t num_smmus;
-  uint32_t status;
-  smmu_master_attributes_t master;
-  pgt_descriptor_t pgt_desc;
 
-  /* Sequence 1 : No Write Permission, Trigger a DMA Write to bar address
-   * It should Result into ACS Violation
-   */
-
-  /* Create VA-PA Mapping in SMMU with PGT permissions as Read Only */
-  /* Initialize DMA master and memory descriptors */
-
-  /* Set the virtual and physical addresses for test buffers */
-  txn_va = (uint64_t)val_memory_phys_to_virt(bar_base);
-
-  /* Get exerciser bdf */
-  e_bdf = val_exerciser_get_bdf(req_instance);
-
-  num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0);
-
-  status = create_va_pa_mapping(txn_va, bar_base, &master,
-                                &pgt_desc, e_bdf,
-                                PGT_STAGE1_AP_RO);
-  if (status) {
-      val_print(ACS_PRINT_DEBUG,
-                      "\n       Seq1:SMMU Mapping Failed For : %4x", req_instance);
-      goto test_fail;
-  }
-
-  /* Trigger DMA from req_e_bdf */
-  val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)txn_va, 1, req_instance);
+  uint32_t index;
+  uint32_t e_bdf = 0;
+  uint32_t req_bdf = 0;
+  uint32_t timeout;
+  uint32_t status;
+  uint32_t num_cards;
+  uint32_t num_smmus;
+  uint32_t test_skip = 1;
+  uint32_t msi_index = 0;
+  uint32_t msi_cap_offset = 0;
 
-  /* Clear Error Status Bits */
-  val_pcie_clear_device_status_error(req_rp_bdf);
-  val_pcie_clear_sig_target_abort(req_rp_bdf);
+  uint32_t device_id = 0;
+  uint32_t stream_id = 0;
+  uint32_t its_id = 0;
+  uint32_t req_instance;
 
-  /* DMA Should fail because Write permission not given */
-  if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance) == 0) {
-      val_print(ACS_PRINT_DEBUG,
-                "\n       Seq1:DMA Write Should not happen For : %4x", req_instance);
-      goto test_fail;
-  }
+  index = val_pe_get_index_mpid (val_pe_get_mpid());
 
-  /* Check For Error in Device Status Register / Status Register
-   * Secondary Status Register
-   */
-  if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) &&
-     (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) {
-      val_print(ACS_PRINT_DEBUG, "\n       Seq1:Expected Error For RootPort : 0x%x", req_rp_bdf);
-      goto test_fail;
+  if (val_gic_get_info(GIC_INFO_NUM_ITS) == 0) {
+      val_print(ACS_PRINT_DEBUG, "\n       No ITS, Skipping Test.\n", 0);
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
+      return;
   }
 
-  /* Unmap SMMU & Pgt */
-  val_smmu_unmap(master);
-  val_pgt_destroy(pgt_desc);
+  /* Read the number of excerciser cards */
+  num_cards = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
 
   /* Disable all SMMUs */
+  num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0);
   for (instance = 0; instance < num_smmus; ++instance)
      val_smmu_disable(instance);
 
-  /* Sequence 2 : Read Write Permission, Trigger a DMA Write to bar address
-   * It should NOT Result into ACS Violation
-   */
-
-  /* Create VA-PA Mapping in SMMU with PGT permissions as Read Write */
-  status = create_va_pa_mapping(txn_va, bar_base, &master,
-                                &pgt_desc, e_bdf,
-                                PGT_STAGE1_AP_RW);
-  if (status) {
-      val_print(ACS_PRINT_DEBUG, "\n       Seq2:SMMU Mapping Failed For : %4x", req_instance);
-      goto test_fail;
-  }
-
-  /* Trigger DMA from req_e_bdf */
-  val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)txn_va, 1, req_instance);
-
-  /* Clear Error Status Bits */
-  val_pcie_clear_device_status_error(req_rp_bdf);
-  val_pcie_clear_sig_target_abort(req_rp_bdf);
+  for (instance = 0; instance < num_cards; instance++)
+  {
 
-  /* DMA Should fail not because Write permission given */
-  if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance) != 0) {
-      val_print(ACS_PRINT_DEBUG, "\n       Seq2:DMA Write Should happen For : %4x", req_instance);
-      goto test_fail;
-  }
+    /* if init fail moves to next exerciser */
+    if (val_exerciser_init(instance))
+        continue;
+
+    /* Get the exerciser BDF */
+    e_bdf = val_exerciser_get_bdf(instance);
+
+    /* Search for MSI-X Capability */
+    if (val_pcie_find_capability(e_bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset)) {
+      val_print(ACS_PRINT_INFO, "\n       No MSI-X Capability, Skipping for 0x%x", e_bdf);
+      continue;
+    }
+
+    /* Get DeviceID & ITS_ID for this device */
+    status = val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf),
+                                        PCIE_EXTRACT_BDF_SEG(e_bdf), &device_id,
+                                        &stream_id, &its_id);
+    if (status) {
+        val_print(ACS_PRINT_ERR,
+            "\n       Could not get device info for BDF : 0x%x", e_bdf);
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
+        return;
+    }
+
+    /* Search for an exerciser within the same ITS Group */
+    status = get_exerciser_in_its_group(its_id, &req_instance);
+    if (status) {
+        val_print(ACS_PRINT_INFO,
+            "\n       Could not find another exerciser : 0x%x", e_bdf);
+        continue;
+    }
+
+    /* Get the other exerciser BDF, for which we will not create the mappings */
+    req_bdf = val_exerciser_get_bdf(req_instance);
+
+    test_skip = 0;
+
+    /* Create mappings for device = device_id & fill msi address and data to
+     * other exerciser = req_bdf's MSI Table */
+    status = val_gic_request_msi(req_bdf, device_id, its_id, lpi_int_id + instance, msi_index);
+    if (status) {
+        val_print(ACS_PRINT_ERR,
+            "\n       MSI Assignment failed for bdf : 0x%x", req_bdf);
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
+        return;
+    }
+
+    status = val_gic_install_isr(lpi_int_id + instance, intr_handler);
+
+    if (status) {
+        val_print(ACS_PRINT_ERR,
+            "\n       Intr handler registration failed Interrupt : 0x%x", lpi_int_id + instance);
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
+        return;
+    }
+
+    /* Set the interrupt trigger status to pending */
+    irq_pending = 1;
+
+    /* Trigger the interrupt from other exerciser */
+    val_exerciser_ops(GENERATE_MSI, msi_index, req_instance);
+
+    /* PE busy polls to check the completion of interrupt service routine */
+    timeout = TIMEOUT_MEDIUM;
+    while ((--timeout > 0) && irq_pending)
+        {};
+
+    /* Interrupt should not be generated */
+    if (irq_pending == 0) {
+        val_print(ACS_PRINT_ERR,
+            "\n       Interrupt triggered from diff exerciser : 0x%x, ", req_bdf);
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 5));
+        val_gic_free_msi(req_bdf, device_id, its_id, lpi_int_id + instance, msi_index);
+        return;
+    }
+
+    /* Clear Interrupt and Mappings */
+    val_gic_free_msi(req_bdf, device_id, its_id, lpi_int_id + instance, msi_index);
 
-  /* Check For Error in Device Status Register / Status Register
-   * Secondary Status Register
-   */
-  if (val_pcie_is_device_status_error(req_rp_bdf) ||
-     val_pcie_is_sig_target_abort(req_rp_bdf)) {
-      val_print(ACS_PRINT_DEBUG, "\n       Seq2:Expected No Error For RootPort : 0x%x", req_rp_bdf);
-      goto test_fail;
   }
 
-  status = ACS_STATUS_PASS;
-  goto test_clean;
-
-test_fail:
-  status = ACS_STATUS_FAIL;
-
-test_clean:
-  val_smmu_unmap(master);
-  val_pgt_destroy(pgt_desc);
-
-  /* Clear Error Status Bits */
-  val_pcie_clear_device_status_error(req_rp_bdf);
-  val_pcie_clear_sig_target_abort(req_rp_bdf);
-
-  /* Disable all SMMUs */
-  for (instance = 0; instance < num_smmus; ++instance)
-     val_smmu_disable(instance);
-  return status;
-}
-
-static
-void
-payload(void)
-{
-
-  uint32_t status;
-  uint32_t pe_index;
-  uint32_t bdf;
-  uint32_t req_e_bdf;
-  uint32_t req_rp_bdf;
-  uint32_t tgt_e_bdf;
-  uint32_t tgt_rp_bdf;
-  uint32_t instance;
-  uint32_t fail_cnt;
-  uint32_t cap_base;
-  uint32_t reg_value;
-  uint32_t test_skip;
-  uint32_t tbl_index;
-  uint64_t bar_base;
-
-  fail_cnt = 0;
-  test_skip = 1;
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  tbl_index = 0;
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  /* Check If PCIe Hierarchy supports P2P. */
-  if (val_pcie_p2p_support())
-  {
-    val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+  if (test_skip) {
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
-  while (tbl_index < bdf_tbl_ptr->num_entries)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) == PCIE_SUCCESS) {
-          /* Enable P2P Request Redirect & Upstream Forwarding */
-          val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, &reg_value);
-
-          reg_value = reg_value | (1 << ACS_CTRL_RRE_SHIFT) | (1 << ACS_CTRL_UFE_SHIFT);
-          val_pcie_write_cfg(bdf, cap_base + ACSCR_OFFSET, reg_value);
-      }
-  }
-
-  while (instance-- != 0)
-  {
-
-      /* if init fail moves to next exerciser */
-      if (val_exerciser_init(instance))
-          continue;
-
-      req_e_bdf = val_exerciser_get_bdf(instance);
-
-      /* Get RP of the exerciser */
-      if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf))
-          continue;
-
-      /* It ACS Not Supported, Fail.*/
-      if (val_pcie_find_capability(req_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) {
-          val_print(ACS_PRINT_ERR, "\n       ACS Not Supported for BDF : 0x%x", req_rp_bdf);
-          fail_cnt++;
-          continue;
-      }
-
-      /* Find another exerciser on other rootport,
-         Break from the test if no such exerciser if found */
-      if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base))
-          break;
-
-      /* If Both RP's Supports ACS Then Only Run Otherwise Skip the EP */
-      test_skip = 0;
-
-      /* Check For Redirected Request Validation Functionality */
-      status = check_redirected_req_validation(instance, req_e_bdf, req_rp_bdf,
-                                               tgt_e_bdf, bar_base);
-      if (status == ACS_STATUS_SKIP)
-          val_print(ACS_PRINT_ERR, "\n       ACS Validation Check Skipped for 0x%x", req_rp_bdf);
-      else if (status) {
-          fail_cnt++;
-          val_print(ACS_PRINT_ERR, "\n       ACS Redirected Req Check Failed for 0x%x", req_rp_bdf);
-      }
-
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (fail_cnt)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-
-  return;
+  /* Pass Test */
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
 uint32_t
 os_e013_entry(void)
 {
-  uint32_t num_pe = 1;
+
   uint32_t status = ACS_STATUS_FAIL;
 
+  uint32_t num_pe = 1;  //This test is run on single processor
+
   status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
   if (status != ACS_STATUS_SKIP)
       val_run_test_payload(TEST_NUM, num_pe, payload, 0);
 
-  /* Get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
+  /* get the result from all PE and check for failure */
+  status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
 
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
+  val_report_status(0, BSA_ACS_END(TEST_NUM), NULL);
 
   return status;
 }
diff --git a/test_pool/exerciser/operating_system/test_os_e014.c b/test_pool/exerciser/operating_system/test_os_e014.c
new file mode 100644
index 00000000..6bc99d0e
--- /dev/null
+++ b/test_pool/exerciser/operating_system/test_os_e014.c
@@ -0,0 +1,198 @@
+/** @file
+ * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **/
+#include "val/include/bsa_acs_val.h"
+#include "val/include/val_interface.h"
+
+#include "val/include/bsa_acs_pcie.h"
+#include "val/include/bsa_acs_memory.h"
+#include "val/include/bsa_acs_pcie_enumeration.h"
+#include "val/include/bsa_acs_exerciser.h"
+
+#define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 14)
+#define TEST_RULE  "PCI_PP_02"
+#define TEST_DESC  "P2P transactions should not deadlock  "
+
+uint32_t
+get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf,
+                    uint32_t *tgt_rp_bdf, uint64_t *bar_base)
+{
+
+  uint32_t erp_bdf;
+  uint32_t e_bdf;
+  uint32_t instance;
+  uint32_t req_rp_ecam_index;
+  uint32_t erp_ecam_index;
+  uint32_t status;
+
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+
+  while (instance-- != 0)
+  {
+      /* if init fail moves to next exerciser */
+      if (val_exerciser_init(instance))
+          continue;
+
+      e_bdf = val_exerciser_get_bdf(instance);
+
+      /* Read e_bdf BAR Register to get the Address to perform P2P */
+      /* If No BAR Space, continue */
+      val_pcie_get_mmio_bar(e_bdf, bar_base);
+      if (*bar_base == 0)
+          continue;
+
+      /* Get RP of the exerciser */
+      if (val_pcie_get_rootport(e_bdf, &erp_bdf))
+          continue;
+
+      if (req_rp_bdf != erp_bdf)
+      {
+          status = val_pcie_get_ecam_index(req_rp_bdf, &req_rp_ecam_index);
+          if (status)
+          {
+             val_print(ACS_PRINT_ERR, "\n       Error Ecam index for req RP BDF: 0x%x", req_rp_bdf);
+             goto test_fail;
+          }
+
+          status = val_pcie_get_ecam_index(erp_bdf, &erp_ecam_index);
+          if (status)
+          {
+             val_print(ACS_PRINT_ERR, "\n       Error Ecam index for tgt RP BDF: 0x%x", erp_bdf);
+             goto test_fail;
+          }
+
+          if (req_rp_ecam_index != erp_ecam_index)
+              continue;
+
+          *tgt_e_bdf = e_bdf;
+          *tgt_rp_bdf = erp_bdf;
+
+          /* Enable Bus Master Enable */
+          val_pcie_enable_bme(e_bdf);
+          /* Enable Memory Space Access */
+          val_pcie_enable_msa(e_bdf);
+
+          return ACS_STATUS_PASS;
+      }
+  }
+
+test_fail:
+  /* Return failure if No Such Exerciser Found */
+  *tgt_e_bdf = 0;
+  *tgt_rp_bdf = 0;
+  *bar_base = 0;
+  return ACS_STATUS_FAIL;
+}
+
+uint32_t
+check_p2p_transaction(uint32_t req_instance, uint32_t req_rp_bdf,
+                                               uint64_t bar_base)
+{
+  /* P2P transaction should fail */
+  val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)bar_base, 1, req_instance);
+  val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, req_instance);
+
+  return ACS_STATUS_PASS;
+}
+
+static
+void
+payload(void)
+{
+
+  uint32_t status;
+  uint32_t index;
+  uint32_t req_e_bdf;
+  uint32_t req_rp_bdf;
+  uint32_t tgt_e_bdf;
+  uint32_t tgt_rp_bdf;
+  uint32_t instance;
+  uint32_t test_skip;
+  uint64_t bar_base;
+
+  test_skip = 1;
+  index = val_pe_get_index_mpid(val_pe_get_mpid());
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+
+  /* Check If PCIe Hierarchy supports P2P. */
+  if (!val_pcie_p2p_support())
+  {
+    val_print(ACS_PRINT_DEBUG, "\n       P2P is supported, Skipping Test", 0);
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
+    return;
+  }
+
+  while (instance-- != 0)
+  {
+
+      /* if init fail moves to next exerciser */
+      if (val_exerciser_init(instance))
+          continue;
+
+      req_e_bdf = val_exerciser_get_bdf(instance);
+
+      /* Get RP of the exerciser */
+      if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf))
+          continue;
+
+      /* Find another exerciser on other rootport,
+         Skip the current exerciser if no such exerciser if found */
+      if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base))
+          continue;
+
+      test_skip = 0;
+
+      /* Check if P2P transaction causes any deadlock */
+      status = check_p2p_transaction(instance, req_rp_bdf, bar_base);
+      if (status)
+      {
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
+          return;
+      }
+
+      /* Clear Error Status Bits */
+      val_pcie_clear_device_status_error(req_rp_bdf);
+      val_pcie_clear_sig_target_abort(req_rp_bdf);
+    }
+
+    if (test_skip) {
+        val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
+        return;
+    }
+
+  /* Pass Test */
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
+}
+
+uint32_t
+os_e014_entry(void)
+{
+
+  uint32_t status = ACS_STATUS_FAIL;
+
+  uint32_t num_pe = 1;  //This test is run on single processor
+
+  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
+  if (status != ACS_STATUS_SKIP)
+      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
+
+  /* get the result from all PE and check for failure */
+  status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
+
+  val_report_status(0, BSA_ACS_END(TEST_NUM), NULL);
+
+  return status;
+}
diff --git a/test_pool/exerciser/operating_system/test_os_e015.c b/test_pool/exerciser/operating_system/test_os_e015.c
index ccb5d1e0..80d8dabe 100644
--- a/test_pool/exerciser/operating_system/test_os_e015.c
+++ b/test_pool/exerciser/operating_system/test_os_e015.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -26,309 +26,151 @@
 #include "val/include/bsa_acs_exerciser.h"
 
 #define TEST_NUM   (ACS_EXERCISER_TEST_NUM_BASE + 15)
-#define TEST_DESC  "RE_ORD_1 & 2,IE_ORD_1 & 2,PCI_MM_01:Arrival order Chk "
-/* This test checks for the Arrival Order & Gathering Check */
+#define TEST_RULE  "PCI_IN_17"
+#define TEST_DESC  "Check ARI forwarding enable rule      "
 
-/* 0 means read transction, 1 means write transaction */
-static uint32_t transaction_order[] = {1, 1, 0, 1, 0, 0, 0, 0};
-static uint32_t pattern[16] = {0};
-static uint32_t run_flag;
-static uint32_t fail_cnt;
-
-static uint32_t read_config_space(uint32_t *addr)
-{
-  uint32_t idx;
-
-  for (idx = 0; idx < 16; idx++) {
-    addr = addr + idx;
-    pattern[idx] = val_mmio_read((addr_t)addr);
-  }
-
-  return 0;
-}
-
-/* num of transactions captured and thier attributes is checked */
-static uint32_t test_sequence_check(uint32_t instance)
-{
-  uint64_t idx;
-  uint64_t num_transactions;
-  uint64_t transaction_type;
-
-  /* Get number of transactions captured from exerciser */
-  val_exerciser_get_param(NUM_TRANSACTIONS, NULL, &num_transactions, instance);
-  if (num_transactions !=  sizeof(transaction_order)/sizeof(transaction_order[0])) {
-      val_print(ACS_PRINT_ERR, "\n       Exerciser %d gathering check failed", instance);
-      return 1;
-  }
-
-  /* Check transactions arrival order */
-  for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) {
-      val_exerciser_get_param(TRANSACTION_TYPE, &idx, &transaction_type, instance);
-      if (transaction_type !=  transaction_order[idx]) {
-          val_print(ACS_PRINT_ERR, "\n       Exerciser %d arrival order check failed", instance);
-          return 1;
-      }
-  }
-  return 0;
-}
-
-/* Performs reads/write on 1B data */
-static uint32_t test_sequence_1B(uint8_t *addr, uint8_t increment_addr, uint32_t instance)
-{
-  uint64_t idx;
-  uint8_t write_val;
-  uint32_t pidx;
-  uint8_t *pattern_ptr;
-
-  /* Start monitoring exerciser transactions */
-  if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance))
-      return ACS_STATUS_SKIP;
-
-  run_flag = 1;
-
-  /* Send the transaction on incrementalt addresses */
-  for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) {
-      pidx = ((uint64_t)addr & 0xFF);
-      pattern_ptr = (uint8_t *)&pattern;
-      write_val = pattern_ptr[pidx];
-      /* Write transaction */
-      if (transaction_order[idx])
-          val_mmio_write8((addr_t)addr, write_val);
-      else
-          val_mmio_read8((addr_t)addr);
-      if (increment_addr)
-          addr++;
-  }
-
-  /* Stop monitoring exerciser transactions */
-  val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
-
-  return test_sequence_check(instance);
-}
-
-/* Performs reads/write on 2B data */
-static uint32_t test_sequence_2B(uint16_t *addr, uint8_t increment_addr, uint32_t instance)
-{
-  uint64_t idx;
-  uint16_t write_val;
-  uint32_t pidx;
-  uint16_t *pattern_ptr;
-
-  /* Start monitoring exerciser transactions */
-  if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance))
-      return ACS_STATUS_SKIP;
-
-  run_flag = 1;
-
-  /* Send the transaction on incrementalt addresses */
-  for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) {
-      pidx = ((uint64_t)addr & 0xFF)/2;
-      pattern_ptr = (uint16_t *)&pattern;
-      write_val = pattern_ptr[pidx];
-      /* Write transaction */
-      if (transaction_order[idx])
-          val_mmio_write16((addr_t)addr, write_val);
-      else
-          val_mmio_read16((addr_t)addr);
-      if (increment_addr)
-          addr++;
-  }
-
-  /* Stop monitoring exerciser transactions */
-  val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
-
-  return test_sequence_check(instance);
-}
-
-/* Performs reads/write on 4B data */
-static uint32_t test_sequence_4B(uint32_t *addr, uint8_t increment_addr, uint32_t instance)
-{
-  uint64_t idx;
-  uint32_t write_val, pidx;
-  uint32_t *pattern_ptr;
-  /* Start monitoring exerciser transactions */
-  if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance))
-      return ACS_STATUS_SKIP;
-
-  run_flag = 1;
-
-  /* Send the transaction on incrementalt addresses */
-  for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) {
-      pidx = ((uint64_t)addr & 0xFF)/4;
-      pattern_ptr = (uint32_t *)&pattern;
-      write_val = pattern_ptr[pidx];
-      /* Write transaction */
-      if (transaction_order[idx])
-          val_mmio_write((addr_t)addr, write_val);
-      else
-          val_mmio_read((addr_t)addr);
-      if (increment_addr)
-          addr++;
-  }
-
-  /* Stop monitoring exerciser transactions */
-  val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
-
-  return test_sequence_check(instance);
-}
-
-/* Performs reads/write on 8B data */
-static uint32_t test_sequence_8B(uint64_t *addr, uint8_t increment_addr, uint32_t instance)
-{
-  uint64_t idx;
-  uint64_t write_val;
-  uint32_t pidx;
-  uint64_t *pattern_ptr;
-  /* Start monitoring exerciser transactions */
-  if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance))
-      return ACS_STATUS_SKIP;
-
-  run_flag = 1;
-
-  /* Send the transaction on incrementalt addresses */
-  for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) {
-      pidx = ((uint64_t)addr & 0xFF)/8;
-      pattern_ptr = (uint64_t *)&pattern;
-      write_val = pattern_ptr[pidx];
-      /* Write transaction */
-      if (transaction_order[idx])
-          val_mmio_write64((addr_t)addr, write_val);
-      else
-          val_mmio_read64((addr_t)addr);
-      if (increment_addr)
-          addr++;
-  }
-
-  /* Stop monitoring exerciser transactions */
-  val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
-
-  return test_sequence_check(instance);
-}
-
-/* Read and Write on config space mapped to Device memory */
 
 static
 void
-cfgspace_transactions_order_check(void)
-{
-  uint32_t instance;
-  uint32_t bdf;
-  char *baseptr;
-  uint32_t cid_offset;
-  uint64_t bdf_addr;
-
-  /* Read the number of excerciser cards */
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
-
-  while (instance-- != 0) {
-
-    /* if init fail moves to next exerciser */
-    if (val_exerciser_init(instance))
-        continue;
-
-    /* Get exerciser bdf */
-    bdf = val_exerciser_get_bdf(instance);
-
-    /* If exerciser doesn't have PCI_ECAP skip the bdf */
-    if (val_pcie_find_capability(bdf, PCIE_ECAP, CID_PCIECS, &cid_offset) == PCIE_CAP_NOT_FOUND)
-        continue;
-
-    bdf_addr = val_pcie_get_bdf_config_addr(bdf);
-
-    /* Map config space to ARM device memory in MMU page tables */
-    baseptr = (char *)val_memory_ioremap((void *)bdf_addr, 512, DEVICE_nGnRnE);
-
-    if (!baseptr) {
-        val_print(ACS_PRINT_ERR, "\n       Failed in config ioremap for instance %x", instance);
-        continue;
-    }
-
-    read_config_space((uint32_t *)baseptr);
-
-    /* Test Scenario 1 : Transactions on incremental aligned address */
-    fail_cnt += test_sequence_1B((uint8_t *)baseptr, 1, instance);
-    fail_cnt += test_sequence_2B((uint16_t *)baseptr, 1, instance);
-    fail_cnt += test_sequence_4B((uint32_t *)baseptr, 1, instance);
-
-    /* Test Scenario 2 : Transactions on same address */
-    fail_cnt += test_sequence_1B((uint8_t *)baseptr, 0, instance);
-    fail_cnt += test_sequence_2B((uint16_t *)baseptr, 0, instance);
-    fail_cnt += test_sequence_4B((uint32_t *)baseptr, 0, instance);
-
-  }
-}
-
-/* Read and Write on BAR space mapped to Device memory */
-
-static
-void
-barspace_transactions_order_check(void)
+payload(void)
 {
+  uint32_t pe_index;
+  uint32_t e_bdf;
+  uint32_t erp_bdf;
+  uint32_t reg_value;
   uint32_t instance;
-  exerciser_data_t e_data;
-  char *baseptr;
-
-  /* Read the number of excerciser cards */
+  uint64_t header_type;
+  uint32_t bus_value;
+  uint32_t test_skip = 1;
+  uint32_t cap_base;
+  uint32_t seg_num;
+  uint32_t sub_bus;
+  uint32_t dev_num;
+  uint32_t dev_bdf;
+  uint32_t sec_bus;
+  uint32_t dp_type;
+  uint32_t func_num;
+
+  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
   instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
 
-  while (instance-- != 0) {
-
-    /* if init fail moves to next exerciser */
-    if (val_exerciser_init(instance))
-        continue;
-
-    /* Get BAR 0 details for this instance */
-    if (val_exerciser_get_data(EXERCISER_DATA_BAR0_SPACE, &e_data, instance)) {
-        val_print(ACS_PRINT_ERR, "\n       Exerciser %d data read error     ", instance);
-        continue;
-    }
-
-    /* If BAR region is not Prefetchable, skip the exerciser */
-    if (e_data.bar_space.type != MMIO_PREFETCHABLE)
-        continue;
-
-    /* Map mmio space to ARM device memory in MMU page tables */
-    baseptr = (char *)val_memory_ioremap((void *)e_data.bar_space.base_addr, 512, DEVICE_nGnRnE);
+  while (instance-- != 0)
+  {
+      /* if init fail moves to next exerciser */
+      if (val_exerciser_init(instance))
+          continue;
+
+      e_bdf = val_exerciser_get_bdf(instance);
+
+      /* ARI Capability not applicable for RCiEP */
+      dp_type = val_pcie_device_port_type(e_bdf);
+      if (dp_type == RCiEP)
+          continue;
+
+      /* Check if exerciser is child of one of the rootports */
+      if (val_pcie_parent_is_rootport(e_bdf, &erp_bdf))
+          continue;
+
+      /* If test runs for atleast an endpoint */
+      test_skip = 0;
+
+      /* Enable the ARI forwarding enable bit in RP */
+      val_pcie_find_capability(erp_bdf, PCIE_CAP, CID_PCIECS, &cap_base);
+      val_pcie_read_cfg(erp_bdf, cap_base + DCTL2R_OFFSET, &reg_value);
+      reg_value &= DCTL2R_MASK;
+      reg_value |= (DCTL2R_AFE_MASK << DCTL2R_AFE_SHIFT);
+      val_pcie_write_cfg(erp_bdf, cap_base + DCTL2R_OFFSET, reg_value);
+
+      /* Enable the ARI forwarding enable bit in Exerciser */
+      val_pcie_find_capability(e_bdf, PCIE_CAP, CID_PCIECS, &cap_base);
+      val_pcie_read_cfg(e_bdf, cap_base + DCTL2R_OFFSET, &reg_value);
+      reg_value &= DCTL2R_MASK;
+      reg_value |= (DCTL2R_AFE_MASK << DCTL2R_AFE_SHIFT);
+      val_pcie_write_cfg(e_bdf, cap_base + DCTL2R_OFFSET, reg_value);
+
+      /* Read the secondary, subordinate bus and segment number */
+      val_pcie_read_cfg(erp_bdf, TYPE1_PBN, &bus_value);
+      sec_bus = ((bus_value >> SECBN_SHIFT) & SECBN_MASK);
+      sub_bus = ((bus_value >> SUBBN_SHIFT) & SUBBN_MASK);
+      seg_num = PCIE_EXTRACT_BDF_SEG(erp_bdf);
+
+      /*
+       * Generate a config request from PE to the Secondary bus
+       * of the exerciser's root port. Exerciser should see this
+       * request as a Type 0 Request.
+       */
+      for (dev_num = 0; dev_num < PCIE_MAX_DEV; dev_num++)
+      {
+          for (func_num = 0; func_num < PCIE_MAX_FUNC; func_num++)
+          {
+              /* Create bdf for function 0 to 255 below the RP and check request type */
+              dev_bdf = PCIE_CREATE_BDF(seg_num, sec_bus, dev_num, func_num);
+              val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance);
+              val_pcie_read_cfg(dev_bdf, TYPE01_VIDR, &reg_value);
+              val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
+              val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance);
+              if (header_type != TYPE0)
+              {
+                  val_print(ACS_PRINT_ERR, "\n       RP BDF 0x%x ", erp_bdf);
+                  val_print(ACS_PRINT_ERR, "Transaction not Type0 on sec bus",
+                                                                           0);
+                  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1));
+                  return;
+              }
+          }
+      }
 
-    if (!baseptr) {
-        val_print(ACS_PRINT_ERR, "\n       Failed in BAR ioremap for instance %x", instance);
-        continue;;
-    }
+      /* Skip the port, if there is only one device below it */
+      if (sec_bus == sub_bus)
+          continue;
+
+      /* Change the bus number to a Bus number > RP secondary bus number
+       * and < RP subordinate bus number.
+       */
+      bus_value &= SECBN_EXTRACT;
+      bus_value |= (sec_bus + 1) << SECBN_SHIFT;
+      val_pcie_write_cfg(erp_bdf, TYPE1_PBN, bus_value);
+
+      /*
+       * Generate a config request from PE to the Secondary bus
+       * of the exerciser's root port. Exerciser should see this
+       * request as a Type 1 Request.
+       */
+      for (dev_num = 0; dev_num < PCIE_MAX_DEV; dev_num++)
+      {
+          for (func_num = 0; func_num < PCIE_MAX_FUNC; func_num++)
+          {
+              /* Create bdf for function 0 to 255 below the RP and check request type */
+              dev_bdf = PCIE_CREATE_BDF(seg_num, sec_bus, dev_num, func_num);
+              val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance);
+              val_pcie_read_cfg(dev_bdf, TYPE01_VIDR, &reg_value);
+              val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
+              val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance);
+              if (header_type != TYPE1)
+              {
+                  val_print(ACS_PRINT_ERR, "\n       RP BDF 0x%x ", erp_bdf);
+                  val_print(ACS_PRINT_ERR, "Transaction not Type1 on sec bus",
+                                                                            0);
+                  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
+                  return;
+              }
+          }
+      }
 
-    /* Test Scenario 1 : Transactions on incremental aligned address */
-    fail_cnt += test_sequence_1B((uint8_t *)baseptr, 1, instance);
-    fail_cnt += test_sequence_2B((uint16_t *)baseptr, 1, instance);
-    fail_cnt += test_sequence_4B((uint32_t *)baseptr, 1, instance);
-    fail_cnt += test_sequence_8B((uint64_t *)baseptr, 1, instance);
+      /* Restore the Bus value */
+      bus_value &= SECBN_EXTRACT;
+      bus_value |= (sec_bus - 1) << SECBN_SHIFT;
+      val_pcie_write_cfg(erp_bdf, TYPE1_PBN, bus_value);
 
-    /* Test Scenario 2 : Transactions on same address */
-    fail_cnt += test_sequence_1B((uint8_t *)baseptr, 0, instance);
-    fail_cnt += test_sequence_2B((uint16_t *)baseptr, 0, instance);
-    fail_cnt += test_sequence_4B((uint32_t *)baseptr, 0, instance);
-    fail_cnt += test_sequence_8B((uint64_t *)baseptr, 0, instance);
   }
-}
 
-static
-void
-payload(void)
-{
-  uint32_t pe_index;
-
-  pe_index = val_pe_get_index_mpid (val_pe_get_mpid());
+  if (test_skip)
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
+  else
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
-  cfgspace_transactions_order_check();
-  barspace_transactions_order_check();
+  return;
 
-  if (!run_flag) {
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  if (fail_cnt)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
 }
 
 uint32_t
@@ -342,9 +184,9 @@ os_e015_entry(void)
       val_run_test_payload(TEST_NUM, num_pe, payload, 0);
 
   /* Get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
+  status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
 
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
+  val_report_status(0, BSA_ACS_END(TEST_NUM), NULL);
 
   return status;
 }
diff --git a/test_pool/gic/hypervisor/test_hyp_g001.c b/test_pool/gic/hypervisor/test_hyp_g001.c
index 0b26dca4..c769f20c 100644
--- a/test_pool/gic/hypervisor/test_hyp_g001.c
+++ b/test_pool/gic/hypervisor/test_hyp_g001.c
@@ -38,7 +38,7 @@ isr_vir()
   /* We received our interrupt, so disable timer from generating further interrupts */
   val_timer_set_vir_el2(0);
   val_print(ACS_PRINT_INFO, "\n       Received interrupt    ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(intid);
 }
 
@@ -51,7 +51,7 @@ isr_phy()
   /* We received our interrupt, so disable timer from generating further interrupts */
   val_timer_set_phy_el2(0);
   val_print(ACS_PRINT_INFO, "\n       Received interrupt     ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(intid);
 }
 
@@ -68,7 +68,7 @@ isr_mnt()
   data &= ~0x7;
   val_gic_reg_write(ICH_HCR_EL2, data);
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_print(ACS_PRINT_INFO, "\n       Received GIC maintenance interrupt ", 0);
   val_gic_end_of_interrupt(intid);
 
@@ -92,7 +92,7 @@ payload()
   if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) {
       val_print(ACS_PRINT_DEBUG, "\n       Skipping. Test accesses EL2"
                                     " Registers       ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -105,10 +105,10 @@ payload()
   /* Check for EL2 virtual timer interrupt, if PE supports 8.1 or greater */
   if ((data >> 8) & 0xF) {
     intid = val_timer_get_info(TIMER_INFO_VIR_EL2_INTID, 0);
-    if (intid > 15 && intid < 32) {
+    if ((intid > 15 && intid < 32) || val_gic_is_valid_eppi(intid)) {
         if (val_gic_install_isr(intid, isr_vir)) {
             val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
             return;
         }
 
@@ -121,27 +121,28 @@ payload()
         if (timeout == 0) {
             val_print(ACS_PRINT_ERR,
                 "\n       EL2-Virtual timer interrupt %d not received", intid);
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
         }
     } else
         val_print(ACS_PRINT_DEBUG,
-          "\n       EL2-Virtual timer interrupt not mapped to PPI", intid);
+          "\n       EL2-Virtual timer interrupt not mapped"
+          "\n       to PPI                                ", intid);
   } else
         val_print(ACS_PRINT_DEBUG, "\n       v8.1 VHE not supported on this PE ", 0);
 
   // Check non-secure EL2 physical timer
   val_set_status(index, RESULT_PENDING(TEST_NUM));
   intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0);
-  if (intid < 16 || intid > 31) {
+  if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid))) {
       val_print(ACS_PRINT_DEBUG,
           "\n       EL2-Phy timer not mapped to PPI base range, INTID: %d   ", intid);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
       return;
   }
 
   if (val_gic_install_isr(intid, isr_phy)) {
      val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-     val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+     val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
      return;
   }
 
@@ -154,22 +155,23 @@ payload()
   if (timeout == 0) {
     val_print(ACS_PRINT_ERR,
         "\n       EL2-Phy timer interrupt not received on INTID: %d   ", intid);
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 05));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 5));
   }
 
   // Check maintenance interrupt
   val_set_status(index, RESULT_PENDING(TEST_NUM));
   intid = val_pe_get_gmain_gsiv(index);
-  if (intid < 16 || intid > 31) {
+  if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid))) {
       val_print(ACS_PRINT_DEBUG,
-          "\n       GIC Maintenance interrupt not mapped to PPI base range, INTID: %d   ", intid);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 05));
+          "\n       GIC Maintenance interrupt not mapped to PPI base range,"
+          "\n       INTID: %d   ", intid);
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 5));
       return;
   }
 
   if (val_gic_install_isr(intid, isr_mnt)) {
      val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-     val_set_status(index, RESULT_FAIL(TEST_NUM, 06));
+     val_set_status(index, RESULT_FAIL(TEST_NUM, 6));
      return;
   }
 
@@ -184,7 +186,7 @@ payload()
 
   if (timeout == 0) {
       val_print(ACS_PRINT_ERR, "\n       Interrupt not received within timeout", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 07));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 7));
       return;
   }
   return;
diff --git a/test_pool/gic/operating_system/test_os_g001.c b/test_pool/gic/operating_system/test_os_g001.c
index faca3841..d94fc376 100755
--- a/test_pool/gic/operating_system/test_os_g001.c
+++ b/test_pool/gic/operating_system/test_os_g001.c
@@ -37,11 +37,11 @@ payload()
 
   if (gic_version < 2) {
       val_print(ACS_PRINT_ERR, "\n       GIC version is %x                 ", gic_version);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/gic/operating_system/test_os_g002.c b/test_pool/gic/operating_system/test_os_g002.c
index 0add14c9..0ea7f2ff 100755
--- a/test_pool/gic/operating_system/test_os_g002.c
+++ b/test_pool/gic/operating_system/test_os_g002.c
@@ -48,15 +48,15 @@ payload()
   if (gic_version < 3) {
     if ((num_ecam > 0) && (num_msi_frame == 0)) {
       val_print(ACS_PRINT_ERR, "\n       GICv2 with PCIe : Invalid Configuration", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
     }
   } else {
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
     return;
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/gic/operating_system/test_os_g003.c b/test_pool/gic/operating_system/test_os_g003.c
index c51e80b9..fdca6e98 100755
--- a/test_pool/gic/operating_system/test_os_g003.c
+++ b/test_pool/gic/operating_system/test_os_g003.c
@@ -44,7 +44,7 @@ payload()
     if (data == 0)
     {
         val_print(ACS_PRINT_ERR, "\n       GICv3 and PCIe : ITS Not Present", 0);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
         return;
     }
 
@@ -52,17 +52,17 @@ payload()
     if (data == 0)
     {
         val_print(ACS_PRINT_ERR, "\n       GICv3 and PCIe : LPI Not Supported", 0);
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
         return;
     }
 
-    val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+    val_set_status(index, RESULT_PASS(TEST_NUM, 1));
     return;
   }
 
   /* If PCIe is not present or Gic version is older then GICv3,
      just Skip the test */
-  val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+  val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/gic/operating_system/test_os_g004.c b/test_pool/gic/operating_system/test_os_g004.c
index b0ecf259..2eb81917 100755
--- a/test_pool/gic/operating_system/test_os_g004.c
+++ b/test_pool/gic/operating_system/test_os_g004.c
@@ -34,17 +34,17 @@ payload()
 
   gic_version = val_gic_get_info(GIC_INFO_VERSION);
   if (gic_version < 3) {
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
     return;
   }
 
   data = val_gic_get_info(GIC_INFO_SEC_STATES);
   if (data != 0) {
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     return;
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/gic/operating_system/test_os_g005.c b/test_pool/gic/operating_system/test_os_g005.c
index 202bb348..a420d3e2 100644
--- a/test_pool/gic/operating_system/test_os_g005.c
+++ b/test_pool/gic/operating_system/test_os_g005.c
@@ -52,8 +52,8 @@ payload()
 
   // Distributor must forward NS Group 1 interrupt
   if (!enable_grp1ns) {
-    val_print(ACS_PRINT_ERR, "\n      Non-secure SGIs not forwarded", 0);
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+    val_print(ACS_PRINT_ERR, "\n       Non-secure SGIs not forwarded", 0);
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     return;
   }
   else {
@@ -64,15 +64,15 @@ payload()
         val_mmio_write(val_get_gicr_base(&rdbase_len) + RD_FRAME_SIZE + GICR_ISENABLER, data);
         data = VAL_EXTRACT_BITS(val_gic_get_info(GIC_INFO_SGI_NON_SECURE), 0, 7);
         if (data == 0xFF) {
-            val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+            val_set_status(index, RESULT_PASS(TEST_NUM, 1));
             return;
         }
         else {
             val_print(ACS_PRINT_DEBUG,
-                "\n      GICR_ISENABLER0: %X\n ", data);
+                "\n       GICR_ISENABLER0: %X\n ", data);
             val_print(ACS_PRINT_ERR,
-                "\n      INTID 0 - 7 not implemented as non-secure SGIs", 0);
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+                "\n       INTID 0 - 7 not implemented as non-secure SGIs", 0);
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
             return;
         }
     }
@@ -82,15 +82,15 @@ payload()
         val_mmio_write((val_get_gicd_base() + GICD_ISENABLER), data);
         data = VAL_EXTRACT_BITS(val_gic_get_info(GIC_INFO_SGI_NON_SECURE_LEGACY), 0, 7);
         if (data == 0xFF) {
-            val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+            val_set_status(index, RESULT_PASS(TEST_NUM, 1));
             return;
         }
         else {
             val_print(ACS_PRINT_DEBUG,
-                "\n      GICD_IENABLER<n>: %X\n ", data);
+                "\n       GICD_IENABLER<n>: %X\n ", data);
             val_print(ACS_PRINT_ERR,
-                "\n      INTID 0 - 7 not implemented as non-secure SGIs", 0);
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+                "\n       INTID 0 - 7 not implemented as non-secure SGIs", 0);
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
             return;
         }
     }
diff --git a/test_pool/gic/operating_system/test_os_g006.c b/test_pool/gic/operating_system/test_os_g006.c
index 36ee5d3a..01caa630 100644
--- a/test_pool/gic/operating_system/test_os_g006.c
+++ b/test_pool/gic/operating_system/test_os_g006.c
@@ -33,7 +33,7 @@ isr_phy()
 {
   val_timer_set_phy_el1(0);
   val_print(ACS_PRINT_INFO, "\n       Received interrupt   ", 0);
-  val_set_status(0, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(0, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(intid);
 }
 
@@ -43,7 +43,7 @@ isr_vir()
 {
   val_timer_set_vir_el1(0);
   val_print(ACS_PRINT_INFO, "\n       Received interrupt   ", 0);
-  val_set_status(0, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(0, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(intid);
 }
 
@@ -64,7 +64,7 @@ payload()
 
   /* Check non-secure physical timer assignment */
   intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0);
-  if (intid < 16 || intid > 31)
+  if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid)))
       val_print(ACS_PRINT_WARN,
           "\n       EL0-Phy timer not mapped to PPI recommended range, INTID: %d   ", intid);
 
@@ -78,14 +78,14 @@ payload()
   if (timeout == 0) {
     val_print(ACS_PRINT_ERR,
         "\n       EL0-Phy timer interrupt not received on INTID: %d   ", intid);
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     return;
   }
 
   /* Check non-secure virtual timer assignment */
   val_set_status(0, RESULT_PENDING(TEST_NUM));
   intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0);
-  if (intid < 16 || intid > 31)
+  if ((intid < 16 || intid > 31) && (!val_gic_is_valid_eppi(intid)))
       val_print(ACS_PRINT_WARN,
           "\n       EL0-Virtual timer not mapped to PPI recommended range, INTID: %d   ", intid);
 
@@ -99,7 +99,7 @@ payload()
   if (timeout == 0) {
     val_print(ACS_PRINT_ERR,
         "\n       EL0-Virtual timer interrupt not received on INTID: %d   ", intid);
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     return;
   }
 
diff --git a/test_pool/gic/operating_system/test_os_its001.c b/test_pool/gic/operating_system/test_os_its001.c
index 8ed2772f..3d039479 100644
--- a/test_pool/gic/operating_system/test_os_its001.c
+++ b/test_pool/gic/operating_system/test_os_its001.c
@@ -33,13 +33,13 @@ payload()
   status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group);
   if (status) {
       val_print(ACS_PRINT_ERR, "\n       ITS get group number failed          ", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 0x1));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
 
   if (!num_group) {
       val_print(ACS_PRINT_DEBUG, "\n       No ITS group found            ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 0x1));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
   val_print(ACS_PRINT_DEBUG, "\n       Number of ITS groups = %d", num_group);
@@ -47,17 +47,18 @@ payload()
       status = val_iovirt_get_its_info(ITS_GROUP_NUM_BLOCKS, i, 0, &num_blocks);
       if (status) {
           val_print(ACS_PRINT_ERR, "\n       ITS get number of blocks failed        ", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x2));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           return;
       }
       if (!num_blocks) {
           val_print(ACS_PRINT_ERR, "\n       No valid ITS Blocks found in group %d  ", i);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x3));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
           return;
       }
-      val_print(ACS_PRINT_DEBUG, "\n       Number of ITS Blocks = %d", num_blocks);
+      val_print(ACS_PRINT_DEBUG, "\n       Number of ITS Blocks = %d        "
+                                            "      ", num_blocks);
   }
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/gic/operating_system/test_os_its002.c b/test_pool/gic/operating_system/test_os_its002.c
index 50364051..8f1cdac1 100644
--- a/test_pool/gic/operating_system/test_os_its002.c
+++ b/test_pool/gic/operating_system/test_os_its002.c
@@ -34,12 +34,12 @@ payload()
   status = val_iovirt_get_its_info(ITS_NUM_GROUPS, 0, 0, &num_group);
   if (status) {
       val_print(ACS_PRINT_ERR, "\n       ITS get group number failed          ", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 0x1));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
   if (!num_group) {
       val_print(ACS_PRINT_DEBUG, "\n       No ITS group found            ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 0x1));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -49,13 +49,13 @@ payload()
       status = val_iovirt_get_its_info(ITS_GROUP_NUM_BLOCKS, i, 0, &num_blocks);
       if (status) {
           val_print(ACS_PRINT_ERR, "\n       ITS get number of blocks failed        ", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x2));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           return;
       }
 
       if (!num_blocks) {
           val_print(ACS_PRINT_ERR, "\n       No valid ITS Blocks found in group %d  ", i);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x3));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
           return;
       }
       val_print(ACS_PRINT_DEBUG, "\n       ITS group index      = %d", i);
@@ -65,24 +65,25 @@ payload()
           status = val_iovirt_get_its_info(ITS_GET_ID_FOR_BLK_INDEX, i, j, &its_id);
           if (status) {
               val_print(ACS_PRINT_ERR, "\n       ITS get id failed        ", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 0x4));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
               return;
           }
 
-          val_print(ACS_PRINT_DEBUG, "\n       ITS block index  = %d", j);
+          val_print(ACS_PRINT_DEBUG, "\n       ITS block index  = %d         "
+                                            "         ", j);
           for (k = (i + 1); k < num_group; k++) {
               status =
                   val_iovirt_get_its_info(ITS_GET_BLK_INDEX_FOR_ID, k, its_id, &blk_index);
               if (status != ACS_INVALID_INDEX) {
                   val_print(ACS_PRINT_ERR, "\n       ITS ID (%d) repeated in multiple groups",
                             its_id);
-                  val_set_status(index, RESULT_FAIL(TEST_NUM, 0x5));
+                  val_set_status(index, RESULT_FAIL(TEST_NUM, 5));
                   return;
               }
           }
       }
   }
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/gic/operating_system/test_os_its003.c b/test_pool/gic/operating_system/test_os_its003.c
new file mode 100644
index 00000000..c2df4163
--- /dev/null
+++ b/test_pool/gic/operating_system/test_os_its003.c
@@ -0,0 +1,128 @@
+/** @file
+ * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **/
+#include "val/include/bsa_acs_val.h"
+#include "val/include/val_interface.h"
+#include "val/include/bsa_acs_iovirt.h"
+#include "val/include/bsa_acs_pcie.h"
+
+#define TEST_NUM   (ACS_GIC_ITS_TEST_NUM_BASE + 3)
+#define TEST_RULE  "ITS_DEV_2"
+#define TEST_DESC  "Check uniqueness of StreamID          "
+
+static uint32_t streamID[PCIE_MAX_DEV];
+
+static
+void
+payload()
+{
+  uint32_t bdf;
+  uint32_t status;
+  uint32_t pe_index;
+  uint32_t tbl_index;
+  uint32_t dev_index = 0;
+  uint32_t device_id, req_id;
+  uint32_t stream_id, its_id;
+  uint32_t cap_base;
+  uint32_t test_skip = 1;
+  pcie_device_bdf_table *bdf_tbl_ptr;
+  int32_t prev_its_id = -1, i, j;
+
+  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
+  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
+
+  /* Check for all the function present in bdf table */
+  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
+  {
+    bdf = bdf_tbl_ptr->device[tbl_index].bdf;
+
+    /* If MSI or MSI-X not supported, Skip current device */
+    if ((val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base) == PCIE_CAP_NOT_FOUND) &&
+        (val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base) == PCIE_CAP_NOT_FOUND))
+      continue;
+
+    /* If test runs for atleast an endpoint */
+    test_skip = 0;
+
+    /* If MSI Supported then Check for Valid DeviceID */
+    req_id = GET_DEVICE_ID(PCIE_EXTRACT_BDF_BUS(bdf),
+                           PCIE_EXTRACT_BDF_DEV(bdf),
+                           PCIE_EXTRACT_BDF_FUNC(bdf));
+
+    status = val_iovirt_get_device_info(req_id, PCIE_EXTRACT_BDF_SEG(bdf), &device_id,
+                                        &stream_id, &its_id);
+    if (status) {
+        val_print(ACS_PRINT_DEBUG,
+            "\n       Could not get device info for BDF : 0x%x", bdf);
+        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1));
+        return;
+    }
+
+    /* Update ITS id for first group */
+    if (prev_its_id == -1)
+      prev_its_id = its_id;
+
+    /* Update streamID & index for the last device before checking streamID uniqueness*/
+    if (tbl_index == (bdf_tbl_ptr->num_entries - 1)) {
+      streamID[dev_index] = stream_id;
+      dev_index++;
+    }
+
+    /* Check uniqueness of streamID if ITS group changed or for the last group*/
+    if ((prev_its_id != its_id) || (tbl_index == (bdf_tbl_ptr->num_entries - 1))) {
+      for (i = 0; i < (dev_index - 1); i++) {
+          for (j = (i + 1); j < dev_index; j++) {
+            if (streamID[i] == streamID[j]) {
+                val_print(ACS_PRINT_DEBUG,
+                        "\n       Stream ID is not unique for bdf : 0x%x", bdf);
+                val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
+                return;
+            }
+          }
+      }
+      prev_its_id = its_id;
+      dev_index = 0;
+    }
+    /* Skip exicuting remaining steps for last device to avoid buffer overflow*/
+    if (tbl_index == (bdf_tbl_ptr->num_entries - 1))
+      break;
+
+    /* Update streamID & index */
+    streamID[dev_index] = stream_id;
+    dev_index++;
+  }
+
+  if (test_skip == 1)
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
+  else
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
+}
+
+uint32_t
+os_its003_entry(uint32_t num_pe)
+{
+  uint32_t status = ACS_STATUS_FAIL;
+
+  num_pe = 1;  //This test is run on single processor
+
+  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
+  if (status != ACS_STATUS_SKIP)
+      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
+  /* get the result from all PE and check for failure */
+  status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
+  val_report_status(0, BSA_ACS_END(TEST_NUM), NULL);
+
+  return status;
+}
diff --git a/test_pool/gic/operating_system/test_os_its004.c b/test_pool/gic/operating_system/test_os_its004.c
new file mode 100644
index 00000000..7821a7be
--- /dev/null
+++ b/test_pool/gic/operating_system/test_os_its004.c
@@ -0,0 +1,135 @@
+/** @file
+ * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **/
+#include "val/include/bsa_acs_val.h"
+#include "val/include/val_interface.h"
+#include "val/include/bsa_acs_iovirt.h"
+#include "val/include/bsa_acs_pcie.h"
+
+#define TEST_NUM   (ACS_GIC_ITS_TEST_NUM_BASE + 4)
+#define TEST_RULE  "ITS_DEV_7,ITS_DEV_8"
+#define TEST_DESC  "Check Device's ReqID-DeviceID-StreamID"
+
+static
+void
+payload()
+{
+  uint32_t bdf;
+  uint32_t status;
+  uint32_t pe_index;
+  uint32_t tbl_index;
+  uint32_t device_id, req_id;
+  uint32_t stream_id, its_id;
+  uint32_t cap_base;
+  uint32_t test_skip = 1;
+  uint32_t curr_grp_did_cons, curr_grp_sid_cons;
+  uint32_t curr_grp_its_id = -1;
+  pcie_device_bdf_table *bdf_tbl_ptr;
+
+  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
+  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
+
+  /* Check for all the function present in bdf table */
+  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
+  {
+    bdf = bdf_tbl_ptr->device[tbl_index].bdf;
+
+    /* If MSI or MSI-X not supported, Skip current device */
+    if ((val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base) == PCIE_CAP_NOT_FOUND) &&
+        (val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base) == PCIE_CAP_NOT_FOUND))
+      continue;
+
+    /* If test runs for atleast an endpoint */
+    test_skip = 0;
+
+    /* If MSI Supported then Check for Valid DeviceID */
+    req_id = PCIE_CREATE_BDF_PACKED(bdf);
+
+    status = val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(bdf),
+                                        PCIE_EXTRACT_BDF_SEG(bdf), &device_id,
+                                        &stream_id, &its_id);
+    if (status) {
+        val_print(ACS_PRINT_DEBUG, "\n       Could not get device info for BDF : 0x%x", bdf);
+        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1));
+        return;
+    }
+
+    /* Store the Current group SID Constant offset & Dev ID Constant offset using first device */
+    if (its_id != curr_grp_its_id) {
+      curr_grp_its_id = its_id;
+
+      /* stream_id returned is 0 when Root Complex is not behind an SMMU */
+      if (stream_id != 0) {
+        /* Device behind SMMU */
+        curr_grp_sid_cons = stream_id - req_id;
+        curr_grp_did_cons = device_id - stream_id;
+      } else {
+        /* No SMMU, stream_id returned is 0 */
+        curr_grp_sid_cons = 0;
+        curr_grp_did_cons = device_id - req_id;
+      }
+      continue;
+    }
+
+    if (stream_id == 0) {
+      /* No SMMU, Check only for device_id */
+      if (curr_grp_did_cons != (device_id - req_id)) {
+        /* DeviceID Constant Base Failure */
+        val_print(ACS_PRINT_DEBUG,
+                  "\n       ReqID-DeviceID Association Fail for Bdf : %x", bdf);
+        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
+        return;
+      }
+    } else {
+      /* Check for stream_id & device_id */
+      if (curr_grp_sid_cons != (stream_id - req_id)) {
+        /* StreamID Constant Base Failure */
+        val_print(ACS_PRINT_DEBUG, "\n       ReqID-StreamID Association Fail for Bdf : %x", bdf);
+        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3));
+        return;
+      }
+
+      if (curr_grp_did_cons != (device_id - stream_id)) {
+        /* DeviceID Constant Base Failure */
+        val_print(ACS_PRINT_DEBUG,
+                  "\n       StreamID-DeviceID Association Fail for Bdf : %x", bdf);
+        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4));
+        return;
+      }
+    }
+  }
+
+  if (test_skip == 1)
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
+  else
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
+}
+
+uint32_t
+os_its004_entry(uint32_t num_pe)
+{
+  uint32_t status = ACS_STATUS_FAIL;
+  num_pe = 1;  //This test is run on single processor
+
+  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
+  if (status != ACS_STATUS_SKIP)
+      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
+
+  /* get the result from all PE and check for failure */
+  status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
+
+  val_report_status(0, BSA_ACS_END(TEST_NUM), NULL);
+  return status;
+}
diff --git a/test_pool/gic/operating_system/test_os_v2m001.c b/test_pool/gic/operating_system/test_os_v2m001.c
index 2803ed2a..ffbaeb3d 100644
--- a/test_pool/gic/operating_system/test_os_v2m001.c
+++ b/test_pool/gic/operating_system/test_os_v2m001.c
@@ -40,7 +40,7 @@ payload()
   msi_frame   = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
   if (msi_frame == 0) {
       val_print(ACS_PRINT_DEBUG, "\n       No MSI frame, Skipping               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -59,7 +59,7 @@ payload()
       /* Read GICD_ICFGR register to Check for Level/Edge Sensitive. */
       status = val_gic_get_intr_trigger_type(spi_id, &trigger_type);
       if (status) {
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
         return;
       }
 
@@ -72,17 +72,17 @@ payload()
 
   if (test_skip) {
       val_print(ACS_PRINT_WARN, "\n       No SPI Information Found. Skipping   ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
       return;
   }
 
   if (fail_cnt) {
       val_print(ACS_PRINT_ERR, "\n       SPI Trigger Type Check Failed", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
       return;
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/gic/operating_system/test_os_v2m002.c b/test_pool/gic/operating_system/test_os_v2m002.c
index d42c617a..580d691e 100644
--- a/test_pool/gic/operating_system/test_os_v2m002.c
+++ b/test_pool/gic/operating_system/test_os_v2m002.c
@@ -39,7 +39,7 @@ payload()
   msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
   if (msi_frame == 0) {
       val_print(ACS_PRINT_DEBUG, "\n       No MSI frame, Skipping               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -85,11 +85,11 @@ payload()
 
   if (fail_cnt) {
       val_print(ACS_PRINT_ERR, "\n       MSI_TYPER Register Check Failed", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/gic/operating_system/test_os_v2m003.c b/test_pool/gic/operating_system/test_os_v2m003.c
index d796305e..46abd5ef 100644
--- a/test_pool/gic/operating_system/test_os_v2m003.c
+++ b/test_pool/gic/operating_system/test_os_v2m003.c
@@ -33,7 +33,7 @@ isr()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
   val_print(ACS_PRINT_INFO, "\n Received SPI ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(int_id);
 
   return;
@@ -54,7 +54,7 @@ payload()
   msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
   if (msi_frame == 0) {
       val_print(ACS_PRINT_DEBUG, "\n       No MSI frame, Skipping               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -69,7 +69,7 @@ payload()
     /* Register an interrupt handler to verify */
     if (val_gic_install_isr(int_id, isr)) {
       val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
     }
 
@@ -83,7 +83,7 @@ payload()
 
     if (timeout == 0) {
       val_print(ACS_PRINT_ERR, "\n       Interrupt not received within timeout", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
       return;
     }
 
@@ -97,7 +97,7 @@ payload()
 
     if (timeout == 0) {
       val_print(ACS_PRINT_ERR, "\n       Interrupt not received within timeout", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
       return;
     }
   }
diff --git a/test_pool/gic/operating_system/test_os_v2m004.c b/test_pool/gic/operating_system/test_os_v2m004.c
index 8ee13579..664c3392 100644
--- a/test_pool/gic/operating_system/test_os_v2m004.c
+++ b/test_pool/gic/operating_system/test_os_v2m004.c
@@ -33,7 +33,7 @@ isr()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
   val_print(ACS_PRINT_INFO, "\n Received SPI ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(int_id);
 
   return;
@@ -56,7 +56,7 @@ payload()
   msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
   if (msi_frame == 0) {
       val_print(ACS_PRINT_DEBUG, "\n       No MSI frame, Skipping               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -71,7 +71,7 @@ payload()
     /* Register an interrupt handler to verify */
     if (val_gic_install_isr(int_id, isr)) {
       val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
     }
 
@@ -92,7 +92,7 @@ payload()
     /* If the Status is changed that means interrupt handler is called & test is failed. */
     if (timeout != 0) {
       val_print(ACS_PRINT_ERR, "\n       Interrupt generated by GICD registers", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
       return;
     }
 
@@ -106,7 +106,7 @@ payload()
 
     if (timeout == 0) {
       val_print(ACS_PRINT_ERR, "\n       Interrupt not received within timeout", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
       return;
     }
   }
diff --git a/test_pool/gic_v2m/operating_system/test_os_v001.c b/test_pool/gic_v2m/operating_system/test_os_v001.c
deleted file mode 100755
index 2d0a7797..00000000
--- a/test_pool/gic_v2m/operating_system/test_os_v001.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/** @file
- * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_gic.h"
-
-#define TEST_NUM   (ACS_GIC_V2M_TEST_NUM_BASE + 1)
-#define TEST_DESC  "Check MSI SPI are Edge Triggered            "
-
-static
-void
-payload()
-{
-
-  uint32_t status;
-  uint32_t test_skip;
-  uint32_t fail_cnt, instance;
-  uint32_t msi_frame, spi_id;
-  uint32_t spi_base, num_spi;
-  INTR_TRIGGER_INFO_TYPE_e trigger_type;
-  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  msi_frame   = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
-  if (msi_frame == 0) {
-      val_print(ACS_PRINT_DEBUG, "\n       No MSI frame, Skipping               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  fail_cnt = 0;
-  test_skip = 1;
-
-  for (instance = 0; instance < msi_frame; instance++) {
-    spi_base = val_gic_v2m_get_info(V2M_MSI_SPI_BASE, instance);
-    num_spi  = val_gic_v2m_get_info(V2M_MSI_SPI_NUM, instance);
-
-    /* Check All the SPIs which are mapped to MSI are Edge Triggered */
-    for (spi_id = spi_base; spi_id < spi_base+num_spi; spi_id++) {
-
-      test_skip = 0;
-
-      /* Read GICD_ICFGR register to Check for Level/Edge Sensitive. */
-      status = val_gic_get_intr_trigger_type(spi_id, &trigger_type);
-      if (status) {
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
-        return;
-      }
-
-      if (trigger_type != INTR_TRIGGER_INFO_EDGE_RISING) {
-        val_print(ACS_PRINT_DEBUG, "\n       Error : SPI ID 0x%x Level Triggered ", spi_id);
-        fail_cnt++;
-      }
-    }
-  }
-
-  if (test_skip) {
-      val_print(ACS_PRINT_WARN, "\n       No SPI Information Found. Skipping   ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
-      return;
-  }
-
-  if (fail_cnt) {
-      val_print(ACS_PRINT_ERR, "\n       SPI Trigger Type Check Failed", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
-      return;
-  }
-
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_v001_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This GIC test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/gic_v2m/operating_system/test_os_v002.c b/test_pool/gic_v2m/operating_system/test_os_v002.c
deleted file mode 100755
index 0316047a..00000000
--- a/test_pool/gic_v2m/operating_system/test_os_v002.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/** @file
- * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_gic.h"
-
-#define TEST_NUM   (ACS_GIC_V2M_TEST_NUM_BASE + 2)
-#define TEST_DESC  "Check GICv2m MSI Frame Register             "
-
-static
-void
-payload()
-{
-
-  uint32_t num_spi;
-  uint32_t data, new_data;
-  uint32_t fail_cnt, instance;
-  uint32_t msi_frame, min_spi_id;
-  uint64_t frame_base;
-  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
-  if (msi_frame == 0) {
-      val_print(ACS_PRINT_DEBUG, "\n       No MSI frame, Skipping               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  fail_cnt = 0;
-
-  for (instance = 0; instance < msi_frame; instance++) {
-    frame_base = val_gic_v2m_get_info(V2M_MSI_FRAME_BASE, instance);
-
-    /* Part 1 : GICv2m_MSI_TYPER Read Only Register */
-    data = val_mmio_read(frame_base + GICv2m_MSI_TYPER);
-
-    /* Try Changing all the bits of the RO register */
-    val_mmio_write(frame_base + GICv2m_MSI_TYPER, (data ^ 0xFFFFFFFF));
-
-    new_data = val_mmio_read(frame_base + GICv2m_MSI_TYPER);
-    if (data != new_data) {
-      fail_cnt++;
-      val_print(ACS_PRINT_DEBUG, "\n       MSI_TYPER RO Check Failed for instance %d", instance);
-    }
-
-    /* Part 2 : Check SPI ID allocated is b/w 32-1020 */
-    min_spi_id = val_gic_v2m_get_info(V2M_MSI_SPI_BASE, instance);
-    num_spi  = val_gic_v2m_get_info(V2M_MSI_SPI_NUM, instance);
-
-    if ((min_spi_id < 32) || (min_spi_id + num_spi) > 1020) {
-      fail_cnt++;
-      val_print(ACS_PRINT_DEBUG, "\n       SPI ID Check Failed for instance %d", instance);
-    }
-
-    /* Part 3 : GICv2m_MSI_IIDR Read Only Register */
-    data = val_mmio_read(frame_base + GICv2m_MSI_IIDR);
-
-    /* Try Changing all the bits of the RO register */
-    val_mmio_write(frame_base + GICv2m_MSI_IIDR, (data ^ 0xFFFFFFFF));
-
-    new_data = val_mmio_read(frame_base + GICv2m_MSI_IIDR);
-    if (data != new_data) {
-      fail_cnt++;
-      val_print(ACS_PRINT_DEBUG, "\n       MSI_IIDR RO Check Failed for instance %d", instance);
-    }
-
-  }
-
-  if (fail_cnt) {
-      val_print(ACS_PRINT_ERR, "\n       MSI_TYPER Register Check Failed", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
-      return;
-  }
-
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_v002_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This GIC test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/gic_v2m/operating_system/test_os_v003.c b/test_pool/gic_v2m/operating_system/test_os_v003.c
deleted file mode 100755
index 60c93bba..00000000
--- a/test_pool/gic_v2m/operating_system/test_os_v003.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/** @file
- * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_gic.h"
-
-#define TEST_NUM   (ACS_GIC_V2M_TEST_NUM_BASE + 3)
-#define TEST_DESC  "Check GICv2m MSI to SPI Generation          "
-
-static uint32_t int_id;
-
-static
-void
-isr()
-{
-  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  val_print(ACS_PRINT_INFO, "\n Received SPI ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
-  val_gic_end_of_interrupt(int_id);
-
-  return;
-}
-
-static
-void
-payload()
-{
-
-  uint32_t num_spi;
-  uint32_t instance;
-  uint32_t timeout = TIMEOUT_MEDIUM;
-  uint32_t msi_frame, min_spi_id;
-  uint64_t frame_base;
-  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
-  if (msi_frame == 0) {
-      val_print(ACS_PRINT_DEBUG, "\n       No MSI frame, Skipping               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  for (instance = 0; instance < msi_frame; instance++) {
-    frame_base = val_gic_v2m_get_info(V2M_MSI_FRAME_BASE, instance);
-
-    min_spi_id = val_gic_v2m_get_info(V2M_MSI_SPI_BASE, instance);
-    num_spi  = val_gic_v2m_get_info(V2M_MSI_SPI_NUM, instance);
-
-    int_id = min_spi_id + num_spi - 1;
-
-    /* Register an interrupt handler to verify */
-    if (val_gic_install_isr(int_id, isr)) {
-      val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
-      return;
-    }
-
-    /* Part 1 : SPI Generation using 32 Bit Write */
-    /* Generate the Interrupt by writing the int_id to SETSPI_NS Register */
-    val_mmio_write(frame_base + GICv2m_MSI_SETSPI, int_id);
-
-    while ((timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))) {
-      timeout--;
-    }
-
-    if (timeout == 0) {
-      val_print(ACS_PRINT_ERR, "\n       Interrupt not received within timeout", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
-      return;
-    }
-
-    /* Part 2 : SETSPI Should Support 16 Bit Access. */
-    /* Generate the Interrupt by writing the int_id to SETSPI_NS Register */
-    val_mmio_write16(frame_base + GICv2m_MSI_SETSPI, int_id);
-
-    while ((timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))) {
-      timeout--;
-    }
-
-    if (timeout == 0) {
-      val_print(ACS_PRINT_ERR, "\n       Interrupt not received within timeout", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
-      return;
-    }
-  }
-}
-
-uint32_t
-os_v003_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This GIC test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/gic_v2m/operating_system/test_os_v004.c b/test_pool/gic_v2m/operating_system/test_os_v004.c
deleted file mode 100755
index 5590137e..00000000
--- a/test_pool/gic_v2m/operating_system/test_os_v004.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/** @file
- * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_gic.h"
-
-#define TEST_NUM   (ACS_GIC_V2M_TEST_NUM_BASE + 4)
-#define TEST_DESC  "Check GICv2m SPI allocated to MSI Control   "
-
-static uint32_t int_id;
-
-static
-void
-isr()
-{
-  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  val_print(ACS_PRINT_INFO, "\n Received SPI ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
-  val_gic_end_of_interrupt(int_id);
-
-  return;
-}
-
-static
-void
-payload()
-{
-
-  uint32_t num_spi;
-  uint32_t instance;
-  uint32_t timeout = TIMEOUT_MEDIUM;
-  uint32_t msi_frame, min_spi_id;
-  uint64_t frame_base;
-  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-  uint32_t reg_offset;
-  uint32_t reg_shift;
-
-  msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
-  if (msi_frame == 0) {
-      val_print(ACS_PRINT_DEBUG, "\n       No MSI frame, Skipping               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  for (instance = 0; instance < msi_frame; instance++) {
-    frame_base = val_gic_v2m_get_info(V2M_MSI_FRAME_BASE, instance);
-
-    min_spi_id = val_gic_v2m_get_info(V2M_MSI_SPI_BASE, instance);
-    num_spi  = val_gic_v2m_get_info(V2M_MSI_SPI_NUM, instance);
-
-    int_id = min_spi_id + num_spi - 1;
-
-    /* Register an interrupt handler to verify */
-    if (val_gic_install_isr(int_id, isr)) {
-      val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
-      return;
-    }
-
-    /* Part 1 : Generate SPI using GICD Regsiters, It should Not generate the MSI/SPI */
-
-    /* Follwing code calculates the GICD_ISPENDR offset for int_id.
-     * Every ISPENDR register add the pending state for 32 Interrupts hence reg_offset
-     * reg_shift is the bit number which need to be set for a particular interrupt */
-    reg_offset = int_id / 32;
-    reg_shift = int_id % 32;
-
-    val_mmio_write(val_get_gicd_base() + GICD_ISPENDR + (4 * reg_offset), 1 << reg_shift);
-
-    while ((timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))) {
-      timeout--;
-    }
-
-    /* If the Status is changed that means interrupt handler is called & test is failed. */
-    if (timeout != 0) {
-      val_print(ACS_PRINT_ERR, "\n       Interrupt generated by GICD registers", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
-      return;
-    }
-
-    /* Part 2 : SETSPI Should Generate the SPI. */
-    /* Generate the Interrupt by writing the int_id to SETSPI_NS Register */
-    val_mmio_write(frame_base + GICv2m_MSI_SETSPI, int_id);
-
-    while ((timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))) {
-      timeout--;
-    }
-
-    if (timeout == 0) {
-      val_print(ACS_PRINT_ERR, "\n       Interrupt not received within timeout", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
-      return;
-    }
-  }
-}
-
-uint32_t
-os_v004_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This GIC test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/memory_map/operating_system/test_os_m001.c b/test_pool/memory_map/operating_system/test_os_m001.c
index 35619588..5ab9130b 100644
--- a/test_pool/memory_map/operating_system/test_os_m001.c
+++ b/test_pool/memory_map/operating_system/test_os_m001.c
@@ -44,7 +44,7 @@ esr(uint64_t interrupt_type, void *context)
   val_pe_update_elr(context, (uint64_t)branch_to_test);
 
   val_print(ACS_PRINT_INFO, "\n       Received DAbort Exception ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 static
@@ -62,24 +62,28 @@ payload()
   val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr);
 
   /* If we don't find a single un-populated address, mark this test as skipped */
-  val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+  val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
 
   while (loop_var) {
       /* Get the base address of unpopulated region */
       status = val_memory_get_unpopulated_addr(&addr, instance);
       if (status == PCIE_NO_MAPPING) {
-          val_print(ACS_PRINT_INFO, "\n      All instances of unpopulated memory were obtained", 0);
+          val_print(ACS_PRINT_INFO,
+                    "\n       All instances of unpopulated memory were obtained",
+                    0);
           return;
       }
 
       if (status) {
-          val_print(ACS_PRINT_ERR, "\n      Error in obtaining unpopulated memory for instance 0x%d", instance);
+          val_print(ACS_PRINT_ERR,
+                    "\n       Error in obtaining unpopulated memory for instance %d",
+                    instance);
           return;
       }
 
       if (val_memory_get_info(addr, &attr) == MEM_TYPE_NOT_POPULATED) {
          /* default value of FAIL, Pass is set in the exception handler */
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
           branch_to_test = &&exception_taken;
 
@@ -87,7 +91,9 @@ payload()
 exception_taken:
           /* if the access did not go to our exception handler, fail and exit */
           if (IS_TEST_FAIL(val_get_status(index))) {
-              val_print(ACS_PRINT_ERR, "\n      Memory access check fails at address = 0x%llx ", addr);
+              val_print(ACS_PRINT_ERR,
+                        "\n       Memory access check fails at address = 0x%llx ",
+                        addr);
               return;
           }
 
diff --git a/test_pool/memory_map/operating_system/test_os_m002.c b/test_pool/memory_map/operating_system/test_os_m002.c
index a035502c..87b40423 100644
--- a/test_pool/memory_map/operating_system/test_os_m002.c
+++ b/test_pool/memory_map/operating_system/test_os_m002.c
@@ -58,7 +58,7 @@ payload()
 
   val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr);
   val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr);
-  val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+  val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
 
   branch_to_test = &&exception_taken_d;
   while (loop_var) {
@@ -66,8 +66,8 @@ payload()
       /* Get the address of device memory region */
       addr = val_memory_get_addr(MEMORY_TYPE_DEVICE, instance, &attr);
       if (!addr) {
-          val_print(ACS_PRINT_DEBUG, "\n       Error in obtaining dev mem for"
-                                   " instance %d", instance);
+          val_print(ACS_PRINT_DEBUG, "\n       Error in getting dev mem for"
+                                   " index %d  ", instance);
           goto normal_mem_test;
       }
 
@@ -78,7 +78,7 @@ payload()
           {};
 
 exception_taken_d:
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
       loop_var--;
       instance++;
   }
@@ -92,7 +92,7 @@ payload()
       /* Get the address of normal memory region */
       addr = val_memory_get_addr(MEMORY_TYPE_NORMAL, instance, &attr);
       if (!addr) {
-          val_print(ACS_PRINT_DEBUG, "\n      Error in obtaining normal memory for"
+          val_print(ACS_PRINT_DEBUG, "\n       Error in obtaining normal memory for"
                                    " instance %d", instance);
           return;
       }
@@ -104,7 +104,7 @@ payload()
           {};
 
 exception_taken_n:
-      val_set_status(index, RESULT_PASS(TEST_NUM, 02));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 2));
       loop_var--;
       instance++;
   }
diff --git a/test_pool/memory_map/operating_system/test_os_m003.c b/test_pool/memory_map/operating_system/test_os_m003.c
index 181bf75c..02115089 100644
--- a/test_pool/memory_map/operating_system/test_os_m003.c
+++ b/test_pool/memory_map/operating_system/test_os_m003.c
@@ -47,7 +47,7 @@ static uint64_t check_number_of_bits(uint32_t index, uint64_t data)
             return ((uint64_t)0x1 << (int)52);
          else
          {
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
            return 0;
          }
 }
@@ -69,11 +69,11 @@ payload()
   if (addr < value)
   {
       /* PE can access the Non-Secure address space*/
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
       return;
   }
 
-  val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+  val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
   return;
 }
 
diff --git a/test_pool/memory_map/operating_system/test_os_m004.c b/test_pool/memory_map/operating_system/test_os_m004.c
index c6646e93..e367f216 100644
--- a/test_pool/memory_map/operating_system/test_os_m004.c
+++ b/test_pool/memory_map/operating_system/test_os_m004.c
@@ -20,7 +20,7 @@
 #include "val/include/bsa_acs_pcie.h"
 
 #define TEST_NUM   (ACS_MEMORY_MAP_TEST_BASE + 4)
-#define TEST_RULE  "B_MEM_03-04, B_MEM_06"
+#define TEST_RULE  "B_MEM_03, B_MEM_04, B_MEM_06"
 #define TEST_DESC  "Addressability                        "
 
 static
@@ -38,8 +38,8 @@ payload (void)
   count = val_peripheral_get_info (NUM_ALL, 0);
 
   if (!count) {
-     val_print (ACS_PRINT_DEBUG, "\n       Skip as No peripherals detected   ", 0);
-     val_set_status (index, RESULT_SKIP (TEST_NUM, 1));
+     val_print(ACS_PRINT_DEBUG, "\n       Skip as No peripherals detected   ", 0);
+     val_set_status(index, RESULT_SKIP (TEST_NUM, 1));
      return;
   }
 
@@ -57,20 +57,20 @@ payload (void)
       data = val_pcie_is_devicedma_64bit(dev_bdf);
       if (data == 0) {
           if (!val_pcie_is_device_behind_smmu(dev_bdf)) {
-              val_print (ACS_PRINT_ERR, "\n       WARNING:The device with bdf=0x%x", dev_bdf);
-              val_print (ACS_PRINT_ERR, "\n       doesn't support 64 bit addressing and is not", 0);
-              val_print (ACS_PRINT_ERR, "\n       behind SMMU. Please install driver for this", 0);
-              val_print (ACS_PRINT_ERR, "\n       device and test again. If driver is already", 0);
-              val_print (ACS_PRINT_ERR, "\n       installed, this test has failed.", 0);
-              val_print (ACS_PRINT_ERR, "\n       The device is of type = %d", dev_type);
-              val_set_status (index, RESULT_FAIL (TEST_NUM, 1));
+              val_print(ACS_PRINT_ERR, "\n       WARNING:The device with bdf=0x%x", dev_bdf);
+              val_print(ACS_PRINT_ERR, "\n       doesn't support 64 bit addressing and is not", 0);
+              val_print(ACS_PRINT_ERR, "\n       behind SMMU. Please install driver for this", 0);
+              val_print(ACS_PRINT_ERR, "\n       device and test again. If driver is already", 0);
+              val_print(ACS_PRINT_ERR, "\n       installed, this test has failed.", 0);
+              val_print(ACS_PRINT_ERR, "\n       The device is of type = %d", dev_type);
+              val_set_status(index, RESULT_FAIL (TEST_NUM, 1));
               return;
           }
       }
 
   }
 
-  val_set_status (index, RESULT_PASS (TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS (TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p001.c b/test_pool/pcie/operating_system/test_os_p001.c
index bb49a61a..8bc3d0c9 100644
--- a/test_pool/pcie/operating_system/test_os_p001.c
+++ b/test_pool/pcie/operating_system/test_os_p001.c
@@ -36,10 +36,10 @@ payload(void)
   num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
   if (num_ecam == 0) {
       val_print(ACS_PRINT_ERR, "\n       No ECAMs discovered              ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p002.c b/test_pool/pcie/operating_system/test_os_p002.c
index 45a10921..cf9f0764 100644
--- a/test_pool/pcie/operating_system/test_os_p002.c
+++ b/test_pool/pcie/operating_system/test_os_p002.c
@@ -21,7 +21,7 @@
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 2)
 #define TEST_RULE  "PCI_IN_02"
-#define TEST_DESC  "PE - ECAM Region accessiblity check   "
+#define TEST_DESC  "PE - ECAM Region accessibility check  "
 
 #define PCIE_VENDOR_ID_REG_OFFSET 0x0
 #define PCIE_CACHE_LINE_SIZE_REG_OFFSET 0xC
@@ -48,7 +48,7 @@ payload(void)
   num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
   if (num_ecam == 0) {
       val_print(ACS_PRINT_DEBUG, "\n       No ECAM in MCFG                   ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -56,7 +56,7 @@ payload(void)
       ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, num_ecam);
       if (ecam_base == 0) {
           val_print(ACS_PRINT_DEBUG, "\n       ECAM Base in MCFG is 0            ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
           return;
       }
 
@@ -68,7 +68,7 @@ payload(void)
       ret = val_pcie_read_cfg(bdf, PCIE_VENDOR_ID_REG_OFFSET, &data);
       if (data == PCIE_UNKNOWN_RESPONSE) {
           val_print(ACS_PRINT_ERR,
-                "\n      First device in a ECAM space is not a valid device", 0);
+                "\n       First device in a ECAM space is not a valid device", 0);
            val_set_status(index, RESULT_FAIL(TEST_NUM, (bus << 8)));
            return;
       }
@@ -84,7 +84,7 @@ payload(void)
                //If this is really PCIe CFG space, Device ID and Vendor ID cannot be 0
                if (ret == PCIE_NO_MAPPING || (data == 0)) {
                   val_print(ACS_PRINT_ERR,
-                        "\n      Incorrect data at ECAM Base %4x    ", data);
+                        "\n       Incorrect data at ECAM Base %4x    ", data);
                   val_set_status(index, RESULT_FAIL(TEST_NUM, (bus_index << 8)|dev_index));
                   return;
                }
@@ -92,7 +92,7 @@ payload(void)
                ret = val_pcie_read_cfg(bdf, PCIE_CACHE_LINE_SIZE_REG_OFFSET, &data);
                if (ret == PCIE_NO_MAPPING) {
                   val_print(ACS_PRINT_ERR,
-                        "\n      Incorrect PCIe CFG Hdr type %4x    ", data);
+                        "\n       Incorrect PCIe CFG Hdr type %4x    ", data);
                   val_set_status(index, RESULT_FAIL(TEST_NUM, (bus_index << 8)|dev_index));
                   return;
                }
@@ -101,7 +101,7 @@ payload(void)
                ret = val_pcie_read_cfg(bdf, PCIE_ECAP_START + 0x100, &data);
                if (ret == PCIE_NO_MAPPING) {
                   val_print(ACS_PRINT_ERR,
-                        "\n      PCIe Extended Capability region error for BDF %x", bdf);
+                        "\n       PCIe Extended Capability region error for BDF %x", bdf);
                   val_set_status(index, RESULT_FAIL(TEST_NUM, (bus_index << 8)|dev_index));
                   return;
                }
@@ -109,7 +109,7 @@ payload(void)
                ret = val_pcie_read_cfg(bdf, PCIE_ECAP_END - 0x100, &data);
                if (ret == PCIE_NO_MAPPING) {
                   val_print(ACS_PRINT_ERR,
-                        "\n      PCIe Extended Capability region error for BDF %x", bdf);
+                        "\n       PCIe Extended Capability region error for BDF %x", bdf);
                   val_set_status(index, RESULT_FAIL(TEST_NUM, (bus_index << 8)|dev_index));
                   return;
                }
@@ -118,7 +118,7 @@ payload(void)
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p003.c b/test_pool/pcie/operating_system/test_os_p003.c
index 9da1d73a..d2a2b386 100644
--- a/test_pool/pcie/operating_system/test_os_p003.c
+++ b/test_pool/pcie/operating_system/test_os_p003.c
@@ -107,11 +107,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p004.c b/test_pool/pcie/operating_system/test_os_p004.c
index 3bcaa43a..fa98e153 100644
--- a/test_pool/pcie/operating_system/test_os_p004.c
+++ b/test_pool/pcie/operating_system/test_os_p004.c
@@ -40,7 +40,7 @@ esr(uint64_t interrupt_type, void *context)
   val_pe_update_elr(context, (uint64_t)branch_to_test);
 
   val_print(ACS_PRINT_INFO, "\n       Received exception of type: %d", interrupt_type);
-  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01));
+  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1));
 }
 
 static
@@ -129,7 +129,7 @@ payload(void)
 
         if (val_pcie_is_urd(bdf) ||
           (old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE)) {
-            val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+            val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
             val_pcie_clear_urd(bdf);
             return;
         }
@@ -137,9 +137,9 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p005.c b/test_pool/pcie/operating_system/test_os_p005.c
index ba299d4f..c5d31588 100644
--- a/test_pool/pcie/operating_system/test_os_p005.c
+++ b/test_pool/pcie/operating_system/test_os_p005.c
@@ -61,7 +61,7 @@ payload(void)
       {
          /* Check if Address Translation Cache is Present in this device. */
          /* If ATC Not present, skip the test.*/
-         if (!val_pcie_is_cache_present(bdf))
+         if (val_pcie_is_cache_present(bdf))
              continue;
 
          test_skip = 0;
@@ -69,18 +69,19 @@ payload(void)
          /* If ATC Present, Check ATS Capability should be present. */
          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS)
          {
-             val_print(ACS_PRINT_ERR, "\n       ATS Capability Not Present, Bdf : 0x%x", bdf);
+             val_print(ACS_PRINT_ERR, "\n       BDF 0x%x :ATS Cap Not Present",
+                                                                bdf);
              test_fails++;
          }
       }
   }
 
   if (test_skip)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p006.c b/test_pool/pcie/operating_system/test_os_p006.c
index 79cb736a..4568a35d 100644
--- a/test_pool/pcie/operating_system/test_os_p006.c
+++ b/test_pool/pcie/operating_system/test_os_p006.c
@@ -46,8 +46,8 @@ payload(void)
   /* Allocate memory for interrupt mappings */
   intr_map = val_memory_alloc(sizeof(PERIPHERAL_IRQ_MAP));
   if (!intr_map) {
-    val_print (ACS_PRINT_ERR, "\n       Memory allocation error", 0);
-    val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 01));
+    val_print(ACS_PRINT_ERR, "\n       Memory allocation error", 0);
+    val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 1));
     return;
   }
 
@@ -68,7 +68,7 @@ payload(void)
       status = val_pci_get_legacy_irq_map(bdf, intr_map);
       if (status) {
         // Skip the test if the Legacy IRQ map does not exist
-        val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
+        val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2));
         return;
       }
 
@@ -85,7 +85,7 @@ payload(void)
       }
       else {
           val_print(ACS_PRINT_ERR, "\n Int id %d is not SPI", intr_line);
-          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03));
+          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3));
           return;
       }
 
@@ -96,20 +96,20 @@ payload(void)
           status = val_gic_get_espi_intr_trigger_type(intr_line, &trigger_type);
 
       if (status) {
-        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04));
+        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4));
         return;
       }
 
       if (trigger_type != INTR_TRIGGER_INFO_LEVEL_HIGH) {
-        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 05));
+        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 5));
         return;
       }
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p007.c b/test_pool/pcie/operating_system/test_os_p007.c
deleted file mode 100644
index 440ff651..00000000
--- a/test_pool/pcie/operating_system/test_os_p007.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/** @file
- * Copyright (c) 2016-2018,2021 Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 7)
-#define TEST_DESC  "PCI_MSI_01: Check MSI support for PCIe dev         "
-
-static
-void
-payload(void)
-{
-
-  uint32_t count = val_peripheral_get_info(NUM_ALL, 0);
-  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-  uint32_t data;
-  uint32_t dev_type;
-  uint64_t dev_bdf;
-  uint32_t status = 0;
-
-  if (!count) {
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  while (count > 0) {
-      count--;
-      dev_bdf = val_peripheral_get_info(ANY_BDF, count);
-      /* Check for pcie device */
-      if (!val_peripheral_is_pcie(dev_bdf))
-          continue;
-
-      dev_type = val_pcie_get_device_type(dev_bdf);
-      /* Skipping MSI check for type-1 and type-2 headers */
-      if ((!dev_type) || (dev_type > 1))
-          continue;
-
-      data = val_peripheral_get_info(ANY_FLAGS, count);
-
-      if ((data & PER_FLAG_MSI_ENABLED) == 0) {
-          val_print(ACS_PRINT_ERR, "\n       MSI should be enabled for a PCIe device ", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
-          status = 1;
-          break;
-      }
-  }
-  if (!status)
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p007_entry(uint32_t num_pe)
-{
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p008.c b/test_pool/pcie/operating_system/test_os_p008.c
index 45f63c77..3c0fb376 100644
--- a/test_pool/pcie/operating_system/test_os_p008.c
+++ b/test_pool/pcie/operating_system/test_os_p008.c
@@ -76,7 +76,7 @@ payload(void)
       /* Get the maximum bus value from PCIe info table */
       end_bus = val_pcie_get_info(PCIE_INFO_END_BUS, ecam_index);
       segment = val_pcie_get_info(PCIE_INFO_SEGMENT, ecam_index);
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
 
       /* Get the highest BDF value for that segment */
       bdf = get_max_bdf(segment, end_bus);
@@ -88,8 +88,9 @@ payload(void)
 
       /* Bus value should not exceed 255 */
       if (bus_index > end_bus) {
-          val_print(ACS_PRINT_ERR, "\n Bus index exceeded END_BUS Number", 0);
-          val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
+          val_print(ACS_PRINT_ERR, "\n       Bus index exceeded END_BUS Number",
+                                                                            0);
+          val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2));
           return;
       }
 
@@ -108,7 +109,7 @@ payload(void)
 
               if (ecam_base == 0) {
                   val_print(ACS_PRINT_ERR, "\n       ECAM Base is zero ", 0);
-                  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01));
+                  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1));
                   return;
               }
 
@@ -122,11 +123,11 @@ payload(void)
               if (reg_value != PCIE_UNKNOWN_RESPONSE)
               {
                   val_print(ACS_PRINT_ERR, "\n       Failed for BDF: 0x%x", bdf);
-                  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+                  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
                   return;
               }
 
-              val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+              val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
           }
       }
   }
diff --git a/test_pool/pcie/operating_system/test_os_p009.c b/test_pool/pcie/operating_system/test_os_p009.c
index c829ea0f..6aad5bfd 100644
--- a/test_pool/pcie/operating_system/test_os_p009.c
+++ b/test_pool/pcie/operating_system/test_os_p009.c
@@ -105,13 +105,13 @@ payload(void)
             if (check_pcie_cfg_space(bdf)) {
                 val_print(ACS_PRINT_ERR,
                     "\n       Invalid PCIe capability found on dev: %d", tbl_index);
-                val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+                val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
                 return;
             }
         }
     }
 
-    val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+    val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
     return;
 
 }
diff --git a/test_pool/pcie/operating_system/test_os_p010.c b/test_pool/pcie/operating_system/test_os_p010.c
index 090b9974..8e5ace7f 100644
--- a/test_pool/pcie/operating_system/test_os_p010.c
+++ b/test_pool/pcie/operating_system/test_os_p010.c
@@ -64,9 +64,9 @@ payload(void)
 
            while (offset <= TYPE1_BAR_MAX_OFFSET) {
               val_pcie_read_cfg(bdf, offset, &bar_value);
-              val_print(ACS_PRINT_DEBUG, "\n       The BAR value of bdf %x",
-                                                                         bdf);
-              val_print(ACS_PRINT_DEBUG, " is %x ", bar_value);
+              val_print(ACS_PRINT_DEBUG, "\n       BDF %.6x ", bdf);
+              val_print(ACS_PRINT_DEBUG, "BAR offset0x%x value", offset);
+              val_print(ACS_PRINT_DEBUG, " is 0x%x     ", bar_value);
               bar_orig = 0;
               bar_new = 0;
 
@@ -137,11 +137,11 @@ payload(void)
 
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
       }
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p011.c b/test_pool/pcie/operating_system/test_os_p011.c
index 829fea92..1a0acd83 100644
--- a/test_pool/pcie/operating_system/test_os_p011.c
+++ b/test_pool/pcie/operating_system/test_os_p011.c
@@ -81,7 +81,7 @@ payload(void)
         if ((ecam_cr != ecam_cr_8) || (ecam_cr_8 != ecam_cr_16))
         {
           val_print(ACS_PRINT_ERR, "\n        Byte Enable Read Failed", 0);
-          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1));
           return;
         }
 
@@ -96,7 +96,7 @@ payload(void)
         if (write_value != ecam_cr_new)
         {
           val_print(ACS_PRINT_ERR, "\n        8 Bit Write Failed", 0);
-          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
           return;
         }
 
@@ -114,7 +114,7 @@ payload(void)
         if (write_value != ecam_cr_new)
         {
           val_print(ACS_PRINT_ERR, "\n        16 Bit Write Failed", 0);
-          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03));
+          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 3));
           return;
         }
 
@@ -132,7 +132,7 @@ payload(void)
         if (write_value != ecam_cr_new)
         {
           val_print(ACS_PRINT_ERR, "\n        32 Bit Write Failed", 0);
-          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04));
+          val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 4));
           return;
         }
 
@@ -143,9 +143,9 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p012.c b/test_pool/pcie/operating_system/test_os_p012.c
index 247313b6..786769b5 100644
--- a/test_pool/pcie/operating_system/test_os_p012.c
+++ b/test_pool/pcie/operating_system/test_os_p012.c
@@ -64,11 +64,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p013.c b/test_pool/pcie/operating_system/test_os_p013.c
index 9d04fcd3..bda44dd3 100644
--- a/test_pool/pcie/operating_system/test_os_p013.c
+++ b/test_pool/pcie/operating_system/test_os_p013.c
@@ -77,11 +77,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p014.c b/test_pool/pcie/operating_system/test_os_p014.c
index fafa65b1..04409e0a 100644
--- a/test_pool/pcie/operating_system/test_os_p014.c
+++ b/test_pool/pcie/operating_system/test_os_p014.c
@@ -65,7 +65,7 @@ payload(void)
 
           link_cap_sup = val_pcie_link_cap_support(bdf);
           if (link_cap_sup != 0) {
-              val_print(ACS_PRINT_ERR, "\n         Invalid Link Capabilities 0x%x", link_cap_sup);
+              val_print(ACS_PRINT_ERR, "\n       Invalid Link Capabilities 0x%x", link_cap_sup);
               val_print(ACS_PRINT_ERR, " Bdf : 0x%x", bdf);
               fail_cnt++;
           }
@@ -74,11 +74,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p015.c b/test_pool/pcie/operating_system/test_os_p015.c
index bd28c3d0..af7517b9 100644
--- a/test_pool/pcie/operating_system/test_os_p015.c
+++ b/test_pool/pcie/operating_system/test_os_p015.c
@@ -119,11 +119,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p016.c b/test_pool/pcie/operating_system/test_os_p016.c
index cf12f360..cbd21f55 100644
--- a/test_pool/pcie/operating_system/test_os_p016.c
+++ b/test_pool/pcie/operating_system/test_os_p016.c
@@ -69,11 +69,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p017.c b/test_pool/pcie/operating_system/test_os_p017.c
index cfeb6e4d..3dade587 100644
--- a/test_pool/pcie/operating_system/test_os_p017.c
+++ b/test_pool/pcie/operating_system/test_os_p017.c
@@ -89,11 +89,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p018.c b/test_pool/pcie/operating_system/test_os_p018.c
index 06aed24e..dc465053 100644
--- a/test_pool/pcie/operating_system/test_os_p018.c
+++ b/test_pool/pcie/operating_system/test_os_p018.c
@@ -45,7 +45,7 @@ payload(void)
   /* Check If PCIe Hierarchy supports P2P */
   if (val_pcie_p2p_support())
   {
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -66,25 +66,27 @@ payload(void)
 
           /* It ACS Not Supported, Fail. */
           if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) {
-              val_print(ACS_PRINT_ERR, "\n       ACS Capability not supported, Bdf : 0x%x", bdf);
+              val_print(ACS_PRINT_ERR, "\n       BDF 0x%x: ACS Cap unsupported",
+                                                                bdf);
               test_fails++;
               continue;
           }
 
           /* If AER Not Supported, Fail. */
           if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS) {
-              val_print(ACS_PRINT_DEBUG, "\n       AER Capability not supported, Bdf : 0x%x", bdf);
+              val_print(ACS_PRINT_DEBUG, "\n       BDF 0x%x: AER Cap "
+                                                        "unsupported", bdf);
               test_fails++;
           }
       }
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p019.c b/test_pool/pcie/operating_system/test_os_p019.c
index 9ecfde3d..001e12f9 100644
--- a/test_pool/pcie/operating_system/test_os_p019.c
+++ b/test_pool/pcie/operating_system/test_os_p019.c
@@ -47,7 +47,7 @@ payload(void)
   /* Check If PCIe Hierarchy supports P2P */
   if (val_pcie_p2p_support())
   {
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -122,11 +122,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 2));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p020.c b/test_pool/pcie/operating_system/test_os_p020.c
index 8e29cf06..0e17d242 100644
--- a/test_pool/pcie/operating_system/test_os_p020.c
+++ b/test_pool/pcie/operating_system/test_os_p020.c
@@ -38,11 +38,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table20, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p021.c b/test_pool/pcie/operating_system/test_os_p021.c
index 784f6062..68f9e8fc 100644
--- a/test_pool/pcie/operating_system/test_os_p021.c
+++ b/test_pool/pcie/operating_system/test_os_p021.c
@@ -38,11 +38,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table21, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p022.c b/test_pool/pcie/operating_system/test_os_p022.c
index c8d3cdc9..e7e15146 100644
--- a/test_pool/pcie/operating_system/test_os_p022.c
+++ b/test_pool/pcie/operating_system/test_os_p022.c
@@ -38,11 +38,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table22, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p023.c b/test_pool/pcie/operating_system/test_os_p023.c
index 77282589..ed6f6aa3 100644
--- a/test_pool/pcie/operating_system/test_os_p023.c
+++ b/test_pool/pcie/operating_system/test_os_p023.c
@@ -39,11 +39,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table23, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p024.c b/test_pool/pcie/operating_system/test_os_p024.c
index fb3f633a..9a2e4c6e 100644
--- a/test_pool/pcie/operating_system/test_os_p024.c
+++ b/test_pool/pcie/operating_system/test_os_p024.c
@@ -39,11 +39,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table24, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p025.c b/test_pool/pcie/operating_system/test_os_p025.c
index d5c66e25..3f081194 100644
--- a/test_pool/pcie/operating_system/test_os_p025.c
+++ b/test_pool/pcie/operating_system/test_os_p025.c
@@ -39,11 +39,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table25, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p026.c b/test_pool/pcie/operating_system/test_os_p026.c
index 037b7b89..ed929960 100644
--- a/test_pool/pcie/operating_system/test_os_p026.c
+++ b/test_pool/pcie/operating_system/test_os_p026.c
@@ -39,11 +39,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table26, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p027.c b/test_pool/pcie/operating_system/test_os_p027.c
index b32fb635..2b78101c 100644
--- a/test_pool/pcie/operating_system/test_os_p027.c
+++ b/test_pool/pcie/operating_system/test_os_p027.c
@@ -39,11 +39,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table27, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p028.c b/test_pool/pcie/operating_system/test_os_p028.c
index f35c85e8..b9957fc8 100644
--- a/test_pool/pcie/operating_system/test_os_p028.c
+++ b/test_pool/pcie/operating_system/test_os_p028.c
@@ -39,11 +39,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table28, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p029.c b/test_pool/pcie/operating_system/test_os_p029.c
index c5019086..3f75f6f8 100644
--- a/test_pool/pcie/operating_system/test_os_p029.c
+++ b/test_pool/pcie/operating_system/test_os_p029.c
@@ -39,11 +39,11 @@ payload(void)
   ret = val_pcie_register_bitfields_check((void *)&bf_info_table29, table_entries);
 
   if (ret == ACS_STATUS_SKIP)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (ret)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, ret));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p030.c b/test_pool/pcie/operating_system/test_os_p030.c
index c35cdfa0..98f45e22 100644
--- a/test_pool/pcie/operating_system/test_os_p030.c
+++ b/test_pool/pcie/operating_system/test_os_p030.c
@@ -39,7 +39,7 @@ esr(uint64_t interrupt_type, void *context)
   val_pe_update_elr(context, (uint64_t)branch_to_test);
 
   val_print(ACS_PRINT_INFO, "\n       Received exception of type: %d", interrupt_type);
-  val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 static
@@ -108,7 +108,7 @@ payload(void)
       val_pcie_disable_msa(bdf);
 
       /* Set test status as FAIL, update to PASS in exception handler */
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
 
       /* If test runs for atleast an endpoint */
       test_skip = 0;
@@ -133,7 +133,7 @@ payload(void)
           val_pcie_clear_urd(bdf);
        } else
        {
-           val_print(ACS_PRINT_ERR, "\n      BDF %x MSE functionality failure", bdf);
+           val_print(ACS_PRINT_ERR, "\n       BDF %x MSE functionality failure", bdf);
            test_fails++;
        }
 
@@ -145,11 +145,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p031.c b/test_pool/pcie/operating_system/test_os_p031.c
index f13067a1..eccddb84 100644
--- a/test_pool/pcie/operating_system/test_os_p031.c
+++ b/test_pool/pcie/operating_system/test_os_p031.c
@@ -71,11 +71,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p032.c b/test_pool/pcie/operating_system/test_os_p032.c
index 5a98f04c..013541ab 100644
--- a/test_pool/pcie/operating_system/test_os_p032.c
+++ b/test_pool/pcie/operating_system/test_os_p032.c
@@ -68,11 +68,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p033.c b/test_pool/pcie/operating_system/test_os_p033.c
index 5b6a0e8d..31fe1082 100644
--- a/test_pool/pcie/operating_system/test_os_p033.c
+++ b/test_pool/pcie/operating_system/test_os_p033.c
@@ -72,11 +72,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p034.c b/test_pool/pcie/operating_system/test_os_p034.c
index dbba3d01..80509add 100644
--- a/test_pool/pcie/operating_system/test_os_p034.c
+++ b/test_pool/pcie/operating_system/test_os_p034.c
@@ -98,7 +98,7 @@ payload(void)
               /* Check BAR should be MMIO */
               if (reg_value & BAR_MIT_MASK)
               {
-                 val_print(ACS_PRINT_ERR, "\n        BDF 0x%x Not MMIO", 0);
+                 val_print(ACS_PRINT_ERR, "\n       BDF 0x%x Not MMIO", 0);
                  test_fails++;
               }
            }
@@ -106,11 +106,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p035.c b/test_pool/pcie/operating_system/test_os_p035.c
index 49592734..e5586bd0 100644
--- a/test_pool/pcie/operating_system/test_os_p035.c
+++ b/test_pool/pcie/operating_system/test_os_p035.c
@@ -162,11 +162,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p036.c b/test_pool/pcie/operating_system/test_os_p036.c
index 5abf2be5..46fe63fa 100644
--- a/test_pool/pcie/operating_system/test_os_p036.c
+++ b/test_pool/pcie/operating_system/test_os_p036.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2020,2021 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -35,7 +35,6 @@ payload(void)
   uint32_t tbl_index;
   uint32_t dp_type;
   uint32_t cap_base;
-  uint32_t ari_frwd_enable;
   uint32_t seg_num;
   uint32_t dev_num;
   uint32_t dev_bdf;
@@ -44,6 +43,8 @@ payload(void)
   uint32_t test_fails;
   uint32_t test_skip = 1;
   uint32_t reg_value;
+  uint32_t status;
+
   pcie_device_bdf_table *bdf_tbl_ptr;
 
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
@@ -60,33 +61,39 @@ payload(void)
       /* Check entry is Downstream port or RP */
       if ((dp_type == DP) || (dp_type == iEP_RP) || (dp_type == RP))
       {
-          /* Read the ARI forwarding enable bit */
+          /* Disable the ARI forwarding enable bit */
           val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base);
           val_pcie_read_cfg(bdf, cap_base + DCTL2R_OFFSET, &reg_value);
-          ari_frwd_enable = (reg_value >> DCTL2R_AFE_SHIFT) & DCTL2R_AFE_MASK;
-
-          /* If ARI forwarding enable set, skip the entry */
-          if (ari_frwd_enable != 0)
-              continue;
+          reg_value &= DCTL2R_AFE_NORMAL;
+          val_pcie_write_cfg(bdf, cap_base + DCTL2R_OFFSET, reg_value);
 
+          /* Read the secondary and subordinate bus number */
           val_pcie_read_cfg(bdf, TYPE1_PBN, &reg_value);
           sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK);
           sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK);
 
-          /* Skip the port, if switch is present below it */
-          if (sec_bus != sub_bus)
+          /* Skip the port, if switch is present below it or no device present*/
+          if ((sec_bus != sub_bus) || (sec_bus == 0))
               continue;
 
           /* If test runs for atleast an endpoint */
           test_skip = 0;
 
+          seg_num = PCIE_EXTRACT_BDF_SEG(bdf);
+          dev_bdf = PCIE_CREATE_BDF(seg_num, sec_bus, 0, 0);
+          status = val_pcie_read_cfg(dev_bdf, TYPE01_VIDR, &reg_value);
+          if (status || (reg_value == PCIE_UNKNOWN_RESPONSE))
+          {
+              test_fails++;
+              val_print(ACS_PRINT_ERR, "\n    Dev 0x%x found under", dev_bdf);
+              val_print(ACS_PRINT_ERR, " RP bdf 0x%x", bdf);
+          }
+
           /* Configuration Requests specifying Device Numbers (1-31) must be terminated by the
            * Downstream Port or the Root Port with an Unsupported Request Completion Status
            */
-
           for (dev_num = 1; dev_num < PCIE_MAX_DEV; dev_num++)
           {
-              seg_num = PCIE_EXTRACT_BDF_SEG(bdf);
 
               /* Create bdf for Dev 1 to 31 below the RP */
               dev_bdf = PCIE_CREATE_BDF(seg_num, sec_bus, dev_num, 0);
@@ -102,11 +109,11 @@ payload(void)
   }
 
   if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 1));
   else if (test_fails)
       val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
   else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p037.c b/test_pool/pcie/operating_system/test_os_p037.c
deleted file mode 100644
index 6cbefae0..00000000
--- a/test_pool/pcie/operating_system/test_os_p037.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/** @file
- * Copyright (c) 2019-2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 37)
-#define TEST_DESC  "IE_REG_2: Check OBFF supported rule                "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t rp_bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t reg_value;
-  uint32_t dp_type;
-  uint32_t cap_base;
-  uint32_t ep_obff_support;
-  uint32_t rp_obff_support;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is iEP endpoint */
-      if (dp_type == iEP_EP)
-      {
-          /* Read endpoint OBFF supported bit value */
-          val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base);
-          val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, &reg_value);
-          ep_obff_support = (reg_value >> DCAP2R_OBFF_SHIFT) & DCAP2R_OBFF_MASK;
-
-          /* Get the rootport of ARI device */
-          rp_bdf = bdf_tbl_ptr->device[tbl_index].rp_bdf;
-
-          /* Read rootport OBFF supported bit value */
-          val_pcie_find_capability(rp_bdf, PCIE_CAP, CID_PCIECS, &cap_base);
-          val_pcie_read_cfg(rp_bdf, cap_base + DCAP2R_OFFSET, &reg_value);
-          rp_obff_support = (reg_value >> DCAP2R_OBFF_SHIFT) & DCAP2R_OBFF_MASK;
-
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* As per SBSA spec iRP must have same value as of iEP */
-          if (ep_obff_support != rp_obff_support)
-           {
-              val_print(ACS_PRINT_DEBUG, "\n    iEP 0x%x", bdf);
-              val_print(ACS_PRINT_DEBUG, " OBFF support %d", ep_obff_support);
-              val_print(ACS_PRINT_DEBUG, "\n    iRP 0x%x", rp_bdf);
-              val_print(ACS_PRINT_DEBUG, " OBFF support %d", rp_obff_support);
-              test_fails++;
-          }
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p037_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p038.c b/test_pool/pcie/operating_system/test_os_p038.c
deleted file mode 100644
index 4a823457..00000000
--- a/test_pool/pcie/operating_system/test_os_p038.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/** @file
- * Copyright (c) 2019-2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 38)
-#define TEST_DESC  "IE_REG_2: Check CTRS and CTDS rule                 "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t reg_value;
-  uint32_t dp_type;
-  uint32_t iep_rp_found;
-  uint32_t cap_base;
-  uint32_t ctrs_value;
-  uint32_t ctds_value;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  tbl_index = 0;
-  test_fails = 0;
-  iep_rp_found = 0;
-
-  /* Check for all the function present in bdf table */
-  while (tbl_index < bdf_tbl_ptr->num_entries)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is iRP endpoint */
-      if (dp_type == iEP_RP)
-      {
-          iep_rp_found = 1;
-
-          /* If rootport invovled in transaction forwarding, move to next */
-          if (val_pcie_get_rp_transaction_frwd_support(bdf))
-             continue;
-
-          /* Read rootport Completion Timeout Ranges supported bit value */
-          val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base);
-          val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, &reg_value);
-          ctrs_value = (reg_value >> DCAP2R_CTRS_SHIFT) & DCAP2R_CTRS_MASK;
-
-          /* Read rootport Completion Timeout Disable supported bit value */
-          ctds_value = (reg_value >> DCAP2R_CTDS_SHIFT) & DCAP2R_CTDS_MASK;
-
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* CTRS and CTDS bit is handwired to 0, if transaction forwarding not support */
-          if ((ctrs_value != 0) || (ctds_value != 0))
-          {
-              val_print(ACS_PRINT_DEBUG, "\n    BDF 0x%x", bdf);
-              val_print(ACS_PRINT_DEBUG, " ctrs %d", ctrs_value);
-              val_print(ACS_PRINT_DEBUG, " ctds %d", ctds_value);
-              test_fails++;
-          }
-     }
-  }
-
-  /* Skip the test if no iEP_RP found */
-  if (iep_rp_found == 0) {
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p038_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p039.c b/test_pool/pcie/operating_system/test_os_p039.c
deleted file mode 100644
index 68ce2b50..00000000
--- a/test_pool/pcie/operating_system/test_os_p039.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/** @file
- * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 39)
-#define TEST_DESC  "IE_REG_2: Check i-EP atomicop rule                 "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t rp_bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t reg_value;
-  uint32_t dp_type;
-  uint32_t cap_base;
-  uint32_t atomicop_32_cap;
-  uint32_t atomicop_64_cap;
-  uint32_t atomicop_128_cap;
-  uint32_t rp_routing_cap;
-  uint32_t rp_requester_cap;
-  uint32_t ep_requester_cap;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  tbl_index = 0;
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is i-EP */
-      if (dp_type == iEP_EP)
-      {
-          /* Read iEP atomicop completer bits */
-          val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &cap_base);
-          val_pcie_read_cfg(bdf, cap_base + DCAP2R_OFFSET, &reg_value);
-          atomicop_32_cap = (reg_value >> DCAP2R_A32C_SHIFT) & DCAP2R_A32C_MASK;
-          atomicop_64_cap = (reg_value >> DCAP2R_A64C_SHIFT) & DCAP2R_A64C_MASK;
-          atomicop_128_cap = (reg_value >> DCAP2R_A128C_SHIFT) & DCAP2R_A128C_MASK;
-
-          /* Read RP atomicop routing capability */
-          rp_bdf = bdf_tbl_ptr->device[tbl_index].rp_bdf;
-          val_pcie_find_capability(rp_bdf, PCIE_CAP, CID_PCIECS, &cap_base);
-          val_pcie_read_cfg(rp_bdf, cap_base + DCAP2R_OFFSET, &reg_value);
-          rp_routing_cap = (reg_value >> DCAP2R_ARS_SHIFT) & DCAP2R_ARS_MASK;
-
-          rp_requester_cap = val_pcie_get_atomicop_requester_capable(rp_bdf);
-
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* if iEP is atomicop completer capable, RP should be routing or requester capable */
-          if ((atomicop_32_cap || atomicop_64_cap || atomicop_128_cap) &&
-             ((rp_routing_cap == 0) && (rp_requester_cap == 0)))
-          {
-              val_print(ACS_PRINT_DEBUG, " BDF 0x%x atomicop completer fail", bdf);
-              test_fails++;
-          }
-
-          ep_requester_cap = val_pcie_get_atomicop_requester_capable(bdf);
-
-          /* if iEP is atomicop requester capable, RP should be routing or completer capable */
-          if ((ep_requester_cap) &&
-             ((rp_routing_cap == 0) && (rp_requester_cap == 0)))
-          {
-              val_print(ACS_PRINT_DEBUG, " BDF 0x%x atomicop requester fail", bdf);
-              test_fails++;
-          }
-     }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p039_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p041.c b/test_pool/pcie/operating_system/test_os_p041.c
deleted file mode 100644
index c18ba298..00000000
--- a/test_pool/pcie/operating_system/test_os_p041.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/** @file
- * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 41)
-#define TEST_DESC  "RE_INT_1,IE_INT_1:Check MSI and MSI-X support rule "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t cap_base;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Skip this Check for Host Bridge */
-      if (val_pcie_is_host_bridge(bdf))
-        continue;
-
-      /* Check entry is endpoint or rciep */
-      if ((dp_type == iEP_EP) || (dp_type == RCiEP))
-      {
-         /* If test runs for atleast an endpoint */
-         test_skip = 0;
-
-         /* If MSI or MSI-X not supported, test fails */
-         if ((val_pcie_find_capability(bdf, PCIE_CAP, CID_MSI, &cap_base) == PCIE_CAP_NOT_FOUND) &&
-             (val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &cap_base) == PCIE_CAP_NOT_FOUND))
-              test_fails++;
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p041_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p042.c b/test_pool/pcie/operating_system/test_os_p042.c
deleted file mode 100644
index b2081bbd..00000000
--- a/test_pool/pcie/operating_system/test_os_p042.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/** @file
- * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 42)
-#define TEST_DESC  "RE_PWR_1,IE_PWR_1:Check Power Management rules     "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t cap_base;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is onchip peripherals */
-      if ((dp_type == iEP_EP) || (dp_type == RCiEP) || (dp_type == iEP_RP))
-      {
-         /* If test runs for atleast an endpoint */
-         test_skip = 0;
-
-         /* If Power Management capability not supported, test fails */
-         if (val_pcie_find_capability(bdf, PCIE_CAP, CID_PMC, &cap_base) == PCIE_CAP_NOT_FOUND)
-              test_fails++;
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p042_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p044.c b/test_pool/pcie/operating_system/test_os_p044.c
deleted file mode 100644
index 450a24c7..00000000
--- a/test_pool/pcie/operating_system/test_os_p044.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/** @file
- * Copyright (c) 2016-2018, 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 44)
-#define TEST_DESC  "PCI_IN_04: All EP/Sw under RP in same ECAM Region  "
-
-uint8_t func_ecam_is_rp_ecam(uint32_t dsf_bdf)
-{
-
-  uint8_t dsf_bus;
-  uint32_t bdf;
-  uint32_t dp_type;
-  uint32_t tbl_index;
-  uint32_t reg_value;
-  addr_t ecam_base;
-  addr_t dev_ecam_base;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  tbl_index = 0;
-  dsf_bus = PCIE_EXTRACT_BDF_BUS(dsf_bdf);
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  while (tbl_index < bdf_tbl_ptr->num_entries) {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check if this table entry is a Root Port */
-      if (dp_type == RP || dp_type == iEP_RP) {
-          if (PCIE_EXTRACT_BDF_SEG(bdf) != PCIE_EXTRACT_BDF_SEG(dsf_bdf))
-              continue;
-
-          /* Check if the entry's bus range covers down stream function */
-          val_pcie_read_cfg(bdf, TYPE1_PBN, &reg_value);
-          if ((dsf_bus >= ((reg_value >> SECBN_SHIFT) & SECBN_MASK)) &&
-              (dsf_bus <= ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK))) {
-              ecam_base = val_pcie_get_ecam_base(bdf);
-              dev_ecam_base = val_pcie_get_ecam_base(dsf_bdf);
-
-              /* Return success if both RP and EP / SW share the same ECAM region */
-              if (ecam_base == dev_ecam_base)
-                  return 0;
-              else
-                  return 1;
-          }
-      }
-  }
-
-  return 1;
-}
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t dp_type;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t fail_cnt;
-  uint32_t test_skip = 1;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  fail_cnt = 0;
-  tbl_index = 0;
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  while (tbl_index < bdf_tbl_ptr->num_entries) {
-      /*
-       * If a function is in the hierarchy domain
-       * originated by a Root Port, check its ECAM
-       * is same as its RootPort ECAM.
-       */
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-      if (dp_type == EP || dp_type == iEP_EP ||
-               dp_type == UP || dp_type == DP) {
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          if (func_ecam_is_rp_ecam(bdf)) {
-              val_print(ACS_PRINT_ERR, "\n        bdf: 0x%x ", bdf);
-              val_print(ACS_PRINT_ERR, "dp_type: 0x%x ", dp_type);
-              fail_cnt++;
-          }
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (fail_cnt)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p044_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p048.c b/test_pool/pcie/operating_system/test_os_p048.c
deleted file mode 100644
index 4bc2e9ac..00000000
--- a/test_pool/pcie/operating_system/test_os_p048.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/** @file
- * Copyright (c) 2016-2018, 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_pcie.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 48)
-#define TEST_DESC  "PCI_IN_13: PHB, RP must recognize Txn from upstream"
-
-#define KNOWN_DATA  0xABABABAB
-
-static void *branch_to_test;
-
-static
-void
-esr(uint64_t interrupt_type, void *context)
-{
-  uint32_t pe_index;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  /* Update the ELR to return to test specified address */
-  val_pe_update_elr(context, (uint64_t)branch_to_test);
-
-  val_print(ACS_PRINT_INFO, "\n       Received exception of type: %d", interrupt_type);
-  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01));
-}
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t dp_type;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t read_value, old_value;
-  uint32_t test_skip = 1;
-  uint64_t mem_base;
-  uint64_t mem_lim;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  tbl_index = 0;
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  /* Install sync and async handlers to handle exceptions.*/
-  val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr);
-  val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr);
-  branch_to_test = &&exception_return;
-
-  /* Since this is a memory space access test.
-   * Enable BME & MSE for all the BDFs.
-  */
-  while (tbl_index < bdf_tbl_ptr->num_entries)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      /* Enable Bus Master Enable */
-      val_pcie_enable_bme(bdf);
-      /* Enable Memory Space Access */
-      val_pcie_enable_msa(bdf);
-  }
-
-  tbl_index = 0;
-  while (tbl_index < bdf_tbl_ptr->num_entries)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      if ((dp_type == RP) || (dp_type == iEP_RP)) {
-        /* Part 1:
-         * Check When Address is within the Range of Non-Prefetchable
-         * Memory Range.
-        */
-        /* Clearing UR in Device Status Register */
-        val_pcie_clear_urd(bdf);
-
-        /* Read Function's NP Memory Base Limit Register */
-        val_pcie_read_cfg(bdf, TYPE1_NP_MEM, &read_value);
-        if (read_value == 0)
-          continue;
-
-        mem_base = (read_value & MEM_BA_MASK) << MEM_BA_SHIFT;
-        mem_lim = (read_value & MEM_LIM_MASK) | MEM_LIM_LOWER_BITS;
-
-        /* If Memory Limit is programmed with value less the Base, then Skip.*/
-        if (mem_lim < mem_base)
-          continue;
-
-        /* If test runs for atleast an endpoint */
-        test_skip = 0;
-
-        /* Write known value to an address which is in range
-         * Base + 0x10 will always be in the range.
-         * Read the same
-        */
-        old_value = (*(volatile uint32_t *)(mem_base + MEM_OFFSET_10));
-        *(volatile uint32_t *)(mem_base + MEM_OFFSET_10) = KNOWN_DATA;
-        read_value = (*(volatile uint32_t *)(mem_base + MEM_OFFSET_10));
-
-exception_return:
-        /* Memory Space might have constraint on RW/RO behaviour
-         * So not checking for Read-Write Data mismatch.
-        */
-        if (IS_TEST_FAIL(val_get_status(pe_index))) {
-          val_print(ACS_PRINT_ERR,
-            "\n       Failed. Exception on Memory Access For Bdf : 0x%x", bdf);
-          val_pcie_clear_urd(bdf);
-          return;
-        }
-
-        if (val_pcie_is_urd(bdf) ||
-          (old_value != read_value && read_value == PCIE_UNKNOWN_RESPONSE)) {
-            val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
-            val_pcie_clear_urd(bdf);
-            return;
-        }
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p048_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p050.c b/test_pool/pcie/operating_system/test_os_p050.c
deleted file mode 100644
index dd023262..00000000
--- a/test_pool/pcie/operating_system/test_os_p050.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/** @file
- * Copyright (c) 2016-2018, 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 50)
-#define TEST_DESC  "PCI_LI_03: Legacy SPI are programme as lvl-sensitiv"
-
-static
-void
-payload(void)
-{
-  uint32_t status;
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t reg_value;
-  uint32_t test_skip = 1;
-  uint32_t intr_pin, intr_line;
-  PERIPHERAL_IRQ_MAP *intr_map;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-  INTR_TRIGGER_INFO_TYPE_e trigger_type;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  /* Allocate memory for interrupt mappings */
-  intr_map = val_memory_alloc(sizeof(PERIPHERAL_IRQ_MAP));
-  if (!intr_map) {
-    val_print (ACS_PRINT_ERR, "\n       Memory allocation error", 0);
-    val_set_status(pe_index, RESULT_FAIL (TEST_NUM, 01));
-    return;
-  }
-
-  tbl_index = 0;
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  while (tbl_index < bdf_tbl_ptr->num_entries)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-
-      /* Read Interrupt Line Register */
-      val_pcie_read_cfg(bdf, TYPE01_ILR, &reg_value);
-
-      intr_pin = (reg_value >> TYPE01_IPR_SHIFT) & TYPE01_IPR_MASK;
-      if ((intr_pin == 0) || (intr_pin > 0x4))
-        continue;
-
-      status = val_pci_get_legacy_irq_map(bdf, intr_map);
-      if (!status) {
-        // Skip the test if the Legacy IRQ map does not exist
-        val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
-        return;
-      }
-
-      /* If test runs for atleast an endpoint */
-      test_skip = 0;
-
-      intr_line = intr_map->legacy_irq_map[intr_pin-1].irq_list[0];
-
-      /* Read GICD_ICFGR register to Check for Level/Edge Sensitive. */
-      status = val_gic_get_intr_trigger_type(intr_line, &trigger_type);
-      if (status) {
-        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 03));
-        return;
-      }
-
-      if (trigger_type != INTR_TRIGGER_INFO_LEVEL_HIGH) {
-        val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 04));
-        return;
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p050_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p051.c b/test_pool/pcie/operating_system/test_os_p051.c
deleted file mode 100644
index c8569a46..00000000
--- a/test_pool/pcie/operating_system/test_os_p051.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/** @file
- * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 51)
-#define TEST_DESC  "IE_RST_2: Check Sec Bus Reset For iEP_RP           "
-
-uint32_t
-get_iep_bdf_under_rp (uint32_t rp_bdf)
-{
-  uint32_t reg_value;
-  uint32_t sec_bus;
-  uint32_t dev_num;
-  uint32_t seg;
-  uint32_t dev_bdf;
-  uint32_t dp_type;
-
-  /* Read Secondary Bus from Config Space */
-  val_pcie_read_cfg(rp_bdf, TYPE1_PBN, &reg_value);
-  sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK);
-
-  /* Find iEP_EP device type under iEP_RP */
-  for (dev_num = 0; dev_num < PCIE_MAX_DEV; dev_num++) {
-      seg = PCIE_EXTRACT_BDF_SEG(rp_bdf);
-
-      /* Create bdf for Dev 0 to 31 below the iEP_RP */
-      dev_bdf = PCIE_CREATE_BDF(seg, sec_bus, dev_num, 0);
-
-      val_pcie_read_cfg(dev_bdf, TYPE01_VIDR, &reg_value);
-      if (reg_value == PCIE_UNKNOWN_RESPONSE)
-          continue;
-
-      dp_type = val_pcie_device_port_type(dev_bdf);
-      if (dp_type == iEP_EP)
-          return dev_bdf;
-  }
-
-  /* Could not find iEP */
-  return 0x0;
-}
-
-uint32_t
-is_sbr_failed (uint32_t bdf)
-{
-  uint32_t reg_value;
-  uint32_t index;
-  uint32_t check_failed;
-
-  check_failed = 0;
-  /* Check BAR base address is cleared */
-  for (index = 0; index < TYPE0_MAX_BARS; index++) {
-
-      val_pcie_read_cfg(bdf, TYPE01_BAR + (index * BAR_BASE_SHIFT), &reg_value);
-      if ((reg_value >> BAR_BASE_SHIFT) != 0) {
-          val_print(ACS_PRINT_ERR, "\n       BAR%d base addr not cleared", index);
-          check_failed++;
-      }
-  }
-
-  /* Check the Bus Master Enable bit & Memory Space Enable
-   * bit is cleared
-   */
-  val_pcie_read_cfg(bdf, TYPE01_CR, &reg_value);
-  if ((((reg_value >> CR_BME_SHIFT) & CR_BME_MASK) != 0) ||
-      (((reg_value >> CR_MSE_SHIFT) & CR_MSE_MASK) != 0))
-  {
-      val_print(ACS_PRINT_ERR, "\n       BME/MSE not cleared", 0);
-      check_failed++;
-  }
-
-  return check_failed;
-}
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t iep_bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t reg_value;
-  uint32_t iep_rp_found;
-  uint32_t test_fails;
-  uint32_t idx;
-  void     *cfg_space_buf;
-  addr_t   cfg_space_addr;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  tbl_index = 0;
-  test_fails = 0;
-  iep_rp_found = 0;
-  cfg_space_buf = NULL;
-
-  /* Check for all the function present in bdf table */
-  while (tbl_index < bdf_tbl_ptr->num_entries)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is iEP_RP */
-      if (dp_type == iEP_RP)
-      {
-          iep_rp_found = 1;
-
-          /* Get BDF for iEP_EP under iEP_RP */
-          iep_bdf = get_iep_bdf_under_rp(bdf);
-          if (iep_bdf == 0x0) {
-              val_print(ACS_PRINT_ERR, "\n       Could Not Find iEP_EP under iEP_RP.", 0);
-              val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-              return;
-          }
-
-          /* Allocate 4KB of space for saving function configuration space */
-          /* If memory allocation fail, fail the test */
-          cfg_space_buf = val_memory_alloc(PCIE_CFG_SIZE);
-          if (cfg_space_buf == NULL)
-          {
-              val_print(ACS_PRINT_ERR, "\n       Memory allocation failed.", 0);
-              val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
-              return;
-          }
-
-          /* Get configuration space address for iEP_EP */
-          cfg_space_addr = val_pcie_get_bdf_config_addr(iep_bdf);
-          val_print(ACS_PRINT_INFO, "\n       iEP_EP BDF 0x%x : ", iep_bdf);
-          val_print(ACS_PRINT_INFO, "Config space addr 0x%x", cfg_space_addr);
-
-          /* Save the iEP_EP config space to restore after Secondary Bus Reset */
-          for (idx = 0; idx < PCIE_CFG_SIZE / 4; idx++) {
-              *((uint32_t *)cfg_space_buf + idx) = *((uint32_t *)cfg_space_addr + idx);
-          }
-
-          /* Set Secondary Bus Reset Bit in Bridge Control
-           * Register of iEP_RP
-           */
-          val_pcie_read_cfg(bdf, TYPE01_ILR, &reg_value);
-          reg_value = reg_value | BRIDGE_CTRL_SBR_SET;
-          val_pcie_write_cfg(bdf, TYPE01_ILR, reg_value);
-
-          /* Wait for Timeout */
-          val_time_delay_ms(100 * ONE_MILLISECOND);
-
-          /* Check whether iEP_RP Secondary Bus Reset works fine. */
-          if (is_sbr_failed(iep_bdf)) {
-              test_fails++;
-          }
-
-          /* Restore iEP_EP Config Space */
-          for (idx = 0; idx < PCIE_CFG_SIZE / 4; idx++) {
-              *((uint32_t *)cfg_space_addr + idx) = *((uint32_t *)cfg_space_buf + idx);
-          }
-
-          val_memory_free(cfg_space_buf);
-      }
-  }
-
-  /* Skip the test if no iEP_RP found */
-  if (iep_rp_found == 0)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p051_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p052.c b/test_pool/pcie/operating_system/test_os_p052.c
deleted file mode 100644
index a214bed0..00000000
--- a/test_pool/pcie/operating_system/test_os_p052.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/** @file
- * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 52)
-#define TEST_DESC  "RE_SMU_2,IE_SMU_1: Check ATS Support Rule          "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t cap_base;
-  uint32_t test_skip;
-  uint32_t test_fails;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  test_fails = 0;
-  test_skip = 1;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Skip this Check for Host Bridge */
-      if (val_pcie_is_host_bridge(bdf))
-        continue;
-
-      /* Check entry is integrated endpoint or rciep */
-      if ((dp_type == iEP_EP) || (dp_type == RCiEP))
-      {
-         /* Check if Address Translation Cache is Present in this device. */
-         /* If ATC Not present, skip the test.*/
-         if (!val_pcie_is_cache_present(bdf))
-             continue;
-
-         test_skip = 0;
-
-         /* If ATC Present, Check ATS Capability should be present. */
-         if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS)
-         {
-             val_print(ACS_PRINT_ERR, "\n       ATS Capability Not Present, Bdf : 0x%x", bdf);
-             test_fails++;
-         }
-      }
-  }
-
-  if (test_skip)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p052_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p053.c b/test_pool/pcie/operating_system/test_os_p053.c
deleted file mode 100644
index ba131b19..00000000
--- a/test_pool/pcie/operating_system/test_os_p053.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/** @file
- * Copyright (c) 2016-2018, 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 53)
-#define TEST_DESC  "PCI_PP_03: RP must suport ACS if P2P Txn are allow "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t cap_base = 0;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  uint32_t acs_data;
-  uint32_t data;
-  uint32_t curr_bdf_failed = 0;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  /* Check If PCIe Hierarchy supports P2P */
-  if (val_pcie_p2p_support())
-  {
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is RP */
-      if (dp_type == RP)
-      {
-          /* Test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* Read the ACS Capability */
-          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) {
-              val_print(ACS_PRINT_ERR,
-                    "\n       ACS Capability not supported, Bdf : 0x%x", bdf);
-              test_fails++;
-              continue;
-          }
-
-          val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, &acs_data);
-
-          /* Extract ACS source validation bit */
-          data = VAL_EXTRACT_BITS(acs_data, 0, 0);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG,
-                    "\n       Source validation not supported, Bdf : 0x%x", bdf);
-              curr_bdf_failed++;
-          }
-          /* Extract ACS translation blocking bit */
-          data = VAL_EXTRACT_BITS(acs_data, 1, 1);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG,
-                    "\n       Translation blocking not supported, Bdf : 0x%x", bdf);
-              curr_bdf_failed++;
-          }
-          /* Extract ACS P2P request redirect bit */
-          data = VAL_EXTRACT_BITS(acs_data, 2, 2);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG,
-                    "\n       P2P request redirect not supported, Bdf : 0x%x", bdf);
-              curr_bdf_failed++;
-          }
-          /* Extract ACS P2P completion redirect bit */
-          data = VAL_EXTRACT_BITS(acs_data, 3, 3);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG,
-                    "\n       P2P completion redirect not supported, Bdf : 0x%x", bdf);
-              curr_bdf_failed++;
-          }
-          /* Extract ACS upstream forwarding bit */
-          data = VAL_EXTRACT_BITS(acs_data, 4, 4);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG,
-                    "\n       Upstream forwarding not supported, Bdf : 0x%x", bdf);
-              curr_bdf_failed++;
-          }
-
-          if (curr_bdf_failed > 0) {
-              val_print(ACS_PRINT_ERR,
-                    "\n       ACS Capability Check Failed, Bdf : 0x%x", bdf);
-              curr_bdf_failed = 0;
-              test_fails++;
-          }
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p053_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p054.c b/test_pool/pcie/operating_system/test_os_p054.c
deleted file mode 100644
index 06516fa7..00000000
--- a/test_pool/pcie/operating_system/test_os_p054.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/** @file
- * Copyright (c) 2020,2021 Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 54)
-#define TEST_DESC  "RB_PCI_PP_05: Check RP Adv Error Report            "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t cap_base = 0;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  /* Check If PCIe Hierarchy supports P2P */
-  if (val_pcie_p2p_support())
-  {
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is RP */
-      if (dp_type == RP)
-      {
-          /* Test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* It ACS Not Supported, Fail. */
-          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) {
-              val_print(ACS_PRINT_ERR, "\n       ACS Capability not supported, Bdf : 0x%x", bdf);
-              test_fails++;
-              continue;
-          }
-
-          /* If AER Not Supported, Fail. */
-          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS) {
-              val_print(ACS_PRINT_DEBUG, "\n       AER Capability not supported, Bdf : 0x%x", bdf);
-              test_fails++;
-          }
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p054_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p055.c b/test_pool/pcie/operating_system/test_os_p055.c
deleted file mode 100644
index a66ba64e..00000000
--- a/test_pool/pcie/operating_system/test_os_p055.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/** @file
- * Copyright (c) 2020,2021 Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 55)
-#define TEST_DESC  "RB_PCI_PP_05: Check Direct Transl P2P Supp         "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t cap_base = 0;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  uint32_t acs_data;
-  uint32_t data;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is RP */
-      if (dp_type == RP)
-      {
-          /* Check If RP supports P2P with other RP's. */
-          if (val_pcie_dev_p2p_support(bdf))
-              continue;
-
-          /* It ATS Not supported, Skip the BDF. */
-          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS) {
-              continue;
-          }
-
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          val_print(ACS_PRINT_DEBUG, "\n       For BDF : 0x%x", bdf);
-
-          /* Read the ACS Capability */
-          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) {
-              val_print(ACS_PRINT_ERR, "\n       ACS Capability not supported, Bdf : 0x%x", bdf);
-              test_fails++;
-              continue;
-          }
-          val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, &acs_data);
-
-          /* Extract ACS directed translated p2p bit */
-          data = VAL_EXTRACT_BITS(acs_data, 6, 6);
-          if (data == 0) {
-              val_print(ACS_PRINT_ERR,
-                              "\n       Directed Translated P2P not supported, Bdf : 0x%x", bdf);
-              test_fails++;
-          }
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p055_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p056.c b/test_pool/pcie/operating_system/test_os_p056.c
deleted file mode 100644
index 7fd21eb7..00000000
--- a/test_pool/pcie/operating_system/test_os_p056.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/** @file
- * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 56)
-#define TEST_DESC  "IE_ACS_2 :Check iEP-RootPort P2P Support           "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t cap_base = 0;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  uint32_t acs_data;
-  uint32_t data;
-  uint32_t iep_rp_bdf;
-  uint32_t curr_bdf_failed = 0;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  /* Check If PCIe Hierarchy supports P2P */
-  if (val_pcie_p2p_support())
-  {
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-      return;
-  }
-
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is iEP_EP */
-      if (dp_type == iEP_EP)
-      {
-          /* Check If iEP_EP supports P2P with others. */
-          if (val_pcie_dev_p2p_support(bdf))
-              continue;
-
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* Find iEP_RP for this iEP_EP */
-          if (val_pcie_get_rootport(bdf, &iep_rp_bdf))
-          {
-              val_print(ACS_PRINT_ERR, "\n       Root Port Not found for iEP_EP 0x%x", bdf);
-              test_fails++;
-              continue;
-          }
-
-          /* Read the ACS Capability */
-          if (val_pcie_find_capability(iep_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS)
-          {
-              val_print(ACS_PRINT_ERR, "\n       ACS Capability not supported, Bdf : 0x%x",
-                        iep_rp_bdf);
-              test_fails++;
-              continue;
-          }
-
-          val_pcie_read_cfg(iep_rp_bdf, cap_base + ACSCR_OFFSET, &acs_data);
-
-          /* Extract ACS source validation bit */
-          data = VAL_EXTRACT_BITS(acs_data, 0, 0);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG, "\n       Source validation not supported, Bdf : 0x%x",
-                        iep_rp_bdf);
-              curr_bdf_failed++;
-          }
-          /* Extract ACS translation blocking bit */
-          data = VAL_EXTRACT_BITS(acs_data, 1, 1);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG, "\n       Translation blocking not supported, Bdf : 0x%x",
-                        iep_rp_bdf);
-              curr_bdf_failed++;
-          }
-          /* Extract ACS P2P request redirect bit */
-          data = VAL_EXTRACT_BITS(acs_data, 2, 2);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG, "\n       P2P request redirect not supported, Bdf : 0x%x",
-                        iep_rp_bdf);
-              curr_bdf_failed++;
-          }
-          /* Extract ACS P2P completion redirect bit */
-          data = VAL_EXTRACT_BITS(acs_data, 3, 3);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG,
-                        "\n       P2P completion redirect not supported, Bdf : 0x%x", iep_rp_bdf);
-              curr_bdf_failed++;
-          }
-          /* Extract ACS upstream forwarding bit */
-          data = VAL_EXTRACT_BITS(acs_data, 4, 4);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG, "\n       Upstream forwarding not supported, Bdf : 0x%x",
-                        iep_rp_bdf);
-              curr_bdf_failed++;
-          }
-
-          /* If iEP_RP supports ACS then it should have AER Capability */
-          if (val_pcie_find_capability(iep_rp_bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS)
-          {
-              val_print(ACS_PRINT_DEBUG, "\n       AER Capability not supported, Bdf : 0x%x",
-                        iep_rp_bdf);
-              curr_bdf_failed++;
-          }
-
-          if (curr_bdf_failed > 0) {
-              val_print(ACS_PRINT_ERR, "\n       ACS Capability Check Failed, Bdf : 0x%x",
-                        iep_rp_bdf);
-              curr_bdf_failed = 0;
-              test_fails++;
-          }
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 02));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p056_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p057.c b/test_pool/pcie/operating_system/test_os_p057.c
deleted file mode 100644
index cde56d67..00000000
--- a/test_pool/pcie/operating_system/test_os_p057.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/** @file
- * Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 57)
-#define TEST_DESC  "RE_ACS_1 & 2,IE_ACS_1: Check RCiEP, iEP_EP P2P Supp"
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t dp_type;
-  uint32_t cap_base = 0;
-  uint32_t test_fails;
-  uint32_t test_skip = 1;
-  uint32_t acs_data;
-  uint32_t data;
-  uint8_t p2p_support_flag = 0;
-  uint32_t curr_bdf_failed = 0;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-
-  test_fails = 0;
-
-  /* Check for all the function present in bdf table */
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-
-      /* Check entry is RCiEP or iEP end point */
-      if ((dp_type == RCiEP) || (dp_type == iEP_EP))
-      {
-          /* Check if the EP Supports Multifunction */
-          if (val_pcie_multifunction_support(bdf))
-              continue;
-
-          /* Check If Endpoint supports P2P with other Functions. */
-          if (val_pcie_dev_p2p_support(bdf))
-              continue;
-
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* Read the ACS Capability */
-          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS)
-          {
-              val_print(ACS_PRINT_ERR, "\n       ACS Capability not supported, Bdf : 0x%x", bdf);
-              test_fails++;
-              continue;
-          }
-
-          /* If RCiEP or iEP_EP supports ACS then it should have AER Capability */
-          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS)
-          {
-              val_print(ACS_PRINT_DEBUG, "\n       AER Capability not supported, Bdf : 0x%x", bdf);
-              curr_bdf_failed++;
-          }
-
-          val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, &acs_data);
-
-          /* Extract ACS p2p Request Redirect bit */
-          data = VAL_EXTRACT_BITS(acs_data, 2, 2);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG, "\n       Request Redirect P2P not supported", 0);
-              p2p_support_flag++;
-          }
-          /* Extract ACS p2p Completion Redirect bit */
-          data = VAL_EXTRACT_BITS(acs_data, 3, 3);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG, "\n       Completion Redirect P2P not supported", 0);
-              p2p_support_flag++;
-          }
-          /* Extract ACS p2p Direct Translated bit */
-          data = VAL_EXTRACT_BITS(acs_data, 6, 6);
-          if (data == 0) {
-              val_print(ACS_PRINT_DEBUG, "\n       Direct Translated P2P not supported", 0);
-              p2p_support_flag++;
-          }
-          if (p2p_support_flag > 0) {
-              val_print(ACS_PRINT_ERR, "\n       P2P not supported for bdf: %d", bdf);
-              p2p_support_flag = 0;
-              curr_bdf_failed++;
-          }
-
-          if (curr_bdf_failed > 0) {
-              val_print(ACS_PRINT_ERR, "\n       ACS Capability Check Failed, Bdf : 0x%x", bdf);
-              curr_bdf_failed = 0;
-              test_fails++;
-          }
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (test_fails)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, test_fails));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p057_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p058.c b/test_pool/pcie/operating_system/test_os_p058.c
deleted file mode 100644
index 1b4a4cf9..00000000
--- a/test_pool/pcie/operating_system/test_os_p058.c
+++ /dev/null
@@ -1,101 +0,0 @@
-/** @file
- * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 58)
-#define TEST_DESC  "RE_PCI_1: Check RCiEP Hdr type & link Cap          "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t dp_type;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t fail_cnt;
-  uint32_t test_skip = 1;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-  uint32_t hdr_type;
-  uint32_t link_cap_sup;
-
-  fail_cnt = 0;
-  tbl_index = 0;
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  while (tbl_index < bdf_tbl_ptr->num_entries)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-      if ((dp_type == RCiEP) || (dp_type == RCEC)) {
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* Extract Hdr Type */
-          hdr_type = val_pcie_function_header_type(bdf);
-          /* Type should be 0 for RCiEP*/
-          if (hdr_type != TYPE0_HEADER) {
-              val_print(ACS_PRINT_ERR, "\n         Invalid HDR TYPE 0x%x", hdr_type);
-              val_print(ACS_PRINT_ERR, " Bdf : 0x%x", bdf);
-              fail_cnt++;
-              continue;
-          }
-
-          link_cap_sup = val_pcie_link_cap_support(bdf);
-          if (link_cap_sup != 0) {
-              val_print(ACS_PRINT_ERR, "\n         Invalid Link Capabilities 0x%x", link_cap_sup);
-              val_print(ACS_PRINT_ERR, " Bdf : 0x%x", bdf);
-              fail_cnt++;
-          }
-
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (fail_cnt)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p058_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from the PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p059.c b/test_pool/pcie/operating_system/test_os_p059.c
deleted file mode 100644
index 03fdcd73..00000000
--- a/test_pool/pcie/operating_system/test_os_p059.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/** @file
- * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 59)
-#define TEST_DESC  "RE_PCI_2: Check RCEC Class code and Ext Cap        "
-
-static
-void
-payload(void)
-{
-
-  uint32_t bdf;
-  uint32_t dp_type;
-  uint32_t pe_index;
-  uint32_t tbl_index;
-  uint32_t fail_cnt;
-  uint32_t test_skip = 1;
-  uint32_t cap_base;
-  pcie_device_bdf_table *bdf_tbl_ptr;
-  uint32_t reg_value;
-
-  fail_cnt = 0;
-  tbl_index = 0;
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-
-  while (tbl_index < bdf_tbl_ptr->num_entries)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index++].bdf;
-      dp_type = val_pcie_device_port_type(bdf);
-      if (dp_type == RCEC) {
-          /* If test runs for atleast an endpoint */
-          test_skip = 0;
-
-          /* Read Function's Class Code */
-          val_pcie_read_cfg(bdf, TYPE01_RIDR, &reg_value);
-
-          if ((RCEC_BASE_CLASS != ((reg_value >> CC_BASE_SHIFT) & CC_BASE_MASK)) ||
-                (RCEC_SUB_CLASS != ((reg_value >> CC_SUB_SHIFT) & CC_SUB_MASK)) ||
-                (RCEC_PGMING_IF != ((reg_value >> CC_PGM_IF_SHIFT) & CC_PGM_IF_MASK)))
-          {
-              val_print(ACS_PRINT_ERR, "        Class code mismatch for bdf: 0x%x\n", bdf);
-              val_print(ACS_PRINT_ERR, "        dp_type: 0x%x\n", dp_type);
-              val_print(ACS_PRINT_ERR, "        CCR: 0x%x\n", reg_value);
-              fail_cnt++;
-          }
-
-          /* If Root Complex Event
-            Collector Endpoint Association Extended Capability not supported for RCEC, test fails*/
-          if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_RCECEA, &cap_base) != PCIE_SUCCESS) {
-              fail_cnt++;
-              continue;
-          }
-
-      }
-  }
-
-  if (test_skip == 1)
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-  else if (fail_cnt)
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, fail_cnt));
-  else
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-}
-
-uint32_t
-os_p059_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from all PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p060.c b/test_pool/pcie/operating_system/test_os_p060.c
deleted file mode 100644
index 2529cf03..00000000
--- a/test_pool/pcie/operating_system/test_os_p060.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/** @file
- * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
- * SPDX-License-Identifier : Apache-2.0
-
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- **/
-
-#include "val/include/bsa_acs_val.h"
-#include "val/include/val_interface.h"
-
-#include "val/include/bsa_acs_pcie.h"
-#include "val/include/bsa_acs_pe.h"
-#include "val/include/bsa_acs_memory.h"
-
-#define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 60)
-#define TEST_DESC  "PCI_IN_16: Check all 1's for out of range          "
-
-/* Returns the maximum bdf value for that segment from bdf table */
-static uint32_t get_max_bdf(uint32_t segment)
-{
-  pcie_device_bdf_table *bdf_tbl_ptr;
-  uint32_t seg_num;
-  uint32_t bdf;
-  uint32_t tbl_index = 0;
-  uint32_t max_bdf = 0;
-
-  bdf_tbl_ptr = val_pcie_bdf_table_ptr();
-  for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
-  {
-      bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      seg_num = PCIE_EXTRACT_BDF_SEG(bdf);
-
-      if (segment == seg_num)
-          max_bdf = bdf;
-  }
-
-  return max_bdf;
-}
-
-static
-void
-payload(void)
-{
-
-  uint32_t reg_value;
-  uint32_t pe_index;
-  uint32_t ecam_index;
-  uint32_t num_ecam;
-  uint32_t end_bus;
-  uint32_t cfg_addr;
-  uint32_t bus_index;
-  uint32_t dev_index;
-  uint32_t func_index;
-  uint32_t bdf;
-  uint32_t segment = 0;
-  addr_t   ecam_base = 0;
-
-  pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
-
-  for (ecam_index = 0; ecam_index < num_ecam; ecam_index++)
-  {
-      /* Get the maximum bus value from PCIe info table */
-      end_bus = val_pcie_get_info(PCIE_INFO_END_BUS, ecam_index);
-      segment = val_pcie_get_info(PCIE_INFO_SEGMENT, ecam_index);
-      val_set_status(pe_index, RESULT_SKIP(TEST_NUM, 01));
-
-      /* Get the highest BDF value for that segment */
-      bdf = get_max_bdf(segment);
-
-      /* Get the least highest of max bus number */
-      bus_index = (PCIE_EXTRACT_BDF_BUS(bdf) < end_bus) ? PCIE_EXTRACT_BDF_BUS(bdf):end_bus;
-      val_print(ACS_PRINT_INFO, "Maximum bus value is 0x%x", bus_index);
-      bus_index += 1;
-
-      /* Bus value should not exceed 255 */
-      if (bus_index > 255) {
-          val_print(ACS_PRINT_ERR, "\n Bus index exceeded maximum value", 0);
-          return;
-      }
-
-      for (dev_index = 0; dev_index < PCIE_MAX_DEV; dev_index++)
-      {
-          for (func_index = 0; func_index < PCIE_MAX_FUNC; func_index++)
-          {
-              /* Form bdf using seg, bus, device, function numbers.
-               * This BDF does not fall into the secondary and subordinate
-               * bus of any of the rootports because the bus value is one
-               * greater than the higest bus value. This BDF also doesn't
-               * match any of the existing BDF.
-               */
-              bdf = PCIE_CREATE_BDF(segment, bus_index, dev_index, func_index);
-              ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, ecam_index);
-
-              if (ecam_base == 0) {
-                  val_print(ACS_PRINT_ERR, "\n       ECAM Base is zero ", 0);
-                  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01));
-                  return;
-              }
-
-              /* There are 8 functions / device, 32 devices / Bus and each has a 4KB config space */
-              cfg_addr = (bus_index * PCIE_MAX_DEV * PCIE_MAX_FUNC * 4096) + \
-                         (dev_index * PCIE_MAX_FUNC * 4096) + (func_index * 4096);
-
-              val_print(ACS_PRINT_INFO, "\n       Calculated config address is %lx",
-                                                  ecam_base + cfg_addr + TYPE01_VIDR);
-              reg_value = pal_mmio_read(ecam_base + cfg_addr + TYPE01_VIDR);
-              if (reg_value != PCIE_UNKNOWN_RESPONSE)
-              {
-                  val_print(ACS_PRINT_ERR, "\n       Failed for BDF: 0x%x", bdf);
-                  val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
-                  return;
-              }
-
-              val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
-          }
-      }
-  }
-}
-
-uint32_t
-os_p060_entry(uint32_t num_pe)
-{
-
-  uint32_t status = ACS_STATUS_FAIL;
-
-  num_pe = 1;  //This test is run on single processor
-
-  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe);
-  if (status != ACS_STATUS_SKIP)
-      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
-
-  /* get the result from single PE and check for failure */
-  status = val_check_for_error(TEST_NUM, num_pe);
-
-  val_report_status(0, BSA_ACS_END(TEST_NUM));
-
-  return status;
-}
diff --git a/test_pool/pcie/operating_system/test_os_p061.c b/test_pool/pcie/operating_system/test_os_p061.c
index bc0961c4..644d7cc7 100644
--- a/test_pool/pcie/operating_system/test_os_p061.c
+++ b/test_pool/pcie/operating_system/test_os_p061.c
@@ -21,7 +21,7 @@
 #include "val/include/bsa_acs_memory.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 61)
-#define TEST_RULE  "PCI_MM_01-02, RE_BAR_2"
+#define TEST_RULE  "PCI_MM_01, PCI_MM_02, PCI_MM_03, RE_BAR_2"
 #define TEST_DESC  "PCIe Unaligned access                 "
 
 #define DATA 0xC0DECAFE
@@ -54,7 +54,7 @@ payload(void)
 
       while (offset <= BAR_MAX_OFFSET) {
           val_pcie_read_cfg(bdf, offset, &bar_value);
-          val_print(ACS_PRINT_DEBUG, "\n       The BAR value of bdf %x", bdf);
+          val_print(ACS_PRINT_DEBUG, "\n       The BAR value of bdf %.6x", bdf);
           val_print(ACS_PRINT_DEBUG, " is %x ", bar_value);
           base = 0;
 
@@ -70,7 +70,7 @@ payload(void)
               count--;
               goto next_bdf;
           }
-
+#
           if (BAR_REG(bar_value) == BAR_64_BIT)
           {
               val_print(ACS_PRINT_INFO, "BAR supports 64-bit address decoding capability \n", 0);
diff --git a/test_pool/pcie/operating_system/test_os_p062.c b/test_pool/pcie/operating_system/test_os_p062.c
index 5c5c1714..b827ba88 100644
--- a/test_pool/pcie/operating_system/test_os_p062.c
+++ b/test_pool/pcie/operating_system/test_os_p062.c
@@ -21,7 +21,7 @@
 #include "val/include/bsa_acs_smmu.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 62)
-#define TEST_RULE  "PCI_MM_05-07"
+#define TEST_RULE  "PCI_MM_05, PCI_MM_06, PCI_MM_07"
 #define TEST_DESC  "No extra address translation          "
 
 
@@ -44,7 +44,7 @@ payload(void)
 
   if (!target_dev_index) {
       val_print(ACS_PRINT_TEST, "\n       No DMA controllers detected...    ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
       return;
   }
 
@@ -58,7 +58,7 @@ payload(void)
           val_dma_device_get_dma_addr(target_dev_index, &dma_addr, &dma_len);
           status = val_smmu_ops(SMMU_CHECK_DEVICE_IOVA, 0, &target_dev_index, &dma_addr);
           if (status) {
-              val_print(ACS_PRINT_ERR, "\n   The DMA address %lx used by device ", dma_addr);
+              val_print(ACS_PRINT_ERR, "\n       The DMA address %lx used by device ", dma_addr);
               val_print(ACS_PRINT_ERR, "\n       is not present in the SMMU IOVA table \n", 0);
               val_set_status(index, RESULT_FAIL(TEST_NUM, target_dev_index));
               return;
@@ -78,7 +78,8 @@ payload(void)
           dma_addr = val_dma_mem_alloc(&buffer, 512, target_dev_index, DMA_COHERENT);
           status = val_smmu_ops(SMMU_CHECK_DEVICE_IOVA, 0, &target_dev_index, &dma_addr);
           if (status) {
-              val_print(ACS_PRINT_ERR, "\n The DMA addr allocated to device %d ", target_dev_index);
+              val_print(ACS_PRINT_ERR, "\n       The DMA addr allocated to device %d ",
+                        target_dev_index);
               val_print(ACS_PRINT_ERR, "\n       is not present in the SMMU IOVA table \n", 0);
               val_set_status(index, RESULT_FAIL(TEST_NUM, target_dev_index));
               return;
@@ -89,9 +90,9 @@ payload(void)
   }
 
   if (iommu_flag)
-      val_set_status(index, RESULT_PASS(TEST_NUM, 02));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 2));
   else
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
 
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p063.c b/test_pool/pcie/operating_system/test_os_p063.c
index 1bab6fae..2c414e9d 100644
--- a/test_pool/pcie/operating_system/test_os_p063.c
+++ b/test_pool/pcie/operating_system/test_os_p063.c
@@ -36,7 +36,7 @@ payload(void)
   uint32_t status = 0;
 
   if (!count) {
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -56,13 +56,13 @@ payload(void)
 
       if ((data & PER_FLAG_MSI_ENABLED) == 0) {
           val_print(ACS_PRINT_ERR, "\n       MSI should be enabled for a PCIe device ", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           status = 1;
           break;
       }
   }
   if (!status)
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pcie/operating_system/test_os_p064.c b/test_pool/pcie/operating_system/test_os_p064.c
index 91cd3ad1..76ab9cec 100644
--- a/test_pool/pcie/operating_system/test_os_p064.c
+++ b/test_pool/pcie/operating_system/test_os_p064.c
@@ -37,7 +37,7 @@ payload(void)
 
   if (!num_pcie_rc) {
      val_print(ACS_PRINT_WARN, "\n       Skip because no PCIe RC detected  ", 0);
-     val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+     val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
      return;
   }
 
@@ -46,10 +46,10 @@ payload(void)
       mem_attr = val_iovirt_get_pcie_rc_info(RC_MEM_ATTRIBUTE, num_pcie_rc);
 
       if (mem_attr == INNER_SHAREABLE)
-         val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+         val_set_status(index, RESULT_PASS(TEST_NUM, 1));
       else {
          val_print(ACS_PRINT_ERR, "\n    Failed mem attribute check for PCIe RC %d", num_pcie_rc);
-         val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+         val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
          return;
       }
   }
diff --git a/test_pool/pcie/operating_system/test_os_p065.c b/test_pool/pcie/operating_system/test_os_p065.c
index 12af943a..8e35f3aa 100644
--- a/test_pool/pcie/operating_system/test_os_p065.c
+++ b/test_pool/pcie/operating_system/test_os_p065.c
@@ -21,7 +21,7 @@
 #include "val/include/bsa_acs_pcie.h"
 
 #define TEST_NUM   (ACS_PCIE_TEST_NUM_BASE + 65)
-#define TEST_RULE  "PCI_LI_01"
+#define TEST_RULE  "PCI_LI_02"
 #define TEST_DESC  "PCI legacy intr SPI ID unique         "
 
 static inline char pin_name(int pin)
@@ -53,14 +53,14 @@ payload (void)
   count = val_peripheral_get_info (NUM_ALL, 0);
 
   if (!count) {
-     val_set_status (index, RESULT_SKIP (TEST_NUM, 01));
+     val_set_status(index, RESULT_SKIP (TEST_NUM, 1));
      return;
   }
 
   irq_map = val_memory_alloc(sizeof(PERIPHERAL_IRQ_MAP));
   if (!irq_map) {
-    val_print (ACS_PRINT_ERR, "\n       Memory allocation error", 0);
-    val_set_status (index, RESULT_FAIL (TEST_NUM, 01));
+    val_print(ACS_PRINT_ERR, "\n       Memory allocation error", 0);
+    val_set_status(index, RESULT_FAIL (TEST_NUM, 1));
     return;
   }
 
@@ -75,31 +75,31 @@ payload (void)
       case 0:
         break;
       case 1:
-        val_print (ACS_PRINT_WARN, "\n       Unable to access PCI bridge device", 0);
+        val_print(ACS_PRINT_WARN, "\n       Unable to access PCI bridge device", 0);
         break;
       case 2:
-        val_print (ACS_PRINT_WARN, "\n       Unable to fetch _PRT ACPI handle", 0);
+        val_print(ACS_PRINT_WARN, "\n       Unable to fetch _PRT ACPI handle", 0);
         /* Not a fatal error, just skip this device */
         status = 0;
         continue;
       case 3:
-        val_print (ACS_PRINT_WARN, "\n       Unable to access _PRT ACPI object", 0);
+        val_print(ACS_PRINT_WARN, "\n       Unable to access _PRT ACPI object", 0);
         /* Not a fatal error, just skip this device */
         status = 0;
         continue;
       case 4:
-        val_print (ACS_PRINT_WARN, "\n       Interrupt hard-wire error", 0);
+        val_print(ACS_PRINT_WARN, "\n       Interrupt hard-wire error", 0);
         /* Not a fatal error, just skip this device */
         status = 0;
         continue;
       case 5:
-        val_print (ACS_PRINT_ERR, "\n       Legacy interrupt out of range", 0);
+        val_print(ACS_PRINT_ERR, "\n       Legacy interrupt out of range", 0);
         break;
       case 6:
-        val_print (ACS_PRINT_ERR, "\n       Maximum number of interrupts has been reached", 0);
+        val_print(ACS_PRINT_ERR, "\n       Maximum number of interrupts has been reached", 0);
         break;
       default:
-        val_print (ACS_PRINT_ERR, "\n       Unknown error", 0);
+        val_print(ACS_PRINT_ERR, "\n       Unknown error", 0);
         break;
       }
     }
@@ -117,9 +117,9 @@ payload (void)
               if (irq_map->legacy_irq_map[current_irq_pin].irq_list[ccnt] ==
                   irq_map->legacy_irq_map[next_irq_pin].irq_list[ncnt]) {
                 status = 7;
-                val_print (ACS_PRINT_ERR, "\n       Legacy interrupt %c routing",
+                val_print(ACS_PRINT_ERR, "\n       Legacy interrupt %c routing",
                                                             pin_name(current_irq_pin));
-                val_print (ACS_PRINT_ERR, "\n       is the same as %c routing",
+                val_print(ACS_PRINT_ERR, "\n       is the same as %c routing",
                                                             pin_name(next_irq_pin));
               }
             }
@@ -137,14 +137,14 @@ payload (void)
 
 
   if (test_skip) {
-    val_set_status (index, RESULT_SKIP (TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP (TEST_NUM, 2));
     return;
   }
 
   if (!status) {
-    val_set_status (index, RESULT_PASS (TEST_NUM, 01));
+    val_set_status(index, RESULT_PASS (TEST_NUM, 1));
   } else {
-    val_set_status (index, RESULT_FAIL (TEST_NUM, status));
+    val_set_status(index, RESULT_FAIL (TEST_NUM, status));
   }
 }
 
diff --git a/test_pool/pcie/operating_system/test_os_p066.c b/test_pool/pcie/operating_system/test_os_p066.c
index beda0fc0..759ecd25 100644
--- a/test_pool/pcie/operating_system/test_os_p066.c
+++ b/test_pool/pcie/operating_system/test_os_p066.c
@@ -64,7 +64,7 @@ payload(void)
                 data = VAL_EXTRACT_BITS(bar_data, 1, 2);
                 if (data != 0) {
                     val_print(ACS_PRINT_ERR, "\n       NP type-1 pcie is not 32-bit mem type", 0);
-                    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+                    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
                     status = 2;
                     break;
                 }
@@ -73,7 +73,7 @@ payload(void)
                 if (ret) {
                     val_print(ACS_PRINT_ERR, "\n       NP type-1 pcie bridge end device"
                                                                  "is not 32-bit mem type", 0);
-                    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+                    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
                     status = 2;
                     break;
                 }
@@ -84,7 +84,7 @@ payload(void)
     if (!status)
         val_set_status(index, RESULT_SKIP (TEST_NUM, 3));
     else if (status == 1)
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/hypervisor/test_hyp_c001.c b/test_pool/pe/hypervisor/test_hyp_c001.c
index 2b4286c6..0be2ff75 100755
--- a/test_pool/pe/hypervisor/test_hyp_c001.c
+++ b/test_pool/pe/hypervisor/test_hyp_c001.c
@@ -32,9 +32,9 @@ payload()
   data = val_pe_reg_read(ID_AA64PFR0_EL1);
 
   if (data & 0x0F00) //bits 11:8 for EL2 support
-	val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+	val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-	val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+	val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/pe/hypervisor/test_hyp_c002.c b/test_pool/pe/hypervisor/test_hyp_c002.c
index 3c99161a..30ce9156 100755
--- a/test_pool/pe/hypervisor/test_hyp_c002.c
+++ b/test_pool/pe/hypervisor/test_hyp_c002.c
@@ -36,9 +36,9 @@ payload()
    */
 
   if ((VAL_EXTRACT_BITS(data, 40, 43) != 0x1))
-    val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+    val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/hypervisor/test_hyp_c003.c b/test_pool/pe/hypervisor/test_hyp_c003.c
index 75761123..cfb98a60 100644
--- a/test_pool/pe/hypervisor/test_hyp_c003.c
+++ b/test_pool/pe/hypervisor/test_hyp_c003.c
@@ -41,19 +41,19 @@ payload()
 
   if ((Gran4_2 == 0x1) && (Gran4 != 0xF)) {
      /* 4KB granule not supported at stage 2 & supported at stage 1*/
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     return;
   }
 
   if ((Gran4_2 == 0x2) && (Gran4 != 0x0)) {
     /* 4KB granule size with 48-bit addresses supported at stage 2, but not stage 1*/
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
     return;
   }
 
   if ((Gran4_2 == 0x3) && (Gran4 != 0x1)) {
     /* 4KB granule size with 52-bit addresses supported at stage 2, but not stage 1*/
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
     return;
   }
 
@@ -64,19 +64,19 @@ payload()
 
   if ((Gran16_2 == 0x1) && (Gran16 != 0x0)) {
     /* Stage 2 not supported 16KB granules & but stage 1 support */
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
     return;
   }
 
   if ((Gran16_2 == 0x2) && (Gran16 != 0x1)) {
     /* 16KB granule size with 48-bit addresses supported at stage 2, but not stage 1*/
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 05));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 5));
     return;
   }
 
   if ((Gran16_2 == 0x3) && (Gran16 != 0x2)) {
     /* 16KB granule size with 52-bit addresses supported at stage 2, but not stage 1*/
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 06));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 6));
     return;
   }
 
@@ -87,7 +87,7 @@ payload()
 
   if ((Gran64_2 == 0x1) && (Gran64 != 0xF)) {
     /* Stage 2 not supported 64KB granules & but stage 1 support */
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 07));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 7));
     return;
   }
 
@@ -97,7 +97,7 @@ payload()
     return;
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/hypervisor/test_hyp_c004.c b/test_pool/pe/hypervisor/test_hyp_c004.c
index d1e5c1c7..2a66ab97 100644
--- a/test_pool/pe/hypervisor/test_hyp_c004.c
+++ b/test_pool/pe/hypervisor/test_hyp_c004.c
@@ -31,9 +31,9 @@ payload()
 
   data = val_pe_reg_read(PMCR_EL0);
   if (((data & 0x0F800) >> 11) > 1) //bits 15:11 for Number of counters.
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 }
diff --git a/test_pool/pe/hypervisor/test_hyp_c005.c b/test_pool/pe/hypervisor/test_hyp_c005.c
index 9c8c7e96..a42f14ce 100644
--- a/test_pool/pe/hypervisor/test_hyp_c005.c
+++ b/test_pool/pe/hypervisor/test_hyp_c005.c
@@ -35,9 +35,9 @@ payload()
   /*bits [31:28] Number of breakpoints that are context-aware, minus 1*/
   context_aware_breakpoints = VAL_EXTRACT_BITS(data, 28, 31) + 1;
   if (context_aware_breakpoints > 1)
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
   else
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 }
diff --git a/test_pool/pe/operating_system/test_os_c001.c b/test_pool/pe/operating_system/test_os_c001.c
index 213fed51..642b31ea 100755
--- a/test_pool/pe/operating_system/test_os_c001.c
+++ b/test_pool/pe/operating_system/test_os_c001.c
@@ -162,7 +162,7 @@ id_regs_check(void)
 
           if ((reg_read_data & (~reg_list[0].reg_mask)) != (cache_list[i] & (~reg_list[0].reg_mask))) {
               val_set_test_data(index, (reg_read_data & (~reg_list[0].reg_mask)), 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
               return;
           }
       }
@@ -175,12 +175,12 @@ id_regs_check(void)
       if((reg_read_data & (~reg_list[i].reg_mask)) != (rd_data_array[i] & (~reg_list[i].reg_mask)))
       {
           val_set_test_data(index, (reg_read_data & (~reg_list[i].reg_mask)), i);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           return;
       }
       reg_read_data = 0;
   }
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
   return;
 }
@@ -196,7 +196,7 @@ payload(uint32_t num_pe)
 
   if (num_pe == 1) {
       val_print(ACS_PRINT_DEBUG, "\n       Skipping as num of PE is 1    ", 0);
-      val_set_status(my_index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(my_index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -209,7 +209,7 @@ payload(uint32_t num_pe)
          val_pe_reg_write(CSSELR_EL1, i << 1);
          cache_list[i] = return_reg_value(reg_list[0].reg_name, reg_list[0].dependency);
          val_data_cache_ops_by_va((addr_t)(cache_list + i), CLEAN_AND_INVALIDATE);
-         val_print(ACS_PRINT_INFO, "\n      cache size read is %x ", cache_list[i]);
+         val_print(ACS_PRINT_INFO, "\n       cache size read is %x ", cache_list[i]);
       }
       i++;
   }
@@ -227,7 +227,7 @@ payload(uint32_t num_pe)
 
           if(timeout == 0) {
               val_print(ACS_PRINT_ERR, "\n       **Timed out** for PE index = %d", i);
-              val_set_status(i, RESULT_FAIL(TEST_NUM, 02));
+              val_set_status(i, RESULT_FAIL(TEST_NUM, 2));
               return;
           }
 
diff --git a/test_pool/pe/operating_system/test_os_c002.c b/test_pool/pe/operating_system/test_os_c002.c
index ed9ee39e..29abe4ee 100755
--- a/test_pool/pe/operating_system/test_os_c002.c
+++ b/test_pool/pe/operating_system/test_os_c002.c
@@ -36,14 +36,14 @@ payload()
   /* For Gic v2 number of max PE 8, for GIC v3 and higher number of max PE 2^28 */
   if (((gic_version == 2) && (num_of_pe <= 8)) ||
       ((gic_version >= 3)  && (num_of_pe <= (2 << 27)))) {
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
       return;
   }
 
   val_print(ACS_PRINT_DEBUG, "\n       Number of PE is %d", num_of_pe);
   val_print(ACS_PRINT_DEBUG, "\n       Gic version is %d", gic_version);
 
-  val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+  val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 }
diff --git a/test_pool/pe/operating_system/test_os_c003.c b/test_pool/pe/operating_system/test_os_c003.c
index 1982628a..bd399dca 100755
--- a/test_pool/pe/operating_system/test_os_c003.c
+++ b/test_pool/pe/operating_system/test_os_c003.c
@@ -33,9 +33,9 @@ payload()
   data = (data & 0xF00000) >> 20;
 
   if ((data == 0x0) || (data == 0x1))
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/pe/operating_system/test_os_c004.c b/test_pool/pe/operating_system/test_os_c004.c
index 5158d511..42343b08 100755
--- a/test_pool/pe/operating_system/test_os_c004.c
+++ b/test_pool/pe/operating_system/test_os_c004.c
@@ -36,9 +36,9 @@ payload()
    */
 
   if (VAL_EXTRACT_BITS(data, 28, 31) == 0)
-    val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+    val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/operating_system/test_os_c005.c b/test_pool/pe/operating_system/test_os_c005.c
index 195ceb17..94520155 100755
--- a/test_pool/pe/operating_system/test_os_c005.c
+++ b/test_pool/pe/operating_system/test_os_c005.c
@@ -35,16 +35,16 @@ payload()
                 1:((pfr0 & 0xf0) == 0x20) ? 1:((pfr0 & 0xf) == 0x2) ? 1:0;
 
   if (a32_support == 0) {
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
   data = val_pe_reg_read(ID_MMFR0_EL1);
 
   if ((((data >> 28) & 0xF) == 1) && (((data >> 12) & 0xF) == 1)) //bits 31:28 and 15:12 should be 1
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/pe/operating_system/test_os_c006.c b/test_pool/pe/operating_system/test_os_c006.c
index 1e0b1893..c492a7eb 100755
--- a/test_pool/pe/operating_system/test_os_c006.c
+++ b/test_pool/pe/operating_system/test_os_c006.c
@@ -33,9 +33,9 @@ payload()
 
   //bits 7:4, 11:8, 15:12 must be non-zero
   if (((data >> 4) & 0xF) && ((data >> 8) & 0xF) && ((data >> 12) & 0xF))
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/pe/operating_system/test_os_c007.c b/test_pool/pe/operating_system/test_os_c007.c
index ea565dec..5cb222e1 100755
--- a/test_pool/pe/operating_system/test_os_c007.c
+++ b/test_pool/pe/operating_system/test_os_c007.c
@@ -37,9 +37,9 @@ payload()
   }
 
   if (((data >> 25) & 1) == 0) //Bit 25 must be 0
-      val_set_status(index, RESULT_PASS(TEST_NUM, 02));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 2));
   else
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
 
   return;
 }
diff --git a/test_pool/pe/operating_system/test_os_c008.c b/test_pool/pe/operating_system/test_os_c008.c
index bc855686..834819e0 100755
--- a/test_pool/pe/operating_system/test_os_c008.c
+++ b/test_pool/pe/operating_system/test_os_c008.c
@@ -32,9 +32,9 @@ payload()
   data = val_pe_reg_read(ID_AA64PFR0_EL1);
 
   if ((data & 0x3) && (data & 0x30)) //bits 1:0 and 5:4 must not be zero
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/pe/operating_system/test_os_c009.c b/test_pool/pe/operating_system/test_os_c009.c
index 579dc25f..57e34e15 100755
--- a/test_pool/pe/operating_system/test_os_c009.c
+++ b/test_pool/pe/operating_system/test_os_c009.c
@@ -36,12 +36,12 @@ payload()
     /* PMCR_EL0 Bits 15:11 for Number of counters. */
     data = VAL_EXTRACT_BITS(val_pe_reg_read(PMCR_EL0), 11, 15);
     if (data > 3)
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
     else
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   } else {
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
   }
 
   return;
diff --git a/test_pool/pe/operating_system/test_os_c010.c b/test_pool/pe/operating_system/test_os_c010.c
index f25a1cb5..f3394f3d 100755
--- a/test_pool/pe/operating_system/test_os_c010.c
+++ b/test_pool/pe/operating_system/test_os_c010.c
@@ -36,7 +36,7 @@ esr(uint64_t interrupt_type, void *context)
   val_pe_update_elr(context, (uint64_t)branch_to_test);
 
   val_print(ACS_PRINT_ERR, "\n       Error : Received Sync Exception ", 0);
-  val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+  val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 }
 
 static
@@ -67,7 +67,7 @@ isr()
   /* We received our interrupt, so disable PMUIRQ from generating further interrupts */
   val_pe_reg_write(PMOVSCLR_EL0, 0x1);
   val_print(ACS_PRINT_INFO, "\n Received PMUIRQ ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(int_id);
 
   return;
@@ -86,20 +86,20 @@ payload()
   data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 8, 11);
   if ((data == 0x0) || (data == 0xF)) {
       /* PMUver not implemented, Skipping. */
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
   int_id = val_pe_get_pmu_gsiv(index);
   if (int_id == 0) {
       /* PMU interrupt number not updated */
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
       return;
   }
 
   if (val_gic_install_isr(int_id, isr)) {
       val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
 
@@ -116,7 +116,7 @@ payload()
 exception_taken:
   if (timeout == 0) {
       val_print(ACS_PRINT_ERR, "\n       Interrupt not recieved within timeout", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
   }
 }
 
diff --git a/test_pool/pe/operating_system/test_os_c011.c b/test_pool/pe/operating_system/test_os_c011.c
index d60fc2e0..38fc329d 100644
--- a/test_pool/pe/operating_system/test_os_c011.c
+++ b/test_pool/pe/operating_system/test_os_c011.c
@@ -36,16 +36,16 @@ payload()
   /* bits 15:12 for Number of breakpoints - 1 */
   breakpointcount = VAL_EXTRACT_BITS(data, 12, 15) + 1;
   if (breakpointcount < 6) {
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
 
   /*bits [31:28] Number of breakpoints that are context-aware, minus 1*/
   context_aware_breakpoints = VAL_EXTRACT_BITS(data, 28, 31) + 1;
   if (context_aware_breakpoints > 1)
-      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(pe_index, RESULT_PASS(TEST_NUM, 1));
   else
-      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(pe_index, RESULT_FAIL(TEST_NUM, 2));
 
   return;
 
diff --git a/test_pool/pe/operating_system/test_os_c012.c b/test_pool/pe/operating_system/test_os_c012.c
index 53dd50f4..d0d5e198 100755
--- a/test_pool/pe/operating_system/test_os_c012.c
+++ b/test_pool/pe/operating_system/test_os_c012.c
@@ -32,9 +32,9 @@ payload()
   data = val_pe_reg_read(ID_AA64DFR0_EL1);
 
   if (((data >> 20) & 0xF) > 2) //bits 23:20 for Number of watchpoints - 1
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/pe/operating_system/test_os_c013.c b/test_pool/pe/operating_system/test_os_c013.c
index 34f85057..b8e7a5dc 100755
--- a/test_pool/pe/operating_system/test_os_c013.c
+++ b/test_pool/pe/operating_system/test_os_c013.c
@@ -32,9 +32,9 @@ payload()
   data = val_pe_reg_read(ID_AA64ISAR0_EL1);
 
   if ((data >> 16) & 0xF) //bits 19:16 are CRC32 and should not be zero
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/pe/operating_system/test_os_c014.c b/test_pool/pe/operating_system/test_os_c014.c
index f625a6b4..36a5076e 100644
--- a/test_pool/pe/operating_system/test_os_c014.c
+++ b/test_pool/pe/operating_system/test_os_c014.c
@@ -30,12 +30,12 @@ static void check_pauth_algorithm(uint32_t index, uint64_t data)
      */
     if ((VAL_EXTRACT_BITS(data, 4, 7) == 0) && (VAL_EXTRACT_BITS(data, 24, 27) == 0)) {
         if ((VAL_EXTRACT_BITS(data, 8, 11) != 0) && (VAL_EXTRACT_BITS(data, 28, 31) != 0))
-            val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+            val_set_status(index, RESULT_PASS(TEST_NUM, 1));
         else
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     }
     else
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 static
@@ -50,7 +50,7 @@ payload()
     if ((VAL_EXTRACT_BITS(data, 4, 7) == 0) && (VAL_EXTRACT_BITS(data, 8, 11) == 0) &&
         (VAL_EXTRACT_BITS(data, 24, 27) == 0) && (VAL_EXTRACT_BITS(data, 28, 31) == 0)) {
         /* Pointer signing not implemented, Skip the test */
-        val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+        val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
         return;
     }
 
diff --git a/test_pool/pe/operating_system/test_os_c015.c b/test_pool/pe/operating_system/test_os_c015.c
index 32e4df26..3e1653b4 100644
--- a/test_pool/pe/operating_system/test_os_c015.c
+++ b/test_pool/pe/operating_system/test_os_c015.c
@@ -36,7 +36,7 @@ payload()
 
     if (data == 0) {
        /* SVE Not Implemented Skip the test */
-        val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+        val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
         return;
     }
 
@@ -45,13 +45,13 @@ payload()
 
     if (data == 0) {
         /*SPE Not Implemented Skip the test */
-        val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+        val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
         return;
     }
     else if (data != 2)
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     else
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/pe/operating_system/test_os_c016.c b/test_pool/pe/operating_system/test_os_c016.c
index 0fbbdfdd..346d404c 100644
--- a/test_pool/pe/operating_system/test_os_c016.c
+++ b/test_pool/pe/operating_system/test_os_c016.c
@@ -37,11 +37,11 @@ payload()
     data_csv3 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 60, 63);
 
     if (data_csv2 != 2)
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     else if (data_csv3 != 1)
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
     else
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/operating_system/test_os_c017.c b/test_pool/pe/operating_system/test_os_c017.c
index 0e82529a..0c33f6d2 100755
--- a/test_pool/pe/operating_system/test_os_c017.c
+++ b/test_pool/pe/operating_system/test_os_c017.c
@@ -34,9 +34,9 @@ payload()
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7);
 
     if (data != 2)
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     else
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/operating_system/test_os_c018.c b/test_pool/pe/operating_system/test_os_c018.c
index b6785fa9..1406efd6 100755
--- a/test_pool/pe/operating_system/test_os_c018.c
+++ b/test_pool/pe/operating_system/test_os_c018.c
@@ -34,9 +34,9 @@ payload()
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7);
 
     if (data == 0)
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     else
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/operating_system/test_os_c019.c b/test_pool/pe/operating_system/test_os_c019.c
index c60b4b14..cb7e6150 100755
--- a/test_pool/pe/operating_system/test_os_c019.c
+++ b/test_pool/pe/operating_system/test_os_c019.c
@@ -34,9 +34,9 @@ payload()
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 36, 39);
 
     if (data != 1)
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     else
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/operating_system/test_os_c020.c b/test_pool/pe/operating_system/test_os_c020.c
index ae378ab5..05c87008 100755
--- a/test_pool/pe/operating_system/test_os_c020.c
+++ b/test_pool/pe/operating_system/test_os_c020.c
@@ -34,9 +34,9 @@ payload()
     data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 40, 43);
 
     if (data != 1)
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
     else
-        val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+        val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/pe/platform_security/test_ps_c001.c b/test_pool/pe/platform_security/test_ps_c001.c
index 5834b02f..1a7b3e8c 100755
--- a/test_pool/pe/platform_security/test_ps_c001.c
+++ b/test_pool/pe/platform_security/test_ps_c001.c
@@ -32,9 +32,9 @@ payload()
   data = val_pe_reg_read(ID_AA64PFR0_EL1);
 
   if (data & 0xF000) //bits 15:12 for EL3 support
-	val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+	val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-	val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+	val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
   return;
 
diff --git a/test_pool/peripherals/operating_system/test_os_d001.c b/test_pool/peripherals/operating_system/test_os_d001.c
index b8f4d669..430868e2 100755
--- a/test_pool/peripherals/operating_system/test_os_d001.c
+++ b/test_pool/peripherals/operating_system/test_os_d001.c
@@ -23,7 +23,7 @@
 
 #define TEST_NUM   (ACS_PER_TEST_NUM_BASE + 1)
 #define TEST_RULE  "B_PER_01, B_PER_02"
-#define TEST_DESC  "USB CTRL Interface (PCIe)             "
+#define TEST_DESC  "USB CTRL Interface                    "
 
 static
 void
@@ -37,34 +37,48 @@ payload()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
   if (count == 0) {
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
   while (count != 0) {
-      bdf = val_peripheral_get_info(USB_BDF, count - 1);
-      ret = val_pcie_read_cfg(bdf, 0x8, &interface);
-      interface = (interface >> 8) & 0xFF;
-      if (ret == PCIE_NO_MAPPING || (interface < 0x20) || (interface == 0xFF)) {
-          val_print(ACS_PRINT_WARN, "\n       WARN: USB CTRL ECAM access failed 0x%x  ", interface);
-          val_print(ACS_PRINT_WARN, "\n       Re-checking using PCIIO protocol",
-                                                                            0);
-          ret = val_pcie_io_read_cfg(bdf, 0x8, &interface);
-          if (ret == PCIE_NO_MAPPING) {
-              val_print(ACS_PRINT_ERR, "\n       Reading device class code using PciIo protocol failed ", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      if (val_peripheral_get_info(USB_PLATFORM_TYPE, count - 1) == PLATFORM_TYPE_DT) {
+          interface = val_peripheral_get_info(USB_INTERFACE_TYPE, count - 1);
+          if ((interface != USB_TYPE_EHCI) && (interface != USB_TYPE_XHCI)) {
+              val_print(ACS_PRINT_DEBUG, "\n       Detected USB CTRL not EHCI/XHCI 0x%x  ",
+                        interface);
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
               return;
           }
+      }
+      else {
+          bdf = val_peripheral_get_info(USB_BDF, count - 1);
+          ret = val_pcie_read_cfg(bdf, 0x8, &interface);
           interface = (interface >> 8) & 0xFF;
-          if ((interface < 0x20) || (interface == 0xFF)) {
-              val_print(ACS_PRINT_ERR, "\n       Detected USB CTRL not EHCI/XHCI 0x%x  ", interface);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
-              return;
+          if (ret == PCIE_NO_MAPPING || (interface < 0x20) || (interface == 0xFF)) {
+              val_print(ACS_PRINT_INFO, "\n       WARN: USB CTRL ECAM access failed 0x%x  ",
+                        interface);
+              val_print(ACS_PRINT_INFO, "\n       Re-checking using PCIIO protocol",
+                        0);
+              ret = val_pcie_io_read_cfg(bdf, 0x8, &interface);
+              if (ret == PCIE_NO_MAPPING) {
+                  val_print(ACS_PRINT_DEBUG,
+                            "\n       Reading device class code using PciIo protocol failed ", 0);
+                  val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
+                  return;
+              }
+              interface = (interface >> 8) & 0xFF;
+              if ((interface < 0x20) || (interface == 0xFF)) {
+                  val_print(ACS_PRINT_DEBUG, "\n       Detected USB CTRL not EHCI/XHCI 0x%x  ",
+                            interface);
+                  val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
+                  return;
+              }
           }
       }
       count--;
   }
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   return;
 }
 
diff --git a/test_pool/peripherals/operating_system/test_os_d002.c b/test_pool/peripherals/operating_system/test_os_d002.c
index 9b8ef153..262390a9 100755
--- a/test_pool/peripherals/operating_system/test_os_d002.c
+++ b/test_pool/peripherals/operating_system/test_os_d002.c
@@ -23,7 +23,7 @@
 
 #define TEST_NUM   (ACS_PER_TEST_NUM_BASE + 2)
 #define TEST_RULE  "B_PER_03"
-#define TEST_DESC  "Check SATA CTRL Interface via PCIe    "
+#define TEST_DESC  "Check SATA CTRL Interface             "
 
 static
 void
@@ -37,34 +37,46 @@ payload()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
   if (count == 0) {
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
   while (count != 0) {
-      bdf = val_peripheral_get_info(SATA_BDF, count - 1);
-      ret = val_pcie_read_cfg(bdf, 0x8, &interface);
-      interface = (interface >> 8) & 0xFF;
-      if (ret == PCIE_NO_MAPPING || interface != 0x01) {
-          val_print(ACS_PRINT_WARN, "       WARN: SATA CTRL ECAM access failed %x \n", interface);
-          val_print(ACS_PRINT_WARN, "       Re-checking SATA CTRL using PciIo protocol\n", 0);
-          ret = val_pcie_io_read_cfg(bdf, 0x8, &interface);
-          if (ret == PCIE_NO_MAPPING) {
-              val_print(ACS_PRINT_ERR, "       Reading device class code using PciIo"
-                                       " protocol failed\n", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      if (val_peripheral_get_info(SATA_PLATFORM_TYPE, count - 1) == PLATFORM_TYPE_DT) {
+          interface = val_peripheral_get_info(SATA_INTERFACE_TYPE, count - 1);
+          if (interface != SATA_TYPE_AHCI) {
+              val_print(ACS_PRINT_DEBUG, "\n       Detected SATA CTRL not AHCI 0x%x  ",
+                        interface);
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
               return;
           }
+      }
+      else {
+          bdf = val_peripheral_get_info(SATA_BDF, count - 1);
+          ret = val_pcie_read_cfg(bdf, 0x8, &interface);
           interface = (interface >> 8) & 0xFF;
-          if (interface != 0x01) {
-              val_print(ACS_PRINT_ERR, " Detected SATA CTRL not AHCI\n", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
-              return;
+          if (ret == PCIE_NO_MAPPING || interface != 0x01) {
+              val_print(ACS_PRINT_INFO, "       WARN: SATA CTRL ECAM access failed %x \n",
+                        interface);
+              val_print(ACS_PRINT_INFO, "       Re-checking SATA CTRL using PciIo protocol\n", 0);
+              ret = val_pcie_io_read_cfg(bdf, 0x8, &interface);
+              if (ret == PCIE_NO_MAPPING) {
+                  val_print(ACS_PRINT_DEBUG, "       Reading device class code using PciIo"
+                            " protocol failed\n", 0);
+                  val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
+                  return;
+              }
+              interface = (interface >> 8) & 0xFF;
+              if (interface != 0x01) {
+                  val_print(ACS_PRINT_DEBUG, " Detected SATA CTRL not AHCI\n", 0);
+                  val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
+                  return;
+              }
           }
       }
       count--;
   }
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   return;
 }
 
diff --git a/test_pool/peripherals/operating_system/test_os_d003.c b/test_pool/peripherals/operating_system/test_os_d003.c
index 7890817c..66e08196 100755
--- a/test_pool/peripherals/operating_system/test_os_d003.c
+++ b/test_pool/peripherals/operating_system/test_os_d003.c
@@ -1,3 +1,4 @@
+
 /** @file
  * Copyright (c) 2016-2018, 2021 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
@@ -24,15 +25,16 @@
 
 #define TEST_NUM   (ACS_PER_TEST_NUM_BASE + 3)
 #define TEST_RULE  "B_PER_05"
-#define TEST_DESC  "Check Arm BSA UART register offsets   "
+/*one space character is removed from TEST_DESC, to nullify a space written as part of the test */
+#define TEST_DESC  "Check Arm BSA UART register offsets  "
 #define TEST_NUM1  (ACS_PER_TEST_NUM_BASE + 4)
 #define TEST_RULE1 "B_PER_06, B_PER_07"
 #define TEST_DESC1 "Check Arm GENERIC UART Interrupt      "
 
-uint64_t l_uart_base;
+static uint64_t l_uart_base;
 static uint32_t int_id;
 static void *branch_to_test;
-static uint32_t test_pass, test_fail;
+static uint32_t test_fail;
 
 static
 void
@@ -44,7 +46,7 @@ esr(uint64_t interrupt_type, void *context)
   val_pe_update_elr(context, (uint64_t)branch_to_test);
 
   val_print(ACS_PRINT_ERR, "\n       Error : Received Sync Exception ", 0);
-  val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+  val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 }
 
 uint32_t
@@ -116,9 +118,8 @@ isr()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
   uart_disable_txintr();
-  test_pass++;
-  val_print(ACS_PRINT_DEBUG, "\n      Received interrupt on %d     ", int_id);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 0x01));
+  val_print(ACS_PRINT_DEBUG, "\n       Received interrupt on %d     ", int_id);
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(int_id);
 }
 
@@ -167,19 +168,19 @@ payload()
 
   uint32_t count = val_peripheral_get_info(NUM_UART, 0);
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-  uint32_t data;
+  uint32_t data1, data2;
   uint32_t interface_type;
 
   val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr);
   val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr);
 
   branch_to_test = &&exception_taken;
-
-  val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
   if (count == 0) {
-      val_print(ACS_PRINT_WARN, "\n        No UART defined by Platform      ", 0);
+      val_print(ACS_PRINT_ERR, "\n       No UART defined by Platform      ", 0);
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
+  val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
 
   while (count != 0) {
       interface_type = val_peripheral_get_info(UART_INTERFACE_TYPE, count - 1);
@@ -189,7 +190,7 @@ payload()
       {
           l_uart_base = val_peripheral_get_info(UART_BASE0, count - 1);
           if (l_uart_base == 0) {
-              val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+              val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
               return;
           }
 
@@ -205,16 +206,19 @@ payload()
               return;
 
           /* Check bits 11:8 in the UARTDR reg are read-only */
-          data = uart_reg_read(BSA_UARTDR, WIDTH_BIT32);
-          uart_reg_write(BSA_UARTDR, WIDTH_BIT32, data | 0x0F00);
-          data = (data >> 8) & 0x0F;
-          if (data != ((uart_reg_read(BSA_UARTDR, WIDTH_BIT32)>>8) & 0x0F)) {
-              val_print(ACS_PRINT_ERR, "\n     UARTDR Bits 11:8 are not Read Only", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, BSA_UARTDR));
+          data1 = uart_reg_read(BSA_UARTDR, WIDTH_BIT32);
+          /* Negating bits 11:8 and writing space character (0x20) to UART data register */
+          data2 = data1 ^ 0x0F00 ;
+          data2 = (data2 & (~0xFF)) | 0x20;
+          uart_reg_write(BSA_UARTDR, WIDTH_BIT32, data2);
+          data1 = (data1 >> 8) & 0x0F;
+          if (data1 != ((uart_reg_read(BSA_UARTDR, WIDTH_BIT32)>>8) & 0x0F)) {
+              val_print(ACS_PRINT_ERR, "\n       UARTDR Bits 11:8 are not Read Only", 0);
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
               return;
           }
 
-          val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+          val_set_status(index, RESULT_PASS(TEST_NUM, 1));
       }
 
       count--;
@@ -229,20 +233,20 @@ payload1()
 {
   uint32_t count = val_peripheral_get_info(NUM_UART, 0);
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-  uint32_t timeout = TIMEOUT_MEDIUM;
+  uint32_t timeout = TIMEOUT_LARGE;
   uint32_t interface_type;
 
   if (count == 0) {
-      val_set_status(index, RESULT_SKIP(TEST_NUM1, 01));
+      val_print(ACS_PRINT_ERR, "\n       No UART defined by Platform      ", 0);
+      val_set_status(index, RESULT_FAIL(TEST_NUM1, 1));
       return;
   }
-
-  val_set_status(index, RESULT_FAIL(TEST_NUM1, 01));
-
+  val_set_status(index, RESULT_SKIP(TEST_NUM1, 1));
   while (count != 0) {
       timeout = TIMEOUT_MEDIUM;
       int_id    = val_peripheral_get_info(UART_GSIV, count - 1);
       interface_type = val_peripheral_get_info(UART_INTERFACE_TYPE, count - 1);
+      l_uart_base = val_peripheral_get_info(UART_BASE0, count - 1);
       if (interface_type != COMPATIBLE_FULL_16550
            && interface_type != COMPATIBLE_SUBSET_16550
            && interface_type != COMPATIBLE_GENERIC_16550) {
@@ -254,31 +258,33 @@ payload1()
 
               if (val_gic_install_isr(int_id, isr)) {
                  val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-                 val_set_status(index, RESULT_FAIL(TEST_NUM1, 02));
+                 val_set_status(index, RESULT_FAIL(TEST_NUM1, 2));
                  return;
               }
 
               uart_enable_txintr();
-              val_print_raw(g_print_level, "\nTest Message    ", 0);
+              val_print_raw(l_uart_base, g_print_level, "\n    Test Message  ", 0);
 
               while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))) {
               };
 
               if (timeout == 0) {
-                  val_print(ACS_PRINT_ERR, "\n     Did not receive UART interrupt on %d  ", int_id);
-                  test_fail++;
+                 val_print(ACS_PRINT_ERR,
+                 "\n       Did not receive UART interrupt on %d  ",
+                 int_id);
+                 test_fail++;
               }
           } else {
-              val_set_status(index, RESULT_SKIP(TEST_NUM1, 02));
+              val_set_status(index, RESULT_SKIP(TEST_NUM1, 2));
           }
       }
       count--;
   }
 
-  if (test_pass)
-    val_set_status(index, RESULT_PASS(TEST_NUM1, 02));
-  else if (test_fail)
-    val_set_status(index, RESULT_FAIL(TEST_NUM1, 03));
+  if (test_fail)
+    val_set_status(index, RESULT_FAIL(TEST_NUM1, 3));
+  else
+    val_set_status(index, RESULT_PASS(TEST_NUM1, 2));
 
   return;
 }
@@ -303,6 +309,8 @@ os_d003_entry(uint32_t num_pe)
   /* get the result from all PE and check for failure */
   status = val_check_for_error(TEST_NUM, num_pe, TEST_RULE);
 
+  val_report_status(0, BSA_ACS_END(TEST_NUM), NULL);
+
   if (!status) {
       status = val_initialize_test(TEST_NUM1, TEST_DESC1, val_pe_get_num());
       if (status != ACS_STATUS_SKIP)
@@ -310,9 +318,8 @@ os_d003_entry(uint32_t num_pe)
 
       /* get the result from all PE and check for failure */
       status = val_check_for_error(TEST_NUM1, num_pe, TEST_RULE1);
+      val_report_status(0, BSA_ACS_END(TEST_NUM1), NULL);
   }
 
-  val_report_status(0, BSA_ACS_END(TEST_NUM), NULL);
-
   return status;
 }
diff --git a/test_pool/peripherals/operating_system/test_os_d004.c b/test_pool/peripherals/operating_system/test_os_d004.c
index 22c970eb..65762325 100644
--- a/test_pool/peripherals/operating_system/test_os_d004.c
+++ b/test_pool/peripherals/operating_system/test_os_d004.c
@@ -45,7 +45,7 @@ payload(void)
   if (!target_dev_index)
   {
       val_print(ACS_PRINT_TEST, "\n       No DMA controllers detected...    ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
       return;
   }
 
@@ -58,16 +58,19 @@ payload(void)
           ret = val_dma_mem_get_attrs(buffer, &attr, &sh);
           if (ret)
           {
-              val_print(ACS_PRINT_ERR, "\n     DMA controller %d: Failed to get"
-                                       " memory attributes\n", target_dev_index);
+              val_print(ACS_PRINT_ERR,
+                        "\n       DMA controller %d: Failed to get  memory attributes\n",
+                        target_dev_index);
               status = 1;
               continue;
           }
           if (!(MEM_NORMAL_WB_IN_OUT(attr) && MEM_SH_INNER(sh)))
           {
-              val_print(ACS_PRINT_INFO, "\n    DMA controler %d: IO Coherent DMA memory should"
-                       " be inner/outer writeback, inner shareable\n", target_dev_index);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+              val_print(ACS_PRINT_INFO,
+                       "\n       DMA controler %d: IO Coherent DMA memory should"
+                       " be inner/outer writeback, inner shareable\n",
+                       target_dev_index);
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
               status = 1;
           }
       } else {
@@ -75,8 +78,10 @@ payload(void)
           ret = val_dma_mem_get_attrs(buffer, &attr, &sh);
           if (ret)
           {
-              val_print(ACS_PRINT_ERR, "\n     DMA controller %d: Failed to get"
-                                       " memory attributes\n", target_dev_index);
+              val_print(ACS_PRINT_ERR,
+                        "\n       DMA controller %d: Failed to get"
+                        " memory attributes\n",
+                        target_dev_index);
               status = 1;
               continue;
           }
@@ -86,9 +91,10 @@ payload(void)
                 MEM_DEVICE(attr)))
           {
               val_print(ACS_PRINT_INFO,
-              "\n     DMA controler %d: DMA memory should be inner/outer writeback inner shareable, inner/outer non-cacheable, or device type\n",
+              "\n       DMA controler %d: DMA memory should be inner/outer writeback inner "
+              "shareable, inner/outer non-cacheable, or device type\n",
               target_dev_index);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
               status = 1;
           }
       }
diff --git a/test_pool/peripherals/operating_system/test_os_d005.c b/test_pool/peripherals/operating_system/test_os_d005.c
index d41c1950..322b19a8 100755
--- a/test_pool/peripherals/operating_system/test_os_d005.c
+++ b/test_pool/peripherals/operating_system/test_os_d005.c
@@ -1,3 +1,4 @@
+
 /** @file
  * Copyright (c) 2016-2019, 2021 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
@@ -80,8 +81,8 @@ payload()
   uint32_t test_fail = 0;
 
   if (count == 0) {
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
-      val_print(ACS_PRINT_DEBUG, "\n        No UART defined by Platform      ", 0);
+      val_print(ACS_PRINT_ERR, "\n       No UART defined by Platform      ", 0);
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
 
@@ -92,7 +93,9 @@ payload()
            || interface_type == COMPATIBLE_GENERIC_16550)
       {
           skip_test = 1;
-          val_print(ACS_PRINT_DEBUG, "\n         UART 16550 found with instance: %x", count - 1);
+          val_print(ACS_PRINT_DEBUG,
+              "\n         UART 16550 found with instance: %x",
+              count - 1);
 
           /* Check the I/O base address */
           uart_base = val_peripheral_get_info(UART_BASE0, count - 1);
@@ -100,7 +103,7 @@ payload()
           {
               val_print(ACS_PRINT_ERR, "\n         UART base must be specified"
                                        " for instance: %x", count - 1);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
               return;
           }
 
@@ -129,7 +132,9 @@ payload()
           baud_rate = counter_freq / (16 * divisor);
           if (baud_rate < BAUDRATE_1200 || baud_rate > BAUDRATE_115200)
           {
-              val_print(ACS_PRINT_ERR, "\n        Baud rate %d outside supported range", baud_rate);
+              val_print(ACS_PRINT_ERR,
+              "\n        Baud rate %d outside supported range",
+              baud_rate);
               val_print(ACS_PRINT_ERR, " for instance %x", count - 1);
               test_fail = 1;
           }
@@ -179,11 +184,11 @@ payload()
   }
 
   if (!skip_test)
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
   else if (test_fail)
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
   else
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
   return;
 }
diff --git a/test_pool/power_wakeup/operating_system/test_os_u001.c b/test_pool/power_wakeup/operating_system/test_os_u001.c
index 28bbebca..ecc39dd7 100755
--- a/test_pool/power_wakeup/operating_system/test_os_u001.c
+++ b/test_pool/power_wakeup/operating_system/test_os_u001.c
@@ -22,19 +22,24 @@
 #include "val/include/bsa_acs_wakeup.h"
 
 #define TEST_NUM1  (ACS_WAKEUP_TEST_NUM_BASE + 1)
-#define TEST_RULE1 "B_WAK_01, B_WAK_02-07, B_WAK_10-11"
+#define TEST_RULE1 "B_WAK_01, B_WAK_02, B_WAK_03, B_WAK_04, B_WAK_05 \
+                    \n       B_WAK_06, B_WAK_07, B_WAK_10, B_WAK_11"
 #define TEST_DESC1 "Wake from Watchdog WS0 Int            "
 #define TEST_NUM2  (ACS_WAKEUP_TEST_NUM_BASE + 2)
-#define TEST_RULE2 "B_WAK_01, B_WAK_02-07, B_WAK_10-11"
+#define TEST_RULE2 "B_WAK_01, B_WAK_02, B_WAK_03, B_WAK_04, B_WAK_05 \
+                    \n       B_WAK_06, B_WAK_07, B_WAK_10, B_WAK_11"
 #define TEST_DESC2 "Wake from System Timer Int            "
 #define TEST_NUM3  (ACS_WAKEUP_TEST_NUM_BASE + 3)
-#define TEST_RULE3 "B_WAK_01, B_WAK_02-07, B_WAK_10-11"
+#define TEST_RULE3 "B_WAK_01, B_WAK_02, B_WAK_03, B_WAK_04, B_WAK_05 \
+                    \n       B_WAK_06, B_WAK_07, B_WAK_10, B_WAK_11"
 #define TEST_DESC3 "Wake from EL0 PHY Timer Int           "
 #define TEST_NUM4  (ACS_WAKEUP_TEST_NUM_BASE + 4)
-#define TEST_RULE4 "B_WAK_01, B_WAK_02-07, B_WAK_10-11"
+#define TEST_RULE4 "B_WAK_01, B_WAK_02, B_WAK_03, B_WAK_04, B_WAK_05 \
+                    \n       B_WAK_06, B_WAK_07, B_WAK_10, B_WAK_11"
 #define TEST_DESC4 "Wake from EL0 VIR Timer Int           "
 #define TEST_NUM5  (ACS_WAKEUP_TEST_NUM_BASE + 5)
-#define TEST_RULE5 "B_WAK_01, B_WAK_02-07, B_WAK_10-11"
+#define TEST_RULE5 "B_WAK_01, B_WAK_02, B_WAK_03, B_WAK_04, B_WAK_05 \
+                    \n       B_WAK_06, B_WAK_07, B_WAK_10, B_WAK_11"
 #define TEST_DESC5 "Wake from EL2 PHY Timer Int           "
 
 static uint32_t intid;
@@ -48,7 +53,7 @@ isr1()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   val_wd_set_ws0(timer_num, 0);
   val_print(ACS_PRINT_INFO, "       Received WS0 interrupt          \n", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM1, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM1, 1));
   intid = val_wd_get_info(timer_num, WD_INFO_GSIV);
   val_gic_end_of_interrupt(intid);
 }
@@ -61,7 +66,7 @@ isr2()
   uint64_t cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num);
   val_timer_disable_system_timer((addr_t)cnt_base_n);
   val_print(ACS_PRINT_INFO, "       Received Sys timer interrupt   \n", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM2, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM2, 1));
   intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num);
   val_gic_end_of_interrupt(intid);
 }
@@ -74,7 +79,7 @@ isr_failsafe()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   val_timer_set_phy_el1(0);
   val_print(ACS_PRINT_ERR, "       Received Failsafe interrupt      \n", 0);
-  val_set_status(index, RESULT_FAIL(failsafe_test_num, 01));
+  val_set_status(index, RESULT_FAIL(failsafe_test_num, 1));
   intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0);
   val_gic_end_of_interrupt(intid);
 }
@@ -86,7 +91,7 @@ isr3()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   val_timer_set_phy_el1(0);
   val_print(ACS_PRINT_INFO, "       Received EL1 PHY interrupt       \n", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM3, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM3, 1));
   intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0);
   val_gic_end_of_interrupt(intid);
 }
@@ -99,7 +104,7 @@ isr4()
   /* We received our interrupt, so disable timer from generating further interrupts */
   val_timer_set_vir_el1(0);
   val_print(ACS_PRINT_INFO, "       Received EL1 VIRT interrupt      \n", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM4, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM4, 1));
   intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0);
   val_gic_end_of_interrupt(intid);
 }
@@ -112,7 +117,7 @@ isr5()
   /* We received our interrupt, so disable timer from generating further interrupts */
   val_timer_set_phy_el2(0);
   val_print(ACS_PRINT_INFO, "       Received EL2 Physical interrupt  \n", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM5, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM5, 1));
   intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0);
   val_gic_end_of_interrupt(intid);
 }
@@ -145,7 +150,7 @@ payload1()
   timer_num = val_wd_get_info(0, WD_INFO_COUNT);
   if(!timer_num){
       val_print(ACS_PRINT_DEBUG, "\n       No watchdog implemented      ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM1, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM1, 1));
       return;
   }
 
@@ -162,20 +167,20 @@ payload1()
           status = val_wd_set_ws0(timer_num, timer_expire_val);
           if (status) {
               val_print(ACS_PRINT_ERR, "\n       Setting watchdog timeout failed", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM1, 02));
+              val_set_status(index, RESULT_FAIL(TEST_NUM1, 2));
               return;
           }
           val_power_enter_semantic(BSA_POWER_SEM_B);
           wakeup_clear_failsafe();
       } else {
           val_print(ACS_PRINT_WARN, "\n       GIC Install Handler Failed...", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM1, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM1, 1));
       }
   }
 
   if(!ns_wdg){
       val_print(ACS_PRINT_DEBUG, "       No non-secure watchdog implemented   \n", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM1, 02));
+      val_set_status(index, RESULT_SKIP(TEST_NUM1, 2));
       return;
   }
 
@@ -192,8 +197,8 @@ payload2()
 
   timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0);
   if(!timer_num){
-      val_print(ACS_PRINT_DEBUG, "       No system timers implemented      \n", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM2, 01));
+      val_print(ACS_PRINT_DEBUG, "\n       No system timers implemented", 0);
+      val_set_status(index, RESULT_SKIP(TEST_NUM2, 1));
       return;
   }
 
@@ -208,14 +213,14 @@ payload2()
       status = val_timer_skip_if_cntbase_access_not_allowed(timer_num);
       if(status == ACS_STATUS_SKIP){
           val_print(ACS_PRINT_DEBUG, "       Timer cntbase can't accessed\n", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM2, 03));
+          val_set_status(index, RESULT_SKIP(TEST_NUM2, 3));
           return;
       }
 
       cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num);
       if(cnt_base_n == 0){
           val_print(ACS_PRINT_DEBUG, "       Timer cntbase is invalid\n", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM2, 04));
+          val_set_status(index, RESULT_SKIP(TEST_NUM2, 4));
           return;
       }
 
@@ -231,14 +236,14 @@ payload2()
           wakeup_clear_failsafe();
       } else{
           val_print(ACS_PRINT_WARN, "\n       GIC Install Handler Failed...", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM2, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM2, 1));
           return;
       }
   }
 
   if(!ns_timer){
       val_print(ACS_PRINT_WARN, "       No non-secure systimer implemented   \n", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM2, 03));
+      val_set_status(index, RESULT_SKIP(TEST_NUM2, 3));
       return;
   }
 }
@@ -250,12 +255,12 @@ payload3()
   uint64_t timer_expire_val = TIMEOUT_SMALL;
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
-  val_set_status(index, RESULT_FAIL(TEST_NUM3, 01));
+  val_set_status(index, RESULT_FAIL(TEST_NUM3, 1));
 
   intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0);
   if (val_gic_install_isr(intid, isr3)) {
     val_print(ACS_PRINT_WARN, "\n       GIC Install Handler Failed...", 0);
-    val_set_status(index, RESULT_FAIL(TEST_NUM3, 02));
+    val_set_status(index, RESULT_FAIL(TEST_NUM3, 2));
     return;
   }
   val_timer_set_phy_el1(timer_expire_val);
@@ -270,11 +275,11 @@ payload4()
   uint64_t timer_expire_val = TIMEOUT_SMALL;
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
-  val_set_status(index, RESULT_FAIL(TEST_NUM4, 01));
+  val_set_status(index, RESULT_FAIL(TEST_NUM4, 1));
   intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0);
   if (val_gic_install_isr(intid, isr4)) {
     val_print(ACS_PRINT_WARN, "\n       GIC Install Handler Failed...", 0);
-    val_set_status(index, RESULT_FAIL(TEST_NUM4, 02));
+    val_set_status(index, RESULT_FAIL(TEST_NUM4, 2));
     return;
   }
   failsafe_test_num = TEST_NUM4;
@@ -293,11 +298,11 @@ payload5()
   uint64_t timer_expire_val = TIMEOUT_SMALL;
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
-  val_set_status(index, RESULT_FAIL(TEST_NUM5, 01));
+  val_set_status(index, RESULT_FAIL(TEST_NUM5, 1));
   intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0);
   if (val_gic_install_isr(intid, isr5)) {
     val_print(ACS_PRINT_WARN, "\n       GIC Install Handler Failed...", 0);
-    val_set_status(index, RESULT_FAIL(TEST_NUM5, 02));
+    val_set_status(index, RESULT_FAIL(TEST_NUM5, 2));
     return;
   }
   failsafe_test_num = TEST_NUM5;
@@ -320,21 +325,25 @@ os_u001_entry(uint32_t num_pe)
   if (status_test != ACS_STATUS_SKIP)
       val_run_test_payload(TEST_NUM1, num_pe, payload1, 0);
   status = val_check_for_error(TEST_NUM1, num_pe, TEST_RULE1);
+  val_report_status(0, BSA_ACS_END(TEST_NUM1), NULL);
 
   status_test = val_initialize_test(TEST_NUM2, TEST_DESC2, num_pe);
   if (status_test != ACS_STATUS_SKIP)
       val_run_test_payload(TEST_NUM2, num_pe, payload2, 0);
   status |= val_check_for_error(TEST_NUM2, num_pe, TEST_RULE2);
+  val_report_status(0, BSA_ACS_END(TEST_NUM2), NULL);
 
   status_test = val_initialize_test(TEST_NUM3, TEST_DESC3, num_pe);
   if (status_test != ACS_STATUS_SKIP)
       val_run_test_payload(TEST_NUM3, num_pe, payload3, 0);
   status |= val_check_for_error(TEST_NUM3, num_pe, TEST_RULE3);
+  val_report_status(0, BSA_ACS_END(TEST_NUM3), NULL);
 
   status_test = val_initialize_test(TEST_NUM4, TEST_DESC4, num_pe);
   if (status_test != ACS_STATUS_SKIP)
       val_run_test_payload(TEST_NUM4, num_pe, payload4, 0);
   status |= val_check_for_error(TEST_NUM4, num_pe, TEST_RULE4);
+  val_report_status(0, BSA_ACS_END(TEST_NUM4), NULL);
 
   /* Run this test if current exception level is EL2 */
   if (val_pe_reg_read(CurrentEL) == AARCH64_EL2) {
@@ -342,9 +351,8 @@ os_u001_entry(uint32_t num_pe)
       if (status_test != ACS_STATUS_SKIP)
           val_run_test_payload(TEST_NUM5, num_pe, payload5, 0);
       status |= val_check_for_error(TEST_NUM5, num_pe, TEST_RULE5);
+      val_report_status(0, BSA_ACS_END(TEST_NUM5), NULL);
   }
 
-  val_report_status(0, BSA_ACS_END(TEST_NUM1), NULL);
-
   return status;
 }
diff --git a/test_pool/power_wakeup/operating_system/test_os_u002.c b/test_pool/power_wakeup/operating_system/test_os_u002.c
index e9b2d7b8..11670c1e 100644
--- a/test_pool/power_wakeup/operating_system/test_os_u002.c
+++ b/test_pool/power_wakeup/operating_system/test_os_u002.c
@@ -23,7 +23,7 @@
 #include "val/include/bsa_std_smc.h"
 
 #define TEST_NUM   (ACS_WAKEUP_TEST_NUM_BASE + 6)
-#define TEST_RULE  "B_WAK_02,B_WAK_09-10"
+#define TEST_RULE  "B_WAK_02, B_WAK_09, B_WAK_10"
 #define TEST_DESC  "Test No-Wake from Power Semantic F    "
 
 static uint32_t intid, wakeup_event, cnt_base_n;
@@ -48,7 +48,7 @@ isr()
           val_print(ACS_PRINT_ERR, "\n       Setting watchdog timeout failed", 0);
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(intid);
 }
 
@@ -107,7 +107,7 @@ payload_target_pe()
   val_gic_cpuif_init();
   val_suspend_pe(0, 0);
   // Set the status to indicate that target PE has resumed execution from sleep mode
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 static
@@ -139,7 +139,7 @@ payload()
   wakeup_event = wakeup_event_for_semantic_f();
   if (wakeup_event == 0) {
       val_print(ACS_PRINT_DEBUG, "\n       No Watchdogs and system timers present", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -147,7 +147,7 @@ payload()
   val_gic_route_interrupt_to_pe(intid, val_pe_get_mpid_index(target_pe));
   if (val_gic_install_isr(intid, isr)) {
       val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       val_gic_route_interrupt_to_pe(intid, index);
       return;
   }
@@ -169,7 +169,7 @@ payload()
       status = val_wd_set_ws0(wd_num, timer_expire_ticks);
       if (status) {
           val_print(ACS_PRINT_ERR, "\n       Setting watchdof timeout failed", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           return;
       }
   }
@@ -192,7 +192,7 @@ payload()
           status = val_wd_set_ws0(wd_num, 0);
           if (status) {
               val_print(ACS_PRINT_ERR, "\n       Setting watchdof timeout failed", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
               return;
           }
      }
@@ -211,7 +211,7 @@ payload()
   val_gic_route_interrupt_to_pe(intid, val_pe_get_mpid_index(target_pe));
   if (val_gic_install_isr(intid, isr)) {
       val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
       val_gic_route_interrupt_to_pe(intid, index);
       return;
   }
@@ -223,7 +223,7 @@ payload()
       status = val_wd_set_ws0(wd_num, timer_expire_ticks);
           if (status) {
               val_print(ACS_PRINT_ERR, "\n       Setting watchdof timeout failed", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
               return;
           }
   }
@@ -246,7 +246,7 @@ payload()
           status = val_wd_set_ws0(wd_num, 0);
           if (status) {
               val_print(ACS_PRINT_ERR, "\n       Setting watchdof timeout failed", 0);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 05));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 5));
               return;
           }
       }
@@ -261,9 +261,9 @@ payload()
   val_execute_on_pe(target_pe, payload_dummy, 0);
 
   if (IS_TEST_FAIL(val_get_status(target_pe)) || IS_RESULT_PENDING(val_get_status(target_pe)))
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
   else
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
   // Step12:  Route interrupt back to main PE*/
   val_gic_route_interrupt_to_pe(intid, index);
diff --git a/test_pool/smmu/hypervisor/test_hyp_i001.c b/test_pool/smmu/hypervisor/test_hyp_i001.c
index ace22f0a..a6eb0b8d 100644
--- a/test_pool/smmu/hypervisor/test_hyp_i001.c
+++ b/test_pool/smmu/hypervisor/test_hyp_i001.c
@@ -40,7 +40,7 @@ payload()
     num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
     if (num_smmu == 0) {
         val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
-        val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+        val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
         return;
     }
 
@@ -52,7 +52,7 @@ payload()
             /* Check Stage2 translation support */
             if (VAL_EXTRACT_BITS(data, 29, 29) == 0) {
                 val_print(ACS_PRINT_ERR, "\n\t Stage 2 Translation not supported ", 0);
-                val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+                val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
                 return;
             }
         }
@@ -62,13 +62,13 @@ payload()
             /* Check Stage2 translation support */
             if (VAL_EXTRACT_BITS(data, 0, 0) == 0) {
                 val_print(ACS_PRINT_ERR, "\n\t Stage 2 Translation not supported ", 0);
-                val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+                val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
                 return;
             }
         }
     }
 
-    val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+    val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/smmu/hypervisor/test_hyp_i002.c b/test_pool/smmu/hypervisor/test_hyp_i002.c
index 903cadfc..a6ee6799 100644
--- a/test_pool/smmu/hypervisor/test_hyp_i002.c
+++ b/test_pool/smmu/hypervisor/test_hyp_i002.c
@@ -44,7 +44,7 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
   if (num_smmu == 0) {
       val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
       return;
   }
 
@@ -58,7 +58,7 @@ payload()
                 if (s2ts) {
                     val_print(ACS_PRINT_ERR,
                         "\n       SMMUv2 detected: revision must be v3.2 or higher  ", 0);
-                    val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+                    val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
                     return;
                 }
             }
@@ -69,7 +69,7 @@ payload()
                 if ((minor < 2) && s2p) {
                     val_print(ACS_PRINT_ERR,
                         "\n       SMMUv3.%d detected: revision must be v3.2 or higher  ", minor);
-                    val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+                    val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
                     return;
                 }
             }
@@ -77,12 +77,12 @@ payload()
       if (smmu_rev < 2) {
             val_print(ACS_PRINT_ERR,
                 "\n       SMMU revision must be at least v2  ", 0);
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
             return;
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/hypervisor/test_hyp_i004.c b/test_pool/smmu/hypervisor/test_hyp_i004.c
index c062853f..9fbd73d4 100644
--- a/test_pool/smmu/hypervisor/test_hyp_i004.c
+++ b/test_pool/smmu/hypervisor/test_hyp_i004.c
@@ -39,7 +39,7 @@ payload()
   data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
   if (data == 0) {
       val_print(ACS_PRINT_WARN, "\n       PCIe Subsystem not  discovered   ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -47,14 +47,14 @@ payload()
 
   if (num_smmu == 0) {
       val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
   while (num_smmu--) {
       if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) {
           val_print(ACS_PRINT_WARN, "\n       Not valid for SMMU v2           ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
           return;
       }
 
@@ -62,12 +62,12 @@ payload()
       // Check I/O coherent access
       if (VAL_EXTRACT_BITS(data, 4, 4) == 0)      {
           val_print(ACS_PRINT_ERR, "\n\t IO-Coherent access not supported  ", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
           return;
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/smmu/hypervisor/test_hyp_i005.c b/test_pool/smmu/hypervisor/test_hyp_i005.c
index 01a76b48..aaf95193 100644
--- a/test_pool/smmu/hypervisor/test_hyp_i005.c
+++ b/test_pool/smmu/hypervisor/test_hyp_i005.c
@@ -42,28 +42,28 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
   if (num_smmu == 0) {
       val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
       return;
   }
 
   while (num_smmu--) {
       if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) {
           val_print(ACS_PRINT_WARN, "\n       Not valid for SMMU v2           ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 04));
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 4));
           return;
       }
 
       data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 18, 18);
 
       if (!data && pe_vmid) {
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           val_print(ACS_PRINT_ERR, "\n       16 bit VMID not "
                                    "supported for SMMU %x", num_smmu);
           return;
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i001.c b/test_pool/smmu/operating_system/test_os_i001.c
index f4405932..7c7e212b 100755
--- a/test_pool/smmu/operating_system/test_os_i001.c
+++ b/test_pool/smmu/operating_system/test_os_i001.c
@@ -38,7 +38,7 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
   if (num_smmu == 0) {
       val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered                  ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -53,11 +53,11 @@ payload()
   if ((smmuv2_flag) && (smmuv3_flag)) {
       val_print(ACS_PRINT_ERR, "\n       ALL SMMUs are not of the same "
                                 "Architecture version \n", 0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i002.c b/test_pool/smmu/operating_system/test_os_i002.c
index 09a78e14..e1041245 100755
--- a/test_pool/smmu/operating_system/test_os_i002.c
+++ b/test_pool/smmu/operating_system/test_os_i002.c
@@ -41,7 +41,7 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
   if (num_smmu == 0) {
       val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered                  ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -65,7 +65,7 @@ payload()
       if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 28, 31) == 0x0) ||
           (VAL_EXTRACT_BITS(data_pe_mmfr0, 40, 43) == 0x2)) {
           if (is_smmu_4k != 1) {
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
               val_print(ACS_PRINT_ERR, "\n       PE supports 4kB granules, "
                                        "but SMMU %x does not", num_smmu);
               return;
@@ -76,7 +76,7 @@ payload()
       if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 20, 23) == 0x1) ||
           (VAL_EXTRACT_BITS(data_pe_mmfr0, 32, 35) == 0x2)) {
           if (is_smmu_16k != 1) {
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
               val_print(ACS_PRINT_ERR, "\n       PE supports 16kB granules, "
                                        "but SMMU %x does not", num_smmu);
               return;
@@ -87,7 +87,7 @@ payload()
       if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 24, 27) == 0x0) ||
           (VAL_EXTRACT_BITS(data_pe_mmfr0, 36, 39) == 0x2)) {
           if (is_smmu_64k != 1) {
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
               val_print(ACS_PRINT_ERR, "\n       PE supports 64kB granules, "
                                        "but SMMU %x does not", num_smmu);
               return;
@@ -95,7 +95,7 @@ payload()
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i003.c b/test_pool/smmu/operating_system/test_os_i003.c
index 9947f397..15cd8825 100755
--- a/test_pool/smmu/operating_system/test_os_i003.c
+++ b/test_pool/smmu/operating_system/test_os_i003.c
@@ -39,21 +39,21 @@ payload()
   data_va_range = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 16, 19);
   if (data_va_range == 0) {
     val_print(ACS_PRINT_DEBUG, "\n       Large VA Not Supported by PE                        ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
     return;
   }
 
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
   if (num_smmu == 0) {
     val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered                  ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
   while (num_smmu--) {
       if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) {
           val_print(ACS_PRINT_WARN, "\n       Large VA Not Supported in SMMUv2", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           return;
       }
 
@@ -63,13 +63,13 @@ payload()
       if (data_va_range == 1) {
           if (data_vax != 1) {
               val_print(ACS_PRINT_ERR, "\n       Large VA Not Supported in SMMU %x", num_smmu);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
               return;
           }
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i004.c b/test_pool/smmu/operating_system/test_os_i004.c
index e061adec..798b0db1 100755
--- a/test_pool/smmu/operating_system/test_os_i004.c
+++ b/test_pool/smmu/operating_system/test_os_i004.c
@@ -40,7 +40,7 @@ payload()
   if (data_pe_tlb != 0x2) {
       val_print(ACS_PRINT_DEBUG, "\n       TLB Range Invalid Not "
                                 "Supported For PE              ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -48,7 +48,7 @@ payload()
   if (num_smmu == 0) {
     val_print(ACS_PRINT_DEBUG, "\n       No SMMU Controllers are discovered"
                                  "                  ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
@@ -56,7 +56,7 @@ payload()
     if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) < 3) {
       val_print(ACS_PRINT_DEBUG, "\n       Not valid for SMMUv2 or older"
                                     "version               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
       return;
     }
 
@@ -65,15 +65,15 @@ payload()
     /* If PE TLB Range Invalidation then SMMU_IDR3.RIL = 0b1 */
     if (data_pe_tlb == 0x2) {
         if (data_ril != 0x1) {
-            val_print(ACS_PRINT_ERR, "\n       Range Invalidation not "
-                                     "supported for SMMU %x", num_smmu);
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+            val_print(ACS_PRINT_ERR, "\n       Range Invalidation unsupported "
+                                     "for SMMU %x", num_smmu);
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
             return;
         }
     }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i005.c b/test_pool/smmu/operating_system/test_os_i005.c
index 73b73297..c328668a 100644
--- a/test_pool/smmu/operating_system/test_os_i005.c
+++ b/test_pool/smmu/operating_system/test_os_i005.c
@@ -40,7 +40,7 @@ payload()
   if (data_pa_range != 0x6) {
    val_print(ACS_PRINT_DEBUG, "\n       Large PA Not Supported by PE        "
                                       "                  ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
     return;
   }
 
@@ -48,7 +48,7 @@ payload()
   if (num_smmu == 0) {
     val_print(ACS_PRINT_DEBUG, "\n       No SMMU Controllers are discovered "
                                     "                   ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
@@ -56,7 +56,7 @@ payload()
       if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) {
           val_print(ACS_PRINT_ERR, "\n       Large PA Not Supported in"
                                     " SMMUv2", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           return;
       }
 
@@ -66,13 +66,13 @@ payload()
       if (data_pa_range == 0x6) {
           if (data_oas != 0x6) {
               val_print(ACS_PRINT_WARN, "\n       Large PA Not Supported in SMMU %x", num_smmu);
-              val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+              val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
               return;
           }
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i006.c b/test_pool/smmu/operating_system/test_os_i006.c
index 6255a24b..b7e4531c 100755
--- a/test_pool/smmu/operating_system/test_os_i006.c
+++ b/test_pool/smmu/operating_system/test_os_i006.c
@@ -44,7 +44,7 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
   if (num_smmu == 0) {
     val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered                  ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
     return;
   }
 
@@ -58,7 +58,7 @@ payload()
                 if (s1ts) {
                     val_print(ACS_PRINT_ERR,
                         "\n       SMMUv2 detected: revision must be v3.2 or higher  ", 0);
-                    val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+                    val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
                     return;
                 }
             }
@@ -69,7 +69,7 @@ payload()
                 if ((minor < 2) && s1p) {
                     val_print(ACS_PRINT_ERR,
                         "\n       SMMUv3.%d detected: revision must be v3.2 or higher  ", minor);
-                    val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+                    val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
                     return;
                 }
             }
@@ -77,12 +77,12 @@ payload()
       if (smmu_rev < 2) {
             val_print(ACS_PRINT_ERR,
                 "\n       SMMU revision must be at least v2  ", 0);
-            val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+            val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
             return;
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i007.c b/test_pool/smmu/operating_system/test_os_i007.c
index 505cb365..bc0869b2 100644
--- a/test_pool/smmu/operating_system/test_os_i007.c
+++ b/test_pool/smmu/operating_system/test_os_i007.c
@@ -43,7 +43,7 @@ payload()
   data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
   if (data == 0) {
     val_print(ACS_PRINT_WARN, "\n       PCIe Subsystem not discovered                       ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
@@ -51,14 +51,14 @@ payload()
 
   if (num_smmu == 0) {
     val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered                  ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
     return;
   }
 
   while (num_smmu--) {
     if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) {
       val_print(ACS_PRINT_WARN, "\n       Not valid for SMMU v2                               ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 04));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 4));
       return;
     }
 
@@ -68,14 +68,14 @@ payload()
     asid = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 12, 12);
 
     if (s1p && !asid && pe_asid) {
-        val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
-        val_print(ACS_PRINT_ERR, "\n       16 bit ASID not "
-                                 "supported for SMMU %x", num_smmu);
+        val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
+        val_print(ACS_PRINT_ERR, "\n       16 bit ASID unsupported "
+                                 "for SMMU %x", num_smmu);
         return;
     }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i008.c b/test_pool/smmu/operating_system/test_os_i008.c
index 918a702a..dc85fd2c 100644
--- a/test_pool/smmu/operating_system/test_os_i008.c
+++ b/test_pool/smmu/operating_system/test_os_i008.c
@@ -41,7 +41,7 @@ payload()
   data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
   if (data == 0) {
     val_print(ACS_PRINT_WARN, "\n       PCIe Subsystem not discovered                       ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
     return;
   }
 
@@ -49,7 +49,7 @@ payload()
 
   if (num_smmu == 0) {
     val_print(ACS_PRINT_ERR, "\n       No SMMU Controllers are discovered                  ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
     return;
   }
 
@@ -63,7 +63,7 @@ payload()
   while (num_smmu--) {
       if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) {
           val_print(ACS_PRINT_WARN, "\n       Not valid for SMMU v2           ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 04));
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 4));
           return;
       }
 
@@ -71,20 +71,20 @@ payload()
 
       if ((data_pe_endian == 1) && ((data == 1) || (data == 2))) {
           /* If PE supports big endian */
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           val_print(ACS_PRINT_ERR, "\n       PE supports big endian, "
                                    "but SMMU %x does not", num_smmu);
           return;
       } else if ((data_pe_endian == 0) && ((data == 1) || (data == 3))) {
           /* If PE supports little endian */
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           val_print(ACS_PRINT_ERR, "\n       PE supports little endian, "
                                    "but SMMU %x does not", num_smmu);
           return;
       }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/smmu/operating_system/test_os_i009.c b/test_pool/smmu/operating_system/test_os_i009.c
index 1756df0e..cc8e63eb 100644
--- a/test_pool/smmu/operating_system/test_os_i009.c
+++ b/test_pool/smmu/operating_system/test_os_i009.c
@@ -47,13 +47,13 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
   if (num_smmu == 0) {
     val_print(ACS_PRINT_DEBUG, "\n       No SMMU Controllers are discovered                 ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
     return;
   }
 
   if (!(pe_mpam || frac)) {
     val_print(ACS_PRINT_DEBUG, "\n       No MPAM controlled resources present               ", 0);
-    val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+    val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
     return;
   }
 
@@ -62,7 +62,7 @@ payload()
         if (smmu_rev < 3) {
                 // MPAM support not required for SMMUv2 and below
                 val_print(ACS_PRINT_DEBUG, "\n       SMMU revision v2 or lower detected  ", 0);
-                val_set_status(index, RESULT_SKIP(TEST_NUM, 04));
+                val_set_status(index, RESULT_SKIP(TEST_NUM, 4));
                 return;
         }
         else {
@@ -78,7 +78,7 @@ payload()
                         if (!(mpam && max_id)) {
                                 val_print(ACS_PRINT_ERR,
                                           "\n       SMMU without MPAM support detected  ", 0);
-                                val_set_status(index, RESULT_FAIL(TEST_NUM, 04));
+                                val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
                                 return;
                         }
                 }
@@ -86,13 +86,13 @@ payload()
                         // MPAM support not required for SMMUv3.0/3.1
                         val_print(ACS_PRINT_WARN,
                               "\n       SMMU revision v3.0/3.1 detected  ", 0);
-                        val_set_status(index, RESULT_SKIP(TEST_NUM, 04));
+                        val_set_status(index, RESULT_SKIP(TEST_NUM, 4));
                         return;
                 }
         }
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 }
 
 uint32_t
diff --git a/test_pool/timer/operating_system/test_os_t001.c b/test_pool/timer/operating_system/test_os_t001.c
index 60d9e686..4c1ede88 100755
--- a/test_pool/timer/operating_system/test_os_t001.c
+++ b/test_pool/timer/operating_system/test_os_t001.c
@@ -35,12 +35,12 @@ payload()
   counter_freq = val_timer_get_info(TIMER_INFO_CNTFREQ, 0);
 
   if (counter_freq > 10*1000*1000) {
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
       return;
   }
 
-  val_print(ACS_PRINT_ERR, "\n      Counter frequency is %x     ", counter_freq);
-  val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+  val_print(ACS_PRINT_ERR, "\n       Counter frequency is %x     ", counter_freq);
+  val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/timer/operating_system/test_os_t002.c b/test_pool/timer/operating_system/test_os_t002.c
index 567c82f8..4541b65c 100644
--- a/test_pool/timer/operating_system/test_os_t002.c
+++ b/test_pool/timer/operating_system/test_os_t002.c
@@ -42,14 +42,14 @@ payload()
       if ((val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS, 0) & BSA_TIMER_FLAG_ALWAYS_ON) &&
         (val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS, 0) & BSA_TIMER_FLAG_ALWAYS_ON) &&
         (val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS, 0) & BSA_TIMER_FLAG_ALWAYS_ON)) {
-          val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+          val_set_status(index, RESULT_PASS(TEST_NUM, 1));
       } else {
           val_print(ACS_PRINT_ERR, "\n       PE Timers are not always-on \n"
-                                   "&       No system wake up timer", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+                                   "       And no system wake up timer", 0);
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       }
   } else {
-      val_set_status(index, RESULT_PASS(TEST_NUM, 02));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 2));
   }
 
 }
diff --git a/test_pool/timer/operating_system/test_os_t003.c b/test_pool/timer/operating_system/test_os_t003.c
index 2248dcfd..60622409 100644
--- a/test_pool/timer/operating_system/test_os_t003.c
+++ b/test_pool/timer/operating_system/test_os_t003.c
@@ -31,13 +31,14 @@ payload()
 {
 
   uint64_t cnt_ctl_base, cnt_base_n;
-  uint32_t data, data1, status, ns_timer = 0;
+  uint32_t data, status, ns_timer = 0;
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   uint64_t timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0);
+  uint64_t data1;
 
   if (!timer_num) {
       val_print(ACS_PRINT_DEBUG, "\n       No System timers are defined  ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 0x1));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -52,16 +53,16 @@ payload()
       cnt_base_n   = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num);
 
       if (cnt_ctl_base == 0) {
-          val_print(ACS_PRINT_WARN, "\n       CNTCTL BASE is zero             ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 0x2));
+          val_print(ACS_PRINT_DEBUG, "\n       CNTCTL BASE is zero             ", 0);
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
           return;
       }
       //Read CNTACR to determine whether access permission from NS state is permitted
       status = val_timer_skip_if_cntbase_access_not_allowed(timer_num);
       if (status == ACS_STATUS_SKIP) {
-          val_print(ACS_PRINT_WARN,
+          val_print(ACS_PRINT_DEBUG,
                     "\n       Security doesn't allow access to timer registers      ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
           return;
       }
 
@@ -69,29 +70,55 @@ payload()
       data = val_mmio_read(cnt_ctl_base + CNTTIDR);
       val_mmio_write(cnt_ctl_base + CNTTIDR, 0xFFFFFFFF);
       if (data != val_mmio_read(cnt_ctl_base + CNTTIDR)) {
-          val_print(ACS_PRINT_ERR, "\n       Read-write check failed for"
+          val_print(ACS_PRINT_DEBUG, "\n       Read-write check failed for"
               " CNTCTLBase.CNTTIDR, expected value %x ", data);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x2));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           return;
       }
 
       if (cnt_base_n == 0) {
-          val_print(ACS_PRINT_WARN, "\n      CNT_BASE_N is zero                 ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 0x3));
+          val_print(ACS_PRINT_DEBUG, "\n       CNT_BASE_N is zero                 ", 0);
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 4));
           return;
       }
 
-      data = val_mmio_read(cnt_base_n + CNTPCT_LOWER);
-      data1 = val_mmio_read(cnt_base_n + CNTPCT_HIGHER);
+      // Read CNTPCT register
+      data1 = val_mmio_read64(cnt_base_n + CNTPCT_LOWER);
+      val_print(ACS_PRINT_DEBUG, "\n       CNTPCT Read value = 0x%llx       ", data1);
 
       // Writes to Read-Only registers should be ignore
-      val_mmio_write(cnt_base_n + CNTPCT_LOWER, data - ARBIT_VALUE);
-      val_mmio_write(cnt_base_n + CNTPCT_HIGHER, data1 - ARBIT_VALUE);
+      val_mmio_write64(cnt_base_n + CNTPCT_LOWER, (data1 - ARBIT_VALUE));
 
-      if ((val_mmio_read(cnt_base_n + CNTPCT_LOWER) != data) ||
-         (val_mmio_read(cnt_base_n + CNTPCT_HIGHER) != data1)) {
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x4));
-          val_print(ACS_PRINT_ERR, "\n      CNTBaseN: CNTPCT reg should be read-only ", 0);
+      if (val_mmio_read64(cnt_base_n + CNTPCT_LOWER) < data1) {
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
+          val_print(ACS_PRINT_DEBUG, "\n       CNTBaseN: CNTPCT reg should be read-only ", 0);
+          return;
+      }
+
+      // Read CNTVCT register
+      data1 = val_mmio_read64(cnt_base_n + CNTVCT_LOWER);
+      val_print(ACS_PRINT_DEBUG, "\n       CNTVCT Read value = 0x%llx       ", data1);
+
+      // Writes to Read-Only registers should be ignore
+      val_mmio_write64(cnt_base_n + CNTVCT_LOWER, (data1 - ARBIT_VALUE));
+
+      if (val_mmio_read64(cnt_base_n + CNTVCT_LOWER) < data1) {
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
+          val_print(ACS_PRINT_DEBUG, "\n       CNTBaseN: CNTVCT reg should be read-only ", 0);
+          return;
+      }
+
+      // Read CNTFRQ register
+      data = val_mmio_read(cnt_base_n + CNTBaseN_CNTFRQ);
+      val_print(ACS_PRINT_DEBUG, "\n       CNTFRQ Read value = 0x%x         ",
+                                                                        data);
+
+      // Writes to Read-Only registers should be ignore
+      val_mmio_write(cnt_base_n + CNTBaseN_CNTFRQ, (data - ARBIT_VALUE));
+
+      if (val_mmio_read(cnt_base_n + CNTBaseN_CNTFRQ) != data) {
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 4));
+          val_print(ACS_PRINT_DEBUG, "\n       CNTBaseN: CNTFRQ reg should be read-only ", 0);
           return;
       }
 
@@ -101,8 +128,9 @@ payload()
       if (data != (val_mmio_read(cnt_base_n + CNTP_CTL) & 0x3)) {
           val_print(ACS_PRINT_ERR, "\n       Read-write check failed for "
               "CNTBaseN.CNTP_CTL, expected value %x ", data);
-          val_print(ACS_PRINT_ERR, "\n       Read value %x ", val_mmio_read(cnt_base_n + CNTP_CTL));
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x5));
+          val_print(ACS_PRINT_DEBUG, "\n       Read value %x ",
+                    val_mmio_read(cnt_base_n + CNTP_CTL));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 5));
           val_mmio_write(cnt_base_n + CNTP_CTL, 0x0); // Disable the timer before return
           return;
       }
@@ -115,27 +143,27 @@ payload()
       val_mmio_write(cnt_base_n + CNTP_CVAL_HIGHER, data);
 
       if (data != val_mmio_read(cnt_base_n + CNTP_CVAL_LOWER)) {
-          val_print(ACS_PRINT_ERR, "\n       Read-write check failed for "
+          val_print(ACS_PRINT_DEBUG, "\n       Read-write check failed for "
               "CNTBaseN.CNTP_CVAL[31:0], read value %x ",
               val_mmio_read(cnt_base_n + CNTP_CVAL_LOWER));
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x6));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 6));
           return;
       }
 
       if (data != val_mmio_read(cnt_base_n + CNTP_CVAL_HIGHER)) {
-          val_print(ACS_PRINT_ERR, "\n       Read-write check failed for"
+          val_print(ACS_PRINT_DEBUG, "\n       Read-write check failed for"
               " CNTBaseN.CNTP_CVAL[63:32], read value %x ",
               val_mmio_read(cnt_base_n + CNTP_CVAL_HIGHER));
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 0x7));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 7));
           return;
       }
 
-      val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+      val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   }
 
   if (!ns_timer) {
-      val_print(ACS_PRINT_WARN, "\n       No non-secure systimer implemented", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+      val_print(ACS_PRINT_DEBUG, "\n       No non-secure systimer implemented", 0);
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 5));
       return;
   }
 
diff --git a/test_pool/timer/operating_system/test_os_t004.c b/test_pool/timer/operating_system/test_os_t004.c
index 2c1cde3f..74303aa9 100644
--- a/test_pool/timer/operating_system/test_os_t004.c
+++ b/test_pool/timer/operating_system/test_os_t004.c
@@ -36,7 +36,7 @@ isr()
 
   val_print(ACS_PRINT_INFO, "\n       Received interrupt   ", 0);
   val_timer_disable_system_timer((addr_t)cnt_base_n);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(intid);
 }
 
@@ -54,7 +54,7 @@ payload()
 
   if (!timer_num) {
       val_print(ACS_PRINT_DEBUG, "\n       No System timers are defined  ", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -73,14 +73,14 @@ payload()
       if (status == ACS_STATUS_SKIP) {
           val_print(ACS_PRINT_WARN,
                     "\n       Security doesn't allow access to timer registers      ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
           return;
       }
 
       cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num);
       if (cnt_base_n == 0) {
-          val_print(ACS_PRINT_WARN, "\n      CNT_BASE_N is zero                 ", 0);
-          val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+          val_print(ACS_PRINT_WARN, "\n       CNT_BASE_N is zero                 ", 0);
+          val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
           return;
       }
 
@@ -88,7 +88,7 @@ payload()
       intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num);
       if (val_gic_install_isr(intid, isr)) {
           val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           return;
       }
 
@@ -100,14 +100,14 @@ payload()
 
       if (timeout == 0) {
           val_print(ACS_PRINT_ERR, "\n       Sys timer interrupt not received on %d   ", intid);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           return;
       }
   }
 
   if (!ns_timer) {
       val_print(ACS_PRINT_WARN, "\n       No non-secure systimer implemented", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 05));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 5));
       return;
   }
 
diff --git a/test_pool/timer/operating_system/test_os_t005.c b/test_pool/timer/operating_system/test_os_t005.c
index b030c679..f4d916c6 100644
--- a/test_pool/timer/operating_system/test_os_t005.c
+++ b/test_pool/timer/operating_system/test_os_t005.c
@@ -62,7 +62,7 @@ payload()
 
   if (!ns_timer) {
       val_print(ACS_PRINT_DEBUG, "\n       No non-secure systimer implemented", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -85,7 +85,7 @@ payload()
       val_timer_disable_system_timer((addr_t)cnt_base_n);
       val_gic_clear_interrupt(intid);
       val_timer_set_phy_el1(0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 02));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 2));
       return;
   }
 
@@ -94,7 +94,7 @@ payload()
       val_timer_disable_system_timer((addr_t)cnt_base_n);
       val_gic_clear_interrupt(intid);
       val_timer_set_phy_el1(0);
-      val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+      val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
       return;
   }
 
@@ -110,9 +110,9 @@ payload()
   /* Check whether count is moved or not*/
   if ((timer_cnt < ((pe_timer_ticks - sys_timer_ticks) + (sys_timer_ticks/100)))
                                                       && (timer_cnt != 0))
-    val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+    val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   else
-    val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+    val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
 }
 
 uint32_t
diff --git a/test_pool/watchdog/operating_system/test_os_w001.c b/test_pool/watchdog/operating_system/test_os_w001.c
index eda547bc..c7d56a33 100755
--- a/test_pool/watchdog/operating_system/test_os_w001.c
+++ b/test_pool/watchdog/operating_system/test_os_w001.c
@@ -21,7 +21,7 @@
 #include "val/include/bsa_acs_wd.h"
 
 #define TEST_NUM   (ACS_WD_TEST_NUM_BASE + 1)
-#define TEST_RULE  "B_WD_01-02"
+#define TEST_RULE  "B_WD_01, B_WD_02"
 #define TEST_DESC  "Non Secure Watchdog Access            "
 
 static
@@ -35,10 +35,12 @@ payload()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   uint32_t data, ns_wdg = 0;
 
-  val_print(ACS_PRINT_DEBUG, "\n       Found %d watchdogs in table ", wd_num);
+  val_print(ACS_PRINT_DEBUG,
+            "\n       Found %d watchdogs in table             ",
+            wd_num);
 
   if (wd_num == 0) {
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -50,39 +52,39 @@ payload()
 
       ns_wdg++;
       refresh_base = val_wd_get_info(wd_num, WD_INFO_REFRESH_BASE);
-      val_print(ACS_PRINT_INFO, "\n      Watchdog Refresh base is %x ", refresh_base);
+      val_print(ACS_PRINT_INFO, "\n       Watchdog Refresh base is %x ", refresh_base);
       ctrl_base    = val_wd_get_info(wd_num, WD_INFO_CTRL_BASE);
-      val_print(ACS_PRINT_INFO, "\n      Watchdog CTRL base is  %x      ", ctrl_base);
+      val_print(ACS_PRINT_INFO, "\n       Watchdog CTRL base is  %x      ", ctrl_base);
 
       data = val_mmio_read(ctrl_base);
       //Control register bits 31:3 are reserved 0
       if(data >> WD_CSR_RSRV_SHIFT) {
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           return;
       }
 
       data = val_mmio_read(refresh_base);
       //refresh frame offset 0 must return 0 on reads.
       if(data) {
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           return;
       }
 
       /* WOR.Upper word  [31:16] is reserved & must be zero */
       data = val_mmio_read(ctrl_base + WD_OR_UPPER_WORD_OFFSET);
       if(data >> WD_OR_RSRV_SHIFT) {
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 03));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 3));
           return;
       }
   } while(wd_num);
 
   if(!ns_wdg) {
       val_print(ACS_PRINT_WARN, "\n       No non-secure Watchdogs reported", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
       return;
   }
 
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
 
 }
 
diff --git a/test_pool/watchdog/operating_system/test_os_w002.c b/test_pool/watchdog/operating_system/test_os_w002.c
index 294dbe23..6e93d90a 100644
--- a/test_pool/watchdog/operating_system/test_os_w002.c
+++ b/test_pool/watchdog/operating_system/test_os_w002.c
@@ -34,8 +34,8 @@ isr()
 {
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   val_wd_set_ws0(wd_num, 0);
-  val_print(ACS_PRINT_DEBUG, "\n       Received WS0 interrupt            ", 0);
-  val_set_status(index, RESULT_PASS(TEST_NUM, 01));
+  val_print(ACS_PRINT_DEBUG, "\n       Received WS0 interrupt                ", 0);
+  val_set_status(index, RESULT_PASS(TEST_NUM, 1));
   val_gic_end_of_interrupt(int_id);
 }
 
@@ -52,7 +52,7 @@ payload()
 
   if (wd_num == 0) {
       val_print(ACS_PRINT_DEBUG, "\n       No Watchdogs reported          %d  ", wd_num);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 01));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 1));
       return;
   }
 
@@ -71,7 +71,7 @@ payload()
 
       if (val_gic_install_isr(int_id, isr)) {
           val_print(ACS_PRINT_ERR, "\n       GIC Install Handler Failed...", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 01));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 1));
           return;
       }
 
@@ -84,7 +84,7 @@ payload()
       status = val_wd_set_ws0(wd_num, timer_expire_ticks);
       if (status) {
           val_print(ACS_PRINT_ERR, "\n       Setting watchdof timeout failed", 0);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           return;
       }
 
@@ -92,7 +92,7 @@ payload()
 
       if (timeout == 0) {
           val_print(ACS_PRINT_ERR, "\n       WS0 Interrupt not received on %d   ", int_id);
-          val_set_status(index, RESULT_FAIL(TEST_NUM, 02));
+          val_set_status(index, RESULT_FAIL(TEST_NUM, 2));
           return;
       }
 
@@ -100,7 +100,7 @@ payload()
 
   if(!ns_wdg) {
       val_print(ACS_PRINT_WARN, "\n       No non-secure Watchdogs reported", 0);
-      val_set_status(index, RESULT_SKIP(TEST_NUM, 03));
+      val_set_status(index, RESULT_SKIP(TEST_NUM, 3));
       return;
   }
 
diff --git a/uefi_app/BsaAcs.h b/uefi_app/BsaAcs.h
index 35c1507a..4ae22f76 100755
--- a/uefi_app/BsaAcs.h
+++ b/uefi_app/BsaAcs.h
@@ -20,8 +20,8 @@
 
 
 
-  #define BSA_ACS_MAJOR_VER  0
-  #define BSA_ACS_MINOR_VER  9
+  #define BSA_ACS_MAJOR_VER  1
+  #define BSA_ACS_MINOR_VER  0
 
   #define G_PRINT_LEVEL ACS_PRINT_TEST
 
diff --git a/uefi_app/BsaAcs.inf b/uefi_app/BsaAcs.inf
index a9b3050c..582b3dcc 100644
--- a/uefi_app/BsaAcs.inf
+++ b/uefi_app/BsaAcs.inf
@@ -72,6 +72,8 @@
   ../test_pool/gic/operating_system/test_os_v2m004.c
   ../test_pool/gic/operating_system/test_os_its001.c
   ../test_pool/gic/operating_system/test_os_its002.c
+  ../test_pool/gic/operating_system/test_os_its003.c
+  ../test_pool/gic/operating_system/test_os_its004.c
   ../test_pool/gic/hypervisor/test_hyp_g001.c
   ../test_pool/timer/operating_system/test_os_t001.c
   ../test_pool/timer/operating_system/test_os_t002.c
@@ -147,6 +149,9 @@
   ../test_pool/exerciser/operating_system/test_os_e010.c
   ../test_pool/exerciser/operating_system/test_os_e011.c
   ../test_pool/exerciser/operating_system/test_os_e012.c
+  ../test_pool/exerciser/operating_system/test_os_e013.c
+  ../test_pool/exerciser/operating_system/test_os_e014.c
+  ../test_pool/exerciser/operating_system/test_os_e015.c
 
 [Packages]
   StdLib/StdLib.dec
diff --git a/uefi_app/BsaAcsMain.c b/uefi_app/BsaAcsMain.c
index c828be82..ae73aaab 100644
--- a/uefi_app/BsaAcsMain.c
+++ b/uefi_app/BsaAcsMain.c
@@ -455,10 +455,8 @@ ShellAppMain (
   Print(L"\n      *** Starting Peripheral tests ***  ");
   Status |= val_peripheral_execute_tests(val_pe_get_num(), g_sw_view);
 
-  if (val_wd_get_info(0, WD_INFO_COUNT)) {
-      Print(L"\n      *** Starting Watchdog tests ***  ");
-      Status |= val_wd_execute_tests(val_pe_get_num(), g_sw_view);
-  }
+  Print(L"\n      *** Starting Watchdog tests ***  ");
+  Status |= val_wd_execute_tests(val_pe_get_num(), g_sw_view);
 
   Print(L"\n      *** Starting PCIe tests ***  ");
   Status |= val_pcie_execute_tests(val_pe_get_num(), g_sw_view);
@@ -468,10 +466,10 @@ ShellAppMain (
 
 print_test_status:
   val_print(ACS_PRINT_TEST, "\n     ------------------------------------------------------- \n", 0);
-  val_print(ACS_PRINT_TEST, "     Total Tests run  = %4d;", g_bsa_tests_total);
+  val_print(ACS_PRINT_TEST, "     Total Tests run  = %4d", g_bsa_tests_total);
   val_print(ACS_PRINT_TEST, "  Tests Passed  = %4d", g_bsa_tests_pass);
   val_print(ACS_PRINT_TEST, "  Tests Failed = %4d\n", g_bsa_tests_fail);
-  val_print(ACS_PRINT_TEST, "     --------------------------------------------------------- \n", 0);
+  val_print(ACS_PRINT_TEST, "     ------------------------------------------------------- \n", 0);
 
   freeBsaAcsMem();
 
diff --git a/val/BsaValLib.inf b/val/BsaValLib.inf
index a4d54902..d34788ae 100644
--- a/val/BsaValLib.inf
+++ b/val/BsaValLib.inf
@@ -51,6 +51,7 @@
   sys_arch_src/gic/bsa_exception.c
   sys_arch_src/gic/AArch64/bsa_exception_asm.S
   sys_arch_src/gic/v3/gic_v3.c
+  sys_arch_src/gic/v3/gic_v3_extended.c
   sys_arch_src/gic/v3/AArch64/v3_asm.S
   sys_arch_src/gic/v2/gic_v2.c
   sys_arch_src/pcie/pcie.c
diff --git a/val/include/bsa_acs_exerciser.h b/val/include/bsa_acs_exerciser.h
index 0d7019ca..f6372172 100644
--- a/val/include/bsa_acs_exerciser.h
+++ b/val/include/bsa_acs_exerciser.h
@@ -64,5 +64,8 @@ uint32_t os_e009_entry(void);
 uint32_t os_e010_entry(void);
 uint32_t os_e011_entry(void);
 uint32_t os_e012_entry(void);
+uint32_t os_e013_entry(void);
+uint32_t os_e014_entry(void);
+uint32_t os_e015_entry(void);
 
 #endif
diff --git a/val/include/bsa_acs_gic.h b/val/include/bsa_acs_gic.h
index 7a31ebfb..e086b3e3 100644
--- a/val/include/bsa_acs_gic.h
+++ b/val/include/bsa_acs_gic.h
@@ -41,14 +41,22 @@
 #define GICD_ICPENDR0       0x280
 #define GICD_ICACTIVER0     0x380
 #define GICD_ICFGR          0xC00
-#define GICD_ICFGRE         0x3000
 #define GICD_IROUTER        0x6000
 #define GICD_PIDR2          0xFFE8
 
+#define GICD_ICENABLERE     0x1400
+#define GICD_ICPENDRE0      0x1800
+#define GICD_ICACTIVERE0    0x1C00
+#define GICD_IPRIORITYRE    0x2000
+#define GICD_ICFGRE         0x3000
+#define GICD_IROUTERnE      0x8000
+
 #define GICR_ISENABLER      0x100
 
 #define RD_FRAME_SIZE       0x10000
 
+#define GITS_TRANSLATER     0x10040
+
 #define GICD_ICFGR_INTR_STRIDE          16 /* (32/2) Interrupt per Register */
 #define GICD_ICFGR_INTR_CONFIG1(intid)  ((1+int_id*2) % 32) /* Bit Config[2x+1] for config type level/edge */
 
@@ -109,6 +117,15 @@ val_gic_espi_supported(void);
 uint32_t
 val_gic_max_espi_val(void);
 
+uint32_t
+val_gic_max_eppi_val(void);
+
+uint32_t
+val_gic_is_valid_espi(uint32_t int_id);
+
+uint32_t
+val_gic_is_valid_eppi(uint32_t int_id);
+
 uint32_t os_v2m001_entry(uint32_t num_pe);
 uint32_t os_v2m002_entry(uint32_t num_pe);
 uint32_t os_v2m003_entry(uint32_t num_pe);
@@ -117,5 +134,7 @@ uint32_t os_v2m004_entry(uint32_t num_pe);
 /* ITS tests */
 uint32_t os_its001_entry(uint32_t num_pe);
 uint32_t os_its002_entry(uint32_t num_pe);
+uint32_t os_its003_entry(uint32_t num_pe);
+uint32_t os_its004_entry(uint32_t num_pe);
 
 #endif
diff --git a/val/include/bsa_acs_gic_support.h b/val/include/bsa_acs_gic_support.h
index 90436dfc..11f7a987 100644
--- a/val/include/bsa_acs_gic_support.h
+++ b/val/include/bsa_acs_gic_support.h
@@ -39,6 +39,7 @@ void GicWriteIccIgrpen1(uint64_t write_data);
 void GicWriteIccBpr1(uint64_t write_data);
 void GicWriteIccPmr(uint64_t write_data);
 void GicClearDaif(void);
+void TestExecuteBarrier(void);
 void GicWriteHcr(uint64_t write_data);
 
 
diff --git a/val/include/bsa_acs_pcie.h b/val/include/bsa_acs_pcie.h
index fff337d5..b9d0d6ad 100644
--- a/val/include/bsa_acs_pcie.h
+++ b/val/include/bsa_acs_pcie.h
@@ -195,6 +195,15 @@ val_pcie_get_atomicop_requester_capable(uint32_t bdf);
 uint32_t
 val_pcie_is_cache_present(uint32_t bdf);
 
+uint32_t
+val_pcie_get_max_pasid_width(uint32_t bdf, uint32_t *max_pasid_width);
+
+uint32_t
+val_pcie_get_ecam_index(uint32_t bdf, uint32_t *ecam_index);
+
+uint32_t
+val_is_transaction_pending_set(uint32_t bdf);
+
 uint32_t os_p001_entry(uint32_t num_pe);
 uint32_t os_p002_entry(uint32_t num_pe);
 uint32_t os_p003_entry(uint32_t num_pe);
diff --git a/val/include/bsa_acs_pcie_spec.h b/val/include/bsa_acs_pcie_spec.h
index 3e813191..dbe8acd5 100644
--- a/val/include/bsa_acs_pcie_spec.h
+++ b/val/include/bsa_acs_pcie_spec.h
@@ -155,8 +155,10 @@
 #define SUBBN_SHIFT 16
 
 /* Bus Number reg masks */
+#define PRIBN_MASK  0xff
 #define SECBN_MASK  0xff
 #define SUBBN_MASK  0xff
+#define SECBN_EXTRACT 0xffff00ff
 
 /* Capability header reg shifts */
 #define PCIE_CIDR_SHIFT      0
@@ -186,6 +188,7 @@
 #define ECID_ARICS     0x000E
 #define ECID_ATS       0x000F
 #define ECID_PRI       0x0013
+#define ECID_PASID     0x001B
 
 /* PCI Express capability struct offsets */
 #define CIDR_OFFSET    0
@@ -199,6 +202,7 @@
 #define DCTL2R_OFFSET  28
 #define LCAP2R_OFFSET  0x2C
 #define LCTL2R_OFFSET  0x30
+#define DCTL2R_MASK    0xFFFF
 
 /* ACS Capability Register */
 #define ACS_CTRL_SVE_SHIFT  16
@@ -282,6 +286,7 @@
 
 /* Device Control 2 reg mask */
 #define DCTL2R_AFE_MASK  0x1
+#define DCTL2R_AFE_NORMAL 0xFFDF
 
 /* Device bitmask definitions */
 #define RCiEP    (1 << 0b1001)
@@ -306,4 +311,14 @@
 #define MSI_X_TABLE_BIR_MASK        0x7
 #define MSI_X_ENTRY_SIZE            16 /* Size of Single MSI Entry in MSI Table */
 
+/* PASID Capabilities */
+#define PASID_CAPABILITY_OFFSET     0x4
+#define MAX_PASID_MASK              0x1F00
+#define MAX_PASID_SHIFT             0x8
+
+/* ATS Capabilities */
+#define ATS_CTRL                    0x4
+#define ATS_CACHING_EN              (1 << 31)
+#define ATS_CACHING_DIS             0x7FFFFFFF
+
 #endif
diff --git a/val/include/bsa_acs_peripherals.h b/val/include/bsa_acs_peripherals.h
index 3c4823d5..717689a1 100644
--- a/val/include/bsa_acs_peripherals.h
+++ b/val/include/bsa_acs_peripherals.h
@@ -67,4 +67,10 @@ uint32_t os_d005_entry(uint32_t num_pe);
 #define ARM_SBSA_GENERIC_UART     0xE
 #define COMPATIBLE_GENERIC_16550  0x12
 
+#define USB_TYPE_OHCI             0x1
+#define USB_TYPE_EHCI             0x2
+#define USB_TYPE_XHCI             0x3
+
+#define SATA_TYPE_AHCI            0x1
+
 #endif // __BSA_ACS_PERIPHERAL_H__
diff --git a/val/include/bsa_acs_timer.h b/val/include/bsa_acs_timer.h
index f9482019..d63bebcf 100644
--- a/val/include/bsa_acs_timer.h
+++ b/val/include/bsa_acs_timer.h
@@ -43,6 +43,9 @@
 /* CNTBaseN register offset*/
 #define CNTPCT_LOWER     0x00
 #define CNTPCT_HIGHER    0x04
+#define CNTVCT_LOWER     0x08
+#define CNTVCT_HIGHER    0x0C
+#define CNTBaseN_CNTFRQ  0x10
 #define CNTP_CVAL_LOWER  0x20
 #define CNTP_CVAL_HIGHER 0x24
 #define CNTP_TVAL        0x28
diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h
index b2b1ec74..341face0 100644
--- a/val/include/pal_interface.h
+++ b/val/include/pal_interface.h
@@ -383,7 +383,7 @@ typedef struct {
 void pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *iovirt);
 uint32_t pal_iovirt_check_unique_ctx_intid(uint64_t smmu_block);
 uint32_t pal_iovirt_unique_rid_strid_map(uint64_t rc_block);
-uint64_t pal_iovirt_get_rc_smmu_base(IOVIRT_INFO_TABLE *iovirt, uint32_t rc_seg_num);
+uint64_t pal_iovirt_get_rc_smmu_base(IOVIRT_INFO_TABLE *iovirt, uint32_t rc_seg_num, uint32_t rid);
 
 /**
   @brief SMMU Info Table
@@ -462,8 +462,12 @@ typedef struct {
   uint32_t         max_pasids;
   uint32_t         baud_rate;
   uint32_t         interface_type;
+  uint32_t         platform_type;
 }PERIPHERAL_INFO_BLOCK;
 
+#define PLATFORM_TYPE_ACPI   0x0
+#define PLATFORM_TYPE_DT     0x1
+
 /**
   @brief Peripheral Info Structure
 **/
@@ -638,6 +642,8 @@ void     pal_pe_data_cache_ops_by_va(uint64_t addr, uint32_t type);
 #define MAX_ARRAY_SIZE 32
 #define TEST_REG_COUNT 10
 #define TEST_DDR_REGION_CNT 16
+#define RID_VALID      1
+#define RID_NOT_VALID  0
 
 #define EXERCISER_ID   0xED0113B5 //device id + vendor id
 
@@ -675,6 +681,7 @@ typedef enum {
 typedef enum {
     TXN_REQ_ID     = 0x0,
     TXN_ADDR_TYPE  = 0x1,
+    TXN_REQ_ID_VALID    = 0x2,
 } EXERCISER_TXN_ATTR;
 
 typedef enum {
diff --git a/val/include/val_interface.h b/val/include/val_interface.h
index 24f97da6..e82eaad6 100644
--- a/val/include/val_interface.h
+++ b/val/include/val_interface.h
@@ -41,7 +41,8 @@
 void val_allocate_shared_mem(void);
 void val_free_shared_mem(void);
 void val_print(uint32_t level, char8_t *string, uint64_t data);
-void val_print_raw(uint32_t level, char8_t *string, uint64_t data);
+void val_print_raw(uint64_t uart_addr, uint32_t level, char8_t *string,
+                                                                uint64_t data);
 void val_set_test_data(uint32_t index, uint64_t addr, uint64_t test_data);
 void val_get_test_data(uint32_t index, uint64_t *data0, uint64_t *data1);
 uint32_t val_strncmp(char8_t *str1, char8_t *str2, uint32_t len);
@@ -99,6 +100,7 @@ uint32_t val_gic_get_intr_trigger_type(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e
 uint32_t val_gic_get_espi_intr_trigger_type(uint32_t int_id,
                                                           INTR_TRIGGER_INFO_TYPE_e *trigger_type);
 uint32_t val_gic_its_configure(void);
+uint32_t val_gic_its_get_base(uint32_t its_id, uint64_t *its_base);
 uint32_t val_gic_request_msi(uint32_t bdf, uint32_t device_id, uint32_t its_id,
                              uint32_t int_id, uint32_t msi_index);
 void val_gic_free_msi(uint32_t bdf, uint32_t device_id, uint32_t its_id,
@@ -252,7 +254,7 @@ typedef enum {
 
 void     val_iovirt_create_info_table(uint64_t *iovirt_info_table);
 void     val_iovirt_free_info_table(void);
-uint32_t val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num);
+uint32_t val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num, uint32_t rid);
 uint32_t val_smmu_execute_tests(uint32_t num_pe, uint32_t *g_sw_view);
 uint64_t val_smmu_get_info(SMMU_INFO_e, uint32_t index);
 
@@ -304,11 +306,15 @@ typedef enum {
   USB_FLAGS,
   USB_GSIV,
   USB_BDF,
+  USB_INTERFACE_TYPE,
+  USB_PLATFORM_TYPE,
   SATA_BASE0,
   SATA_BASE1,
   SATA_FLAGS,
   SATA_GSIV,
   SATA_BDF,
+  SATA_INTERFACE_TYPE,
+  SATA_PLATFORM_TYPE,
   UART_BASE0,
   UART_BASE1,
   UART_GSIV,
diff --git a/val/src/AArch64/GicSupport.S b/val/src/AArch64/GicSupport.S
index 36dcfb5e..481499fb 100644
--- a/val/src/AArch64/GicSupport.S
+++ b/val/src/AArch64/GicSupport.S
@@ -27,6 +27,7 @@ GCC_ASM_EXPORT(GicWriteIccBpr1)
 GCC_ASM_EXPORT(GicWriteIccPmr)
 GCC_ASM_EXPORT(GicClearDaif)
 GCC_ASM_EXPORT(GicWriteHcr)
+GCC_ASM_EXPORT(TestExecuteBarrier)
 
 ASM_PFX(GicReadIchHcr):
   //mrs_s   x0, ich_hcr_el2
@@ -71,4 +72,9 @@ ASM_PFX(GicWriteHcr):
   msr   hcr_el2, x0
   ret
 
+ASM_PFX(TestExecuteBarrier):
+  dsb sy
+  isb
+  ret
+
 ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/val/src/acs_dma.c b/val/src/acs_dma.c
index 23273684..0960ce28 100644
--- a/val/src/acs_dma.c
+++ b/val/src/acs_dma.c
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2018,2021, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -24,9 +24,12 @@ DMA_INFO_TABLE  *g_dma_info_table;
 /**
   @brief  Allocate memory which is to be used for DMA
 
-  @param  None
+  @param  *buffer    - Address of the Memory Bufffer to be returned
+  @param  size       - Memory size to be allocated
+  @param  dev_index  - DMA Controller Index
+  @param  flags      - Flags to determine if DMA is Coherent
 
-  @result None
+  @result Start Address of the Allocated memory
 **/
 addr_t
 val_dma_mem_alloc(void **buffer, uint32_t size, uint32_t dev_index, uint32_t flags)
@@ -42,7 +45,11 @@ val_dma_mem_alloc(void **buffer, uint32_t size, uint32_t dev_index, uint32_t fla
 /**
   @brief  free memory which is to used for DMA
 
-  @param  None
+  @param  *buffer    - Address of the Memory Bufffer to free
+  @param  mem_dma    - DMA handle of the memory to free
+  @param  size       - Memory size to be allocated
+  @param  dev_index  - DMA Controller Index
+  @param  flags      - Flags to determine if DMA is Coherent
 
   @result None
 **/
@@ -57,12 +64,28 @@ val_dma_mem_free(void *buffer, dma_addr_t mem_dma, uint32_t size, uint32_t dev_i
 
 }
 
+/**
+  @brief  free memory of DMA info table
+
+  @param  None
+
+  @result None
+**/
 void
 val_dma_free_info_table(void)
 {
   pal_mem_free((void *)g_dma_info_table);
 }
 
+/**
+  @brief  Perform the DMA operation for the device
+
+  @param  *Buffer - Memory Buffer
+  @param  length - Length of the buffer
+  @param  ctrl_index - Index of DMA Controller
+
+  @result None
+**/
 uint32_t
 val_dma_start_from_device(void *buffer, uint32_t length, uint32_t ctrl_index)
 {
@@ -100,7 +123,13 @@ val_dma_start_to_device(void *buffer, uint32_t length, uint32_t ctrl_index)
 }
 
 
-/* Pre-requisite - val_peripheral_create_info_table */
+/**
+  @brief  API to keep all DMA Controller related information.
+
+  @param  dma_info_ptr - DMA Info table pointer
+
+  @return None
+**/
 void
 val_dma_create_info_table(uint64_t *dma_info_ptr)
 {
@@ -189,6 +218,15 @@ val_dma_device_get_dma_addr(uint32_t ctrl_index, void *dma_addr, uint32_t *cpu_l
 
 }
 
+/**
+  @brief  Get Memory attributes of the Memory Buffer
+
+  @param  buf - Memory buffer for which we want to get the attributes
+  @param  *attr - Memory attributes to return
+  @param  *sh - Sharability
+
+  @result Status
+**/
 int
 val_dma_mem_get_attrs(void *buf, uint32_t *attr, uint32_t *sh)
 {
diff --git a/val/src/acs_exerciser.c b/val/src/acs_exerciser.c
index 7d96b6ea..448f516f 100644
--- a/val/src/acs_exerciser.c
+++ b/val/src/acs_exerciser.c
@@ -51,7 +51,7 @@ void val_exerciser_create_info_table(void)
       if (val_pcie_read_cfg(Bdf, TYPE01_VIDR, &reg_value) == PCIE_NO_MAPPING)
       {
           /* Return if there is a bdf mapping issue */
-          val_print(ACS_PRINT_ERR, "\n      BDF 0x%x mapping issue", Bdf);
+          val_print(ACS_PRINT_ERR, "\n       BDF 0x%x mapping issue", Bdf);
           return;
       }
 
@@ -101,6 +101,11 @@ uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1,
     return pal_exerciser_set_param(type, value1, value2, bdf, ecam);
 }
 
+/**
+  @brief   This API returns the bdf of the PCIe Stimulus generation hardware
+  @param   instance  - Stimulus hardware instance number
+  @return  bdf       - BDF Number of the instance
+**/
 uint32_t val_exerciser_get_bdf(uint32_t instance)
 {
     return g_exercier_info_table.e_info[instance].bdf;
@@ -180,7 +185,7 @@ uint32_t val_exerciser_init(uint32_t instance)
       g_exercier_info_table.e_info[instance].initialized = 1;
   }
   else
-           val_print(ACS_PRINT_DEBUG, "\n       Already initialized %d",
+           val_print(ACS_PRINT_INFO, "\n       Already initialized %2d",
                                                                     instance);
   return 0;
 }
@@ -218,6 +223,7 @@ uint32_t val_exerciser_get_data(EXERCISER_DATA_TYPE type, exerciser_data_t *data
 /**
   @brief   This API executes all the Exerciser tests sequentially
            1. Caller       -  Application layer.
+  @param   g_sw_view - Keeps the information about which view tests to be run
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -230,7 +236,7 @@ val_exerciser_execute_tests(uint32_t *g_sw_view)
 
   for (i = 0; i < MAX_TEST_SKIP_NUM; i++){
       if (g_skip_test_num[i] == ACS_EXERCISER_TEST_NUM_BASE) {
-          val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all Exerciser tests \n", 0);
+          val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all Exerciser tests \n", 0);
           return ACS_STATUS_SKIP;
       }
   }
@@ -245,7 +251,8 @@ val_exerciser_execute_tests(uint32_t *g_sw_view)
   num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
 
   if (num_instances == 0) {
-      val_print(ACS_PRINT_WARN, "\n     No Exerciser Devices Found, Skipping tests...\n", 0);
+      val_print(ACS_PRINT_WARN, "\n       No Exerciser Devices Found, "
+                                    "Skipping tests...\n", 0);
       return ACS_STATUS_SKIP;
   }
 
@@ -266,14 +273,18 @@ val_exerciser_execute_tests(uint32_t *g_sw_view)
      if (!pal_target_is_dt()) {
        status |= os_e011_entry();
        status |= os_e012_entry();
+       status |= os_e013_entry();
      }
 
+     status |= os_e014_entry();
+     status |= os_e015_entry();
+
   }
 
   if (status != ACS_STATUS_PASS)
     val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-    val_print(ACS_PRINT_TEST, "\n      All Exerciser tests passed!! \n", 0);
+    val_print(ACS_PRINT_TEST, "\n       All Exerciser tests passed!! \n", 0);
 
   return status;
 }
diff --git a/val/src/acs_gic.c b/val/src/acs_gic.c
index f825c9e1..9f778147 100644
--- a/val/src/acs_gic.c
+++ b/val/src/acs_gic.c
@@ -28,6 +28,7 @@ GIC_INFO_TABLE  *g_gic_info_table;
            1. Caller       -  Application layer.
            2. Prerequisite -  val_gic_create_info_table()
   @param   num_pe - the number of PE to run these tests on.
+  @param   g_sw_view - Keeps the information about which view tests to be run
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -39,19 +40,24 @@ val_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i=0 ; i<MAX_TEST_SKIP_NUM ; i++){
       if (g_skip_test_num[i] == ACS_GIC_TEST_NUM_BASE) {
-          val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all GIC tests \n", 0);
+          val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all GIC tests \n", 0);
           return ACS_STATUS_SKIP;
       }
   }
 
-  status = ACS_STATUS_PASS;
+  status      = ACS_STATUS_PASS;
+  gic_version = val_gic_get_info(GIC_INFO_VERSION);
 
   if (g_sw_view[G_SW_OS]) {
       val_print(ACS_PRINT_ERR, "\nOperating System View:\n", 0);
       status |= os_g001_entry(num_pe);
       status |= os_g002_entry(num_pe);
-      status |= os_g003_entry(num_pe);
-      status |= os_g004_entry(num_pe);
+
+      if (gic_version > 2) {
+        status |= os_g003_entry(num_pe);
+        status |= os_g004_entry(num_pe);
+      }
+
       status |= os_g005_entry(num_pe);
       status |= os_g006_entry(num_pe);
   }
@@ -62,16 +68,15 @@ val_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   }
 
   /* Run GICv2m only if GIC Version is v2m. */
-  gic_version   = val_gic_get_info(GIC_INFO_VERSION);
   num_msi_frame = val_gic_get_info(GIC_INFO_NUM_MSI_FRAME);
 
   if ((gic_version != 2) || (num_msi_frame == 0)) {
-      val_print(ACS_PRINT_TEST, "\n      No GICv2m, Skipping all GICv2m tests \n", 0);
+      val_print(ACS_PRINT_TEST, "\n       No GICv2m, Skipping all GICv2m tests \n", 0);
       goto its_test;
   }
 
   if (val_gic_v2m_parse_info()) {
-      val_print(ACS_PRINT_TEST, "\n     GICv2m info mismatch, Skipping all GICv2m tests \n", 0);
+      val_print(ACS_PRINT_TEST, "\n       GICv2m info mismatch, Skipping all GICv2m tests \n", 0);
       goto its_test;
   }
 
@@ -86,7 +91,7 @@ val_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
 its_test:
   if ((val_gic_get_info(GIC_INFO_NUM_ITS) == 0) || (pal_target_is_dt())) {
-      val_print(ACS_PRINT_TEST, "\n      No ITS, Skipping all ITS tests \n", 0);
+      val_print(ACS_PRINT_DEBUG, "\n       No ITS, Skipping all ITS tests \n", 0);
       goto test_done;
   }
   val_print(ACS_PRINT_ERR, "\n      *** Starting ITS tests ***\n", 0);
@@ -94,13 +99,15 @@ val_gic_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
       val_print(ACS_PRINT_ERR, "\nOperating System View:\n", 0);
       status |= os_its001_entry(num_pe);
       status |= os_its002_entry(num_pe);
+      status |= os_its003_entry(num_pe);
+      status |= os_its004_entry(num_pe);
   }
 
 test_done:
   if (status != ACS_STATUS_PASS)
     val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-    val_print(ACS_PRINT_TEST, "\n     All GIC tests Passed!! \n", 0);
+    val_print(ACS_PRINT_TEST, "\n       All GIC tests Passed!! \n", 0);
 
   return status;
 
@@ -123,6 +130,7 @@ val_gic_create_info_table(uint64_t *gic_info_table)
       val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL \n", 0);
       return ACS_STATUS_ERR;
   }
+  val_print(ACS_PRINT_INFO, " Creating GIC INFO table\n", 0);
 
   g_gic_info_table = (GIC_INFO_TABLE *)gic_info_table;
 
@@ -141,8 +149,15 @@ val_gic_create_info_table(uint64_t *gic_info_table)
   return ACS_STATUS_PASS;
 }
 
+/**
+  @brief   This API frees the memory assigned for gic info table
+           1. Caller       -  Application Layer
+           2. Prerequisite -  val_gic_create_info_table
+  @param   None
+  @return  None
+**/
 void
-val_gic_free_info_table()
+val_gic_free_info_table(void)
 {
   pal_mem_free((void *)g_gic_info_table);
 }
@@ -182,7 +197,7 @@ val_get_gicd_base(void)
   @brief   This API returns the base address of the GIC Redistributor for the current PE
            1. Caller       -  Test Suite
            2. Prerequisite -  val_gic_create_info_table
-  @param   None
+  @param   rdbase_len - To Store the Lenght of the Redistributor
   @return  Address of GIC Redistributor
 **/
 addr_t
@@ -344,7 +359,7 @@ val_gic_get_info(uint32_t type)
 uint32_t
 val_get_max_intid(void)
 {
-  return 32 * ((val_mmio_read(val_get_gicd_base() + 0x004) & 0x1F) + 1);
+  return (32 * ((val_mmio_read(val_get_gicd_base() + GICD_TYPER) & 0x1F) + 1));
 }
 
 /**
@@ -402,7 +417,9 @@ void val_gic_clear_interrupt(uint32_t int_id)
     uint32_t reg_offset = int_id / 32;
     uint32_t reg_shift  = int_id % 32;
 
-    if ((int_id > 31) && (int_id < 1020)) {
+    if (val_gic_is_valid_espi(int_id))
+      val_bsa_gic_clear_espi_interrupt(int_id);
+    else if ((int_id > 31) && (int_id < 1020)) {
         val_mmio_write(val_get_gicd_base() + GICD_ICPENDR0 + (4 * reg_offset), (1 << reg_shift));
         val_mmio_write(val_get_gicd_base() + GICD_ICACTIVER0 + (4 * reg_offset), (1 << reg_shift));
     }
@@ -430,6 +447,7 @@ void val_gic_cpuif_init(void)
            1. Caller       -  Test Suite
            2. Prerequisite -  val_gic_create_info_table
   @param   int_id Interrupt ID
+  @param   trigger_type to Store the Interrupt Trigger type
   @return  Status
 **/
 uint32_t val_gic_get_intr_trigger_type(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e *trigger_type)
@@ -461,6 +479,7 @@ uint32_t val_gic_get_intr_trigger_type(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e
            1. Caller       -  Test Suite
            2. Prerequisite -  val_gic_create_info_table
   @param   int_id Interrupt ID
+  @param   trigger_type to Store the Interrupt Trigger type
   @return  Status
 **/
 uint32_t val_gic_get_espi_intr_trigger_type(uint32_t int_id,
@@ -501,11 +520,13 @@ void val_gic_set_intr_trigger(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e trigger_
 {
   uint32_t status;
 
-  val_print(ACS_PRINT_DEBUG, "\n    Setting Trigger type as %d  ", trigger_type);
+  val_print(ACS_PRINT_DEBUG, "\n       Setting Trigger type as %d  ",
+                                                                trigger_type);
   status = pal_gic_set_intr_trigger(int_id, trigger_type);
 
   if (status)
-    val_print(ACS_PRINT_ERR, "\n    Error Could Not Configure Trigger Type", 0);
+    val_print(ACS_PRINT_ERR, "\n       Error Could Not Configure Trigger Type",
+                                                                            0);
 }
 
 /**
@@ -539,3 +560,41 @@ val_gic_max_espi_val(void)
   val_print(ACS_PRINT_INFO, "\n    max ESPI value %d  ", max_espi_val);
   return max_espi_val;
 }
+
+/**
+  @brief   This API returns max extended PPI interrupt value
+  @param   None
+  @return  max extended PPI int value
+**/
+uint32_t
+val_gic_max_eppi_val(void)
+{
+  uint32_t max_eppi_val;
+
+  max_eppi_val = val_bsa_gic_max_eppi_val();
+
+  val_print(ACS_PRINT_INFO, "\n    max EPPI value %d  ", max_eppi_val);
+  return max_eppi_val;
+}
+
+/**
+  @brief  API used to check whether int_id is a espi interrupt
+  @param  interrupt
+  @return 1: espi interrupt, 0: non-espi interrupt
+**/
+uint32_t
+val_gic_is_valid_espi(uint32_t int_id)
+{
+  return val_bsa_gic_check_espi_interrupt(int_id);
+}
+
+/**
+  @brief  API used to check whether int_id is a Extended PPI
+  @param  interrupt
+  @return 1: eppi interrupt, 0: non-eppi interrupt
+**/
+uint32_t
+val_gic_is_valid_eppi(uint32_t int_id)
+{
+  return val_bsa_gic_check_eppi_interrupt(int_id);
+}
diff --git a/val/src/acs_gic_support.c b/val/src/acs_gic_support.c
index 5e7b2ed3..6c0214a1 100644
--- a/val/src/acs_gic_support.c
+++ b/val/src/acs_gic_support.c
@@ -94,6 +94,13 @@ val_gic_reg_write(uint32_t reg_id, uint64_t write_data)
 }
 #endif
 
+/**
+  @brief   This function checks if Interrupt ID is a valid LPI or not
+           1. Caller       -  Test Suite
+           2. Prerequisite -  val_gic_create_info_table
+  @param   int_id Interrupt ID to check
+  @return  1 - If Valid LPI, 0 - Otherwise
+**/
 uint32_t
 val_gic_is_valid_lpi(uint32_t int_id)
 {
@@ -126,7 +133,8 @@ val_gic_install_isr(uint32_t int_id, void (*isr)(void))
   uint32_t      reg_offset = int_id / 32;
   uint32_t      reg_shift  = int_id % 32;
 
-  if (((int_id > val_get_max_intid()) && (!val_gic_is_valid_lpi(int_id))) || (int_id == 0)) {
+  if (((int_id > val_get_max_intid()) && (!val_gic_is_valid_lpi(int_id)) &&
+      (!val_gic_is_valid_espi(int_id)) && (!val_gic_is_valid_eppi(int_id))) || (int_id == 0)) {
       val_print(ACS_PRINT_ERR, "\n       Invalid Interrupt ID number 0x%x ", int_id);
       return ACS_STATUS_ERR;
   }
@@ -134,16 +142,16 @@ val_gic_install_isr(uint32_t int_id, void (*isr)(void))
 
   if (pal_target_is_dt())
       return val_gic_bsa_install_isr(int_id, isr);
-  else
+  else {
       ret_val = pal_gic_install_isr(int_id, isr);
-
 #ifndef TARGET_LINUX
-  if (int_id > 31 && int_id < 1024) {
-      /**** UEFI GIC code is not enabling interrupt in the Distributor ***/
-      /**** So, do this here as a fail-safe. Remove if PAL guarantees this ***/
-      val_mmio_write(val_get_gicd_base() + GICD_ISENABLER + (4 * reg_offset), 1 << reg_shift);
-  }
+      if (int_id > 31 && int_id < 1024) {
+          /**** UEFI GIC code is not enabling interrupt in the Distributor ***/
+          /**** So, do this here as a fail-safe. Remove if PAL guarantees this ***/
+          val_mmio_write(val_get_gicd_base() + GICD_ISENABLER + (4 * reg_offset), 1 << reg_shift);
+      }
 #endif
+  }
 
   return ret_val;
 }
@@ -189,6 +197,13 @@ uint32_t val_gic_end_of_interrupt(uint32_t int_id)
   return 0;
 }
 
+/**
+  @brief   This function gets list of ITS in the system and ITS initialization
+           1. Caller       -  Application Layer
+           2. Prerequisite -  val_gic_create_info_table
+  @param   None
+  @return  Status
+**/
 uint32_t val_gic_its_configure()
 {
   uint32_t Status;
@@ -204,7 +219,8 @@ uint32_t val_gic_its_configure()
   /* Allocate memory to store ITS info */
   g_gic_its_info = (GIC_ITS_INFO *) val_memory_alloc(1024);
   if (!g_gic_its_info) {
-      val_print(ACS_PRINT_ERR, "GIC : ITS table memory allocation failed\n", 0);
+      val_print(ACS_PRINT_ERR, "  ITS Configure: memory allocation failed\n",
+                                                                          0);
       return ACS_STATUS_ERR;
   }
 
@@ -236,13 +252,14 @@ uint32_t val_gic_its_configure()
 
   /* Return if no ITS */
   if (g_gic_its_info->GicNumIts == 0) {
-    val_print(ACS_PRINT_DEBUG, "\n      ITS Configure : No ITS Found", 0);
+    val_print(ACS_PRINT_DEBUG, "  ITS Configure: No ITS Found\n", 0);
     goto its_fail;
   }
 
   /* Base Address Check. */
   if ((g_gic_its_info->GicRdBase == 0) || (g_gic_its_info->GicDBase == 0)) {
-    val_print(ACS_PRINT_DEBUG, "\n      ITS Configure : Could not get GICD/GICRD Base", 0);
+    val_print(ACS_PRINT_DEBUG, "  ITS Configure: GICD/GICRD Base addr failed\n",
+                                                                            0);
     goto its_fail;
   }
 
@@ -250,11 +267,11 @@ uint32_t val_gic_its_configure()
       && val_its_gicr_lpi_support(g_gic_its_info->GicRdBase)) {
     Status = val_its_init();
     if ((Status)) {
-      val_print(ACS_PRINT_DEBUG, "\n      ITS Configure : val_its_init failed", 0);
+      val_print(ACS_PRINT_DEBUG, "  ITS Configure: its_init failed\n", 0);
       goto its_fail;
     }
   } else {
-    val_print(ACS_PRINT_DEBUG, "\n      LPIs not supported in the system", 0);
+    val_print(ACS_PRINT_DEBUG, "  ITS Configure: LPI unsupported\n", 0);
     goto its_fail;
   }
 
@@ -262,13 +279,20 @@ uint32_t val_gic_its_configure()
 
 its_fail:
 
-  val_print(ACS_PRINT_DEBUG, "\n      GIC ITS Initialization Failed", 0);
-  val_print(ACS_PRINT_DEBUG, "\n      LPI Interrupt related test may not pass", 0);
+  val_print(ACS_PRINT_DEBUG, "  ITS Init failed: ", 0);
+  val_print(ACS_PRINT_DEBUG, "LPI Interrupt related test may not pass\n", 0);
   val_memory_free((void *)g_gic_its_info);
 
   return ACS_STATUS_ERR;
 }
 
+/**
+  @brief   This function gets ITS Index in g_gic_its_info for its_id
+           1. Caller       -  VAL Layer
+           2. Prerequisite -  val_gic_its_configure
+  @param   its_id ID of the ITS Block
+  @return  Index in ITS Info Block
+**/
 uint32_t get_its_index(uint32_t its_id)
 {
   uint32_t  index;
@@ -281,6 +305,14 @@ uint32_t get_its_index(uint32_t its_id)
   return ACS_INVALID_INDEX;
 }
 
+/**
+  @brief   This function clear msi-x table in PCIe config space
+           1. Caller       -  val_its_clear_lpi_map
+           2. Prerequisite -  val_gic_its_configure
+  @param   bdf BDF of the device
+  @param   msi_index MSI Index in MSI-X table in Config space
+  @return  None
+**/
 void clear_msi_x_table(uint32_t bdf, uint32_t msi_index)
 {
 
@@ -307,6 +339,16 @@ void clear_msi_x_table(uint32_t bdf, uint32_t msi_index)
   val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_MVC_OFFSET, 0x1);
 }
 
+/**
+  @brief   This function fills msi-x table in PCIe config space
+           1. Caller       -  val_its_create_lpi_map
+           2. Prerequisite -  val_gic_its_configure
+  @param   bdf BDF of the device
+  @param   msi_index MSI Index in MSI-X table in Config space
+  @param   msi_addr MSI Address to be programmed
+  @param   msi_data MSI Data to be programmed
+  @return  Status
+**/
 uint32_t fill_msi_x_table(uint32_t bdf, uint32_t msi_index, uint32_t msi_addr, uint32_t msi_data)
 {
 
@@ -406,7 +448,7 @@ uint32_t val_gic_request_msi(uint32_t bdf, uint32_t device_id, uint32_t its_id,
 
   val_its_create_lpi_map(its_index, device_id, int_id, LPI_PRIORITY1);
 
-  msi_addr = val_its_get_translator_addr(its_index);
+  msi_addr = val_its_get_translater_addr(its_index);
   msi_data = int_id;
 
 
@@ -414,3 +456,29 @@ uint32_t val_gic_request_msi(uint32_t bdf, uint32_t device_id, uint32_t its_id,
 
   return status;
 }
+
+/**
+  @brief   This function gets the ITS Base for an ITS block with its_id
+           1. Caller       -  Validation layer
+           2. Prerequisite -  val_gic_its_configure
+  @param   its_id ITS Block ID
+  @param   *its_base Stores the ITS Base
+  @return  Status
+**/
+uint32_t val_gic_its_get_base(uint32_t its_id, uint64_t *its_base)
+{
+  uint32_t its_index;
+
+   if ((g_gic_its_info == NULL) || (g_gic_its_info->GicNumIts == 0))
+    return ACS_STATUS_ERR;
+
+  its_index = get_its_index(its_id);
+
+  if (its_index >= g_gic_its_info->GicNumIts) {
+    val_print(ACS_PRINT_ERR, "\n       Could not find ITS ID [%x]", its_id);
+    return ACS_STATUS_ERR;
+  }
+
+  *its_base = g_gic_its_info->GicIts[its_index].Base;
+  return 0;
+}
diff --git a/val/src/acs_gic_v2m.c b/val/src/acs_gic_v2m.c
index 81d588a1..aa676e2c 100644
--- a/val/src/acs_gic_v2m.c
+++ b/val/src/acs_gic_v2m.c
@@ -24,6 +24,13 @@
 extern GIC_INFO_TABLE * g_gic_info_table;
 GICv2m_MSI_FRAME_INFO *g_v2m_msi_info;
 
+/**
+  @brief   This function parses the V2M MSI Information from gic info table
+           1. Caller       -  Validation Layer
+           2. Prerequisite -  val_gic_create_info_table
+  @param   None
+  @return  Status
+**/
 uint32_t val_gic_v2m_parse_info(void)
 {
 
@@ -38,7 +45,7 @@ uint32_t val_gic_v2m_parse_info(void)
   /* Allocate memory to store MSI Frame info */
   g_v2m_msi_info = (GICv2m_MSI_FRAME_INFO *) val_memory_alloc(1024);
   if (!g_v2m_msi_info) {
-      val_print(ACS_PRINT_DEBUG, "\n      GICv2m : MSI Frame Info Failed.", 0);
+      val_print(ACS_PRINT_DEBUG, "\n       GICv2m : MSI Frame Info Failed.", 0);
       return ACS_STATUS_SKIP;
   }
 
@@ -61,6 +68,14 @@ uint32_t val_gic_v2m_parse_info(void)
   return 0;
 }
 
+/**
+  @brief   This function gets the V2M MSI Information for Frame instance
+           1. Caller       -  Test Suite
+           2. Prerequisite -  val_gic_create_info_table
+  @param   type Type of information we want to get
+  @param   instance v2m MSI Frame Instance number
+  @return  Status
+**/
 uint64_t val_gic_v2m_get_info(V2M_MSI_INFO_e type, uint32_t instance)
 {
 
diff --git a/val/src/acs_iovirt.c b/val/src/acs_iovirt.c
index 48c4a532..1c333ccb 100644
--- a/val/src/acs_iovirt.c
+++ b/val/src/acs_iovirt.c
@@ -28,6 +28,7 @@ IOVIRT_INFO_TABLE *g_iovirt_info_table;
            1. Caller       -  val_smmu_get_info
            2. Prerequisite -  val_iovirt_create_info_table
   @param   type   the type of information being requested
+  @param   index  smmu index in iovirt table
   @return  64-bit data
 **/
 uint64_t
@@ -85,6 +86,7 @@ val_iovirt_get_smmu_info(SMMU_INFO_e type, uint32_t index)
            1. Caller       -  Test suite
            2. Prerequisite -  val_iovirt_create_info_table
   @param   type   the type of information being requested
+  @param   index  PCIe RC index in iovirt table
   @return  64-bit data
 **/
 uint64_t
@@ -230,6 +232,13 @@ val_iovirt_get_its_info(
   return ACS_INVALID_INDEX;
 }
 
+/**
+  @brief  Check if given root complex node has unique requestor id to stream id mapping
+
+  @param  rc_index root complex IOVIRT block index
+
+  @return 0 if test fails, 1 if test passes
+**/
 uint32_t
 val_iovirt_unique_rid_strid_map(uint32_t rc_index)
 {
@@ -284,14 +293,14 @@ val_iovirt_get_device_info(uint32_t rid, uint32_t segment, uint32_t *device_id,
                   id =  (rid - (*map).map.input_base) + (*map).map.output_base;
                   oref = (*map).map.output_ref;
                   mapping_found = 1;
+                  break;
               }
           }
-          break;
       }
   }
   if (!mapping_found) {
       val_print(ACS_PRINT_ERR,
-             "\n       GET_DEVICE_ID: RID to Stream/Dev ID mapping not found", 0);
+             "\n       RID to Stream/Dev ID map not found ", 0);
       return ACS_STATUS_ERR;
   }
   /* If output reference node is to ITS group, 'id' is device id */
@@ -363,6 +372,7 @@ val_iovirt_create_info_table(uint64_t *iovirt_info_table)
       val_print(ACS_PRINT_ERR, "\n   Input for Create Info table cannot be NULL \n", 0);
       return;
   }
+  val_print(ACS_PRINT_INFO, " Creating SMMU INFO table\n", 0);
 
   g_iovirt_info_table = (IOVIRT_INFO_TABLE *)iovirt_info_table;
 
@@ -374,6 +384,7 @@ val_iovirt_create_info_table(uint64_t *iovirt_info_table)
 
 #ifndef TARGET_LINUX
   uint32_t instance;
+  val_print(ACS_PRINT_INFO, "  Initializing SMMU\n", 0);
 
   val_smmu_init();
 
@@ -384,6 +395,13 @@ val_iovirt_create_info_table(uint64_t *iovirt_info_table)
 
 }
 
+/**
+  @brief Check if given SMMU node has unique context bank interrupt ids
+
+  @param smmu_index smmu index in iovirt table
+
+  @return 0 if test fail ; 1 if test pass
+**/
 uint32_t
 val_iovirt_check_unique_ctx_intid(uint32_t smmu_index)
 {
@@ -391,6 +409,13 @@ val_iovirt_check_unique_ctx_intid(uint32_t smmu_index)
   return pal_iovirt_check_unique_ctx_intid(smmu_block);
 }
 
+/**
+  @brief This API deletes IO virt info table pointed by g_iovirt_info_table pointer
+
+  @param None
+
+  @return None
+**/
 void
 val_iovirt_free_info_table()
 {
@@ -398,14 +423,22 @@ val_iovirt_free_info_table()
   pal_mem_free((void *)g_iovirt_info_table);
 }
 
+/**
+  @brief This API returns the SMMU index of root complex node requested
+
+  @param rc_seg_num Root complex segment number
+  @param rid Unique requester ID
+
+  @return SMMU index of root complex node requested
+**/
 uint32_t
-val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num)
+val_iovirt_get_rc_smmu_index(uint32_t rc_seg_num, uint32_t rid)
 {
 
   uint32_t num_smmu;
   uint64_t smmu_base;
 
-  smmu_base = pal_iovirt_get_rc_smmu_base(g_iovirt_info_table, rc_seg_num);
+  smmu_base = pal_iovirt_get_rc_smmu_base(g_iovirt_info_table, rc_seg_num, rid);
   if (smmu_base) {
       num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
       while (num_smmu--) {
diff --git a/val/src/acs_memory.c b/val/src/acs_memory.c
index 68863e99..bb20df66 100644
--- a/val/src/acs_memory.c
+++ b/val/src/acs_memory.c
@@ -24,10 +24,11 @@
 MEMORY_INFO_TABLE  *g_memory_info_table;
 
 /**
-  @brief   This API will execute all Memory tests designated for a given compliance level
+  @brief   This API will execute all Memory tests
            1. Caller       -  Application layer.
            2. Prerequisite -  val_memory_create_info_table
   @param   num_pe - the number of PE to run these tests on.
+  @param   g_sw_view - Keeps the information about which view tests to be run
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -38,7 +39,7 @@ val_memory_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i = 0 ; i < MAX_TEST_SKIP_NUM ; i++) {
       if (g_skip_test_num[i] == ACS_MEMORY_MAP_TEST_BASE) {
-        val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all Memory tests \n", 0);
+        val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all Memory tests \n", 0);
         return ACS_STATUS_SKIP;
       }
   }
@@ -60,7 +61,7 @@ val_memory_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (status != ACS_STATUS_PASS)
       val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-      val_print(ACS_PRINT_TEST, "\n      All Memory tests have passed!! \n", 0);
+      val_print(ACS_PRINT_TEST, "\n       All Memory tests have passed!! \n", 0);
 
   return status;
 }
@@ -68,6 +69,10 @@ val_memory_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 #ifndef TARGET_LINUX
 /**
   @brief  Free the memory allocated for the Memory Info table
+
+  @param  None
+
+  @return None
 **/
 void
 val_memory_free_info_table()
@@ -90,6 +95,7 @@ val_memory_create_info_table(uint64_t *memory_info_table)
 {
 
   g_memory_info_table = (MEMORY_INFO_TABLE *)memory_info_table;
+  val_print(ACS_PRINT_INFO, " Creating MEMORY INFO table\n", 0);
 
   pal_memory_create_info_table(g_memory_info_table);
 
@@ -199,6 +205,8 @@ val_memory_get_info(addr_t addr, uint64_t *attr)
            1. Caller       - Test Suite
            2. Prerequisite - val_memory_create_info_table
 
+  @param   None
+
   @return  maximum memory address
 **/
 uint64_t
@@ -218,83 +226,200 @@ val_get_max_memory()
 
 }
 
+/**
+  @brief   Maps the physical memory to virtual address space
+           1. Caller       - Test Suite
+           2. Prerequisite - val_memory_create_info_table
+
+  @param   *addr  Physical address
+  @param   size   Size
+  @param   attr   Attributes
+
+  @return  Mapped Address Starting Pointer
+**/
 addr_t
 val_memory_ioremap(void *addr, uint32_t size, uint64_t attr)
 {
   return (pal_memory_ioremap(addr, size, attr));
 }
 
+/**
+  @brief   Removes the physical memory to virtual address space mapping
+           1. Caller       - Test Suite
+           2. Prerequisite - val_memory_ioremap
+
+  @param   *ptr   Pointer to mapped space
+
+  @return  None
+**/
 void
 val_memory_unmap(void *ptr)
 {
   pal_memory_unmap(ptr);
 }
 
+/**
+  @brief  Allocates requested buffer size in bytes in a contiguous memory
+          and returns the base address of the range.
+
+  @param  Size         allocation size in bytes
+
+  @return pointer to allocated memory
+**/
 void *
 val_memory_alloc(uint32_t size)
 {
   return pal_mem_alloc(size);
 }
 
+/**
+  @brief  Allocates requested buffer size in bytes in a cacheable memory
+          and returns the base address of the range.
+
+  @param  Size         allocation size in bytes
+
+  @return pointer to allocated memory
+**/
 void *
 val_memory_alloc_cacheable(uint32_t bdf, uint32_t size, void **pa)
 {
   return pal_mem_alloc_cacheable(bdf, size, pa);
 }
 
+/**
+  @brief  Free Allocated buffer size by val_memory_alloc.
+
+  @param  *addr   pointer to allocated memory
+
+  @return None
+**/
 void
 val_memory_free(void *addr)
 {
   pal_mem_free(addr);
 }
 
+/**
+  @brief  Compare two buffers of length len
+
+  @param  *src  Source Buffer
+  @param  *dest Destination Buffer
+  @param  len   Length
+
+  @return 0 If contents are same
+  @return 1 Otherwise
+**/
 int
 val_memory_compare(void *src, void *dest, uint32_t len)
 {
   return pal_mem_compare(src, dest, len);
 }
 
+/**
+  @brief  Set buffer with value given in arguments
+
+  @param  *buf  Buffer
+  @param  size  size
+  @param  value value to be written
+
+  @return None
+**/
 void
 val_memory_set(void *buf, uint32_t size, uint8_t value)
 {
   pal_mem_set(buf, size, value);
 }
 
+/**
+  @brief  Free Allocated buffer size by val_memory_alloc_cacheable.
+
+  @param  bdf   BDF Value
+  @param  size  Size
+  @param  *va   pointer to virtual address space
+  @param  *pa   pointer to physical address space
+
+  @return None
+**/
 void
 val_memory_free_cacheable(uint32_t bdf, uint32_t size, void *va, void *pa)
 {
   pal_mem_free_cacheable(bdf, size, va, pa);
 }
 
+/**
+  @brief  Returns the physical address for virtual address space.
+
+  @param  *va   pointer to virtual address space
+
+  @return Pointer to Physical address space
+**/
 void *
 val_memory_virt_to_phys(void *va)
 {
   return pal_mem_virt_to_phys(va);
 }
 
+/**
+  @brief  Returns the virtual address for physical address space.
+
+  @param  *pa   pointer to physical address space
+
+  @return Pointer to virtual address space
+**/
 void *
 val_memory_phys_to_virt(uint64_t pa)
 {
   return pal_mem_phys_to_virt(pa);
 }
 
+/**
+  @brief  Return the address of unpopulated memory of requested
+          instance.
+
+  @param  addr      - Address of the unpopulated memory
+          instance  - Instance of memory
+
+  @return unpopulated Address
+**/
 uint64_t
 val_memory_get_unpopulated_addr(addr_t *addr, uint32_t instance)
 {
   return pal_memory_get_unpopulated_addr(addr, instance);
 }
 
+/**
+  @brief  Return the Memory Page Size.
+
+  @param  None
+
+  @return Size of memory page
+**/
 uint32_t val_memory_page_size(void)
 {
     return pal_mem_page_size();
 }
 
+/**
+  @brief  Allocates number of pages in the memory.
+
+  @param  num_pages  Number of memory pages needed
+
+  @return Address of the allocated space.
+**/
 void *
 val_memory_alloc_pages(uint32_t num_pages)
 {
     return pal_mem_alloc_pages(num_pages);
 }
 
+/**
+  @brief  Free number of pages in the memory.
+
+  @param  *addr      Address from where we need to free
+  @param  num_pages  Number of memory pages needed
+
+  @return None
+**/
 void
 val_memory_free_pages(void *addr, uint32_t num_pages)
 {
diff --git a/val/src/acs_pcie.c b/val/src/acs_pcie.c
index 89a5d06f..65c8a1a1 100644
--- a/val/src/acs_pcie.c
+++ b/val/src/acs_pcie.c
@@ -74,7 +74,8 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data)
   }
 
   if (ecam_base == 0) {
-      val_print(ACS_PRINT_ERR, "\n       Read PCIe_CFG: ECAM Base is zero ", 0);
+      val_print(ACS_PRINT_ERR, "\n       Read PCIe_CFG: ECAM Base is zero   "
+                                                        "   ", 0);
       return PCIE_NO_MAPPING;
   }
 
@@ -240,6 +241,9 @@ uint64_t val_pcie_get_bdf_config_addr(uint32_t bdf)
 /**
   @brief  This API performs the PCI enumeration
 
+  @param  None
+
+  @return None
 **/
 void val_pcie_enumerate(void)
 {
@@ -254,6 +258,8 @@ void val_pcie_enumerate(void)
            1. Caller       -  Application layer.
            2. Prerequisite -  val_pcie_create_info_table()
   @param   num_pe      - the number of PE to run these tests on.
+  @param   g_sw_view - Keeps the information about which view tests to be run
+
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -266,14 +272,14 @@ val_pcie_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i=0 ; i<MAX_TEST_SKIP_NUM ; i++){
       if (g_skip_test_num[i] == ACS_PCIE_TEST_NUM_BASE) {
-          val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all PCIe tests \n", 0);
+          val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all PCIe tests \n", 0);
           return ACS_STATUS_SKIP;
       }
   }
 
   num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
   if (!num_ecam) {
-      val_print(ACS_PRINT_WARN, "\n     *** No ECAM region found, Skipping PCIE tests *** \n", 0);
+      val_print(ACS_PRINT_WARN, "\n      *** No ECAM region found, Skipping PCIE tests *** \n", 0);
       return ACS_STATUS_SKIP;
   }
 
@@ -282,13 +288,15 @@ val_pcie_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
       status |= os_p001_entry(num_pe);
       if (status != ACS_STATUS_PASS) {
-        val_print(ACS_PRINT_WARN, "\n     *** Skipping remaining PCIE tests *** \n", 0);
+        val_print(ACS_PRINT_WARN, "\n      *** Skipping remaining PCIE tests *** \n", 0);
         return status;
       }
   }
 
   if (g_pcie_bdf_table->num_entries == 0) {
-      val_print(ACS_PRINT_WARN, "\n     *** No Valid Devices Found, Skipping PCIE tests *** \n", 0);
+      val_print(ACS_PRINT_WARN,
+                "\n      *** No Valid Devices Found, Skipping PCIE tests *** \n",
+                0);
       return ACS_STATUS_SKIP;
   }
 
@@ -343,11 +351,18 @@ val_pcie_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (status != ACS_STATUS_PASS)
     val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-    val_print(ACS_PRINT_TEST, "\n      All PCIe tests passed!! \n", 0);
+    val_print(ACS_PRINT_TEST, "\n       All PCIe tests passed!! \n", 0);
 
   return status;
 }
 
+/**
+  @brief   This API prints all the PCIe Devices info
+           1. Caller       -  Validation layer.
+           2. Prerequisite -  val_pcie_create_info_table()
+  @param   None
+  @return  None
+**/
 void
 val_pcie_print_device_info(void)
 {
@@ -369,7 +384,7 @@ val_pcie_print_device_info(void)
 
   if (bdf_tbl_ptr->num_entries == 0)
   {
-    val_print(ACS_PRINT_ERR, " PCIE_INFO: BDF Table : No Devices Found\n", 0);
+    val_print(ACS_PRINT_ERR, " PCIE_INFO: No entries in BDF Table\n", 0);
     return;
   }
 
@@ -403,8 +418,8 @@ val_pcie_print_device_info(void)
       ecam_end_bus = val_pcie_get_info(PCIE_INFO_END_BUS, ecam_index);
       tbl_index = 0;
 
-      val_print(ACS_PRINT_INFO, "PCIE_INFO: \nECAM %d:\n", ecam_index);
-      val_print(ACS_PRINT_INFO, "  ECAM Base 0x%llx\n", ecam_base);
+      val_print(ACS_PRINT_INFO, "  ECAM %d:", ecam_index);
+      val_print(ACS_PRINT_INFO, "  Base 0x%llx\n", ecam_base);
 
       while (tbl_index < bdf_tbl_ptr->num_entries)
       {
@@ -463,6 +478,7 @@ val_pcie_create_info_table(uint64_t *pcie_info_table)
       val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL \n", 0);
       return;
   }
+  val_print(ACS_PRINT_INFO, " Creating PCIe INFO table\n", 0);
 
   g_pcie_info_table = (PCIE_INFO_TABLE *)pcie_info_table;
 
@@ -505,7 +521,7 @@ static uint32_t val_pcie_populate_device_rootport(void)
   for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++)
   {
       bdf = bdf_tbl_ptr->device[tbl_index].bdf;
-      val_print(ACS_PRINT_DEBUG, "\n       Device bdf 0x%x", bdf);
+      val_print(ACS_PRINT_DEBUG, "  Dev bdf 0x%x", bdf);
 
       /* Fn returns rp_bdf = 0, if RP not found */
       status = val_pcie_get_rootport(bdf, &rp_bdf);
@@ -513,11 +529,18 @@ static uint32_t val_pcie_populate_device_rootport(void)
         return 1;
 
       bdf_tbl_ptr->device[tbl_index].rp_bdf = rp_bdf;
-      val_print(ACS_PRINT_DEBUG, " RP bdf 0x%x", rp_bdf);
+      val_print(ACS_PRINT_DEBUG, " RP bdf 0x%x\n", rp_bdf);
   }
   return 0;
 }
 
+/**
+  @brief   This API creates the device bdf table from enumeration
+
+  @param   None
+
+  @return  0 if Success
+**/
 uint32_t
 val_pcie_create_device_bdf_table()
 {
@@ -544,7 +567,7 @@ val_pcie_create_device_bdf_table()
   if (!g_pcie_bdf_table)
   {
       val_print(ACS_PRINT_ERR,
-        "\n       PCIe BDF table memory allocation failed          ", 0);
+        "       PCIe BDF table memory allocation failed         \n", 0);
       return 1;
   }
 
@@ -554,7 +577,7 @@ val_pcie_create_device_bdf_table()
   if (num_ecam == 0)
   {
       val_print(ACS_PRINT_ERR,
-        "\n       No ECAMs discovered              ", 0);
+        "       No ECAMs discovered             \n ", 0);
       return 1;
   }
 
@@ -602,17 +625,13 @@ val_pcie_create_device_bdf_table()
 
                       g_pcie_bdf_table->device[g_pcie_bdf_table->num_entries++].bdf = bdf;
                   }
-                  else
-                      /* None of the other Function's exist if zeroth Function doesn't exist */
-                      if (func_index == 0)
-                          break;
               }
           }
       }
   }
 
   val_print(ACS_PRINT_INFO,
-    "\n       Number of valid BDFs is %x\n", g_pcie_bdf_table->num_entries);
+    "  Number of valid BDFs is %x\n", g_pcie_bdf_table->num_entries);
 
   /* Sanity Check : Confirm all EP (normal, integrated) have a rootport */
   if (val_pcie_populate_device_rootport())
@@ -677,6 +696,13 @@ addr_t val_pcie_get_ecam_base(uint32_t bdf)
   return ecam_base;
 }
 
+/**
+  @brief  Returns the BDF Table pointer
+
+  @param  None
+
+  @return BDF Table pointer
+**/
 void *
 val_pcie_bdf_table_ptr()
 {
@@ -685,6 +711,10 @@ val_pcie_bdf_table_ptr()
 
 /**
   @brief  Free the memory allocated for the pcie_info_table
+
+  @param  None
+
+  @return None
 **/
 void
 val_pcie_free_info_table()
@@ -1069,12 +1099,29 @@ val_pcie_get_bdf(uint32_t class_code, uint32_t start_bdf)
   return pal_pcie_get_bdf_wrapper(class_code, start_bdf);
 }
 
+/**
+  @brief  Returns the pointer to device structure
+
+  @param  bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+
+  @return Pointer to device structure for this bdf
+**/
 void *
 val_pci_bdf_to_dev(uint32_t bdf)
 {
   return pal_pci_bdf_to_dev(bdf);
 }
 
+/**
+  @brief  Reads the value at offset for Extended Capability
+
+  @param  bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+  @param  ext_cap_id - Extended Capability ID
+  @param  offset - Offset from the Capability base
+  @param  *val - To return the read value
+
+  @return None
+**/
 void
 val_pcie_read_ext_cap_word(uint32_t bdf, uint32_t ext_cap_id, uint8_t offset, uint16_t *val)
 {
@@ -1165,6 +1212,7 @@ val_pcie_device_port_type(uint32_t bdf)
           cid. cid_offset set to the matching cpability offset w.r.t. zero.
 
   @param  bdf        - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+  @param  cid_type   - PCI capability or Extended PCIe capability
   @param  cid        - Capability ID
   @param  cid_offset - On return, points to cid offset in Function config space
   @return PCIE_CAP_NOT_FOUND, if there was a failure in finding required capability.
@@ -1333,8 +1381,10 @@ val_pcie_clear_urd(uint32_t bdf)
    * Get the PCI Express Capability structure offset and use that
    * offset to write 1b to clear URD bit in Device Status register
    */
-  reg_value = (1 << (DCTLR_DSR_SHIFT + DSR_URD_SHIFT));
   val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base);
+  val_pcie_read_cfg(bdf, pciecs_base + DCTLR_OFFSET, &reg_value);
+  reg_value &= DCTLR_MASK;
+  reg_value |= (1 << (DCTLR_DSR_SHIFT + DSR_URD_SHIFT));
   val_pcie_write_cfg(bdf, pciecs_base + DCTLR_OFFSET, reg_value);
 
 }
@@ -1641,6 +1691,7 @@ uint32_t val_pcie_bitfield_check(uint32_t bdf, uint64_t *bitfield_entry)
   @brief  Returns if a PCIe config register bitfields are as per bsa specification.
 
   @param  bf_info_table - table of registers and their bit-fields for checking
+  @param  num_bitfield_entries - Number of entries
   @return Return  0                 for success
                   ACS_STATUS_SKIP   if no checks are executed
                   <value>           number of failures.
@@ -1892,7 +1943,7 @@ val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf)
 
   dp_type = val_pcie_device_port_type(bdf);
 
-  val_print(ACS_PRINT_DEBUG, "\n       DP type  0x%x ", dp_type);
+  val_print(ACS_PRINT_INFO, " type 0x%x", dp_type);
 
   /* If the device is RP, set its rootport value to same */
   if (dp_type == RP)
@@ -1922,19 +1973,27 @@ val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf)
       sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK);
       dp_type = val_pcie_device_port_type(*rp_bdf);
 
-      if (((dp_type == RP) || (dp_type = iEP_RP)) &&
+      if (((dp_type == RP) || (dp_type == iEP_RP)) &&
           (sec_bus <= PCIE_EXTRACT_BDF_BUS(bdf)) &&
           (sub_bus >= PCIE_EXTRACT_BDF_BUS(bdf)))
           return 0;
   }
 
   /* Return failure */
-  val_print(ACS_PRINT_ERR, "\n       PCIe Hierarchy fail: RP of bdf 0x%x not found", bdf);
+  val_print(ACS_PRINT_ERR, "\n  PCIe Hierarchy fail: RP of bdf 0x%x not found", bdf);
   *rp_bdf = 0;
   return 1;
 
 }
 
+/**
+  @brief  Checks if a device has rootport as a parent and returns bdf if present
+
+  @param  dsf_bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+  @param  *rp_bdf - If RP Found, to store the Root Port BDF
+
+  @return Returns 0 if found, otherwise 1
+**/
 uint8_t
 val_pcie_parent_is_rootport(uint32_t dsf_bdf, uint32_t *rp_bdf)
 {
@@ -1995,7 +2054,7 @@ val_pcie_is_host_bridge(uint32_t bdf)
   @brief  Returns whether a PCIe Function has an Address Translation Cache
 
   @param  bdf        - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
-  @return Returns 0  - if Function doesn't have Addr Translation Cache else 1.
+  @return Returns 1  - if Function doesn't have Addr Translation Cache else 0.
 **/
 uint32_t
 val_pcie_is_cache_present(uint32_t bdf)
@@ -2049,3 +2108,113 @@ val_pcie_link_cap_support(uint32_t bdf)
 
   return 0;
 }
+
+/**
+  @brief  Returns Maximum PASID Width for this bdf
+
+  @param  bdf        - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF
+  @param  *max_pasid_width - Stores the max pasid value
+
+  @return Returns 0 if success
+**/
+uint32_t
+val_pcie_get_max_pasid_width(uint32_t bdf, uint32_t *max_pasid_width)
+{
+  uint32_t status;
+  uint32_t pciecs_base;
+
+  status = val_pcie_find_capability(bdf, PCIE_ECAP, ECID_PASID, &pciecs_base);
+  if (status)
+      return status;
+
+  val_pcie_read_cfg(bdf, pciecs_base + PASID_CAPABILITY_OFFSET, max_pasid_width);
+  *max_pasid_width = (*max_pasid_width & MAX_PASID_MASK) >> MAX_PASID_SHIFT;
+
+  return 0;
+}
+
+/**
+  @brief  Returns the ECAM address of the input PCIe function
+
+  @param  bdf   - Segment/Bus/Dev/Func in PCIE_CREATE_BDF format
+  @param *ecam_index - To store the Ecam Index
+  @return 0 - success, 1 - failure
+**/
+uint32_t
+val_pcie_get_ecam_index(uint32_t bdf, uint32_t *ecam_index)
+{
+
+  uint8_t sec_bus;
+  uint8_t sub_bus;
+  uint16_t seg_num;
+  uint32_t reg_value;
+  uint32_t bus_num;
+  uint32_t index = 0;
+
+  seg_num = PCIE_EXTRACT_BDF_SEG(bdf);
+  bus_num = PCIE_EXTRACT_BDF_BUS(bdf);
+
+  while (index < val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0))
+  {
+      if (seg_num == val_pcie_get_info(PCIE_INFO_SEGMENT, index) &&
+         (bus_num >= val_pcie_get_info(PCIE_INFO_START_BUS, index)) &&
+         (bus_num <= val_pcie_get_info(PCIE_INFO_END_BUS, index)))
+      {
+          if (val_pcie_function_header_type(bdf) == TYPE0_HEADER)
+          {
+              /* Return ecam index if Type0 Header */
+              *ecam_index = index;
+              return 0;
+          }
+          else
+          {
+              /* Check for Secondary/Subordinate bus if Type1 Header */
+              val_pcie_read_cfg(bdf, TYPE1_PBN, &reg_value);
+              sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK);
+              sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK);
+
+              if ((sec_bus >= val_pcie_get_info(PCIE_INFO_START_BUS, index)) &&
+                  (sub_bus <= val_pcie_get_info(PCIE_INFO_END_BUS, index)))
+              {
+                    *ecam_index = index;
+                    return 0;
+              }
+          }
+      }
+
+      index++;
+  }
+
+  return 1;
+}
+
+/**
+  @brief  Checks if the Transaction pending bit is set in device status register
+
+  @param  bdf   - Segment/Bus/Dev/Func in PCIE_CREATE_BDF format
+  @return 0 - TP bit not set, 1 - TP bit set
+**/
+uint32_t
+val_is_transaction_pending_set(uint32_t bdf)
+{
+  uint32_t pciecs_base;
+  uint32_t reg_value;
+  uint32_t status;
+
+  /* Get the PCI Express Capability structure offset and
+   * use that offset to read pci express capabilities register
+   */
+  val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base);
+  status = val_pcie_read_cfg(bdf, pciecs_base + DCTLR_OFFSET, &reg_value);
+
+  if (status) {
+      val_print(ACS_PRINT_ERR, "\n       Error in reading transaction pending bit", 0);
+      return 1;
+  }
+
+  reg_value &= DSR_TP_MASK << (DCTLR_DSR_SHIFT + DSR_TP_SHIFT);
+  if (reg_value)
+      return 1;
+
+  return 0;
+}
diff --git a/val/src/acs_pe.c b/val/src/acs_pe.c
index 565de098..d566cc77 100644
--- a/val/src/acs_pe.c
+++ b/val/src/acs_pe.c
@@ -36,6 +36,7 @@ extern ARM_SMC_ARGS g_smc_args;
            1. Caller       -  Application layer.
            2. Prerequisite -  val_pe_create_info_table, val_allocate_shared_mem
   @param   num_pe - the number of PE to run these tests on.
+  @param   g_sw_view - Keeps the information about which view tests to be run
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -45,7 +46,7 @@ val_pe_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i=0 ; i<MAX_TEST_SKIP_NUM ; i++){
       if (g_skip_test_num[i] == ACS_PE_TEST_NUM_BASE) {
-        val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all PE tests \n", 0);
+        val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all PE tests \n", 0);
         return ACS_STATUS_SKIP;
       }
   }
@@ -93,7 +94,7 @@ val_pe_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (status != ACS_STATUS_PASS)
       val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-      val_print(ACS_PRINT_TEST, "\n      All PE tests have passed!! \n", 0);
+      val_print(ACS_PRINT_TEST, "\n       All PE tests have passed!! \n", 0);
 
   return status;
 
@@ -442,6 +443,14 @@ val_pe_spe_disable(void)
   DisableSpe();
 }
 
+/**
+  @brief   This API reads the TCR register and fills info to structure.
+
+  @param   ttbr1  If ttbr1 is used
+  @param   *tcr   To fill the TCR information
+
+  @return  Status 0 if Success
+**/
 uint32_t val_pe_reg_read_tcr(uint32_t ttbr1, PE_TCR_BF *tcr)
 {
     uint64_t val = val_pe_reg_read(TCR_ELx);
@@ -488,6 +497,14 @@ uint32_t val_pe_reg_read_tcr(uint32_t ttbr1, PE_TCR_BF *tcr)
     return 0;
 }
 
+/**
+  @brief   This API reads the TTBR register and fills info to structure.
+
+  @param   ttbr1       If ttbr1 is used
+  @param   *ttbr_ptr   To fill the TTBR information
+
+  @return  Status 0 if Success
+**/
 uint32_t val_pe_reg_read_ttbr(uint32_t ttbr1, uint64_t *ttbr_ptr)
 {
     uint32_t el = AA64ReadCurrentEL() & AARCH64_EL_MASK;
diff --git a/val/src/acs_pe_infra.c b/val/src/acs_pe_infra.c
index fb88e512..7edbd877 100644
--- a/val/src/acs_pe_infra.c
+++ b/val/src/acs_pe_infra.c
@@ -43,6 +43,8 @@ uint32_t
 val_pe_create_info_table(uint64_t *pe_info_table)
 {
 
+  val_print(ACS_PRINT_INFO, " Creating PE INFO table\n", 0);
+
   if (pe_info_table == NULL) {
       val_print(ACS_PRINT_ERR, "Input memory for PE Info table cannot be NULL \n", 0);
       return ACS_STATUS_ERR;
@@ -62,6 +64,13 @@ val_pe_create_info_table(uint64_t *pe_info_table)
   return ACS_STATUS_PASS;
 }
 
+/**
+  @brief  Free the memory allocated for the pe_info_table
+
+  @param  None
+
+  @return None
+**/
 void
 val_pe_free_info_table()
 {
@@ -262,6 +271,11 @@ val_pe_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void *))
 
 /**
   @brief  Save context data (LR, SP and ELR in case of unexpected exception)
+
+  @param  sp Stack Pointer
+  @param  elr ELR register
+
+  @return None
 **/
 void
 val_pe_context_save(uint64_t sp, uint64_t elr)
@@ -273,6 +287,10 @@ val_pe_context_save(uint64_t sp, uint64_t elr)
 
 /**
   @brief  Restore context data (LR, SP for return to a known location)
+
+  @param  sp Stack Pointer
+
+  @return None
 **/
 void
 val_pe_context_restore(uint64_t sp)
@@ -283,6 +301,10 @@ val_pe_context_restore(uint64_t sp)
 
 /**
   @brief  Initialise exception vector with the default handler
+
+  @param  esr Exception Handler function pointer
+
+  @return None
 **/
 void
 val_pe_initialize_default_exception_handler(void (*esr)(uint64_t, void *))
@@ -293,6 +315,11 @@ val_pe_initialize_default_exception_handler(void (*esr)(uint64_t, void *))
 /**
   @brief  Default handler which, if installed into exception vector, will be
           called in case of unexpected exceptions
+
+  @param  interrupt_type Type of Interrupt(IRQ/FIQ/ASYNC/SERROR)
+  @param  context To restore the context
+
+  @return None
 **/
 void
 val_pe_default_esr(uint64_t interrupt_type, void *context)
@@ -310,12 +337,17 @@ val_pe_default_esr(uint64_t interrupt_type, void *context)
     }
 #endif
 
-    val_set_status(index, RESULT_FAIL(0, 01));
+    val_set_status(index, RESULT_FAIL(0, 1));
     val_pe_update_elr(context, g_exception_ret_addr);
 }
 
 /**
   @brief  Cache clean operation on a defined address range
+
+  @param  start_addr Start Address
+  @param  length Length of the block
+
+  @return None
 **/
 void
 val_pe_cache_clean_range(uint64_t start_addr, uint64_t length)
diff --git a/val/src/acs_peripherals.c b/val/src/acs_peripherals.c
index a9973a53..2a158d1f 100644
--- a/val/src/acs_peripherals.c
+++ b/val/src/acs_peripherals.c
@@ -27,6 +27,7 @@ PERIPHERAL_INFO_TABLE  *g_peripheral_info_table;
           1. Caller       - Application
           2. Prerequisite - val_peripheral_create_info_table
   @param  num_pe - number of PEs to run this test on
+  @param  g_sw_view - Keeps the information about which view tests to be run
 
   @result  consolidated status of all the tests
 **/
@@ -40,7 +41,7 @@ val_peripheral_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i=0 ; i<MAX_TEST_SKIP_NUM ; i++){
       if (g_skip_test_num[i] == ACS_PER_TEST_NUM_BASE) {
-          val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all Peripheral tests \n", 0);
+          val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all Peripheral tests \n", 0);
           return ACS_STATUS_SKIP;
       }
   }
@@ -48,10 +49,8 @@ val_peripheral_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (g_sw_view[G_SW_OS]) {
       val_print(ACS_PRINT_ERR, "\nOperating System View:\n", 0);
 #ifndef TARGET_LINUX
-      if (!pal_target_is_dt()) {
-        status |= os_d001_entry(num_pe);
-        status |= os_d002_entry(num_pe);
-      }
+      status |= os_d001_entry(num_pe);
+      status |= os_d002_entry(num_pe);
       status |= os_d003_entry(num_pe);
       status |= os_d005_entry(num_pe);
 #else
@@ -62,7 +61,7 @@ val_peripheral_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (status != ACS_STATUS_PASS)
     val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-    val_print(ACS_PRINT_TEST, "\n      All Peripheral tests passed!! \n", 0);
+    val_print(ACS_PRINT_TEST, "\n       All Peripheral tests passed!! \n", 0);
 
   return status;
 }
@@ -143,6 +142,16 @@ val_peripheral_get_info(PERIPHERAL_INFO_e info_type, uint32_t instance)
           if (i != 0xFFFF)
               return g_peripheral_info_table->info[i].bdf;
           break;
+      case USB_INTERFACE_TYPE:
+          i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_USB, instance);
+          if (i != 0xFFFF)
+              return g_peripheral_info_table->info[i].interface_type;
+          break;
+      case USB_PLATFORM_TYPE:
+          i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_USB, instance);
+          if (i != 0xFFFF)
+              return g_peripheral_info_table->info[i].platform_type;
+          break;
       case SATA_BASE0:
           i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_SATA, instance);
           if (i != 0xFFFF)
@@ -168,6 +177,16 @@ val_peripheral_get_info(PERIPHERAL_INFO_e info_type, uint32_t instance)
           if (i != 0xFFFF)
               return g_peripheral_info_table->info[i].irq;
           break;
+      case SATA_INTERFACE_TYPE:
+          i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_SATA, instance);
+          if (i != 0xFFFF)
+              return g_peripheral_info_table->info[i].interface_type;
+          break;
+      case SATA_PLATFORM_TYPE:
+          i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_SATA, instance);
+          if (i != 0xFFFF)
+              return g_peripheral_info_table->info[i].platform_type;
+          break;
       case UART_BASE0:
           i = val_peripheral_get_entry_index(PERIPHERAL_TYPE_UART, instance);
           if (i != 0xFFFF)
@@ -241,6 +260,7 @@ val_peripheral_create_info_table(uint64_t *peripheral_info_table)
 {
 
   g_peripheral_info_table = (PERIPHERAL_INFO_TABLE *)peripheral_info_table;
+  val_print(ACS_PRINT_INFO, " Creating PERIPHERAL INFO table\n", 0);
 
   pal_peripheral_create_info_table(g_peripheral_info_table);
 
@@ -256,6 +276,10 @@ val_peripheral_create_info_table(uint64_t *peripheral_info_table)
 
 /**
   @brief  Free the memory allocated for Peripheral Info table
+
+  @param  None
+
+  @return None
  **/
 void
 val_peripheral_free_info_table()
diff --git a/val/src/acs_pgt.c b/val/src/acs_pgt.c
index 43c45ca0..a235b7b9 100644
--- a/val/src/acs_pgt.c
+++ b/val/src/acs_pgt.c
@@ -40,18 +40,26 @@ typedef struct
     uint32_t nbits;
 } tt_descriptor_t;
 
+/**
+  @brief  This API fills the translation table
+
+  @param  tt_desc   Translation Table Descriptor
+  @param  mem_desc  Memory Descriptor
+
+  @return 0 if Success
+**/
 uint32_t fill_translation_table(tt_descriptor_t tt_desc, memory_region_descriptor_t *mem_desc)
 {
     uint64_t block_size = 0x1ull << tt_desc.size_log2;
     uint64_t input_address, output_address, table_index, *tt_base_next_level, *table_desc;
     tt_descriptor_t tt_desc_next_level;
 
-    val_print(PGT_DEBUG_LEVEL, "\n      tt_desc.level: %d     ", tt_desc.level);
-    val_print(PGT_DEBUG_LEVEL, "\n      tt_desc.input_base: 0x%llx     ", tt_desc.input_base);
-    val_print(PGT_DEBUG_LEVEL, "\n      tt_desc.input_top: 0x%llx     ", tt_desc.input_top);
-    val_print(PGT_DEBUG_LEVEL, "\n      tt_desc.output_base: 0x%llx     ", tt_desc.output_base);
-    val_print(PGT_DEBUG_LEVEL, "\n      tt_desc.size_log2: %d     ", tt_desc.size_log2);
-    val_print(PGT_DEBUG_LEVEL, "\n      tt_desc.nbits: %d     ", tt_desc.nbits);
+    val_print(PGT_DEBUG_LEVEL, "\n       tt_desc.level: %d     ", tt_desc.level);
+    val_print(PGT_DEBUG_LEVEL, "\n       tt_desc.input_base: 0x%llx     ", tt_desc.input_base);
+    val_print(PGT_DEBUG_LEVEL, "\n       tt_desc.input_top: 0x%llx     ", tt_desc.input_top);
+    val_print(PGT_DEBUG_LEVEL, "\n       tt_desc.output_base: 0x%llx     ", tt_desc.output_base);
+    val_print(PGT_DEBUG_LEVEL, "\n       tt_desc.size_log2: %d     ", tt_desc.size_log2);
+    val_print(PGT_DEBUG_LEVEL, "\n       tt_desc.nbits: %d     ", tt_desc.nbits);
 
     for (input_address = tt_desc.input_base, output_address = tt_desc.output_base;
          input_address < tt_desc.input_top;
@@ -60,7 +68,7 @@ uint32_t fill_translation_table(tt_descriptor_t tt_desc, memory_region_descripto
         table_index = input_address >> tt_desc.size_log2 & ((0x1ull << tt_desc.nbits) - 1);
         table_desc = &tt_desc.tt_base[table_index];
 
-        val_print(PGT_DEBUG_LEVEL, "\n      table_index = %d     ", table_index);
+        val_print(PGT_DEBUG_LEVEL, "\n       table_index = %d     ", table_index);
 
         if (tt_desc.level == 3)
         {
@@ -68,7 +76,7 @@ uint32_t fill_translation_table(tt_descriptor_t tt_desc, memory_region_descripto
             *table_desc = PGT_ENTRY_PAGE_MASK | PGT_ENTRY_VALID_MASK;
             *table_desc |= (output_address & ~(page_size - 1));
             *table_desc |= mem_desc->attributes;
-            val_print(PGT_DEBUG_LEVEL, "\n      page_descriptor = 0x%llx     ", *table_desc);
+            val_print(PGT_DEBUG_LEVEL, "\n       page_descriptor = 0x%llx     ", *table_desc);
             continue;
         }
 
@@ -80,7 +88,7 @@ uint32_t fill_translation_table(tt_descriptor_t tt_desc, memory_region_descripto
             *table_desc = PGT_ENTRY_BLOCK_MASK | PGT_ENTRY_VALID_MASK;
             *table_desc |= (output_address & ~(block_size - 1));
             *table_desc |= mem_desc->attributes;
-            val_print(PGT_DEBUG_LEVEL, "\n      block_descriptor = 0x%llx     ", *table_desc);
+            val_print(PGT_DEBUG_LEVEL, "\n       block_descriptor = 0x%llx     ", *table_desc);
             continue;
         }
         /*
@@ -93,7 +101,9 @@ uint32_t fill_translation_table(tt_descriptor_t tt_desc, memory_region_descripto
             tt_base_next_level = val_memory_alloc_pages(1);
             if (tt_base_next_level == NULL)
             {
-                val_print(ACS_PRINT_ERR, "\n      fill_translation_table: page allocation failed     ", 0);
+                val_print(ACS_PRINT_ERR,
+                "\n       fill_translation_table: page allocation failed     ",
+                0);
                 return ACS_STATUS_ERR;
             }
             val_memory_set(tt_base_next_level, page_size, 0);
@@ -117,11 +127,18 @@ uint32_t fill_translation_table(tt_descriptor_t tt_desc, memory_region_descripto
 
         *table_desc = PGT_ENTRY_TABLE_MASK | PGT_ENTRY_VALID_MASK;
         *table_desc |= (uint64_t)val_memory_virt_to_phys(tt_base_next_level) & ~(page_size - 1);
-        val_print(PGT_DEBUG_LEVEL, "\n      table_descriptor = 0x%llx     ", *table_desc);
+        val_print(PGT_DEBUG_LEVEL, "\n       table_descriptor = 0x%llx     ", *table_desc);
     }
     return 0;
 }
 
+/**
+  @brief  This API returns the log2(page_size)
+
+  @param  size   Size
+
+  @return log2 page size
+**/
 uint32_t log2_page_size(uint64_t size)
 {
     int bit = 0;
@@ -152,13 +169,14 @@ uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t *
     page_size_log2 = log2_page_size(page_size);
     bits_per_level = page_size_log2 - 3;
     num_pgt_levels = (pgt_desc->ias - page_size_log2 + bits_per_level - 1)/bits_per_level;
-    val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_create: nbits_per_level = %d    ", bits_per_level);
-    val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_create: page_size_log2 = %d     ", page_size_log2);
+    num_pgt_levels = (num_pgt_levels > 4)?4:num_pgt_levels;
+    val_print(PGT_DEBUG_LEVEL, "\n       val_pgt_create: nbits_per_level = %d    ", bits_per_level);
+    val_print(PGT_DEBUG_LEVEL, "\n       val_pgt_create: page_size_log2 = %d     ", page_size_log2);
 
     tt_base = (uint64_t*) val_memory_alloc_pages(1);
     if (tt_base == NULL)
     {
-        val_print(ACS_PRINT_ERR, "\n      val_pgt_create: page allocation failed     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       val_pgt_create: page allocation failed     ", 0);
         return ACS_STATUS_ERR;
     }
     val_memory_set(tt_base, page_size, 0);
@@ -167,31 +185,42 @@ uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t *
 
     for (mem_desc_iter = mem_desc; mem_desc_iter->length != 0; ++mem_desc_iter)
     {
-        val_print(PGT_DEBUG_LEVEL, "      val_pgt_create: input addr = 0x%x     ", mem_desc->virtual_address);
-        val_print(PGT_DEBUG_LEVEL, "      val_pgt_create: output addr = 0x%x     ", mem_desc->physical_address);
+        val_print(PGT_DEBUG_LEVEL,
+                  "      val_pgt_create: input addr = 0x%x     ",
+                  mem_desc->virtual_address);
+        val_print(PGT_DEBUG_LEVEL,
+                  "      val_pgt_create: output addr = 0x%x     ",
+                  mem_desc->physical_address);
         val_print(PGT_DEBUG_LEVEL, "      val_pgt_create: length = 0x%x\n     ", mem_desc->length);
         if ((mem_desc->virtual_address & (uint64_t)(page_size - 1)) != 0 ||
             (mem_desc->physical_address & (uint64_t)(page_size - 1)) != 0)
             {
-                val_print(ACS_PRINT_ERR, "\n      val_pgt_create: address alignment error     ", 0);
+                val_print(ACS_PRINT_ERR, "\n       val_pgt_create: addr alignment err     ", 0);
                 return ACS_STATUS_ERR;
             }
 
         if (mem_desc->physical_address >= (0x1ull << pgt_desc->oas))
         {
-            val_print(ACS_PRINT_ERR, "\n      val_pgt_create: output address size error     ", 0);
+            val_print(ACS_PRINT_ERR,
+                      "\n       val_pgt_create: output address size error     ",
+                      0);
             return ACS_STATUS_ERR;
         }
 
         if (mem_desc->virtual_address >= (0x1ull << pgt_desc->ias))
         {
-            val_print(ACS_PRINT_WARN, "\n      val_pgt_create: input address size error, truncating to %d-bits     ", pgt_desc->ias);
+            val_print(ACS_PRINT_WARN,
+                      "\n       val_pgt_create: input address size error, "
+                      "truncating to %d-bits     ",
+                      pgt_desc->ias);
             mem_desc->virtual_address &= ((0x1ull << pgt_desc->ias) - 1);
         }
 
         if ((pgt_desc->tcr.tg_size_log2) != page_size_log2)
         {
-            val_print(ACS_PRINT_ERR, "\n      val_pgt_create: input page_size 0x%x not supported     ", (0x1 << pgt_desc->tcr.tg_size_log2));
+            val_print(ACS_PRINT_ERR,
+                      "\n       val_pgt_create: input page_size 0x%x unsupported    ",
+                      (0x1 << pgt_desc->tcr.tg_size_log2));
             return ACS_STATUS_ERR;
         }
 
@@ -221,7 +250,8 @@ uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t *
   @param attributes - output attributes
   @return status
 **/
-uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_address, uint64_t *attributes)
+uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_address,
+                                uint64_t *attributes)
 {
     uint32_t ias, index, num_pgt_levels, this_level;
     uint32_t bits_at_this_level, bits_remaining;
@@ -248,11 +278,19 @@ uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_addr
         tt_base_virt = (uint64_t*)val_memory_phys_to_virt(tt_base_phys);
         val64 = tt_base_virt[index];
 
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: this_level = %d     ", this_level);
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: index = %d     ", index);
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: bits_remaining = %d     ", bits_remaining);
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: tt_base_virt = %x     ", (uint64_t)tt_base_virt);
-        val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_get_attributes: val64 = %x     ", val64);
+        val_print(PGT_DEBUG_LEVEL,
+                  "\n       val_pgt_get_attributes: this_level = %d     ",
+                  this_level);
+        val_print(PGT_DEBUG_LEVEL,
+                  "\n       val_pgt_get_attributes: index = %d     ",
+                  index);
+        val_print(PGT_DEBUG_LEVEL,
+                  "\n       val_pgt_get_attributes: bits_remaining = %d     ",
+                  bits_remaining);
+        val_print(PGT_DEBUG_LEVEL,
+                  "\n       val_pgt_get_attributes: tt_base_virt = %x     ",
+                  (uint64_t)tt_base_virt);
+        val_print(PGT_DEBUG_LEVEL, "\n       val_pgt_get_attributes: val64 = %x     ", val64);
         if (this_level == 3)
         {
             if (!IS_PGT_ENTRY_PAGE(val64))
@@ -271,7 +309,17 @@ uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_addr
     }
 }
 
-static void free_translation_table(uint64_t *tt_base, uint32_t bits_at_this_level, uint32_t this_level)
+/**
+  @brief  This API free the translation table
+
+  @param  tt_base   Translation Table Base
+  @param  bits_at_this_level  number of bits
+  @param  this_level  current translation level
+
+  @return 0 if Success
+**/
+static void free_translation_table(uint64_t *tt_base, uint32_t bits_at_this_level,
+                                   uint32_t this_level)
 {
     uint32_t index;
     uint64_t *tt_base_next_virt;
@@ -288,7 +336,9 @@ static void free_translation_table(uint64_t *tt_base, uint32_t bits_at_this_leve
             if (tt_base_next_virt == NULL)
                 continue;
             free_translation_table(tt_base_next_virt, bits_per_level, this_level+1);
-            val_print(PGT_DEBUG_LEVEL, "\n      free_translation_table: tt_base_next_virt = %llx     ", (uint64_t)tt_base_next_virt);
+            val_print(PGT_DEBUG_LEVEL,
+                      "\n       free_translation_table: tt_base_next_virt = %llx     ",
+                      (uint64_t)tt_base_next_virt);
             val_memory_free_pages(tt_base_next_virt, 1);
         }
     }
@@ -307,7 +357,7 @@ void val_pgt_destroy(pgt_descriptor_t pgt_desc)
     if (!pgt_desc.pgt_base)
         return;
 
-    val_print(PGT_DEBUG_LEVEL, "\n      val_pgt_destroy: pgt_base = %llx     ", pgt_desc.pgt_base);
+    val_print(PGT_DEBUG_LEVEL, "\n       val_pgt_destroy: pgt_base = %llx     ", pgt_desc.pgt_base);
     page_size = val_memory_page_size();
     page_size_log2 = log2_page_size(page_size);
     bits_per_level =  page_size_log2 - 3;
diff --git a/val/src/acs_smmu.c b/val/src/acs_smmu.c
index a022694f..4fd4ea2a 100644
--- a/val/src/acs_smmu.c
+++ b/val/src/acs_smmu.c
@@ -49,6 +49,7 @@ val_smmu_read_cfg(uint32_t offset, uint32_t index)
            1. Caller       -  Application layer.
            2. Prerequisite -  val_smmu_create_info_table()
   @param   num_pe - the number of PE to run these tests on.
+  @param   g_sw_view - Keeps the information about which view tests to be run
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -61,14 +62,14 @@ val_smmu_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i=0 ; i<MAX_TEST_SKIP_NUM ; i++){
       if (g_skip_test_num[i] == ACS_SMMU_TEST_NUM_BASE) {
-          val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all SMMU tests \n", 0);
+          val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all SMMU tests \n", 0);
           return ACS_STATUS_SKIP;
       }
   }
 
   num_smmu = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0);
   if (num_smmu == 0) {
-    val_print(ACS_PRINT_WARN, "\n     No SMMU Controller Found, Skipping SMMU tests...\n", 0);
+    val_print(ACS_PRINT_WARN, "\n       No SMMU Controller Found, Skipping SMMU tests...\n", 0);
     return ACS_STATUS_SKIP;
   }
 
@@ -101,12 +102,22 @@ val_smmu_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (status != ACS_STATUS_PASS)
     val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-    val_print(ACS_PRINT_TEST, "\n     All SMMU tests Passed!! \n", 0);
+    val_print(ACS_PRINT_TEST, "\n       All SMMU tests Passed!! \n", 0);
 
   return status;
 }
 #endif
 
+/**
+  @brief  This API is used to start the process of saving
+          DMA addresses being used by the input devic. It is
+          used by the test to indicate the upcoming DMA
+          transfers to be recorded
+
+  @param  ctrl_index  dma controller index
+
+  @return 0 for success
+**/
 uint32_t
 val_smmu_start_monitor_dev(uint32_t ctrl_index)
 {
@@ -123,6 +134,14 @@ val_smmu_start_monitor_dev(uint32_t ctrl_index)
   return 0;
 }
 
+/**
+  @brief  Stops the recording of the DMA addresses being
+          used by the input port.
+
+  @param  ctrl_index  dma controller index
+
+  @return 0 for success
+**/
 uint32_t
 val_smmu_stop_monitor_dev(uint32_t ctrl_index)
 {
@@ -166,7 +185,16 @@ val_smmu_check_device_iova(uint32_t ctrl_index, addr_t dma_addr)
   return status;
 }
 
+/**
+  @brief  To implement the requested operation for SMMU.
+
+  @param  ops  Desired Operation
+  @param  smmu_index  SMMU index
+  @param  *param1  Parameter 1
+  @param  *param2  Parameter 2
 
+  @return 0 for success
+**/
 uint64_t
 val_smmu_ops(SMMU_OPS_e ops, uint32_t smmu_index, void *param1, void *param2)
 {
@@ -186,11 +214,18 @@ val_smmu_ops(SMMU_OPS_e ops, uint32_t smmu_index, void *param1, void *param2)
       default:
           break;
   }
-//  pal_smmu_ops(ops, index, param1, param2);
   return 0;
 
 }
 
+/**
+  @brief  Returns the maximum PASID value supported by the SMMU controller
+
+  @param  smmu_index  SMMU index
+
+  @return 0 is returned when PASID support isnot detected.
+          Nonzero is returned ifmaximum PASID value supported
+**/
 uint32_t
 val_smmu_max_pasids(uint32_t smmu_index)
 {
@@ -200,6 +235,14 @@ val_smmu_max_pasids(uint32_t smmu_index)
   return pal_smmu_max_pasids(smmu_base);
 }
 
+/**
+  @brief  Prepares the SMMU page tables to support input PASID.
+
+  @param  smmu_index  SMMU index for which PASID support is needed.
+  @param  pasid       Process Address Space IDentifier.
+
+  @return Returns 0 for success and 1 for failure.
+**/
 uint32_t
 val_smmu_create_pasid_entry(uint32_t smmu_index, uint32_t pasid)
 {
@@ -209,6 +252,14 @@ val_smmu_create_pasid_entry(uint32_t smmu_index, uint32_t pasid)
   return pal_smmu_create_pasid_entry(smmu_base, pasid);
 }
 
+/**
+  @brief  Converts physical address to I/Ovirtual address
+
+  @param  smmu_index  SMMU index
+  @param  pa          Physical address to use in conversion
+
+  @return Returns 0 for success and 1 for failure.
+**/
 uint64_t
 val_smmu_pa2iova(uint32_t smmu_index, uint64_t pa)
 {
diff --git a/val/src/acs_status.c b/val/src/acs_status.c
index 5817a3fb..4c1a84c6 100644
--- a/val/src/acs_status.c
+++ b/val/src/acs_status.c
@@ -23,8 +23,9 @@
   @brief  Parse the input status and print the appropriate information to console
           1. Caller       - Application layer
           2. Prerequisite - None
-  @param  index  - index of the PE who is reporting this status.
-  @param status  - 32-bit value concatenated from state, level, error value
+  @param  index   - index of the PE who is reporting this status.
+  @param  status  - 32-bit value concatenated from state, level, error value
+  @param  *ruleid - Rule ID in the test to print
 
   @return  none
  **/
@@ -41,8 +42,8 @@ val_report_status(uint32_t index, uint32_t status, char8_t *ruleid)
   else
     if (IS_TEST_FAIL(status)) {
         if (ruleid) {
-            val_print(ACS_PRINT_ERR, "\n       ", 0);
-            val_print(ACS_PRINT_ERR, ruleid, 0);
+            val_print(ACS_PRINT_DEBUG, "\n       ", 0);
+            val_print(ACS_PRINT_DEBUG, ruleid, 0);
             val_print(ACS_PRINT_ERR, "\n       Checkpoint -- %2d                      ",
                                                          status & STATUS_MASK);
         }
@@ -51,8 +52,8 @@ val_report_status(uint32_t index, uint32_t status, char8_t *ruleid)
     else
       if (IS_TEST_SKIP(status)) {
           if (ruleid) {
-              val_print(ACS_PRINT_WARN, "\n       ", 0);
-              val_print(ACS_PRINT_WARN, ruleid, 0);
+              val_print(ACS_PRINT_DEBUG, "\n       ", 0);
+              val_print(ACS_PRINT_DEBUG, ruleid, 0);
               val_print(ACS_PRINT_WARN, "\n       Checkpoint -- %2d                      ",
                                                          status & STATUS_MASK);
           }
diff --git a/val/src/acs_test_infra.c b/val/src/acs_test_infra.c
index 8d83bfe4..110853cb 100644
--- a/val/src/acs_test_infra.c
+++ b/val/src/acs_test_infra.c
@@ -46,6 +46,7 @@ val_print(uint32_t level, char8_t *string, uint64_t data)
           1. Caller       - Application layer
           2. Prerequisite - None.
 
+  @param uart_address  Address of UART to be used
   @param level   the print verbosity (1 to 5)
   @param string  formatted ASCII string
   @param data    64-bit data. set to 0 if no data is to sent to console.
@@ -53,11 +54,11 @@ val_print(uint32_t level, char8_t *string, uint64_t data)
   @return        None
  **/
 void
-val_print_raw(uint32_t level, char8_t *string, uint64_t data)
+val_print_raw(uint64_t uart_address, uint32_t level, char8_t *string,
+                                                                uint64_t data)
 {
 
   if (level >= g_print_level){
-      uint64_t uart_address = val_peripheral_get_info(UART_BASE0, 0);
       pal_print_raw(uart_address, string, data);
   }
 
@@ -211,7 +212,6 @@ val_mmio_write64(addr_t addr, uint64_t data)
   @param test_num unique number identifying this test
   @param desc     brief description of the test
   @param num_pe   the number of PE to execute this test on.
-  @param level    compliance level being tested against
 
   @return         Skip - if the user has overriden to skip the test.
  **/
@@ -315,6 +315,8 @@ val_set_test_data(uint32_t index, uint64_t addr, uint64_t test_data)
           2. Prerequisite - val_set_test_data
 
   @param index   PE index whose data parameter has to be returned.
+  @param *data0  Shared Data0.
+  @param *data1  Shared Data1.
 
   @return    64-bit data
  **/
@@ -421,6 +423,7 @@ val_run_test_payload(uint32_t test_num, uint32_t num_pe, void (*payload)(void),
 
   @param test_num   unique test number
   @param num_pe     The number of PEs to query for status
+  @param *ruleid    RuleID of the test
 
   @return     Success or on failure - status of the last failed PE
  **/
@@ -475,6 +478,11 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid)
 /**
   @brief  Clean and Invalidate the Data cache line containing
           the input address tag
+
+  @param  addr Address
+  @param  type type of invalidation
+
+  @return Status
 **/
 void
 val_data_cache_ops_by_va(addr_t addr, uint32_t type)
@@ -485,6 +493,11 @@ val_data_cache_ops_by_va(addr_t addr, uint32_t type)
 
 /**
   @brief  Update ELR based on the offset provided
+
+  @param  *context  Context to re restored
+  @param  offset    Address to be saved
+
+  @return None
 **/
 void
 val_pe_update_elr(void *context, uint64_t offset)
@@ -500,6 +513,10 @@ val_pe_update_elr(void *context, uint64_t offset)
 
 /**
   @brief  Get ESR from exception context
+
+  @param  *context  Context to be read
+
+  @return ESR Value
 **/
 uint64_t
 val_pe_get_esr(void *context)
@@ -509,6 +526,10 @@ val_pe_get_esr(void *context)
 
 /**
   @brief  Get FAR from exception context
+
+  @param  *context  Context to be read
+
+  @return FAR value
 **/
 uint64_t
 val_pe_get_far(void *context)
@@ -518,6 +539,10 @@ val_pe_get_far(void *context)
 
 /**
   @brief  Write to an address, meant for debugging purpose
+
+  @param  data Data to be written
+
+  @return None
 **/
 void
 val_debug_brk(uint32_t data)
diff --git a/val/src/acs_timer.c b/val/src/acs_timer.c
index d47f497a..faf692e8 100644
--- a/val/src/acs_timer.c
+++ b/val/src/acs_timer.c
@@ -29,6 +29,7 @@ TIMER_INFO_TABLE  *g_timer_info_table;
            1. Caller       -  Application layer.
            2. Prerequisite -  val_timer_create_info_table()
   @param   num_pe - the number of PE to run these tests on.
+  @param   g_sw_view - Keeps the information about which view tests to be run
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -40,7 +41,7 @@ val_timer_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i=0 ; i<MAX_TEST_SKIP_NUM ; i++){
       if (g_skip_test_num[i] == ACS_TIMER_TEST_NUM_BASE) {
-          val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all Timer tests \n", 0);
+          val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all Timer tests \n", 0);
           return ACS_STATUS_SKIP;
       }
   }
@@ -57,7 +58,7 @@ val_timer_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (status != ACS_STATUS_PASS)
     val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-    val_print(ACS_PRINT_TEST, "\n      All Timer tests passed!! \n", 0);
+    val_print(ACS_PRINT_TEST, "\n       All Timer tests passed!! \n", 0);
 
   return status;
 }
@@ -67,6 +68,7 @@ val_timer_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
            1. Caller       -  Test Suite
            2. Prerequisite -  val_timer_create_info_table
   @param   info_type  - Type of the information to be returned
+  @param   instance   - timer instance number
 
   @return  64-bit data pertaining to the requested input type
 **/
@@ -125,6 +127,15 @@ val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance)
   }
 }
 
+/**
+  @brief   This API returns the index in timer info table.
+
+  @param   instance - For which info to be returned
+  @param   *block - Information Block
+  @param   *index - Index in timer info table
+
+  @return  None
+**/
 void
 val_platform_timer_get_entry_index(uint64_t instance, uint32_t *block, uint32_t *index)
 {
@@ -314,6 +325,7 @@ val_timer_create_info_table(uint64_t *timer_info_table)
       val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL \n", 0);
       return;
   }
+  val_print(ACS_PRINT_INFO, " Creating TIMER INFO table\n", 0);
 
   g_timer_info_table = (TIMER_INFO_TABLE *)timer_info_table;
 
@@ -330,6 +342,10 @@ val_timer_create_info_table(uint64_t *timer_info_table)
 
 /**
   @brief  Free the memory allocated for the Timer Info table
+
+  @param  None
+
+  @return None
 **/
 void
 val_timer_free_info_table()
@@ -339,6 +355,11 @@ val_timer_free_info_table()
 
 /**
   @brief  This API will program and start the counter
+
+  @param  cnt_base_n  Counter base address
+  @param  timeout     Timeout value
+
+  @return None
 **/
 void
 val_timer_set_system_timer(addr_t cnt_base_n, uint32_t timeout)
@@ -353,6 +374,10 @@ val_timer_set_system_timer(addr_t cnt_base_n, uint32_t timeout)
 
 /**
   @brief  This API will stop the counter
+
+  @param  cnt_base_n  Counter base address
+
+  @return None
 **/
 void
 val_timer_disable_system_timer(addr_t cnt_base_n)
@@ -365,6 +390,10 @@ val_timer_disable_system_timer(addr_t cnt_base_n)
 /**
   @brief  This API will read CNTACR (from CNTCTLBase) to determine whether
           access permission from NS state is permitted
+
+  @param  index  index of SYS counter in timer table
+
+  @return Status 0 if success
 **/
 uint32_t
 val_timer_skip_if_cntbase_access_not_allowed(uint64_t index)
diff --git a/val/src/acs_timer_support.c b/val/src/acs_timer_support.c
index 33894dc3..a48276b5 100644
--- a/val/src/acs_timer_support.c
+++ b/val/src/acs_timer_support.c
@@ -19,7 +19,13 @@
 #include "include/bsa_acs_timer_support.h"
 #include "include/bsa_acs_common.h"
 
+/**
+  @brief   This API is used to read Timer related registers
 
+  @param   Reg  Register to be read
+
+  @return  Register value
+**/
 uint64_t
 ArmArchTimerReadReg (
     ARM_ARCH_TIMER_REGS   Reg
@@ -71,16 +77,25 @@ ArmArchTimerReadReg (
 
     case CnthCtl:
     case CnthpCval:
-      pal_print ("The register is related to Hypervisor Mode. Can't perform requested operation\n ", 0);
+      pal_print("The register is related to Hypervisor Mode. \
+Can't perform requested operation\n ", 0);
       break;
 
     default:
-      pal_print ("Unknown ARM Generic Timer register %x. \n ", Reg);
+      pal_print("Unknown ARM Generic Timer register %x. \n ", Reg);
     }
 
     return 0xFFFFFFFF;
 }
 
+/**
+  @brief   This API is used to write Timer related registers
+
+  @param   Reg  Register to be read
+  @param   data_buf Data to write in register
+
+  @return  None
+**/
 void
 ArmArchTimerWriteReg (
     ARM_ARCH_TIMER_REGS   Reg,
diff --git a/val/src/acs_wakeup.c b/val/src/acs_wakeup.c
index dfab01b7..2730e801 100644
--- a/val/src/acs_wakeup.c
+++ b/val/src/acs_wakeup.c
@@ -27,6 +27,7 @@
            1. Caller       -  Application layer.
            2. Prerequisite -  None
   @param   num_pe - the number of PE to run these tests on.
+  @param   g_sw_view - Keeps the information about which view tests to be run
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -38,7 +39,7 @@ val_wakeup_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i=0 ; i<MAX_TEST_SKIP_NUM ; i++){
       if (g_skip_test_num[i] == ACS_WAKEUP_TEST_NUM_BASE) {
-          val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all Wakeup tests \n", 0);
+          val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all Wakeup tests \n", 0);
           return ACS_STATUS_SKIP;
       }
   }
@@ -53,13 +54,20 @@ val_wakeup_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (status != ACS_STATUS_PASS)
     val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-    val_print(ACS_PRINT_TEST, "\n      All Wakeup tests passed!! \n", 0);
+    val_print(ACS_PRINT_TEST, "\n       All Wakeup tests passed!! \n", 0);
 
   return status;
 
 }
 
-uint32_t val_get_pcsi_ver(void)
+/**
+  @brief  This API is used to get PSCI Version
+
+  @param  None
+
+  @return PSCI Version
+**/
+uint32_t val_get_psci_ver(void)
 {
   ARM_SMC_ARGS smc_args;
 
@@ -72,13 +80,19 @@ uint32_t val_get_pcsi_ver(void)
   return smc_args.Arg0;
 }
 
+/**
+  @brief  This API is used to get PSCI features
+
+  @param  psci_func_id  Function ID
 
-uint32_t val_get_pcsi_features(uint64_t pcsi_func_id)
+  @return PSCI features
+**/
+uint32_t val_get_psci_features(uint64_t psci_func_id)
 {
   ARM_SMC_ARGS smc_args;
 
   smc_args.Arg0 = ARM_SMC_ID_PSCI_FEATURES;
-  smc_args.Arg1 = pcsi_func_id;
+  smc_args.Arg1 = psci_func_id;
 
   pal_pe_call_smc(&smc_args);
 
@@ -101,13 +115,13 @@ val_suspend_pe(uint64_t entry, uint32_t context_id)
   int psci_major_ver, pwr_state_fmt;
   uint32_t power_state;
 
-  psci_major_ver = (val_get_pcsi_ver() >> 16);
+  psci_major_ver = (val_get_psci_ver() >> 16);
   val_print(ACS_PRINT_DEBUG, "\n       PSCI MAJOR VERSION = %X", psci_major_ver);
   if (psci_major_ver < 1)
     power_state = 0;
   else {
-      pwr_state_fmt = (val_get_pcsi_features(ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64) >> 1);
-      val_print(ACS_PRINT_DEBUG, "\n       PSCI PWR_STATE_FMT = %d          ",
+      pwr_state_fmt = (val_get_psci_features(ARM_SMC_ID_PSCI_CPU_SUSPEND_AARCH64) >> 1);
+      val_print(ACS_PRINT_DEBUG, "\n       PSCI PWR_STATE_FMT = %d                ",
                                                                 pwr_state_fmt);
       if (pwr_state_fmt == ARM_SMC_ID_PSCI_POWER_STATE_FMT_ORIGINAL)
         power_state = 0;
diff --git a/val/src/acs_wd.c b/val/src/acs_wd.c
index 3a8d4a11..d560d4ff 100644
--- a/val/src/acs_wd.c
+++ b/val/src/acs_wd.c
@@ -28,6 +28,7 @@ WD_INFO_TABLE  *g_wd_info_table;
            1. Caller       -  Application layer.
            2. Prerequisite -  val_wd_create_info_table
   @param   num_pe - the number of PE to run these tests on.
+  @param   g_sw_view - Keeps the information about which view tests to be run
   @return  Consolidated status of all the tests run.
 **/
 uint32_t
@@ -39,11 +40,17 @@ val_wd_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
 
   for (i=0 ; i<MAX_TEST_SKIP_NUM ; i++){
       if (g_skip_test_num[i] == ACS_WD_TEST_NUM_BASE) {
-          val_print(ACS_PRINT_TEST, "\n      USER Override - Skipping all Watchdog tests \n", 0);
+          val_print(ACS_PRINT_TEST, "\n       USER Override - Skipping all Watchdog tests \n", 0);
           return ACS_STATUS_SKIP;
       }
   }
 
+  if (val_wd_get_info(0, WD_INFO_COUNT) == 0) {
+    val_print(ACS_PRINT_WARN, "\n       No Watchdog Found, Skipping Watchdog "
+                                                    "tests...\n", 0);
+    return ACS_STATUS_SKIP;
+  }
+
   if (g_sw_view[G_SW_OS]) {
     val_print(ACS_PRINT_ERR, "\nOperating System View:\n", 0);
     status |= os_w001_entry(num_pe);
@@ -53,7 +60,7 @@ val_wd_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
   if (status != ACS_STATUS_PASS)
     val_print(ACS_PRINT_TEST, "\n      *** One or more tests have Failed/Skipped.*** \n", 0);
   else
-    val_print(ACS_PRINT_TEST, "\n      All Watchdog tests passed!! \n", 0);
+    val_print(ACS_PRINT_TEST, "\n       All Watchdog tests passed!! \n", 0);
 
   return status;
 }
@@ -63,6 +70,7 @@ val_wd_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
            information stored in the WD Info table
            1. Caller       -  Test Suite
            2. Prerequisite -  val_wd_create_info_table
+  @param   index  watchdog index in the table
   @param   type   the type of information being requested
   @return  64-bit data
 **/
@@ -107,6 +115,7 @@ val_wd_create_info_table(uint64_t *wd_info_table)
       val_print(ACS_PRINT_ERR, "Input for Create Info table cannot be NULL \n", 0);
       return;
   }
+  val_print(ACS_PRINT_INFO, " Creating WATCHDOG INFO table\n", 0);
 
   g_wd_info_table = (WD_INFO_TABLE *)wd_info_table;
 
@@ -117,6 +126,10 @@ val_wd_create_info_table(uint64_t *wd_info_table)
 
 /**
   @brief  Free the memory allocated for the Watchdog information table
+
+  @param  None
+
+  @return None
 **/
 void
 val_wd_free_info_table()
diff --git a/val/sys_arch_src/gic/bsa_exception.c b/val/sys_arch_src/gic/bsa_exception.c
index c86ea065..695bd86b 100644
--- a/val/sys_arch_src/gic/bsa_exception.c
+++ b/val/sys_arch_src/gic/bsa_exception.c
@@ -52,7 +52,7 @@ void default_irq_handler(uint64_t exception_type, void *context)
 
 void bsa_gic_vector_table_init(void)
 {
-  val_print(ACS_PRINT_DEBUG, " GIC_INIT: Setting Up Vector Table...\n", 0);
+  val_print(ACS_PRINT_DEBUG, "  GIC_INIT: Setting Up Vector Table...\n", 0);
 
   /* Setting Up Vector Table */
   bsa_gic_set_el2_vector_table();
diff --git a/val/sys_arch_src/gic/gic.c b/val/sys_arch_src/gic/gic.c
index b408a5ca..861be73c 100644
--- a/val/sys_arch_src/gic/gic.c
+++ b/val/sys_arch_src/gic/gic.c
@@ -142,3 +142,89 @@ val_bsa_gic_max_espi_val(void)
   else
       return 0;
 }
+
+
+/**
+  @brief  API used to check whether int_id is a espi interrupt
+  @param  interrupt
+  @return 1: espi interrupt, 0: non-espi interrupt
+**/
+uint32_t
+val_bsa_gic_check_espi_interrupt(uint32_t int_id)
+{
+  if (val_bsa_gic_espi_support() && v3_is_extended_spi(int_id))
+    return 1;
+  else
+    return 0;
+}
+
+/**
+  @brief  API used to clear espi interrupt
+  @param  interrupt
+  @return none
+**/
+void val_bsa_gic_clear_espi_interrupt(uint32_t int_id)
+{
+  v3_clear_extended_spi_interrupt(int_id);
+}
+
+
+/**
+  @brief  API used to find extended PPI support in system.
+  @param  none
+  @return 0 if not supported, 1 supported
+**/
+uint32_t
+val_bsa_gic_eppi_support(void)
+{
+  uint32_t gic_version;
+
+  gic_version = val_gic_get_info(GIC_INFO_VERSION);
+  if (gic_version >= 3) {
+      if ((v3_read_gicr_typer() >> GICD_TYPER_EPPI_NUM_SHIFT) & GICD_TYPER_EPPI_NUM_MASK)
+        return 1;
+      else
+         return 0;
+  }
+  else
+      return 0;
+}
+
+/**
+  @brief  API used to find  max eppi value
+  @param  none
+  @return max eppi value
+**/
+uint32_t
+val_bsa_gic_max_eppi_val(void)
+{
+  uint32_t gic_version;
+  uint32_t ppi_range;
+
+  gic_version = val_gic_get_info(GIC_INFO_VERSION);
+  if (gic_version >= 3) {
+      ppi_range = ((v3_read_gicr_typer() >> GICD_TYPER_EPPI_NUM_SHIFT) & GICD_TYPER_EPPI_NUM_MASK);
+      if (ppi_range == 1)
+        return 1087;
+      else if (ppi_range == 2)
+        return 1119;
+      else
+        return 0; /* return 0 if EPPI not supported*/
+   }
+  else
+      return 0;
+}
+
+/**
+  @brief  API used to check whether int_id is a eppi interrupt
+  @param  interrupt
+  @return 1: eppi interrupt
+**/
+uint32_t
+val_bsa_gic_check_eppi_interrupt(uint32_t int_id)
+{
+  if (val_bsa_gic_eppi_support() && v3_is_extended_ppi(int_id))
+    return 1;
+  else
+    return 0;
+}
diff --git a/val/sys_arch_src/gic/gic.h b/val/sys_arch_src/gic/gic.h
index d38e1b9e..f963d365 100644
--- a/val/sys_arch_src/gic/gic.h
+++ b/val/sys_arch_src/gic/gic.h
@@ -60,5 +60,10 @@ uint32_t val_bsa_gic_acknowledgeInterrupt(void);
 void val_bsa_gic_endofInterrupt(uint32_t int_id);
 uint32_t val_bsa_gic_espi_support(void);
 uint32_t val_bsa_gic_max_espi_val(void);
+uint32_t val_bsa_gic_check_espi_interrupt(uint32_t int_id);
+void val_bsa_gic_clear_espi_interrupt(uint32_t int_id);
+uint32_t val_bsa_gic_eppi_support(void);
+uint32_t val_bsa_gic_max_eppi_val(void);
+uint32_t val_bsa_gic_check_eppi_interrupt(uint32_t int_id);
 
 #endif /*__GIC_H__ */
diff --git a/val/sys_arch_src/gic/its/bsa_gic_its.c b/val/sys_arch_src/gic/its/bsa_gic_its.c
index 31126a63..d0560e70 100644
--- a/val/sys_arch_src/gic/its/bsa_gic_its.c
+++ b/val/sys_arch_src/gic/its/bsa_gic_its.c
@@ -17,6 +17,7 @@
 
 
 #include "bsa_gic_its.h"
+#include "include/bsa_acs_gic_support.h"
 
 uint64_t ArmReadMpidr(void);
 
@@ -102,7 +103,7 @@ ArmGicSetItsCommandQueueBase(
 
   write_value = val_mmio_read64(ItsBase + ARM_GITS_CBASER) & (~ARM_GITS_CBASER_PA_MASK);
   write_value = write_value | (Address & ARM_GITS_CBASER_PA_MASK);
-  write_value = write_value | ARM_GITS_CBASER_VALID;
+  write_value = write_value | ARM_GITS_CBASER_VALID | (NUM_PAGES_8 - 1);
 
   val_mmio_write64(ItsBase + ARM_GITS_CBASER, write_value);
 
@@ -318,7 +319,8 @@ void PollTillCommandQueueDone(uint32_t its_index)
 
     count++;
     if (count > WAIT_ITS_COMMAND_DONE) {
-      val_print(ACS_PRINT_ERR,  "ITS : Command Queue READR not moving, Test may not pass.\n", 0);
+      val_print(ACS_PRINT_ERR,
+                "\n       ITS : Command Queue READR not moving, Test may not pass", 0);
       break;
     }
 
@@ -369,15 +371,21 @@ void val_its_clear_lpi_map(uint32_t its_index, uint32_t device_id, uint32_t int_
 
   /* Discard Mappings */
   WriteCmdQDISCARD(its_index, (uint64_t *)(ItsCommandBase), device_id, int_id);
+  /* Un Map Device using MAPD */
+  WriteCmdQMAPD(its_index, (uint64_t *)(ItsCommandBase), device_id,
+                g_gic_its_info->GicIts[its_index].ITTBase,
+                0, 0 /*InValid*/);
   /* ITS SYNC Command */
   WriteCmdQSYNC(its_index, (uint64_t *)(ItsCommandBase), RDBase);
 
+  TestExecuteBarrier();
   /* Update the CWRITER Register so that all the commands from Command queue gets executed.*/
   value = ((g_cwriter_ptr[its_index] * NUM_BYTES_IN_DW));
   val_mmio_write64((ItsBase + ARM_GITS_CWRITER), value);
 
   /* Check CREADR value which ensures Command Queue is processed */
   PollTillCommandQueueDone(its_index);
+  TestExecuteBarrier();
 
 }
 
@@ -421,12 +429,15 @@ void val_its_create_lpi_map(uint32_t its_index, uint32_t device_id,
   /* ITS SYNC Command */
   WriteCmdQSYNC(its_index, (uint64_t *)(ItsCommandBase), RDBase);
 
+  TestExecuteBarrier();
+
   /* Update the CWRITER Register so that all the commands from Command queue gets executed.*/
   value = ((g_cwriter_ptr[its_index] * NUM_BYTES_IN_DW));
   val_mmio_write64((ItsBase + ARM_GITS_CWRITER), value);
 
   /* Check CREADR value which ensures Command Queue is processed */
   PollTillCommandQueueDone(its_index);
+  TestExecuteBarrier();
 
 }
 
@@ -453,7 +464,7 @@ uint32_t val_its_get_max_lpi(void)
 }
 
 
-uint64_t val_its_get_translator_addr(uint32_t its_index)
+uint64_t val_its_get_translater_addr(uint32_t its_index)
 {
   return (g_gic_its_info->GicIts[its_index].Base + ARM_GITS_TRANSLATER);
 }
@@ -534,12 +545,12 @@ uint32_t val_its_init(void)
 
   g_its_setup_done = 1;
 
-  val_print(ACS_PRINT_INFO, "ITS : Info Block \n", 0);
+  val_print(ACS_PRINT_INFO, "  ITS : Info Block \n", 0);
   for (index = 0; index < g_gic_its_info->GicNumIts; index++)
   {
-      val_print(ACS_PRINT_INFO, "GIC ITS Index : %x\n", index);
-      val_print(ACS_PRINT_INFO, "GIC ITS ID : %x\n", g_gic_its_info->GicIts[index].ID);
-      val_print(ACS_PRINT_INFO, "GIC ITS Base : %x\n\n", g_gic_its_info->GicIts[index].Base);
+      val_print(ACS_PRINT_INFO, "  GIC ITS Index: %x", index);
+      val_print(ACS_PRINT_INFO, " ID: %x", g_gic_its_info->GicIts[index].ID);
+      val_print(ACS_PRINT_INFO, " Base: %x\n", g_gic_its_info->GicIts[index].Base);
   }
 
   return 0;
diff --git a/val/sys_arch_src/gic/its/bsa_gic_its.h b/val/sys_arch_src/gic/its/bsa_gic_its.h
index 5fd2fefe..4f375ef7 100644
--- a/val/sys_arch_src/gic/its/bsa_gic_its.h
+++ b/val/sys_arch_src/gic/its/bsa_gic_its.h
@@ -178,7 +178,7 @@ void val_its_create_lpi_map(uint32_t its_index, uint32_t device_id,
                             uint32_t int_id, uint32_t Priority);
 void val_its_clear_lpi_map(uint32_t its_index, uint32_t device_id, uint32_t int_id);
 
-uint64_t val_its_get_translator_addr(uint32_t its_index);
+uint64_t val_its_get_translater_addr(uint32_t its_index);
 uint32_t val_its_get_max_lpi(void);
 uint32_t val_its_init(void);
 uint64_t val_its_get_curr_rdbase(uint64_t rd_base, uint32_t length);
diff --git a/val/sys_arch_src/gic/v2/gic_v2.c b/val/sys_arch_src/gic/v2/gic_v2.c
index 524e1c5f..853aee0c 100644
--- a/val/sys_arch_src/gic/v2/gic_v2.c
+++ b/val/sys_arch_src/gic/v2/gic_v2.c
@@ -107,9 +107,9 @@ v2_Init(void)
   /* Get the max interrupt */
   max_num_interrupts = val_get_max_intid();
 
-  val_print(ACS_PRINT_DEBUG, " \n GIC_INIT: D base %x\n", gicd_base);
-  val_print(ACS_PRINT_DEBUG, " \n GIC_INIT: CPU IF base %x\n", cpuif_base);
-  val_print(ACS_PRINT_DEBUG, " \n GIC_INIT: Interrupts %d\n", max_num_interrupts);
+  val_print(ACS_PRINT_DEBUG, "  GIC_INIT: D base %x\n", gicd_base);
+  val_print(ACS_PRINT_DEBUG, "  GIC_INIT: CPU IF base %x\n", cpuif_base);
+  val_print(ACS_PRINT_DEBUG, "  GIC_INIT: Interrupts %d\n", max_num_interrupts);
 
   /* Disable all interrupt */
   for (index = 0; index < max_num_interrupts; index++) {
diff --git a/val/sys_arch_src/gic/v3/gic_v3.c b/val/sys_arch_src/gic/v3/gic_v3.c
index 7c88c1f0..9ceaaa4e 100644
--- a/val/sys_arch_src/gic/v3/gic_v3.c
+++ b/val/sys_arch_src/gic/v3/gic_v3.c
@@ -48,6 +48,18 @@ v3_read_gicdTyper(void)
   return val_mmio_read(val_get_gicd_base() + GICD_TYPER);
 }
 
+/**
+  @brief  Retruns GICR_TYPER value
+  @param  none
+  @return gicr typer value
+**/
+uint64_t
+v3_read_gicr_typer(void)
+{
+  return val_mmio_read64(v3_get_pe_gicr_base() + GICR_TYPER);
+}
+
+
 /**
   @brief  derives current pe rd base
   @param  rd base
@@ -123,6 +135,21 @@ WakeUpRD(void)
   } while (tmp);
 }
 
+/**
+  @brief  derives current pe rd base
+  @param  none
+  @return pe rd base
+**/
+uint64_t v3_get_pe_gicr_base(void)
+{
+  uint32_t                rdbase_len;
+  uint64_t                rd_base;
+
+  rd_base = val_get_gicr_base(&rdbase_len);
+
+  return CurrentCpuRDBase(rd_base, rdbase_len);
+}
+
 /**
   @brief  Acknowledges the interrupt
   @param  none
@@ -159,6 +186,11 @@ v3_DisableInterruptSource(uint32_t int_id)
   uint64_t                rd_base;
   uint64_t                cpuRd_base;
 
+  if (v3_is_extended_spi(int_id) || v3_is_extended_ppi(int_id)) {
+      v3_disable_extended_interrupt_source(int_id);
+      return;
+  }
+
   /* Calculate register offset and bit position */
   regOffset = int_id / 32;
   regShift = int_id % 32;
@@ -190,6 +222,10 @@ v3_EnableInterruptSource(uint32_t int_id)
   uint64_t                rd_base;
   uint64_t                cpuRd_base;
 
+  if (v3_is_extended_spi(int_id) || v3_is_extended_ppi(int_id)) {
+      v3_enable_extended_interrupt_source(int_id);
+      return;
+  }
   /* Calculate register offset and bit position */
   regOffset = int_id / 32;
   regShift = int_id % 32;
@@ -222,6 +258,11 @@ v3_SetInterruptPriority(uint32_t int_id, uint32_t priority)
   uint64_t                rd_base;
   uint64_t                cpuRd_base;
 
+  if (v3_is_extended_spi(int_id) || v3_is_extended_ppi(int_id)) {
+      v3_set_extended_interrupt_priority(int_id, priority);
+      return;
+  }
+
   /* Calculate register offset and bit position */
   regOffset = int_id / 4;
   regShift = (int_id % 4) * 8;
@@ -257,14 +298,17 @@ v3_Init(void)
   uint64_t   cpuTarget;
   uint64_t   Mpidr;
 
+  if (val_bsa_gic_espi_support() || val_bsa_gic_eppi_support())
+    v3_extended_init();
+
   /* Get the distributor base */
   gicd_base = val_get_gicd_base();
 
   /* Get the max interrupt */
   max_num_interrupts = val_get_max_intid();
 
-  val_print(ACS_PRINT_DEBUG, " \n GIC_INIT: D base %x\n", gicd_base);
-  val_print(ACS_PRINT_DEBUG, " \n GIC_INIT: Interrupts %d\n", max_num_interrupts);
+  val_print(ACS_PRINT_DEBUG, "  GIC_INIT: D base %x\n", gicd_base);
+  val_print(ACS_PRINT_DEBUG, "  GIC_INIT: Interrupts %d\n", max_num_interrupts);
 
   /* Disable all interrupt */
   for (index = 0; index < max_num_interrupts; index++) {
@@ -289,7 +333,7 @@ v3_Init(void)
   /* Set ARI bits for v3 mode */
   val_mmio_write(gicd_base + GICD_CTLR, val_mmio_read(gicd_base + GICD_CTLR) | GIC_ARE_ENABLE);
   val_mmio_write(gicd_base + GICD_CTLR, val_mmio_read(gicd_base + GICD_CTLR) | 0x2);
-  val_print(ACS_PRINT_DEBUG, " \n GIC_INIT: GICD_CTLR value 0x%08x\n",
+  val_print(ACS_PRINT_DEBUG, "  GIC_INIT: GICD_CTLR value 0x%08x\n",
                              val_mmio_read(gicd_base + GICD_CTLR));
 
   WakeUpRD();
diff --git a/val/sys_arch_src/gic/v3/gic_v3.h b/val/sys_arch_src/gic/v3/gic_v3.h
index 80a0d1ab..b506e39e 100644
--- a/val/sys_arch_src/gic/v3/gic_v3.h
+++ b/val/sys_arch_src/gic/v3/gic_v3.h
@@ -23,11 +23,29 @@
 #define GICD_TYPER_ESPI_RANGE_SHIFT 27
 #define GICD_TYPER_ESPI_RANGE_MASK  0x1F
 
+#define GICD_TYPER_EPPI_NUM_SHIFT   27
+#define GICD_TYPER_EPPI_NUM_MASK    0x1F
+
+#define EXTENDED_SPI_START_INTID   4096
+#define EXTENDED_PPI_START_INTID   1056
+
+#define EXTENDED_PPI_REG_OFFSET    1024
+
 void v3_Init(void);
 void v3_EnableInterruptSource(uint32_t);
 void v3_DisableInterruptSource(uint32_t);
 uint32_t v3_AcknowledgeInterrupt(void);
 void v3_EndofInterrupt(uint32_t int_id);
 uint32_t v3_read_gicdTyper(void);
+uint64_t v3_get_pe_gicr_base(void);
+uint64_t v3_read_gicr_typer(void);
+
+uint32_t v3_is_extended_spi(uint32_t int_id);
+uint32_t v3_is_extended_ppi(uint32_t int_id);
+void v3_clear_extended_spi_interrupt(uint32_t int_id);
+void v3_disable_extended_interrupt_source(uint32_t int_id);
+void v3_enable_extended_interrupt_source(uint32_t int_id);
+void v3_set_extended_interrupt_priority(uint32_t int_id, uint32_t priority);
+void v3_extended_init(void);
 
 #endif /*__GIC_V3_H__ */
diff --git a/val/sys_arch_src/gic/v3/gic_v3_extended.c b/val/sys_arch_src/gic/v3/gic_v3_extended.c
new file mode 100644
index 00000000..c8d4110b
--- /dev/null
+++ b/val/sys_arch_src/gic/v3/gic_v3_extended.c
@@ -0,0 +1,229 @@
+/** @file
+ * Copyright (c) 2021, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ **/
+
+#include "include/bsa_acs_val.h"
+#include "include/bsa_acs_gic.h"
+#include "include/bsa_acs_gic_support.h"
+#include "include/bsa_acs_pe.h"
+#include "gic_v3.h"
+#include "gic.h"
+#include "bsa_exception.h"
+
+/**
+  @brief  API used to clear espi interrupt
+  @param  interrupt
+  @return none
+**/
+void v3_clear_extended_spi_interrupt(uint32_t int_id)
+{
+  uint32_t reg_offset = (int_id - EXTENDED_SPI_START_INTID) / 32;
+  uint32_t reg_shift  = (int_id - EXTENDED_SPI_START_INTID) % 32;
+
+  val_mmio_write(val_get_gicd_base() + GICD_ICPENDRE0 + (4 * reg_offset), (1 << reg_shift));
+  val_mmio_write(val_get_gicd_base() + GICD_ICACTIVERE0 + (4 * reg_offset), (1 << reg_shift));
+}
+
+/**
+  @brief  checks if given int id is espi
+  @param  int_id
+  @return true if ESPI
+**/
+uint32_t
+v3_is_extended_spi(uint32_t int_id)
+{
+  if (int_id >= EXTENDED_SPI_START_INTID && int_id <= val_bsa_gic_max_espi_val())
+      return 1;
+  else
+      return 0;
+}
+
+/**
+  @brief  checks if given int id is eppi
+  @param  int_id
+  @return true if EPPI
+**/
+uint32_t
+v3_is_extended_ppi(uint32_t int_id)
+{
+  if (int_id >= EXTENDED_PPI_START_INTID && int_id <= val_bsa_gic_max_eppi_val())
+      return 1;
+  else
+      return 0;
+}
+
+/**
+  @brief  Disables the interrupt source
+  @param  interrupt id
+  @return none
+**/
+void
+v3_disable_extended_interrupt_source(uint32_t int_id)
+{
+  uint32_t                regOffset;
+  uint32_t                regShift;
+  uint64_t                cpuRd_base;
+
+  if (v3_is_extended_spi(int_id)) {
+      /* Calculate register offset and bit position */
+      regOffset = (int_id - EXTENDED_SPI_START_INTID) / 32;
+      regShift = (int_id - EXTENDED_SPI_START_INTID) % 32;
+      val_mmio_write(val_get_gicd_base() + GICD_ICENABLERE + (4 * regOffset), 1 << regShift);
+  } else {
+      /* Calculate register offset and bit position */
+      regOffset = (int_id - EXTENDED_PPI_REG_OFFSET) / 32;
+      regShift = (int_id - EXTENDED_PPI_REG_OFFSET) % 32;
+      cpuRd_base = v3_get_pe_gicr_base();
+      if (cpuRd_base == 0) {
+        return;
+      }
+      val_mmio_write(cpuRd_base + GICR_CTLR_FRAME_SIZE + GICR_ICENABLER + (4 * regOffset),
+                   1 << regShift);
+  }
+}
+
+/**
+  @brief  Enables the interrupt source
+  @param  interrupt id
+  @return none
+**/
+void
+v3_enable_extended_interrupt_source(uint32_t int_id)
+{
+  uint32_t                regOffset;
+  uint32_t                regShift;
+  uint64_t                cpuRd_base;
+
+  if (v3_is_extended_spi(int_id)) {
+      /* Calculate register offset and bit position */
+      regOffset = (int_id - EXTENDED_SPI_START_INTID) / 32;
+      regShift = (int_id - EXTENDED_SPI_START_INTID) % 32;
+      val_mmio_write(val_get_gicd_base() + GICD_ICENABLERE + (4 * regOffset), 1 << regShift);
+  } else {
+      /* Calculate register offset and bit position */
+      regOffset = (int_id - EXTENDED_PPI_REG_OFFSET) / 32;
+      regShift = (int_id - EXTENDED_PPI_REG_OFFSET) % 32;
+      cpuRd_base = v3_get_pe_gicr_base();
+      if (cpuRd_base == 0) {
+        return;
+      }
+      val_mmio_write(cpuRd_base + GICR_CTLR_FRAME_SIZE + GICR_ISENABLER + (4 * regOffset),
+                   1 << regShift);
+  }
+}
+
+/**
+  @brief  Sets interrupt priority
+  @param  interrupt id
+  @param  priority
+  @return none
+**/
+void
+v3_set_extended_interrupt_priority(uint32_t int_id, uint32_t priority)
+{
+  uint32_t                regOffset;
+  uint32_t                regShift;
+  uint64_t                cpuRd_base;
+
+  if (v3_is_extended_spi(int_id)) {
+      /* Calculate register offset and bit position */
+      regOffset = (int_id - EXTENDED_SPI_START_INTID) / 4;
+      regShift = ((int_id - EXTENDED_SPI_START_INTID) % 4) * 8;
+
+      val_mmio_write(val_get_gicd_base() + GICD_IPRIORITYRE + (4 * regOffset),
+                    (val_mmio_read(val_get_gicd_base() + GICD_IPRIORITYRE + (4 * regOffset)) &
+                     ~(0xff << regShift)) | priority << regShift);
+  } else {
+     /* Calculate register offset and bit position */
+    regOffset = (int_id - EXTENDED_PPI_REG_OFFSET) / 4;
+    regShift = ((int_id - EXTENDED_PPI_REG_OFFSET) % 4) * 8;
+
+    cpuRd_base = v3_get_pe_gicr_base();
+    if (cpuRd_base == 0) {
+      return;
+    }
+    val_mmio_write(cpuRd_base + GICR_IPRIORITYR + (4 * regOffset),
+                  (val_mmio_read(cpuRd_base + GICR_IPRIORITYR + (4 * regOffset)) &
+                   ~(0xff << regShift)) | priority << regShift);
+  }
+}
+
+/**
+  @brief  Route interrupt to primary PE
+  @param  interrupt id
+  @return none
+**/
+void
+v3_route_extended_interrupt(uint32_t int_id)
+{
+  uint64_t   gicd_base;
+  uint64_t   cpuTarget;
+  uint64_t   Mpidr;
+
+  /* Get the distributor base */
+  gicd_base = val_get_gicd_base();
+
+  Mpidr = ArmReadMpidr();
+  cpuTarget = Mpidr & (PE_AFF0 | PE_AFF1 | PE_AFF2 | PE_AFF3);
+
+  val_mmio_write64(gicd_base + GICD_IROUTERn + (int_id * 8), cpuTarget);
+}
+
+/**
+  @brief  Initializes the GIC v3 Extended Interrupts
+  @param  none
+  @return init success or failure
+**/
+void
+v3_extended_init(void)
+{
+  uint32_t   max_num_espi_interrupts;
+  uint32_t   max_num_eppi_interrupts;
+  uint32_t   index;
+
+  /* Get the max interrupt */
+  max_num_espi_interrupts = val_bsa_gic_max_espi_val();
+  max_num_eppi_interrupts = val_bsa_gic_max_eppi_val();
+
+  val_print(ACS_PRINT_DEBUG, "\n GIC_INIT: Extended SPI Interrupts %d\n", max_num_espi_interrupts);
+  val_print(ACS_PRINT_DEBUG, "\n GIC_INIT: Extended PPI Interrupts %d\n", max_num_eppi_interrupts);
+
+  /* Disable all ESPI interrupt */
+  for (index = EXTENDED_SPI_START_INTID; index <= max_num_espi_interrupts; index++) {
+      v3_disable_extended_interrupt_source(index);
+  }
+
+  /* Disable all EPPI interrupt */
+  for (index = EXTENDED_PPI_START_INTID; index <= max_num_eppi_interrupts; index++) {
+      v3_disable_extended_interrupt_source(index);
+  }
+
+  /* Set default for ESPI priority */
+  for (index = EXTENDED_SPI_START_INTID; index <= max_num_espi_interrupts; index++) {
+      v3_set_extended_interrupt_priority(index, GIC_DEFAULT_PRIORITY);
+  }
+
+  /* Set default for EPPI priority */
+  for (index = EXTENDED_PPI_START_INTID; index <= max_num_eppi_interrupts; index++) {
+      v3_set_extended_interrupt_priority(index, GIC_DEFAULT_PRIORITY);
+  }
+
+  /* Route ESPI to primary PE */
+  for (index = EXTENDED_SPI_START_INTID; index <= (max_num_espi_interrupts); index++) {
+      v3_route_extended_interrupt(index);
+  }
+
+}
diff --git a/val/sys_arch_src/smmu_v3/smmu_v3.c b/val/sys_arch_src/smmu_v3/smmu_v3.c
index bc9ee045..e927ff5f 100644
--- a/val/sys_arch_src/smmu_v3/smmu_v3.c
+++ b/val/sys_arch_src/smmu_v3/smmu_v3.c
@@ -66,7 +66,7 @@ static int smmu_cmdq_build_cmd(uint64_t *cmd, uint8_t opcode)
         cmd[1] |= BITFIELD_SET(CMDQ_CFGI_1_RANGE, CMDQ_CFGI_1_ALL_STES);
         break;
     default:
-        val_print(ACS_PRINT_ERR, "\n      Unsupported SMMU command 0x%x    ", opcode);
+        val_print(ACS_PRINT_ERR, "\n       Unsupported SMMU command 0x%x    ", opcode);
         return -1;
     }
 
@@ -90,7 +90,7 @@ static int smmu_cmdq_write_cmd(smmu_dev_t *smmu, uint64_t *cmd)
     }
 
     if (!timeout) {
-        val_print(ACS_PRINT_ERR, "\n      SMMU CMD queue is full     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       SMMU CMD queue is full     ", 0);
         return -1;
     }
 
@@ -133,10 +133,13 @@ static void smmu_cmdq_poll_until_consumed(smmu_dev_t *smmu)
     }
 
     if (!timeout) {
-        val_print(ACS_PRINT_ERR, "\n      CMDQ poll timeout at 0x%08x", queue.prod);
-        val_print(ACS_PRINT_ERR, "\n      prod_reg = 0x%08x,", val_mmio_read((uint64_t)smmu->cmdq.prod_reg));
-        val_print(ACS_PRINT_ERR, "\n      cons_reg = 0x%08x", val_mmio_read((uint64_t)smmu->cmdq.cons_reg));
-        val_print(ACS_PRINT_ERR, "\n      gerror   = 0x%08x     ", val_mmio_read(smmu->base + SMMU_GERROR_OFFSET));
+        val_print(ACS_PRINT_ERR, "\n       CMDQ poll timeout at 0x%08x", queue.prod);
+        val_print(ACS_PRINT_ERR, "\n       prod_reg = 0x%08x,",
+val_mmio_read((uint64_t)smmu->cmdq.prod_reg));
+        val_print(ACS_PRINT_ERR, "\n       cons_reg = 0x%08x",
+val_mmio_read((uint64_t)smmu->cmdq.cons_reg));
+        val_print(ACS_PRINT_ERR, "\n       gerror   = 0x%08x     ",
+val_mmio_read(smmu->base + SMMU_GERROR_OFFSET));
     }
 }
 
@@ -208,7 +211,7 @@ static uint32_t smmu_strtab_init_linear(smmu_dev_t *smmu)
     size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3);
     cfg->strtab_ptr = val_memory_alloc(2*size);
     if (!cfg->strtab_ptr) {
-        val_print(ACS_PRINT_ERR, "\n      Failed to allocate linear stream table.     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       Failed to allocate linear stream table.     ", 0);
         return 0;
     }
     val_memory_set(cfg->strtab_ptr, 2*size, 0);
@@ -232,7 +235,7 @@ static uint32_t smmu_cmd_queue_init(smmu_dev_t *smmu)
     cmdq_size = (cmdq_size < 32)?32:cmdq_size;
     cmdq->base_ptr = val_memory_alloc (2 * cmdq_size);
     if (!cmdq->base_ptr) {
-        val_print(ACS_PRINT_ERR, "\n      Failed to allocate queue struct.     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       Failed to allocate queue struct.     ", 0);
         return 0;
     }
     val_memory_set(cmdq->base_ptr, 2*cmdq_size, 0);
@@ -300,7 +303,8 @@ static int smmu_strtab_init_level2(smmu_dev_t *smmu, uint32_t sid)
     desc->span = STRTAB_SPLIT + 1;
     desc->l2ptr = val_memory_alloc(size*2);
     if (!desc->l2ptr) {
-        val_print(ACS_PRINT_ERR, "\n      failed to allocate l2 stream table for SID %u     ",    sid);
+        val_print(ACS_PRINT_ERR, "\n       failed to allocate l2 stream table for SID %u     ",
+sid);
         return 0;
     }
     desc->l2desc_phys = align_to_size((uint64_t)val_memory_virt_to_phys(desc->l2ptr), size);
@@ -323,7 +327,7 @@ static int smmu_strtab_init_level1(smmu_dev_t *smmu)
 
     cfg->l1_desc = val_memory_alloc(l1_desc_arr_size);
     if (!cfg->l1_desc) {
-        val_print(ACS_PRINT_ERR, "\n      failed to allocate l1 stream table desc     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       failed to allocate l1 stream table desc     ", 0);
         return 0;
     }
     val_memory_set(cfg->l1_desc, l1_desc_arr_size, 0);
@@ -349,7 +353,7 @@ static int smmu_strtab_init_2level(smmu_dev_t *smmu)
     l1_tbl_size = cfg->l1_ent_count * STRTAB_L1_DESC_SIZE;
     cfg->strtab_ptr = val_memory_alloc(2 * l1_tbl_size);
     if (!cfg->strtab_ptr) {
-        val_print(ACS_PRINT_ERR, "\n      failed to allocate l1 stream table     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       failed to allocate l1 stream table     ", 0);
         return 0;
     }
 
@@ -378,7 +382,7 @@ static uint32_t smmu_strtab_init(smmu_dev_t *smmu)
         ret = smmu_strtab_init_linear(smmu);
 
     if (!ret) {
-        val_print(ACS_PRINT_ERR, "\n      Stream table init failed     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       Stream table init failed     ", 0);
         return ret;
     }
 
@@ -440,7 +444,7 @@ static int smmu_reset(smmu_dev_t *smmu)
 
     ret = smmu_reg_write_sync(smmu, 0, SMMU_CR0_OFFSET, SMMU_CR0ACK_OFFSET);
     if (ret) {
-        val_print(ACS_PRINT_ERR, "\n      failed to clear SMMU_CR0     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       failed to clear SMMU_CR0     ", 0);
         return ret;
     }
 
@@ -463,7 +467,7 @@ static int smmu_reset(smmu_dev_t *smmu)
     ret = smmu_reg_write_sync(smmu, en, SMMU_CR0_OFFSET,
                       SMMU_CR0ACK_OFFSET);
     if (ret) {
-        val_print(ACS_PRINT_ERR, "\n      failed to enable command queue     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       failed to enable command queue     ", 0);
         return ret;
     }
 
@@ -473,7 +477,7 @@ static int smmu_reset(smmu_dev_t *smmu)
     ret = smmu_reg_write_sync(smmu, en, SMMU_CR0_OFFSET,
                       SMMU_CR0ACK_OFFSET);
     if (ret) {
-        val_print(ACS_PRINT_ERR, "\n      failed to enable SMMU     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       failed to enable SMMU     ", 0);
         return ret;
     }
 
@@ -488,14 +492,14 @@ uint32_t smmu_set_state(uint32_t smmu_index, uint32_t en)
 
     if (smmu_index >= g_num_smmus)
     {
-        val_print(ACS_PRINT_ERR, "\n      smmu_set_state: invalid smmu index    ", 0);
+        val_print(ACS_PRINT_ERR, "  smmu_set_state: invalid smmu index\n", 0);
         return 1;
     }
 
     smmu = &g_smmu[smmu_index];
     if (smmu->base == 0)
     {
-        val_print(ACS_PRINT_ERR, "\n      smmu_set_state: smmu unsupported     ", 0);
+        val_print(ACS_PRINT_ERR, "  smmu_set_state: smmu unsupported\n", 0);
         return 1;
     }
 
@@ -510,7 +514,8 @@ uint32_t smmu_set_state(uint32_t smmu_index, uint32_t en)
                       SMMU_CR0ACK_OFFSET);
     if (ret)
     {
-        val_print(ACS_PRINT_ERR, "\n      smmu_set_state: failed to set SMMU state     ", 0);
+        val_print(ACS_PRINT_ERR, "  smmu_set_state: failed to set SMMU state\n",
+                                                                           0);
         return ret;
     }
     return 0;
@@ -559,7 +564,7 @@ static uint32_t smmu_probe(smmu_dev_t *smmu)
         smmu->supported.s2p = 1;
 
     if (!(data & (IDR0_S1P | IDR0_S2P))) {
-        val_print(ACS_PRINT_ERR, "\n      no translation support!     ", 0);
+        val_print(ACS_PRINT_ERR, "  no translation support!\n ", 0);
         return 0;
     }
 
@@ -569,13 +574,13 @@ static uint32_t smmu_probe(smmu_dev_t *smmu)
     case IDR0_TTF_AARCH64:
         break;
     default:
-        val_print(ACS_PRINT_ERR, "\n      AArch64 table format not supported!     ", 0);
+        val_print(ACS_PRINT_ERR, "  AArch64 table format not supported!\n", 0);
         return 0;
     }
 
     data = val_mmio_read(smmu->base + SMMU_IDR1_OFFSET);
     if (data & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET)) {
-        val_print(ACS_PRINT_ERR, "\n      fixed table base address not supported     ", 0);
+        val_print(ACS_PRINT_ERR, "  fixed table base addr not supported\n", 0);
         return 0;
     }
 
@@ -585,8 +590,8 @@ static uint32_t smmu_probe(smmu_dev_t *smmu)
     smmu->sid_bits = BITFIELD_GET(IDR1_SIDSIZE, data);
     smmu->ssid_bits = BITFIELD_GET(IDR1_SSIDSIZE, data);
 
-    val_print(ACS_PRINT_INFO, "ssid_bits = %d\n", smmu->ssid_bits);
-    val_print(ACS_PRINT_INFO, "sid_bits = %d\n", smmu->sid_bits);
+    val_print(ACS_PRINT_INFO, "  ssid_bits = %d", smmu->ssid_bits);
+    val_print(ACS_PRINT_INFO, " sid_bits = %d\n", smmu->sid_bits);
 
     if (smmu->sid_bits <= STRTAB_SPLIT)
         smmu->supported.st_level_2lvl = 0;
@@ -595,14 +600,14 @@ static uint32_t smmu_probe(smmu_dev_t *smmu)
     data = val_mmio_read(smmu->base + SMMU_IDR5_OFFSET);
 
     if (BITFIELD_GET(IDR5_OAS, data) >= SMMU_OAS_MAX_IDX) {
-        val_print(ACS_PRINT_ERR, "\n      Unknown output address size     ", 0);
+        val_print(ACS_PRINT_ERR, "  Unknown output address size\n", 0);
         return 0;
     }
     smmu->oas = smmu_oas[BITFIELD_GET(IDR5_OAS, data)];
     smmu->ias = get_max(smmu->ias, smmu->oas);
 
-    val_print(ACS_PRINT_INFO, "ias %d-bit ", smmu->ias);
-    val_print(ACS_PRINT_INFO, "oas %d-bit ", smmu->oas);
+    val_print(ACS_PRINT_INFO, "  ias %d-bit ", smmu->ias);
+    val_print(ACS_PRINT_INFO, "oas %d-bit \n", smmu->oas);
 
     return 1;
 }
@@ -654,7 +659,7 @@ static int smmu_cdtab_alloc_leaf_table(smmu_cdtab_l1_ctx_desc_t *l1_desc)
 
     l1_desc->l2ptr = val_memory_alloc(size*2);
     if (!l1_desc->l2ptr) {
-        val_print(ACS_PRINT_ERR, "\n      failed to allocate context descriptor table     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       failed to allocate context descriptor table     ", 0);
         return 1;
     }
     l1_desc->l2desc_phys = align_to_size((uint64_t)val_memory_virt_to_phys(l1_desc->l2ptr), size);
@@ -693,14 +698,14 @@ static int smmu_cdtab_write_ctx_desc(smmu_master_t *master,
 
     if (ssid >= (1 << master->stage1_config.s1cdmax))
     {
-        val_print(ACS_PRINT_ERR, "\n      smmu_cdtab_write_ctx_desc: ssid out of range     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       smmu_cdtab_write_ctx_desc: ssid out of range     ", 0);
         return 0;
     }
 
     cdptr = smmu_cdtab_get_ctx_desc(master);
     if (!cdptr)
     {
-        val_print(ACS_PRINT_ERR, "\n      smmu_cdtab_write_ctx_desc: cdptr is NULL     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       smmu_cdtab_write_ctx_desc: cdptr is NULL     ", 0);
         return 0;
     }
 
@@ -773,7 +778,7 @@ static int smmu_cdtab_alloc(smmu_master_t *master)
 
     cdcfg->cdtab_ptr = val_memory_alloc(l1_tbl_size * 2);
     if (!cdcfg->cdtab_ptr) {
-        val_print(ACS_PRINT_ERR, "\n      smmu_cdtab_alloc: alloc failed     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       smmu_cdtab_alloc: alloc failed     ", 0);
         return 0;
     }
 
@@ -833,14 +838,14 @@ uint32_t val_smmu_map(smmu_master_attributes_t master_attr, pgt_descriptor_t pgt
 
     if (master_attr.smmu_index >= g_num_smmus)
     {
-        val_print(ACS_PRINT_ERR, "\n      val_smmu_map: invalid smmu index     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       val_smmu_map: invalid smmu index     ", 0);
         return 1;
     }
 
     smmu = &g_smmu[master_attr.smmu_index];
     if (smmu->base == 0)
     {
-        val_print(ACS_PRINT_ERR, "\n      val_smmu_map: smmu unsupported     ", 0);
+        val_print(ACS_PRINT_ERR, "\n       val_smmu_map: smmu unsupported     ", 0);
         return 1;
     }
 
@@ -873,14 +878,16 @@ uint32_t val_smmu_map(smmu_master_attributes_t master_attr, pgt_descriptor_t pgt
 
     if (master_attr.streamid >= (0x1ul << smmu->sid_bits))
     {
-        val_print(ACS_PRINT_ERR, "\n      val_smmu_map: sid %d out of range     ", master_attr.streamid);
+        val_print(ACS_PRINT_ERR,
+        "\n       val_smmu_map: sid %d out of range     ",
+        master_attr.streamid);
         return 1;
     }
 
     if (smmu->supported.st_level_2lvl) {
         if(!smmu_strtab_init_level2(smmu, master->sid))
         {
-            val_print(ACS_PRINT_ERR, "\n      val_smmu_map: l2 stream table init failed     ", 0);
+            val_print(ACS_PRINT_ERR, "\n       val_smmu_map: l2 stream table init failed     ", 0);
             return 1;
         }
     }
@@ -1013,6 +1020,7 @@ void val_smmu_stop(void)
 uint32_t val_smmu_init(void)
 {
     int i;
+    uint32_t smmu_version;
     g_num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0);
     if (g_num_smmus == 0)
         return ACS_STATUS_ERR;
@@ -1020,21 +1028,24 @@ uint32_t val_smmu_init(void)
     g_smmu = val_memory_alloc(sizeof(smmu_dev_t) * g_num_smmus);
     if (!g_smmu)
     {
-        val_print(ACS_PRINT_ERR, "\n      val_smmu_init: memory allocation failure     ", 0);
+        val_print(ACS_PRINT_ERR, "\n  smmu_init memory allocation failure", 0);
         return ACS_STATUS_ERR;
     }
 
     val_memory_set(g_smmu, sizeof(smmu_dev_t) * g_num_smmus, 0);
 
     for (i = 0; i < g_num_smmus; ++i) {
-        if (val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, i) != 3) {
-            val_print(ACS_PRINT_ERR, "\n      val_smmu_init: only SMMUv3.x supported, skipping smmu %d    ", i);
+        smmu_version = val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, i);
+        if (smmu_version != 3) {
+            val_print(ACS_PRINT_ERR, "  Only SMMUv3.x init supported\n", 0);
+            val_print(ACS_PRINT_ERR, "  smmu %d version is", i);
+            val_print(ACS_PRINT_ERR, "  %d\n", smmu_version);
             continue;
         }
         g_smmu[i].base = val_iovirt_get_smmu_info(SMMU_CTRL_BASE, i);
         if (smmu_init(&g_smmu[i]))
         {
-            val_print(ACS_PRINT_ERR, "\n      val_smmu_init: smmu %d init failed     ", i);
+            val_print(ACS_PRINT_ERR, "  smmu_init: smmu %d init failed\n", i);
             g_smmu[i].base = 0;
             return ACS_STATUS_ERR;
         }
@@ -1054,7 +1065,9 @@ val_smmu_get_info(SMMU_INFO_e type, uint32_t smmu_index)
     smmu_dev_t *smmu;
     if (smmu_index >= g_num_smmus)
     {
-        val_print(ACS_PRINT_ERR, "\n      val_smmu_get_info: invalid smmu index(%d)     ", smmu_index);
+        val_print(ACS_PRINT_ERR,
+                  "\n       val_smmu_get_info: invalid smmu index(%d)     ",
+                  smmu_index);
         return 0;
     }
     smmu = &g_smmu[smmu_index];